ISL1532IRZ-T7 [INTERSIL]
Dual Channel Differential DSL Line Driver; 双通道差动DSL线路驱动器
| 型号： | ISL1532IRZ-T7 |
| 厂家： | 
Intersil |
| 描述： | Dual Channel Differential DSL Line Driver |
| 文件： | 总19页 (文件大小：1008K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL1532
Data Sheet
December 4, 2006
FN6173.3
Dual Channel Differential DSL Line Driver
Features
The ISL1532 is a dual channel differential amplifier designed
for driving full rate ADSL2+ signals at very low power
dissipation. The high drive capability of 450mA makes this
driver ideal for DMT designs. It contains two pairs of
wideband, high-voltage, current mode feedback amplifiers
designed on Intersil’s HS30 Bipolar SOI process for low
power consumption in DSL systems.
• 450mA output drive capability
• 44.4V differential output drive into 100Ω
P-P
• ±5V to ±15V supply operation
• MTPR of -70dB
• Operates down to 2mA per amplifier supply current
• Current control pins
These drivers achieve an MTPR distortion measurement of
better than 70dB, while consuming typically 5mA per DSL
channel of total supply current. This supply current can be
• Channel separation
- 80dB @ 500kHz
set using a resistor on the I
pin. Two other pins (C and
ADJ
0
• Direct pin-to-pin replacement for EL1528
C ) can also be used to adjust supply current to one of four
1
pre-set modes (full-I , 3/4-I , 1/2-I , and full power-down).
• Pb-free plus anneal available (RoHS compliant)
S
S
S
C and C inputs are design to pull high initially. Floating
0
1
Applications
these inputs will put the device in disable mode. This is
contrary to EL1528 where C and C inputs pull low initially
0
1
• Dual port ADSL2+ line drivers
• HDSL line drivers
and is in the enable state when C and C pins are floated.
0
1
The ISL1532 operates on ±5V to ±15V supplies and retains
its bandwidth and linearity over the complete supply range.
The device is supplied in a thermally-enhanced
20 Ld HTSSOP and the small footprint (4x5mm) 24 Ld QFN
packages. The ISL1532 is specified for operation over the
full -40°C to +85°C temperature range.
The ISL1532 provides larger output swing at heavy loads,
higher slew rate, and higher bandwidth while maintaining
pin-to-pin drop-in compatibility with the EL1528. The
ISL1532 integrates 50k pull-up resistors on C and C pins.
0
1
Pinouts
ISL1532 (24 LD QFN)
ISL1532 (20 Ld HTSSOP)
TOP VIEW
TOP VIEW
C0AB
C1AB
VINA+
VINB+
GND
1
2
3
4
5
6
7
8
9
20 VS-
19
18
17
16
15
14
13
12
VOUTA
VINA-
VINA+
1
2
3
4
5
6
7
19 VINA-
18 VINB-
17 VOUTB
16 VOUTC
15 VINC-
14 VIND-
13 VOUTD
VINB+
GND
VINB-
VOUTB
VOUTC
VINC-
THERMAL
PAD*
THERMAL
PAD
IADJ
NC
IADJ
VINC+
VIND+
C1CD
VINC+
VIND+
VIND-
VOUTD
C0CD 10
11 VS+
*THERMAL PAD INTERNALLY CONNECTED TO GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL1532
Ordering Information
PART NUMBER
PACKAGE
(See Note)
PART MARKING
1532 IRZ
TAPE & REEL
(Pb-Free)
PKG. DWG. #
MDP0046
ISL1532IRZ
-
24 Ld QFN
24 Ld QFN
24 Ld QFN
ISL1532IRZ-T7
ISL1532IRZ-T13
ISL1532IVEZ
1532 IRZ
1532 IRZ
1532 IVEZ
1532 IVEZ
1532 IVEZ
7”
MDP0046
MDP0046
MDP0048
MDP0048
MDP0048
13”
-
20 Ld HTSSOP
20 Ld HTSSOP
20 Ld HTSSOP
ISL1532IVEZ-T7
ISL1532IVEZ-T13
7”
13”
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6173.3
December 4, 2006
2
ISL1532
Absolute Maximum Ratings (T = +25°C)
A
V + to V - Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 30V
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Output Current from Driver (Static) . . . . . . . . . . . . . . . . . . . . . 50mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +150°C
S
S
V + Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 30V
S
V - Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30V to 0.3V
S
Driver V + Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V - to V +
IN
S
S
C , C Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
0
1
I
Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V
ADJ
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . .250V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: T = T = T
A.
J
C
Electrical Specifications
PARAMETER
V
= ±12V, R = 3kΩ, R = 65Ω, I = C = C = 0V, T = +25°C. Amplifiers tested separately.
ADJ 0 1 A
S
F
L
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CHARACTERISTICS
I + (Full I )
Positive Supply Current per Amplifier All outputs at 0V, C = C = 0V, R
= 0
= 0
3.75
-6.3
4.9
-4.7
3.8
6.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
S
S
0
1
ADJ
I - (Full I )
Negative Supply Current per Amplifier All outputs at 0V, C = C = 0V, R
-3.5
S
S
0
1
ADJ
I + (3/4 I )
Positive Supply Current per Amplifier All outputs at 0V, C = 5V, C = 0V, R
= 0
= 0
= 0
= 0
S
S
0
1
ADJ
ADJ
ADJ
I - (3/4 I )
Negative Supply Current per Amplifier All outputs at 0V, C = 5V, C = 0V, R
-3.5
2.6
S
S
0
1
I + (1/2 I )
Positive Supply Current per Amplifier All outputs at 0V, C = 0V, C = 5V, R
1.87
3.75
-1.75
1.0
S
S
0
1
I - (1/2 I )
Negative Supply Current per Amplifier All outputs at 0V, C = 0V, C = 5V, R
-3.75
-2.4
0.25
0
S
S
0
1
ADJ
I + (Power-down) Positive Supply Current per Amplifier All outputs at 0V, C = C = 5V, R
= 0
S
0
1
ADJ
I - (Power-down) Negative Supply Current per Amplifier All outputs at 0V, C = C = 5V, R
= 0
-1.0
S
0
1
ADJ
I
GND Supply Current per Amplifier
All outputs at 0V
0.25
GND
INPUT CHARACTERISTICS
Input Offset Voltage
Mismatch
V
-10
-5
1
0
+10
+5
mV
mV
µA
OS
ΔV
V
OS
I +
OS
Non-Inverting Input Bias Current
Inverting Input Bias Current
-15
-30
-25
1
+14
+30
+25
8
B
I -
µA
B
ΔI -
I - Mismatch
B
0
µA
B
R
Transimpedance
3.4
3.5
2
MΩ
OL
e
Input Noise Voltage
-Input Noise Current
Input High Voltage
nV/ Hz
√
N
i
pA/ Hz
√
N
V
C
C
C
and C inputs, with signal
1.8
1.6
V
V
IH
0
0
0
1
and C inputs, without signal
1
V
Input Low Voltage
and C inputs
0.8
40
V
IL
1
I
I
I
Input High Current for C
C
C = 5V, C = 5V
10
20
µA
µA
IH0, IH1
0,
1
0
1
Input Low Current for C or C
0
C
= 0V, C = 0V
-3.0
-0.3
IL
1
0
1
FN6173.3
December 4, 2006
3
ISL1532
Electrical Specifications
PARAMETER
V
= ±12V, R = 3kΩ, R = 65Ω, I
= C = C = 0V, T = +25°C. Amplifiers tested separately. (Continued)
S
F
L
ADJ 0 1 A
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT CHARACTERISTICS
V
Loaded Output Swing
R
R
R
R
R
= 100Ω
±11.1
+10.95
-10.95
+10.7
-10.5
V
V
OUT
L
L
L
L
L
(R Single-ended to GND)
L
= 50Ω (+)
= 50Ω (-)
= 25Ω (+)
= 25Ω (-)
+10.5
+10.0
-10.5
-9.6
V
V
V
I
I
Linear Output Current
Output Current
A
= 5, R = 10Ω, f = 100kHz, THD = -60dBc
450
mA
OL
V
L
(10Ω single-ended)
V
= 1V, R = 1Ω
1
A
OUT
OUT
L
DYNAMIC PERFORMANCE
BW
-3dB Bandwidth
A
= +5, R
L-DIFF
= 100Ω
50
MHz
dBc
V
HD2
2nd Harmonic Distortion
3rd Harmonic Distortion
f
= 1MHz, R = 5kΩ, A = 10,
-90
C
F
V
R
= 100Ω, V
= 2V
L-DIFF
OUT
PP-DIFF
f
= 1MHz, R = 5kΩ, A = 10, R
= 50Ω,
= 50Ω,
-85
-80
-65
-70
400
dBc
dBc
dBc
dBc
V/µs
C
F
V
L-DIFF
V
= 2V
OUT
PP-DIFF
HD3
f
= 1MHz, R = 5kΩ, A = 10,
C
F
V
R
= 100Ω, V
= 2V
L-DIFF
OUT
PP-DIFF
f
= 1MHz, R = 5kΩ, A = 10, R
C
F
V
L-DIFF
V
= 2V
OUT
PP-DIFF
MTPR
SR
Multi-Tone Power Ratio
Slew rate (single-ended)
26kHz to 1.1MHz, R
P
= 100Ω,
LINE
= 20.4dBM
LINE
V
from -8V to +8V measured at ±4V
200
OUT
Pin Descriptions
20 Ld HTSSOP
24 Ld QFN
PIN NAME
FUNCTION
CIRCUIT
1
23
C0AB (Note 1) DSL Channel 1 current control pin
2.6V
V +
S
V +
S
50k
20k
C
OAB
V -
S
I
ADJ
CIRCUIT 1
2
3
24
5, 11, 12, 21
1
C1AB (Note 1) DSL Channel 1 current control pin
(Reference Circuit 1)
NC
Not connected
VINA+
Amplifier A non-inverting input
V +
S
7.5k
V -
S
CIRCUIT 2
4
2
VINB+
Amplifier B non-inverting input
(Reference Circuit 2)
FN6173.3
December 4, 2006
4
ISL1532
Pin Descriptions
20 Ld HTSSOP
24 Ld QFN
PIN NAME
FUNCTION
CIRCUIT
6
4
IADJ (Note 2) Supply current control pin for both DSL
Channels 1 and 2
V +
S
I
ADJ
V -
S
GND
CIRCUIT 3
5
3
GND
VINC+
VIND+
Ground connection
7
6
Amplifier C non-inverting input
Amplifier D non-inverting input
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 1)
(Reference Circuit 1)
8
7
9
8
C1CD (Note 3) DSL Channel 2 current control pin
C0CD (Note 3) DSL Channel 2 current control pin
10
9
11
10
13
14
15
16
17
18
19
20
22
VS+
VOUTD
VIND-
VINC-
VOUTC
VOUTB
VINB-
VINA-
VOUTA
VS-
Positive supply
12
Amplifier D output
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 2)
13
Amplifier D inverting input
Amplifier C inverting input
Amplifier C output
14
15
16
Amplifier B output
17
Amplifier B inverting input
Amplifier A inverting input
Amplifier A output
18
19
20
Negative supply
NOTES:
1. Amplifiers A and B comprise DSL Channel 1. C
0AB
and C control I settings for DSL Channel 1.
1AB S
2. I
controls bias current (I ) setting for both DSL channels.
S
ADJ
3. Amplifiers C and D comprise DSL Channel 2. C
and C
control I settings for DSL Channel 2.
1CD S
0CD
Typical Performance Curves
A = 10
V
A
= 10
= ±12V
= 100Ω
V
R
= 2kΩ
R = 2kΩ
F
F
V
= ±12V
= 100Ω
S
V
S
R
R
R
R
L
L
= 0Ω
= 0Ω
ADJ
ADJ
R
= 3kΩ
F
R
= 3kΩ
F
R
= 4kΩ
R = 4kΩ
F
F
FIGURE 1. DIFFERENTIAL FREQUENCY RESPONSE vs R
FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE vs R
F
F
(FULL I )
(3/4 I )
S
S
FN6173.3
December 4, 2006
5
ISL1532
Typical Performance Curves (Continued)
R
= 2kΩ
A
= 10
= ±12V
= 100Ω
A
= 10
= ±12V
= 100Ω
L
= 1 COMMON-MODE
F
V
V
R
= 2kΩ
V
V
R
F
S
S
R
R
L
R
= 3kΩ
= 0Ω
F
A
ADJ
V
R
= 3kΩ
F
R
= 4kΩ
F
R
= 4kΩ
F
FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE vs R
FIGURE 4. COMMON-MODE FREQUENCY RESPONSE vs R
F
F
(1/2 I )
(FULL I )
S
S
A
= 10
= ±12V
= 100Ω
= 1 COMMON-MODE
A
= 10
= ±12V
= 100Ω
L
= 1 COMMON-MODE
V
V
R
= 2kΩ
F
R
= 2kΩ
F
V
R
V
R
S
S
L
A
A
V
V
R
= 3kΩ
F
R
= 3kΩ
F
R
= 4kΩ
R
= 4kΩ
F
F
FIGURE 5. COMMON-MODE FREQUENCY RESPONSE vs R
FIGURE 6. COMMON-MODE FREQUENCY RESPONSE vs R
F
F
(3/4 I )
S
(1/2 I )
S
A = 5
V
A
= 5
R
= 2kΩ
V
F
R
= 2kΩ
F
V
= ±12V
= 100Ω
= 0Ω
V
= ±12V
= 100Ω
= 0Ω
S
L
S
R
R
R
R
L
ADJ
ADJ
R
= 3kΩ
F
R
= 3kΩ
F
R
= 4kΩ
F
R
= 4kΩ
F
FIGURE 7. DIFFERENTIAL FREQUENCY RESPONSE vs R
FIGURE 8. DIFFERENTIAL FREQUENCY RESPONSE vs R
F
F
(FULL I )
(3/4 I )
S
S
FN6173.3
December 4, 2006
6
ISL1532
Typical Performance Curves (Continued)
A
= 5
= ±12V
= 100Ω
= 1 COMMON_MODE
R
= 2kΩ
A
= 5
V
F
V
V
R
A
V
= ±12V
= 100Ω
= 0Ω
S
S
R
= 2kΩ
= 3kΩ
F
R
R
L
L
V
ADJ
R
F
R
= 3kΩ
F
R
= 4kΩ
F
R
= 4kΩ
F
FIGURE 9. DIFFERENTIAL FREQUENCY RESPONSE vs R
FIGURE 10. COMMON-MODE FREQUENCY RESPONSE vs R
F
F
(1/2 I )
S
(FULL I )
S
A
V
= 5
= ±12V
= 100Ω
= 1 COMMON-MODE
A
V
= 5
= ±12V
= 100Ω
= 1 COMMON-MODE
V
S
L
V
S
L
R
= 2kΩ
F
R
= 2kΩ
F
R
A
R
A
V
V
R
= 4kΩ
F
R = 3kΩ
F
R
= 3kΩ
F
R
= 4kΩ
F
FIGURE 12. COMMON-MODE FREQUENCY RESPONSE vs R
FIGURE 11. COMMON-MODEFREQUENCY RESPONSE vs R
F
F
(1/2 I )
(3/4 I )
S
S
A
= 5
A
= 5
V
V
47pF
47pF
V
= ±12V
= 100Ω
= 3kΩ
V
= ±12V
= 100Ω
= 3kΩ
S
S
R
R
R
R
L
F
L
F
27pF
27pF
15pF
0pF
15pF
0pF
FIGURE 13. DIFFERENTIAL FREQUENCY RESPONSE vs C
FIGURE 14. DIFFERENTIAL FREQUENCY RESPONSE vs C
L
L
(FULL I )
(3/4 I )
S
S
FN6173.3
December 4, 2006
7
ISL1532
Typical Performance Curves (Continued)
47pF
27pF
A
= 10
V
A
= 5
V
47pF
V
= ±12V
= 100Ω
= 3kΩ
S
V
= ±12V
= 100Ω
= 3kΩ
S
R
R
L
F
R
R
L
F
27pF
15pF
15pF
0pF
0pF
FIGURE 15. DIFFERENTIAL FREQUENCY RESPONSE vs C
L
FIGURE 16. DIFFERENTIAL FREQUENCY RESPONSE vs C
L
(1/2 I )
(FULL I )
S
S
A
V
R
R
= 10
47pF
A
V
R
R
= 10
V
S
L
F
V
S
L
F
= ±12V
= 100Ω
= 3kΩ
= ±12V
= 100Ω
= 3kΩ
47pF
27pF
27pF
15pF
15pF
0pF
0pF
FIGURE 17. DIFFERENTIAL FREQUENCY RESPONSE vs C
L
FIGURE 18. DIFFERENTIAL FREQUENCY RESPONSE vs C
L
(3/4 I )
(1/2 I )
S
S
V
R
= ±12V
= 3kΩ
= 10
S
F
V
R
A
V
= ±12V
= 3kΩ
= 10
S
F
R
= 475Ω
L
R
= 475Ω
L
A
V
R
= 365Ω
L
R
= 365Ω
L
R = 220Ω
L
R = 220Ω
L
R
= 100Ω
L
R = 100Ω
L
FIGURE 19. DIFFERENTIAL FREQUENCY RESPONSE vs R
FIGURE 20. DIFFERENTIAL FREQUENCY RESPONSE vs R
L
L
(FULL I )
(3/4 I )
S
S
FN6173.3
December 4, 2006
8
ISL1532
Typical Performance Curves (Continued)
V
R
= ±12V
= 3kΩ
= 10
V
R
A
V
= ±12V
= 3kΩ
= 5
S
F
S
F
R = 475Ω
L
R = 475Ω
L
R = 365Ω
L
A
V
R = 365Ω
L
R = 220Ω
L
R = 220Ω
L
R = 100Ω
L
R = 100Ω
L
FIGURE 21. DIFFERENTIAL FREQUENCY RESPONSE vs R
L
FIGURE 22. DIFFERENTIAL FREQUENCY RESPONSE vs R
L
(1/2 I )
(FULL I )
S
S
V
R
= ±12V
= 3kΩ
= 5
V
= ±12V
= 3kΩ
= 5
S
F
S
F
R = 475Ω
R = 365Ω
L
R
= 475Ω
R = 365Ω
L
L
L
R
A
A
V
V
R = 220Ω
R
= 220Ω
L
L
R = 100Ω
R
= 100Ω
L
L
FIGURE 24. DIFFERENTIAL FREQUENCY RESPONSE vs R
FIGURE 23. DIFFERENTIAL FREQUENCY RESPONSE vs R
L
L
(1/2 I )
(3/4 I )
S
S
V
= ±12V
V
= ±12V
S
S
THD
FREQ =1MHz
HD3
FREQ = 1MHz
A
= 5
= 100Ω
= 3kΩ
A
= 5
= 100Ω
= 3kΩ
V
V
R
R
R
R
L
F
L
F
THD
HD2
HD2
HD3
DIFFERENTIAL V
DIFFERENTIAL V
OP-P
OP-P
FIGURE 25. HARMONICS DISTORTION vs DIFFERENTIAL
FIGURE 26. HARMONICS DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE (3/4 I )
OUTPUT VOLTAGE (FULL I )
S
S
FN6173.3
December 4, 2006
9
ISL1532
Typical Performance Curves (Continued)
V
= ±12V
S
FREQ = 1MHz
HD2
THD
A
R
R
= 5
= 100Ω
= 3kΩ
V
L
F
THD
V
= ±6V
S
FREQ = 1MHz
HD2
A
R
R
= 5
= 100Ω
= 3kΩ
HD3
V
L
F
HD3
DIFFERENTIAL V
DIFFERENTIAL V
OP-P
OP-P
FIGURE 27. HARMONICS DISTORTION vs DIFFERENTIAL
FIGURE 28. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE (1/2 I )
S
OUTPUT VOLTAGE (FULL I )
S
HD3
THD
HD3
THD
V
= ±6V
S
V
= ±6V
S
FREQ = 1MHz
FREQ = 1MHz
A
= 5
= 100Ω
= 3kΩ
V
A
= 5
= 100Ω
= 3kΩ
V
HD2
R
R
L
F
HD2
R
R
L
F
DIFFERENTIAL V
DIFFERENTIAL V
OP-P
OP-P
FIGURE 29. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE (3/4 I )
FIGURE 30. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE (1/2 I )
S
S
V
= ±12V
S
V
= ±12V
S
HD3
FREQ = 200kHz
FREQ = 200kHz
A
= 5
A
= 5
= 100Ω
= 3kΩ
V
V
THD
THD
R
R
= 100Ω
= 3kΩ
R
R
L
F
L
F
HD3
HD2
HD2
DIFFERENTIAL V
DIFFERENTIAL V
OP-P
OP-P
FIGURE 31. HARMONIC DISTORTION vs DIFFERENTIAL
FIGURE 32. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE (3/4 I )
OUTPUT VOLTAGE (FULL I )
S
S
FN6173.3
December 4, 2006
10
ISL1532
Typical Performance Curves (Continued)
V
= ±12V
S
FREQ = 200kHz
FULL POWER MODE
THD
A
R
R
= 5
= 100Ω
= 3kΩ
V
L
F
HD2
3/4 POWER MODE
1/2 POWER MODE
HD3
DIFFERENTIAL V
±V)
OP-P
FIGURE 33. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE (1/2 I )
FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE
S
100
10
±12 VDC
1
0.1
0.01
±6 VDC
1k
10k
100k
1M
10M
100M
R
(Ω)
ADJ
FREQUENCY (Hz)
FIGURE 36. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 35. QUIESCENT SUPPLY CURRENT vs R
ADJ
PSRR-
AB <==>CD
PSRR+
FIGURE 37. CHANNEL SEPARATION vs FREQUENCY
FIGURE 38. PSRR vs FREQUENCY
FN6173.3
December 4, 2006
11
ISL1532
Typical Performance Curves (Continued)
V
= ±12V
= 2
= 3kΩ
V
= ±12V
= 2
= 3kΩ
S
S
A
A
V
V
GAIN
GAIN
R
R
R
R
F
F
= 0Ω
= 0Ω
SET
SET
PHASE
PHASE
RELATIVE GAIN AND PHASE R = 100Ω
RELATIVE GAIN AND PHASE R = 100Ω
L
L
FIGURE 39. DIFFERENTIAL GAIN/PHASE (FULL I )
FIGURE 40. DIFFERENTIAL GAIN/PHASE (3/4 I )
S
S
V
= ±12V
= 2
= 3kΩ
S
A
V
GAIN
R
R
F
E
N
= 0Ω
SET
PHASE
I
N-
RELATIVE GAIN AND PHASE R = 100Ω
L
FIGURE 41. DIFFERENTIAL GAIN/PHASE (1/2 I )
S
FIGURE 42. VOLTAGE AND CURRENT NOISE vs FREQUENCY
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN AND HTSSOP
EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
4.5
1.2
4
1.000W
1
3.571W
3.5
HTSSOP20
HTSSOP20
3.378W
θ
=125°C/W
893mW
JA
3
2.5
2
θ
=35°C/W
0.8
0.6
0.4
0.2
0
JA
QFN24
QFN24
=140°C/W
θ
=37°C/W
θ
JA
JA
1.5
1
0.5
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 44. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 43. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6173.3
December 4, 2006
12
ISL1532
TABLE 1. POWER MODES OF THE ISL1532
OPERATION
Full Power Mode
Applications Information
The ISL1532 consists of two sets of high-power line driver
amplifiers that can be connected for full duplex differential
line transmission. The amplifiers are designed to be used
with signals up to 10MHz and produce low distortion levels.
C
C
0
1
0
0
I
S
0
1
1
1
0
1
3/4 I Power Mode
S
The ISL1532 has been optimized as a line driver for ADSL2+
CO application. The driver output stage has been sized to
provide full ADSL2+ CO power level of 20dBM onto the
telephone lines. Realizing that the actual peak output
voltages and currents vary with the line transformer turns
ratio, the ISL1532 is designed to support 450mA of output
current which exceeds the level required for 1:2 transformer
ratio. A typical ADSL2+ interface circuit is shown in
Figure 45. Each amplifier has identical positive gain
connections, and optimum common-mode rejection occurs.
Further, DC input errors are duplicated and create
1/2 I Power Mode
S
Power-down
Another method for controlling the power consumption of the
ISL1532 is to connect a resistor from the I pin to ground.
ADJ
pin is grounded (the normal state), the supply
When the I
ADJ
current per channel is as per the Electrical Specifications
table on page 3. When a resistor is inserted, the supply
current is scaled according to the “R
Performance Curves section.
vs I ” graphs in the
S
SET
Both methods of power control can be used simultaneously.
In this case, positive and negative supply currents (per amp)
are given by the equations below:
common-mode rather than differential line errors.
R
DRIVER
INPUT +
LINE +
OUT
+
-
5.06mA
------------------------------------------------
I + = 0.34mA +
x
R
R
F
F
S
1 + (R
/ 1300)
SET
(3/4C + 1/2C - C × C × 1/4)
2R
R
LINE
G
1
0
1
0
(EQ. 1)
-5.06mA
R
------------------------------------------------
I - =
x
OUT
S
-
+
1 + (R
/ 1300)
SET
DRIVER
INPUT -
LINE -
(3/4C + 1/2C - C × C × 1/4)
1
0
1
0
R
R
F
R
Power Supplies and Dissipation
IN
-
RECEIVE
OUT +
Due to the high power drive capability of the ISL1532, much
attention needs to be paid to power dissipation. The power
that needs to be dissipated in the ISL1532 has two main
contributors. The first is the quiescent current dissipation.
The second is the dissipation of the output stage.
+
RECEIVE
AMPLIFIERS
+
-
R
R
R
IN
F
RECEIVE
OUT -
The quiescent power in the ISL1532 is not constant with
varying outputs. In reality, 50% of the total quiescent supply
current needed to power each driver is converted in to output
current. Therefore, in the equation below we should subtract
FIGURE 45. TYPICAL LINE INTERFACE CONNECTION
Input Connections
The ISL1532 amplifiers are somewhat sensitive to source
impedance. In particular, they do not like being driven by
inductive sources. More than 100nH of source impedance
can cause ringing or even oscillations. This inductance is
equivalent to about 4” of unshielded wiring, or 6” of
unterminated transmission line. Normal high-frequency
construction obviates any such problem.
the average output current, I , or 1/2 I , whichever is the
O
Q
lowest. We’ll call this term I .
X
P
= V × (I - 2I
X
)
(EQ. 2)
Dquiescent
S
S
where:
• V is the supply voltage (V + to V -)
S
S
S
Power Control Function
• I is the operating supply current (I + - I -) / 2
S
S
S
The ISL1532 contains two forms of power control operation.
• I is the lesser of I or 1/2 I
Q
X
O
Two digital inputs, C and C , can be used to control the
0
1
The dissipation in the output stage has two main contributors.
Firstly, we have the average voltage drop across the output
transistor and secondly, the average output current. For
minimal power dissipation, the user should select the supply
voltage and the line transformer ratio accordingly. The supply
voltage should be kept as low as possible, while the
supply current of the ISL1532 drive amplifiers. C and C
inputs are designed to pull high initially. Floating these inputs
will put the device in disable mode.
0
1
As the supply current is reduced, the ISL1532 will start to
exhibit slightly higher levels of distortion and the frequency
response will be limited. The four power modes of the
ISL1532 are set up as shown in Table 1.
transformer ratio should be selected so that the peak voltage
required from the ISL1532 is close to the maximum available
FN6173.3
December 4, 2006
13
ISL1532
output swing. There is a trade off, however, with the selection
of transformer ratio. As the ratio is increased, the receive
signal available to the receivers is reduced.
The θ requirement needs to be calculated. This is done
JA
using the equation:
T
- T
AMB
JUNCT
--------------------------------------------
Θ
=
JA
Once the user has selected the transformer ratio, the
dissipation in the output stages can be selected with the
following equation:
P
DISS
(EQ. 6)
where:
• T
V
S
2
⎛
⎝
⎞
-------
P
= 2 × I
×
- V
O
⎠
is the maximum die temperature (+150°C)
Dtransistors
O
JUNCT
(EQ. 3)
• T
AMB
is the maximum ambient temperature (+85°C)
is the dissipation calculated above
where:
• V is the supply voltage (V + to V -)
• P
DISS
S
S
S
• θ is the junction to ambient thermal resistance for the
JA
• V is the average output voltage per channel
O
package when mounted on the PCB
• I is the average output current per channel
O
150 - 85
1247mW
------------------------
= 52°C/W
Θ
=
JA
(EQ. 7)
The overall power dissipation (P
) is obtained by
DISS
summing P
and P .
Dtransistor
Dquiescent
V +
S
R
Estimating Line Driver Power Dissipation in
ADSL2+ CO Applications
T
T +
X
+
-
50
TXFR
1:1
V -
S
0.22µF
0.22µF
R
Figure 46 shows a typical ADSL CO line driver
implementation. The average line power requirement for the
ADSL2+ CO application is 20dBM (100mW) into a 100Ω line
F
From
AFE
100
3k
2R
G
1.5kΩ
T -
which translated to 3.16V
line voltage. The ADSL2+
V +
RMS
S
R
T
+
-
X
DMT peak to average ratio (crest factor) of 5.3 implies peak
voltage of 16.7V into the line. Using a differential drive
configuration and transformer coupling with standard back
termination, a transformer ratio of 1:1 is selected. With 1:1
transformer ratio, the impedance across the driver side of
50
V -
S
R
F
3k
FIGURE 46. TYPICAL ADSL CO LINE DRIVER
IMPLEMENTATION
the transformer is 100Ω, the average voltage is 3.16V
RMA
and the average current is 31.6mA. The power dissipated in
the ISL1532 is a combination of the quiescent power and the
output stage power when driving the line:
PCB Layout Considerations for QFN and HTSSOP
Packages
P
= P
+ P
quiescent output-stage
D
D
The ISL1532 die is packaged in two thermally-efficient
packages: a 24 Ld QFN (leadless plastic) and 20 Ld
HTSSOP packages. Both have the thermal pads underneath
the package and can use PCB surface metal vias areas and
internal ground planes to spread heat away from the
package. The larger the PCB area, the lower the junction
temperature of the device will be. In ADSL applications,
multiple layer circuit boards with internal ground plane are
generally used. 13 mil vias are recommended to connect the
metal area under the device with the internal ground plane.
Examples of the PCB layouts for the QFN and HTSSOP
packages are shown in Figures 47 and 48 respectively.
37°C/W (QFN package) and +35°C/W (HTSSOP package)
are obtained with the ISL1532 demoboard. The demoboard
is a 4-layer board built with 2 oz. copper and has a
P
= V × (I - 2I ) + (V - 2 × V
) × I
OUT-RMS
S
S
X
S
OUT-RMS
(EQ. 4)
In the full power mode and with 1.5k R
resistor, the
ADJ
ISL1532 consumes typically 2.7mA quiescent current per
amplifier and still able to maintain very low distortion. The
distortion results are shown in typical performance section of
the data sheet. When driving a load, a large portion (about
50%) of the quiescent current becomes output load current.
The total power dissipation per channel is:
P
= 24 × (2.7mA × 2 × 50%) + 2 × 31.6mA × (12- 3.16)
D
(EQ. 5)
where:
2
dimension of 4 in .
P
= 623mW
D
A separate application note for the QFN package and layout
recommendation is available. If using the QFN package, the
layout and manufacturing process recommendations should
be carefully reviewed.
The total power dissipation for dual channel is:
P
Dtotal
= 2 x P
D
= 1247mW
FN6173.3
December 4, 2006
14
ISL1532
Output Loading
While the drive amplifiers can output in excess of 500mA
transiently, the internal metallization is not designed to carry
more than 100mA of steady DC current and there is no
current-limit mechanism. The device can safely drive RMS
sinusoidal currents of 2 x 100mA, or 200mA. This current is
more than that required to drive line impedances to large
output levels, but output short circuits cannot be tolerated.
The series output resistor will usually limit currents to safe
values in the event of line shorts. Driving lines with no series
resistor is a serious hazard.
TOP METAL
The amplifiers are sensitive to capacitive loading. More than
25pF will cause peaking of the frequency response. The
same is true of badly terminated lines connected without a
series matching resistor.
Power Supplies and Component Placement
The power supplies should be well bypassed close to the
ISL1532. A 2.2µF tantalum capacitor and a 0.1µF ceramic
capacitor for each supply works well. Since the load currents
are differential, they should not travel through the board
copper and set up ground loops that can return to amplifier
inputs. Due to the class AB output stage design, these
currents have heavy harmonic content. If the ground
terminal of the positive and negative bypass capacitors are
connected to each other directly and then returned to circuit
ground, no such ground loops will occur. This scheme is
employed in the layout of the ISL1532 demonstration board,
and documentation can be obtained from the factory.
INTERNAL GROUND PLANE
FIGURE 47. PCB LAYOUT - QFN PACKAGE
The parallel combination of the feedback resistor and gain
setting resistor and parasitic capacitance on the inverting input
node forms a pole in the feedback path. If the frequency of this
pole is low, it can lead to frequency peaking. Since the ISL1532
is a current feedback amplifier, the feedback resistor value is
predetermined by design. The only way to increase the
frequency of this pole is to reduce the parasitic capacitance on
the inverting input node. Ground plane near the inverting input
should be avoided to minimize the parasitic capacitance.
Single Supply Operation
TOP METAL
The ISL1532 can also be powered from a single supply
voltage. When operating in this mode, the GND pins can still
be connected directly to GND and the C and C pins are
0
1
relative to GND. To calculate power dissipation, the
equations in the previous section should be used, with V
equal to half the supply rail.
S
Feedback Resistor Value
The bandwidth and peaking of the amplifiers varies with
supply voltage somewhat and with gain settings. The
feedback resistor values can be adjusted to produce an
optimal frequency response. Here is a series of resistor
values that produce an optimal driver frequency response
(1dB peaking) for different supply voltages and gains:
INTERNAL GROUND PLANE
FIGURE 48. PCB LAYOUT - HTSSOP PACKAGE
FN6173.3
December 4, 2006
15
ISL1532
backmatch resistor without compromising the total source
TABLE 2. OPTIMUM DRIVER FEEDBACK RESISTOR FOR
VARIOUS GAINS AND SUPPLY VOLTAGES
termination impedance relaxes the output and supply
voltage requirement for the amplifier and reduces the overall
power dissipation. R and R are the only additions to the
DRIVER VOLTAGE GAIN
P1
P2
passive circuit and provide the positive feedback for the
amplifier. This feedback synthesizes larger output
impedance for the amplifier, allowing a reduction of the
backmatch resistance. For convenience, a factor K is being
introduced. It is the ratio between the backmatch resistance
and the physical backmatch resistor.
SUPPLY VOLTAGE
5
10
±12V
4k
3k
The ISL1532 features improved frequency compensation for
all power modes and applications, allowing stable operation
at very low power levels and eliminating any need for
external "snubber" circuits. Differential circuits, such as
ADSL2+ line driver applications, can be especially prone to
common-mode oscillation. The ISL1532 is specifically
compensated to eliminate this type of instability and allow for
reliable operation even at very low power levels.
R
L
RBM
-------------
K =
(EQ. 8)
R
R
G
F
Cable Termination Techniques
Z
R
L
BM
The traditional circuit for a line driver with passive
-
V
O
+
termination is shown in Figure 49. R
is the backmatch
BM
R
L
resistance added for proper termination at the source. This
backmatch resistance is typically equal to the value of the
cable line characteristic impedance and the load impedance.
The output impedance of the amplifier is negligible in
comparison with the value of the backmatch resistor it
appears in series with. The gain equation reflects the output
voltage across the load resistance with respect to the input
voltage.
R
R
P2
P1
V
IN
FIGURE 50. ACTIVE TERMINATION TECHNIQUE
The stability of the amplifier and the physical backmatch
resistance tolerance typically limit K to around 4 or 5. The
output impedance of the amplifier is increased by the
positive feedback, allowing the backmatch resistance to
decrease-keeping the total source impedance constant.
R
R
F
G
R
R
G
F
R
Z
L
BM
-
V
O
V
+
IN
R
R
BM
L
-
V
X
+
I
X
V
R
R
L
+ R
BM L
R
R
P2
⎛
⎜
⎝
⎞
⎛
⎜
⎝
⎞
⎟
⎠
P1
O
F
---------
--------
--------------------------
=
1 +
×
⎟
⎠
V
R
G
R
IN
FIGURE 51. MEASURING OUTPUT IMPEDANCE
FIGURE 49. TRADITIONAL CABLE TERMINATION TECHNIQUE
Figure 51 shows a standard method for measuring the
output impedance of any circuit. Ohm's law applies, so a
While functional, this passive termination circuit has some
disadvantages. The output impedance of the driver, while
small, can be a noticeable quantity. The backmatch resistor
is necessary to properly terminate the source end of a
transmission line such as a twisted pair, but now the voltage
delivered to the load is split between that backmatch
resistance and the load resistance. Since there is a required
voltage level at the load, the driver must now produce twice
the voltage swing. The voltage swing and power dissipation
increases. The power burned in the backmatch resistor is
lost as heat which causes the total power dissipation to
doubled. There also is quiescent power used in the op amp.
measured voltage (V ) applied to a node divided by the test
X
current gives the impedance seen at that node. Ideal op amp
simplifications (input terminals are at the same voltage and
there is no current flowing into the inputs) R is assumed
P2
much larger the R
BM
so the current through the positive
feedback loop can be neglected. The voltage at the input
terminals is given by a resistive divider of the output voltage
on either side of the backmatch resistor. These feedback
resistors alter the output resistance for the op amp, allowing
reduction in the backmatch resistance. The derivations are
as follows:
An alternative technique of cable termination using positive
feedback is shown in Figure 50. With negative feedback
already in place to set the gain, positive feedback can be
used to adjust the output impedance. Lowering the
FN6173.3
December 4, 2006
16
ISL1532
Table 3 is a quick comparison of the reduction in voltage and
R
P1
----------------------------
power requirements for the driver with passive or active
termination. The key specification of a ADSL2+ CO driver
are as follows: Peak output line power is 20dBM, POTS line
impedance is 100Ω and the crest factor for ADSL DMT
signal is 14.5dB. This specification translates to 16.76V
peak-to-peak voltage on the line with 5.3 peak to average
ratio PAR and 31.6mA average output current. In the passive
termination case where the load and backmatch resistors
are the same, the amplifier must provide 33.52V
peak-to-peak at its outputs. A high voltage line driver
typically needs 4V of total headroom. As a result the total
supply voltage required is 37.5V. With the necessary output
average current, that translates into 1.185W dissipated in
addition to the quiescent power of the amplifier.
V+ =
V- =
× V
X
R
+ R
P2
P1
R
G
----------------------
× V
O
R
+ R
G
F
V
R
R + R
F G
R
G
⎛
⎜
⎝
⎞
⎟
⎠
X
P1
-------
---------------------------- ----------------------
×
R
=
= R
/
BM
1 -
SOURCE
SOURCE
I
R
+ R
X
P1
P2
R
= R = K × RBM
L
R
R + R
F G
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
P1
----------------------------
----------------------
K = 1 ⁄ 1 -
×
R
+ R
R
G
P1
P2
(EQ. 9)
The overall gain of the active termination circuit is:
TABLE 3.
V
R
/ (R + R
)
P1
⎛
⎜
⎝
⎞
⎟
⎠
O
P2
P2
---------
----------------------------------------------------------------------------------------------
=
PASSIVE TERMINATION
ACTIVE TERMINATION
V
R
+ R
R
IN
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
1
K
G
F
P1
⎛
⎝
⎞
⎠
----------------------
----------------------------
1 + ---
/
-
16.5V
into a 100Ω line
16.5V
into a 100Ω line
P-P
R
G
R
+ R
P2 P1
P-P
(EQ. 10)
V
V
= V
+
V
V
= V
+
RBM
OUT DRIVER
RLOAD
RBM
OUT DRIVER
RLOAD
R
BM
V
+
-
+
IN
V
+
O
RBM = R
RBM = R
/5
LOAD
LOAD
R
R
F
V
V
V
= V
V
V
V
= V
/5
RLOAD
RBM
RLOAD
RBM
R
R
= 33.52V
= 20.11V
OUT DRIVER
G
G
OUT DRIVER
R
L
= 37.52
= 24.11
SUPPLY
SUPPLY
I
= 31.6mA
I
= 31.6mA
OUT
OUT
F
R
BM
P
= V
* I
SUPPLY OUT
P
= V
* I
+
-
OUT DRIVER
OUT DRIVER SUPPLY OUT
V
-
O
= 1.185W (plus quiescent power) = 0.714W (plus quiescent power)
V
-
IN
In the active case, a K of 5 is assumed. This reduces the
backmatch resistor to 20% of its value in the passive case.
The peak-to-peak output voltage provided by the driver is
reduced to 20.11V which allows the use of the EL1508, a
median voltage line driver. The EL1508 requires 2.5V of
headroom. With 2.5V of supply voltage headroom, the power
supply required becomes 22.61. With the same output
current drive, the power dissipation is reduced by 39.7% to
0.714W. While it is true that additional power is dissipated in
the feedback networks, the feedback resistors are typically
much larger than the backmatch resistor and their losses are
negligible.
FIGURE 52. DIFFERENTIAL LINE DRIVER USING ACTIVE
TERMINATION TECHNIQUE
In an ADSL2+ system, the POTS phone line, a twisted pair
cable is used for data transmission. As shown in Figure 52,
the single ended active terminate line driver is reconfigured
to drive differential lines. The gain resistor is shared to allow
accurate gain matching between the two amplifiers. Applying
the same analysis technique as the single ended circuit, the
following relationship can be derived:
R
⎛
⎞
⎟
⎠
F
-------
K = 1 / 1 -
⎜
R
P
⎝
V
1 + R / R + R / R
F G F P
⎛
⎜
⎝
⎞
⎟
⎠
OUT
---------------
-----------------------------------------------------------
=
V
R
IN
⎛
⎞
⎟
⎠
F
-------
2 × 1 -
⎜
R
P
⎝
(EQ. 11)
FN6173.3
December 4, 2006
17
ISL1532
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
SYMBOL QFN44 QFN38
QFN32
TOLERANCE
±0.10
NOTES
D
B
A
A1
b
0.90
0.02
0.25
0.20
7.00
5.10
7.00
5.10
0.50
0.55
44
0.90 0.90
0.90
0.02
0.22
0.20
5.00
-
-
0.02 0.02
0.25 0.23
0.20 0.20
5.00 8.00
+0.03/-0.02
±0.02
-
1
2
3
PIN #1
I.D. MARK
c
Reference
Basic
-
D
-
E
D2
E
3.80 5.80 3.60/2.48
7.00 8.00 6.00
5.80 5.80 4.60/3.40
Reference
Basic
8
-
E2
e
Reference
Basic
8
-
2X
0.075 C
0.50 0.80
0.40 0.53
0.50
0.50
32
L
±0.05
-
2X
0.075 C
N
38
7
32
8
Reference
Reference
Reference
4
6
5
TOP VIEW
ND
NE
11
7
11
12
8
9
0.10 M C A B
b
TOLER-
ANCE NOTES
L
SYMBOL QFN28 QFN24
QFN20
QFN16
0.90
PIN #1 I.D.
A
0.90
0.02
0.90 0.90
0.02 0.02
0.90
0.02
±0.10
-
-
3
1
2
3
A1
0.02
+0.03/
-0.02
b
c
0.25
0.20
4.00
2.65
5.00
3.65
0.50
0.40
28
0.25 0.30
0.20 0.20
4.00 5.00
2.80 3.70
5.00 5.00
3.80 3.70
0.50 0.65
0.40 0.40
0.25
0.20
4.00
2.70
4.00
2.70
0.50
0.40
20
0.33
±0.02
-
-
(E2)
0.20 Reference
4.00 Basic
2.40 Reference
4.00 Basic
2.40 Reference
D
-
5
NE
D2
E
-
-
E2
e
-
7
(D2)
0.65
0.60
16
Basic
-
L
±0.05
-
BOTTOM VIEW
N
24
5
20
5
Reference
Reference
Reference
4
6
5
0.10 C
ND
NE
6
5
4
e
C
8
7
5
5
4
SEATING
PLANE
Rev 10 12/04
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
0.08 C
SEE DETAIL "X"
N LEADS
& EXPOSED PAD
SIDE VIEW
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
(c)
2
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
A
C
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
(L)
A1
DETAIL X
N LEADS
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
FN6173.3
December 4, 2006
18
ISL1532
HTSSOP (Heat-Sink TSSOP) Family
0.25 M C A B
MDP0048
D
A
HTSSOP (Heat-Sink TSSOP) Family
(N/2)+1
N
TOLER-
ANCE
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD
A
A1
A2
b
1.20
1.20
1.20
1.20
1.20
Max
±0.075
PIN #1 I.D.
E
E1
0.075 0.075 0.075 0.075 0.075
0.90
0.25
0.15
5.00
3.2
0.90
0.25
0.15
6.50
4.2
0.90
0.25
0.15
7.80
4.3
0.90
0.25
0.15
9.70
5.0
0.90
0.22
0.15
9.70
7.25
6.40
4.40
3.0
+0.15/-0.10
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
2X
1
(N/2)
c
N/2 LEAD TIPS
TOP VIEW
B
D
D1
E
Reference
Basic
D1
EXPOSED
THERMAL PAD
6.40
4.40
3.0
6.40
4.40
3.0
6.40
4.40
3.0
6.40
4.40
3.0
E1
E2
e
±0.10
Reference
Basic
0.65
0.60
1.00
14
0.65
0.60
1.00
20
0.65
0.60
1.00
24
0.65
0.60
1.00
28
0.50
0.60
1.00
38
E2
L
±0.15
L1
N
Reference
Reference
Rev. 2 12/03
BOTTOM VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15mm per
side.
0.05
H
e
C
2. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm per side.
SEATING
PLANE
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.10 C
N LEADS
SIDE VIEW
SEE DETAIL “X”
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6173.3
December 4, 2006
19
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