ISL21009_0709 [INTERSIL]
High Voltage Input Precision, Low Noise FGA⑩ Voltage References; 高电压输入精密，低噪声FGA⑩电压基准
| 型号： | ISL21009_0709 |
| 厂家： | 
Intersil |
| 描述： | High Voltage Input Precision, Low Noise FGA⑩ Voltage References |
| 文件： | 总19页 (文件大小：640K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL21009
®
Data Sheet
September 12, 2007
FN6327.6
High Voltage Input Precision, Low Noise
FGA™ Voltage References
Features
• Output Voltages . . . . . . . .1.250V, 2.500V, 4.096V, 5.000V
• Initial Accuracy. . . . . . . . . . . . . .±0.5mV, ±1.0mV, ±2.0mV
• Input Voltage Range. . . . . . . . . . . . . . . . . . . 3.5V to 16.5V
• Output Voltage Noise . . . . . . . . .4.5µVP-P (0.1Hz to 10Hz)
• Supply Current . . . . . . . . . . . . . . . . . . . . . . . .180µA (Max)
• Temperature Coefficient. . . 3ppm/°C, 5ppm/°C, 10ppm/°C
• Output Current Capability. . . . . . . . . . . . . . . Up to ±7.0mA
• Operating Temperature Range. . . . . . . . .-40°C to +125°C
• Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC
• Pb-free available (RoHS compliant)
The ISL21009 FGA™ voltage references are extremely low
power, high precision, and low noise voltage references
fabricated on Intersil’s proprietary Floating Gate Analog
technology. The ISL21009 features very low noise (4.5µVP-P
for 0.1Hz to 10Hz), low operating current (180µA, Max), and
3ppm/°C of temperature drift. In addition, the ISL21009
family features guaranteed initial accuracy as low as
±0.5mV.
This combination of high initial accuracy, low power and low
output noise performance of the ISL21009 enables versatile
high performance control and data acquisition applications
with low power consumption.
Available Options
Applications
• High Resolution A/Ds and D/As
• Digital Meters
VOUT
OPTION
(V)
INITIAL
ACCURACY
(mV)
TEMPCO.
(ppm/°C)
PART NUMBER
ISL21009BFB812Z
ISL21009CFB812Z
ISL21009DFB812Z
ISL21009BFB825Z
ISL21009CFB825Z
ISL21009DFB825Z
ISL21009BFB841Z
ISL21009CFB841Z
ISL21009DFB841Z
ISL21009BFB850Z
ISL21009CFB850Z
ISL21009DFB850Z
• Bar Code Scanners
1.250
1.250
1.250
2.500
2.500
2.500
4.096
4.096
4.096
5.000
5.000
5.000
±0.5
±1.0
±2.0
±0.5
±1.0
±2.0
±0.5
±1.0
±2.0
±0.5
±1.0
±2.0
3
5
• Basestations
• Battery Management/Monitoring
• Industrial/Instrumentation Equipment
10
3
5
Pinout
10
3
ISL21009
(8 LD SOIC)
TOP VIEW
5
GND or NC
VIN
1
2
3
4
8
7
6
5
DNC
10
3
DNC
DNC
VOUT
5
GND
TRIM or NC
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FGA is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
ISL21009
Pin Descriptions
PIN NUMBER
PIN NAME
GND or NC
VIN
DESCRIPTION
Can be either Ground or No Connect
1
2
Power Supply Input Connection
4
GND
Ground Connection
5
6
TRIM
Allows user trim typically ±2.5%. Leave Unconnected when unused.
Voltage Reference Output Connection
VOUT
3, 7, 8
DNC
Do Not Connect; Internal Connection – Must Be Left Floating
Ordering Information
PART NUMBER
PART
VOUT OPTION
TEMP.
RANGE (°C)
PACKAGE
(Pb-Free)
(Notes 1, 2)
ISL21009BFB812Z
ISL21009CFB812Z
ISL21009DFB812Z
ISL21009BFB825Z
ISL21009CFB825Z
ISL21009DFB825Z
ISL21009BFB841Z
ISL21009CFB841Z
ISL21009DFB841Z
ISL21009BFB850Z
ISL21009CFB850Z
ISL21009DFB850Z
NOTES:
MARKING
21009BF Z12
21009CF Z12
21009DF Z12
21009BF Z25
21009CF Z25
21009DF Z25
21009BF Z41
21009CF Z41
21009DF Z41
21009BF Z50
21009CF Z50
21009DF Z50
(V)
GRADE
PKG. DWG. #
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
1.250
1.250
1.250
2.500
2.500
2.500
4.096
4.096
4.096
5.000
5.000
5.000
±0.5mV, 3ppm/°C
±1.0mV, 5ppm/°C
±2.0mV, 10ppm/°C
±0.5mV, 3ppm/°C
±1.0mV, 5ppm/°C
±2.0mV, 10ppm/°C
±0.5mV, 3ppm/°C
±1.0mV, 5ppm/°C
±2.0mV, 10ppm/°C
±0.5mV, 3ppm/°C
±1.0mV, 5ppm/°C
±2.0mV, 10ppm/°C
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
FN6327.6
September 12, 2007
2
ISL21009
1
8
GND
VIN
NC
+5V
2
3
4
7
6
5
NC
VOUT
C1
10µF
NC
NC
GND
ISL21009-25
SPI BUS
X79000
1
2
20
19
18
17
16
15
14
13
12
11
SCK
A0
CS
CLR
VCC
VH
3
A1
4
A2
5
SI
VL
C1
0.001µF
6
SO
VREF
VSS
VOUT
VBUF
VFB
7
RDY
UP
8
LOW NOISE DAC OUTPUT
9
DOWN
OE
10
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUB-RANGING DAC
FN6327.6
September 12, 2007
3
ISL21009
Absolute Voltage Ratings
Recommended Operating Conditions
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +18V
Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . -0.5V to VOUT +1V
Voltage on “DNC” pins . . . . No connections permitted to these pins.
ESD Ratings
Temperature Range (Industrial) . . . . . . . . . . . . . . . -40°C to +125°C
Thermal Information
Continuous Power Dissipation (Note 3) . . . . . . . . . . . . . TA = +70°C
8 Ld SOIC derate 5.88mW/°C above +70°C. . . . . . . . . . . . . 471mW
Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at
the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
NOTE:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Common Electrical Specifications (ISL21009-12, -25, -41, -50) TA = -40°C to +125°C, IOUT = 0, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
-0.5
-1.0
-2.0
TYP
MAX
+0.5
+1.0
+2.0
3
UNIT
mV
VOA
VOUT Accuracy @ TA = +25°C
ISL21009B
ISL21009C
ISL21009D
ISL21009B
ISL21009C
ISL21009D
mV
mV
TC VOUT
Output Voltage Temperature
Coefficient (Note 4)
ppm/°C
ppm/°C
ppm/°C
µA
5
10
IIN
Supply Current
95
±2.5
10
180
ΔVOUT / VOUT Trim Range
ISC Short Circuit Current
tR
±2.0
%
TA = +25°C, VOUT tied to GND
VOUT = ±0.1%
mA
Turn-on Settling Time
Ripple Rejection
100
60
µs
f = 10kHz
dB
eN
VN
Output Voltage Noise
Broadband Voltage Noise
0.1Hz ≤ f ≤ 10Hz
10Hz ≤ f ≤ 1kHz
4.5
2.2
µVP-P
µVRMS
Electrical Specifications (ISL21009-12, VOUT = 1.250V) VIN = 5.0V, TA = -40°C to +125°C, IOUT = 0, unless otherwise specified.
PARAMETER
VOUT
DESCRIPTION
Output Voltage
CONDITIONS
MIN
TYP
MAX
UNIT
V
1.250
VIN
Input Voltage Range
Line Regulation
3.5
16.5
150
50
V
ΔVOUT/ΔVIN
3.5V < VIN < 5.5V
50
10
10
20
50
50
µV/V
µV/V
µV/mA
µV/mA
ppm
ppm
5.5V < VIN < 16.5V
Sourcing: 0mA ≤ IOUT ≤ 7mA
Sinking: -7mA ≤ IOUT ≤ 0mA
ΔTA = +165°C
ΔVOUT/ΔIOUT
Load Regulation
50
100
ΔVOUT/ΔTA
ΔVOUT/Δt
Thermal Hysteresis (Note 5)
Long Term Stability (Note 6)
TA = +25°C
FN6327.6
September 12, 2007
4
ISL21009
Electrical Specifications (ISL21009-25, VOUT = 2.50V) VIN = 5.0V, TA = -40°C to +125°C, IOUT = 0, unless otherwise specified.
PARAMETER
VOUT
DESCRIPTION
Output Voltage
CONDITIONS
MIN
TYP
MAX
UNIT
V
2.500
VIN
Input Voltage Range
Line Regulation
3.5
16.5
150
50
V
ΔVOUT/ΔVIN
3.5V < VIN < 5.5V
50
10
10
20
50
50
µV/V
µV/V
µV/mA
µV/mA
ppm
ppm
5.5V < VIN < 16.5V
Sourcing: 0mA ≤ IOUT ≤ 7mA
Sinking: -7mA ≤ IOUT ≤ 0mA
ΔTA = +165°C
ΔVOUT/ΔIOUT
Load Regulation
50
100
ΔVOUT/ΔTA
ΔVOUT/Δt
Thermal Hysteresis (Note 5)
Long Term Stability (Note 6)
TA = +25°C
Electrical Specifications (ISL21009-41, VOUT = 4.096V)
VIN = 5.0V, TA = -40°C to +125°C, IOUT = 0 unless otherwise
specified.
PARAMETER
VOUT
DESCRIPTION
Output Voltage
CONDITIONS
MIN
TYP
MAX
UNIT
V
4.096
VIN
Input Voltage Range
Line Regulation
4.5
16.5
200
100
150
V
ΔVOUT/ΔVIN
ΔVOUT/ΔIOUT
4.5V < VIN < 16.5V
50
20
20
50
50
µV/V
µV/mA
µV/mA
ppm
ppm
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 5mA
Sinking: -5mA ≤ IOUT ≤ 0mA
ΔTA = +165°C
ΔVOUT/ΔTA
ΔVOUT/Δt
Thermal Hysteresis (Note 5)
Long Term Stability (Note 6)
TA = +25°C
Electrical Specifications (ISL21009-50, VOUT = 5.0V) VIN = 10.0V, TA = -40°C to +125°C, IOUT = 0 unless otherwise specified.
PARAMETER
VOUT
DESCRIPTION
Output Voltage
CONDITIONS
MIN
TYP
MAX
UNIT
V
5.000
VIN
Input Voltage Range
Line Regulation
5.5
16.5
90
V
ΔVOUT/ΔVIN
ΔVOUT/ΔIOUT
5.5V < VIN < 16.5V
20
10
20
50
50
µV/V
µV/mA
µV/mA
ppm
ppm
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 7mA
Sinking: -7mA ≤ IOUT ≤ 0mA
ΔTA = +165°C
100
150
ΔVOUT/ΔTA
ΔVOUT/Δt
NOTES:
Thermal Hysteresis (Note 5)
Long Term Stability (Note 6)
TA = +25°C
4. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the
temperature range; in this case, -40°C to +125°C = +165°C.
5. Thermal Hysteresis is the change of VOUT measured @ TA = +25°C after temperature cycling over a specified range, ΔTA. VOUT is read initially
at TA = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference
between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For Δ TA = +165°C, the device under test is cycled
from +25°C to +125°C to -40°C to +25°C.
6. Long term drift is logarithmic in nature and diminishes over time. Drift after the first 1000 hours will be approximately 10ppm/sqrt(1kHrs).
FN6327.6
September 12, 2007
5
ISL21009
Typical Performance Curves (ISL21009-12) (REXT = 100kΩ)
110
105
100
95
100
95
90
85
80
+25°C
UNIT 3
-40°C
UNIT 2
+125°C
90
UNIT 1
85
80
5
7
9
11
13
15
17
5
7
9
11
(V)
13
15
17
V
V
(V)
IN
IN
FIGURE 2. IIN vs VIN, 3 UNITS
FIGURE 3. IIN vs VIN, 3 TEMPERATURES
60
40
60
40
UNIT 1
+25°C
20
UNIT 2
20
-40°C
0
-20
-40
-60
-80
-100
0
+125°C
UNIT 3
-20
-40
-60
3.5
5.5
7.5
9.5
11.5
13.5
15.5
3.50
5.50
7.50
9.50
(V)
11.5
13.5
15.5
V
(V)
V
IN
IN
FIGURE 4. LINE REGULATION, 3 UNITS
FIGURE 5. LINE REGULATION OVER-TEMPERATURE
0.08
1.25020
0.06
0.04
1.25015
UNIT 1
UNIT 2
1.25010
1.25005
1.25000
1.24995
1.24990
1.24985
1.24980
+25°C
0.02
-40°C
+125°C
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
UNIT 3
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
-40
-15
10
35
60
85
110
SINKING
OUTPUT CURRENT (mA)
SOURCING
TEMPERATURE (°C)
FIGURE 6. LOAD REGULATION
FIGURE 7. VOUT vs TEMPERATURE, 3 UNITS
FN6327.6
September 12, 2007
6
ISL21009
Typical Performance Curves (ISL21009-12) (REXT = 100kΩ) (Continued)
X = 10µs/DIV
Y = 200mV/DIV
0
500kHz PEAK
(DC) = 10V
NO LOAD
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
IN
10nF
100nF
1nF
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 8. PSRR AT DIFFERENT CAPACITIVE LOADS
FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
X = 5µs/DIV
V
IN
Y = 20mV/DIV
V
REF
X = 100µs/DIV
Y = 1V/DIV
FIGURE 10. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 11. TURN-ON TIME
GAIN IS x1000,
NOISE IS 4.5µV
200
180
160
P-P
1nF LOAD
NO LOAD
140
120
100
80
60
10nF LOAD
40
20
0
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 12. ZOUT vs FREQUENCY
FIGURE 13. VOUT NOISE, 0.1Hz TO 10Hz
FN6327.6
September 12, 2007
7
ISL21009
Typical Performance Curves (ISL21009-12) (REXT = 100kΩ) (Continued)
X = 5µs/DIV
X = 10µs/DIV
Y = 50mV/DIV
Y = 500mV/DIV
+7mA
+50µA
-50µA
-7mA
FIGURE 14. LOAD TRANSIENT RESPONSE
FIGURE 15. LOAD TRANSIENT RESPONSE
Typical Performance Curves (ISL21009-25) (REXT = 100kΩ)
140
120
100
80
120
110
100
90
UNIT 1
UNIT 2
+125°C
+25°C
UNIT 3
60
-40°C
40
20
0
3.5
80
5.5
7.5
9.5
V
11.5
13.5
15.5
3.5
5.5
7.5
9.5
V
11.5
13.5
15.5
(V)
(V)
IN
IN
FIGURE 16. IIN vs VIN, 3 UNITS
FIGURE 17. IIN vs VIN, 3 TEMPERATURES
2.50010
2.50005
2.50000
2.49995
2.49990
2.49985
2.49980
60
40
UNIT 2
+25°C
20
UNIT 3
-40°C
0
UNIT 1
-20
-40
-60
-80
-100
+125°C
3.50
5.50
7.50
9.50
(V)
11.5
13.5
15.5
3.50
5.50
7.50
9.50
11.5
13.5
15.5
V
(V)
V
IN
IN
FIGURE 18. LINE REGULATION
FIGURE 19. LINE REGULATION OVER-TEMPERATURE
FN6327.6
September 12, 2007
8
ISL21009
Typical Performance Curves (ISL21009-25) (REXT = 100kΩ) (Continued)
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
2.4994
2.4993
UNIT 3
UNIT 2
+125°C
-40°C
UNIT 1
+25°C
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
-40
-20
0
20
40
60
80
100 120 140
SINKING
OUTPUT CURRENT (mA)
SOURCING
TEMPERATURE (°C)
FIGURE 20. LOAD REGULATION
FIGURE 21. VOUT vs TEMPERATURE
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
500kHz PEAK
(DC) = 10V
NO LOAD
V
IN
10nF
1nF
100nF
100k
1
10
100
1k
10k
1M
10M
FREQUENCY (Hz)
FIGURE 22. PSRR AT DIFFERENT CAPACITIVE LOADS
FIGURE 23. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
5.2
4.8
4.4
V
IN
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
HIGH I
IN
MEDIUM I
IN
LOW I
IN
0
0.05
0.10 0.15
0.20 0.25
TIME (ms)
0.30 0.35
0.40
FIGURE 24. LINE TRANSIENT RESPONSE, 0.001µF LOAD
FIGURE 25. TURN-ON TIME
CAPACITANCE
FN6327.6
September 12, 2007
9
ISL21009
Typical Performance Curves (ISL21009-25) (REXT = 100kΩ) (Continued)
GAIN IS x1000, NOISE
IS 4.5µV
P-P
160
140
120
100
80
10nF
1nF
NO LOAD
100nF
60
40
20
0
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 26. ZOUT vs FREQUENCY
FIGURE 27. VOUT NOISE, 0.1Hz TO 10Hz
NO OUTPUT CAPACITANCE
NO OUTPUT CAPACITANCE
7mA
+50µA
-50µA
-7mA
FIGURE 28. LOAD TRANSIENT RESPONSE
FIGURE 29. LOAD TRANSIENT RESPONSE
Typical Performance Curves (ISL21009-41) (REXT = 100kΩ)
110
105
100
95
100
95
+25°C
UNIT 3
-40°C
90
85
80
UNIT 2
+125°C
90
UNIT 1
85
80
5
7
9
11
(V)
13
15
17
5
7
9
11
(V)
13
15
17
V
V
IN
IN
FIGURE 30. IIN vs VIN, 3 UNITS
FIGURE 31. IIN vs VIN, 3 TEMPERATURES
FN6327.6
September 12, 2007
10
ISL21009
Typical Performance Curves (ISL21009-41) (REXT = 100kΩ) (Continued)
4.0963
4.0962
4.0962
4.0961
4.0961
4.0960
4.0960
4.0959
4.0959
4.0958
300
250
200
150
100
50
UNIT 2
UNIT 1
+125°C
+25°C
-40°C
UNIT 3
0
-50
-100
-150
-200
4.50
6.50
8.50
10.5
(V)
12.5
14.5
16.5
4.50
6.50
8.50
10.5
(V)
12.5
14.5
16.5
V
IN
V
IN
FIGURE 32. LINE REGULATION, 3 UNITS
FIGURE 33. LINE REGULATION OVER-TEMPERATURE
0.10
0.05
4.0970
4.0965
0.00
4.0960
+25°C
UNIT 2
-40°C
-0.05
-0.10
-0.15
-0.20
+125°C
4.0955
UNIT 3
4.0950
UNIT 1
4.0945
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SINKING OUTPUT CURRENT (mA)
SOURCING
FIGURE 34. LOAD REGULATION
FIGURE 35. VOUT vs TEMPERATURE
0
-10
-20
-30
-40
-50
-60
-70
-80
V
V
(DC) = 5V
IN
IN
NO LOAD
100nF LOAD
(AC) RIPPLE = 50mV
P-P
10nF LOAD
1nF LOAD
10k 100k
FREQUENCY (Hz)
X = 10µs/DIV
1
10
100
1k
1M
10M
Y = 200mV/DIV
FIGURE 37. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
FIGURE 36. PSRR AT DIFFERENT CAPACITIVE LOADS
FN6327.6
September 12, 2007
11
ISL21009
Typical Performance Curves (ISL21009-41) (REXT = 100kΩ) (Continued)
V
IN
V
REF
X = 50µs/DIV
Y = 2V/DIV
X = 10µs/DIV
Y = 200mV/DIV
FIGURE 39. TURN-ON TIME
FIGURE 38. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
GAIN IS x10,000
NOISE IS 4.5µV
P-P
200
180
160
1nF LOAD
NO LOAD
140
120
100
80
60
10nF LOAD
40
20
0
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
1s/DIV
FIGURE 40. ZOUT vs FREQUENCY
FIGURE 41. VOUT NOISE, 0.1Hz TO 10Hz
7mA
+50µA
-50µA
-7mA
NO OUTPUT CAPACITANCE
X = 5µs/DIV
NO OUTPUT CAPACITANCE
X = 5µs/DIV
Y = 500mA/DIV
Y = 50mV/DIV
FIGURE 42. LOAD TRANSIENT RESPONSE
FIGURE 43. LOAD TRANSIENT RESPONSE
FN6327.6
September 12, 2007
12
ISL21009
Typical Performance Curves (ISL21009-50) (REXT = 100kΩ)
140
120
100
80
110
100
90
+25°C
112µA
104µA
95µA
+125°C
60
40
-40°C
20
0
80
5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5
5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V (V)
IN
V
(V)
IN
FIGURE 44. IIN vs VIN, 3 UNITS
FIGURE 45. IIN vs VIN, 3 TEMPERATURES
5.0001
5.0000
4.9999
4.9998
4.9997
4.9996
4.9995
4.9994
100
0
+125°C
-100
-200
-300
-400
-500
-600
-700
-40°C
+25°C
104µA
95µA
112µA
5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5
5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
(V)
V
(V)
IN
IN
FIGURE 46. LINE REGULATION
FIGURE 47. LINE REGULATION OVER-TEMPERATURE
0.10
0.05
0.00
-40°C
+25°C
-0.05
-0.10
-0.15
-0.20
-0.25
+125°C
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
SINKING
OUTPUT CURRENT (mA)
SOURCING
FIGURE 48. LOAD REGULATION
FN6327.6
September 12, 2007
13
ISL21009
Typical Performance Curves (ISL21009-50) (REXT = 100kΩ) (Continued)
5.001
5.001
5.000
5.000
4.999
4.999
4.998
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
NO LOAD
V
V
(DC) = 10V
NORMALIZED TO +25°C
IN
IN
(AC) RIPPLE = 50mV
P-P
UNIT 1
UNIT 2
10nF
100nF
100k
1nF
UNIT 3
1
10
100
1k
10k
1M
10M
-40
-20
0
20
40
60
80
100 120 140
FREQUENCY (Hz)
TEMPERATURE (°C)
FIGURE 49. VOUT vs TEMPERATURE
FIGURE 50. PSRR AT DIFFERENT CAPACITIVE LOADS
V
= 10V
IN
V
= 10V
DV = 1V
IN
IN
DV = 1V
IN
FIGURE 51. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
FIGURE 52. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
12
10
120
1nF
100
V
IN
8
6
4
2
0
80
60
450nA
NO LOAD
40
20
10nF
270nA
50
340nA
0
0
100
150
TIME (µs)
200
250
300
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 53. TURN-ON TIME
FIGURE 54. ZOUT vs FREQUENCY
FN6327.6
September 12, 2007
14
ISL21009
Typical Performance Curves (ISL21009-50) (REXT = 100kΩ) (Continued)
GAIN IS x1000
NOISE IS 4.5µV
P-P
50µA
-50µA
FIGURE 56. LOAD TRANSIENT RESPONSE
FIGURE 55. VOUT NOISE, 0.1Hz TO 10Hz
7mA
-7mA
FIGURE 57. LOAD TRANSIENT RESPONSE
The process used for these reference devices is a floating
Applications Information
gate CMOS process and the amplifier circuitry uses CMOS
transistors for amplifier and output transistor circuitry. While
providing excellent accuracy, there are limitations in output
noise level and load regulation due to the MOS device
characteristics. These limitations are addressed with circuit
techniques discussed in other sections.
FGA Technology
The ISL21009 voltage reference uses floating gate
technology to create references with very low drift and supply
current. Essentially the charge stored on a floating gate cell is
set precisely in manufacturing. The reference voltage output
itself is a buffered version of the floating gate voltage. The
resulting reference device has excellent characteristics, which
are unique in the industry: very low temperature drift, high
initial accuracy, and almost zero supply current. Also, the
reference voltage itself is not limited by voltage bandgaps or
zener settings, so a wide range of reference voltages can be
programmed (standard voltage settings are provided, but
customer-specific voltages are available).
Micropower Operation
The ISL21009 consumes extremely low supply current due
to the proprietary FGA technology. Low noise performance is
achieved using optimized biasing techniques. Supply current
is typically 95µA and noise is 4.5µVP-P benefitting precision,
low noise portable applications such as handheld meters
and instruments.
FN6327.6
September 12, 2007
15
ISL21009
Data Converters in particular can utilize the ISL21009 as an
Turn-On Time
external voltage reference. Low power DAC and ADC
circuits will realize maximum resolution with lowest noise.
The ISL21009 devices have low supply current and thus the
time to bias up internal circuitry to final values will be longer
than with higher power references. Normal turn-on time is
typically 100µs. This is shown in Figure 25. Circuit design
must take this into account when looking at power-up delays
or sequencing.
Board Mounting Considerations
For applications requiring the highest accuracy, board
mounting location should be reviewed. The device uses a
plastic SOIC package, which will subject the die to mild
stresses when the PC board is heated and cooled, slightly
changing the shape. Placing the device in areas subject to
slight twisting can cause degradation of the accuracy of the
reference voltage due to these die stresses. It is normally
best to place the device near the edge of a board, or the
shortest side, as the axis of bending is most limited at that
location. Mounting the device in a cutout also minimizes flex.
Obviously mounting the device on flexprint or extremely thin
PC material will likewise cause loss of reference accuracy.
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are
governed by the method of measurement. The overwhelming
standard for specifying the temperature drift of a reference is to
measure the reference voltage at two temperatures, take the
total variation, (VHIGH – VLOW), and divide by the temperature
extremes of measurement (THIGH – TLOW). The result is
divided by the nominal reference voltage (at T = +25°C) and
multiplied by 106 to yield ppm/°C. This is the “Box” method for
specifying temperature coefficient.
Noise Performance and Reduction
Output Voltage Adjustment
The output noise voltage in a 0.1Hz to 10Hz bandwidth is
typically 4.5µVP-P. The noise measurement is made with a
bandpass filter made of a 1-pole high-pass filter with a corner
frequency at 0.1Hz and a 2-pole low-pass filter with a corner
frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth.
Noise in the 10kHz to 1MHz bandwidth is approximately
40µVP-P with no capacitance on the output. This noise
measurement is made with a 2 decade bandpass filter made
of a 1-pole high-pass filter with a corner frequency at 1/10 of
the center frequency and 1-pole low-pass filter with a corner
frequency at 10x the center frequency. Load capacitance up
to 1000pF can be added but will result in only marginal
improvements in output noise and transient response. The
output stage of the ISL21009 is not designed to drive heavily
capactive loads, so for load capacitances above 0.001µF, the
noise reduction network shown in Figure 58 is recommended.
This network reduces noise significantly over the full
bandwidth. Noise is reduced to less than 20µVP-P from 1Hz to
1MHz using this network with a 0.01µF capacitor and a 2kΩ
resistor in series with a 10µF capacitor. Also, transient
response is improved with higher value output capacitor. The
0.01µF value can be increased for better load transient
response with little sacrifice in output stability.
The output voltage can be adjusted up or down by 2.5% by
placing a potentiometer from VOUT to GND and connecting the
wiper to the TRIM pin. The TRIM input is high impedance so no
series resistance is needed. The resistor in the potentiometer
should be a low tempco (<50ppm/°C) and the resulting voltage
divider should have very low tempco <5ppm/°C. A digital
potentiometer such as the ISL95810 provides a low tempco
resistance and excellent resistor and tempco matching for trim
applications.
.
V
= 5.0V
IN
V
10µF
IN
V
O
0.1µF
ISL21009-25
GND
2kΩ
0.01µF
10µF
FIGURE 58. HANDLING HIGH LOAD CAPACITANCE
FN6327.6
September 12, 2007
16
ISL21009
Typical Application Circuits
V
= +5.0V
IN
R = 200Ω
2N2905
V
IN
V
2.5V/50mA
OUT
ISL21009
= 2.50V
V
OUT
0.001µF
GND
FIGURE 59. PRECISION 2.5V, 50mA REFERENCE
+3.5V TO 16.5V
0.1µF
10µF
V
IN
V
OUT
ISL21009-25
= 2.50V
V
OUT
GND
0.001µF
V
R
CC
V
H
OUT
X9119
(UNBUFFERED)
+
–
SDA
SCL
2-WIRE BUS
EL8178
V
OUT
(BUFFERED)
V
R
L
SS
FIGURE 60. 2.5V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
FN6327.6
September 12, 2007
17
ISL21009
Typical Application Circuits (Continued)
+3.5V TO 16.5V
0.1µF
10µF
V
IN
EL8178
+
–
V
SENSE
OUT
V
OUT
ISL21009-25
GND
LOAD
FIGURE 61. KELVIN SENSED LOAD
10µF
+3.5V TO 16.5V
0.1µF
V
2.5V ±2.5%
IN
V
OUT
ISL21009-25
TRIM
GND
R
V
H
CC
SDA
SCL
2
I C BUS
ISL95810
R
L
V
SS
FIGURE 62. OUTPUT ADJUSTMENT USING THE TRIM PIN
FN6327.6
September 12, 2007
18
ISL21009
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
a
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6327.6
September 12, 2007
19
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