ISL22319_技术文档

ISL22319

®

Single Digitally Controlled Potentiometer (XDCP™)

Data Sheet

July 3, 2006

FN6310.0

2

Low Noise, Low Power, I C^®Bus,

128 Taps, Wiper Only

Features

• 128 resistor taps

The ISL22319 integrates a single digitally controlled

potentiometer (DCP) and non-volatile memory on a

monolithic CMOS integrated circuit.

2

• I C serial interface

- Two address pins, up to four devices/bus

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ 3.3V

• Shutdown mode

The digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

2

I C bus interface. The potentiometer has an associated

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

• 50kΩ or 10kΩ total resistance

• High reliability

volatile Wiper Register (WR) and a non-volatile Initial Value

Register (IVR) that can be directly written to and read by the

user. The contents of the WR controls the position of the

wiper. At power up the device recalls the content of the

DCP’s IVR to the WR.

- Endurance: 1,000,000 data changes per bit per register

The DCP can be used as a voltage divider in a wide variety

of applications including control, parameter adjustments, AC

measurement and signal processing.

- Register data retention: 50 years @ T ≤ 55 °C

• 8 Ld MSOP

• Pb-free plus anneal product (RoHS compliant)

Pinout

ISL22319

(8 LD MSOP)

TOP VIEW

SCL

SDA

A1

VCC

RW

1

2

3

4

8

7

6

SHDN

GND

5

A0

Ordering Information

RESISTANCE OPTION

TEMP. RANGE

PART NUMBER

ISL22319UFU8Z

PART MARKING

319UZ

(kΩ)

(°C)

PACKAGE

8 Ld MSOP

PKG. DWG. #

50

10

-40 to +125

M8.118

(Notes 1, 2)

(Pb-Free)

ISL22319WFU8Z

(Notes 1, 2)

319WZ

-40 to +125

8 Ld MSOP

(Pb-Free)

M8.118

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL22319

Block Diagram

V

CC

SCL

SDA

A0

POWER-UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

2

I C

INTERFACE

A1

RW

WR

NON-VOLATILE

REGISTERS

SHDN

GND

Pin Descriptions

MSOP PIN

SYMBOL

DESCRIPTION

2

1

2

3

4

5

6

7

8

SCL

SDA

A1

Open drain I C interface clock input

2

Open drain serial data I/O for the I C interface

2

Device address input for the I C interface

2

A0

Device address input for the I C interface

GND

SHDN

RW

Device ground pin

Shutdown active low input

“Wiper” terminal of DCP

Power supply pin

V

CC

FN6310.0

July 3, 2006

2

ISL22319

Absolute Maximum Ratings

Thermal Information

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

Thermal Resistance (Typical, Note 3)

θ

(°C/W)

130

JA

10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package). . . . . . . . . .150°C

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

Voltage at any DCP Pin with

respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

Recommended Operating Conditions

CC

Ambient Temperature (Extended Industrial) . . . . . . .-40°C to 125°C

V

Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

CC

W

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA

Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @+125°C

ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV

(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using

a max negative pulse of -1V for all pins.

Analog Specifications

Over recommended operating conditions unless otherwise stated.

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(NOTE 5)

MAX

UNIT

kΩ

R

End-to-End Resistance

W option

U option

10

50

TOTAL

kΩ

End-to-End Resistance Tolerance

End-to-End Temperature Coefficient

-20

+20

%

W option

U option

±50

±80

70

25

2

ppm/°C

(Note 14)

ppm/°C

(Note 14)

R

Wiper Resistance

Wiper Capacitance

Leakage on RW Pin

V

= 3.3V @ 25°C,

Ω

W

CC

wiper current = V /R

(Note 14)

CC TOTAL

C

pF

µA

W

(Note 14)

I

Voltage at pin from GND to V

4

LkgRW

CC

VOLTAGE DIVIDER MODE ( measured at R , unloaded)

W

INL

(Note 10)

Integral Non-linearity

Differential Non-linearity

Zero-scale Error

-1

1

LSB

(Note 6)

DNL

(Note 9)

Monotonic over all tap positions

-0.5

0.5

LSB

(Note 6)

ZSerror

(Note 7)

W option

0

1

0.5

-1

5

2

0

LSB

(Note 6)

U option

FSerror

(Note 8)

Full-scale Error

W option

-5

-2

LSB

(Note 6)

U option

-1

TC

Ratiometric Temperature Coefficient

DCP register set to 40 hex

±4

ppm/°C

V

(Note 11, 14)

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ISL22319

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(NOTE 5)

MAX

UNIT

2

I

V

Supply Current (volatile

10k DCP, f

= 400kHz; (for I C active,

1

mA

CC1

CC

SCL

read and write states)

write/read)

2

V

Supply Current (volatile

50k DCP, f = 400kHz; (for I C active,

0.5

3.2

2.7

850

550

160

100

3

mA

µA

µs

CC

write/read, non-volatile read)

SCL

read and write states)

2

I

V

Supply Current ( non-volatile

10k DCP, f = 400kHz; (for I C active,

CC2

CC

write/read)

SCL

read and write states)

2

V

Supply Current (non-volatile

50k DCP, f = 400kHz; (for I C active,

CC

write/read)

SCL

read and write states)

2

I

V Current (standby)

V

= +5.5V , 10k DCP, I C interface in

SB

CC

standby state

2

V

= +3.6V, 10k DCP, I C interface in

CC

standby state

2

V

= +5.5V, 50k DCP, I C interface in

CC

standby state

2

V

= +3.6V, 50k DCP, I C interface in

CC

standby state

2

I

V

Current (shutdown)

V

= +5.5V @ +85°C, I C interface in

SD

CC

standby state

2

V

= +5.5V @ +125°C, I C interface in

5

CC

standby state

2

V

= +3.6V @ +85°C, I C interface in

2

CC

standby state

2

V

= +3.6V @ +125°C, I C interface in

4

CC

standby state

I

Leakage Current, at Pins A0, A1,

SHDN, SDA, and SCL

Voltage at pin from GND to V

-1

1

LkgDig

CC

t

DCP Wiper Response Time

SCL falling edge of last bit of DCP data byte

to wiper new position

1.5

DCP

(Note 14)

t

DCP Recall Time from Shutdown

(Note 14) Mode

From rising edge of SHDN signal to wiper

stored position and RH connection

µs

ShdnRec

SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

µs

Vpor

Ramp

Power-on Recall Voltage

Ramp Rate

Minimum V

at which memory recall occurs

2.0

0.2

2.6

3

V

CC

V

V/ms

ms

CC

t

Power-up Delay

V

above Vpor, to DCP Initial Value

CC

D

2

Register recall completed, and I C Interface

in standby state

EEPROM SPECIFICATION

EEPROM Endurance

1,000,000

50

Cycles

Years

ms

EEPROM Retention

Temperature T ≤ 55 °C

t

Non-volatile Write Cycle Time

12

20

WC

(Note 15)

SERIAL INTERFACE SPECS

V

A1, A0, SHDN, SDA, and SCL Input

Buffer LOW Voltage

-0.3

0.3*V

V

IL

CC

V

A1, A0, SHDN, SDA, and SCL Input

Buffer HIGH Voltage

0.7*V

V

+0.3

CC

IH

CC

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ISL22319

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(NOTE 5)

MAX

UNIT

Hysteresis SDA and SCL Input Buffer Hysteresis

0.05*

V

CC

0

V

SDA Output Buffer LOW Voltage,

Sinking 4mA

0.4

10

V

OL

Cpin

A1, A0, SHDN, SDA, and SCL Pin

Capacitance

pF

f

SCL Frequency

400

50

kHz

ns

SCL

t

Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is

and SCL Inputs suppressed

sp

t

SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V , until

CC

900

ns

AA

Valid

SDA exits the 30% to 70% of V

window

CC

t

Time the Bus Must be Free before the SDA crossing 70% of V

during a STOP

1300

BUF

CC

condition, to SDA crossing 70% of V

Start of a New Transmission

CC

during the following START condition

t

Clock LOW Time

Measured at the 30% of V

Measured at the 70% of V

crossing

1300

600

ns

LOW

CC

t

Clock HIGH Time

HIGH

t

START Condition Setup Time

SCL rising edge to SDA falling edge; both

crossing 70% of V

600

SU:STA

HD:STA

SU:DAT

CC

From SDA falling edge crossing 30% of V

t

START Condition Hold Time

Input Data Setup Time

600

100

ns

CC

to SCL falling edge crossing 70% of V

CC

From SDA exiting the 30% to 70% of V

CC

window, to SCL rising edge crossing 30% of

V

CC

t

Input Data Hold Time

From SCL rising edge crossing 70% of V

0

ns

HD:DAT

CC

to SDA entering the 30% to 70% of V

window

CC

t

STOP Condition Setup Time

From SCL rising edge crossing 70% of V

to SDA rising edge crossing 30% of V

,

600

1300

0

ns

SU:STO

CC

t

STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;

HD:STO

or Volatile Only Write

Output Data Hold Time

both crossing 70% of V

CC

t

From SCL falling edge crossing 30% of V

,

DH

CC

until SDA enters the 30% to 70% of V

window

t

SDA and SCL Rise Time

From 30% to 70% of V

20 +

0.1 * Cb

250

400

ns

R

CC

t

SDA and SCL Fall Time

From 70% to 30% of V

20 +

0.1 * Cb

F

CC

Cb

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

Maximum is determined by t and t

10

1

pF

Rpu

SDA and SCL Bus Pull-up Resistor

Off-chip

kΩ

R

F

For Cb = 400pF, max is about 2~2.5kΩ

For Cb = 40pF, max is about 15~20kΩ

t

A1 and A0 Setup Time

A1 and A0 Hold Time

Before START condition

After STOP condition

600

ns

SU:A

t

HD:A

NOTES:

5. Typical values are for T = 25°C and 3.3V supply voltage.

A

6. LSB: [V(R

)

– V(R ) ]/127. V(R

)

and V(R ) are V(R ) for the DCP register set to 7F hex and 00 hex respectively. LSB is the

W 0

W 127

W 0 W 127

W

incremental voltage when changing from one tap to an adjacent tap.

7. ZS error = V(RW) /LSB.

0

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July 3, 2006

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ISL22319

8. FS error = [V(RW)

127

– V ]/LSB.

CC

9. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

i

10. INL = [V(RW) – (i • LSB) – V(RW) ]/LSB for i = 1 to 127

i

0

Max(V(RW) ) – Min(V(RW) )

6

10

i

11.

for i = 16 to 127 decimal, T = -40°C to 125°C. Max( ) is the maximum value of the wiper

[Max(V(RW) ) + Min(V(RW) )] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

--------------------------------------------------------------------------------------------- ----------------

TC

=

×

V

i

12. MI = |RW

– RW |/127. MI is a minimum increment. RW

and RW are the measured resistances for the DCP register set to 7F hex and

127 0

127

0

00 hex respectively.

13. Roffset = RW /MI, when measuring between RW and RL.

0

Roffset = RW

/MI, when measuring between RW and RH.

127

14. This parameter is not 100% tested.

15. t is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-

WC

volatile write cycle.

SDA vs SCL Timing

t

sp

t

R

t

F

HIGH

LOW

HD:STO

SCL

t

SU:DAT

t

SU:STO

SU:STA

HD:DAT

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

AA

DH

SDA

(OUTPUT TIMING)

A0 and A1 Pin Timing

STOP

START

SCL

CLK 1

SDA

t

HD:A

SU:A

A0, A1

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6

ISL22319

Typical Performance Curves

VCC

1.4

1.2

1

100

Vcc = 3.3V, T = 125ºC

90

_T=125ºC

80

70

60

50

40

30

VCC

0.8

0.6

0.4

0.2

0

Vcc = 3.3V, T = -40ºC

_T=25ºC

Vcc = 3.3V, T = 20ºC

20

10

0

2.7

3.2

3.7

4.2

4.7

5.2

0

20

40

60

80

100

120

Vcc, V

TAP POSITION (DECIMAL)

FIGURE 2. STANDBY I

vs V

CC

FIGURE 1. WIPER RESISTANCE vs TAP POSITION

[ I(RW) = V /R ] FOR 10kΩ (W)

CC

CC TOTAL

0.2

0.1

0

0.2

0.1

0

T = 25ºC

Vcc = 2.7V

T = 25ºC

Vcc =2.7V

-0.1

-0.2

-0.1

-0.2

Vcc = 5.5V

20 40

0

20

40

60

80

100

120

0

60

80

100

120

TAP POSITION (DECIMAL)

TAP POSITION(DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

0.00

1.30

10k

1.10

0.90

0.70

-0.30

Vcc = 2.7V

50k

10k

Vcc = 5.5V

-0.60

-0.90

-1.20

-1.50

Vcc =2.7V

0.50

0.30

Vcc =5.5V

0.10

50k

-0.10

-0.30

-40 -20

0

20

40

60

80

100 120

-40

-20

0

20

40

60

80

100 120

TEMPERATURE(ºC)

TEMPERATURE (ºC)

FIGURE 5. ZSerror vs TEMPERATURE

FIGURE 6. FSerror vs TEMPERATURE

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ISL22319

Typical Performance Curves (Continued)

1.00

105

90

75

60

45

30

15

0

50k

Vcc = 2.7V

10k

0.50

0.00

-0.50

50k

Vcc = 5.5V

10k

-1.00

-40

-20

0

20

40

60

80

100 120

16

36

56

76

96

TAP POSITION (DECIMAL)

TEMPERATURE(ºC)

FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm

FIGURE 7. END TO END R

% CHANGE vs

TOTAL

TEMPERATURE

FIGURE 10. LARGE SIGNAL SETTLING TIME

FIGURE 9. MIDSCALE GLITCH, CODE 3Fh TO 40h

Pin Description

Potentiometers Pins

RW

RW is the wiper terminal and is equivalent to the movable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the WR register.

SHDN

FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE

The active low SHDN pin forces the resistor to end-to-end

open circuit condition and shorts RWi to GND. When SHDN

is returned to logic high, the previous latch settings put RW

at the same resistance setting prior to shutdown. This pin is

Bus Interface Pins

Serial Data Input/Output (SDA)

2

logically OR’d with SHDN bit in ACR register. I C interface is

2

The SDA is a bidirectional serial data input/output pin for I C

interface. It receives device address, operation code, wiper

still available in shutdown mode and all registers are

accessible. This pin must remain HIGH for normal operation.

2

address and data from an I C external master device at the

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ISL22319

rising edge of the serial clock SCL, and it shifts out data after

each falling edge of the serial clock.

reading, the WR will be reload with the value stored in a non-

volatile Initial Value Register (IVR).

SDA requires an external pull-up resistor, since it is an open

drain input/output.

The WR and IVR can be read or written to directly using the

I C serial interface as described in the following sections.

2

Serial Clock (SCL)

Memory Description

The ISL22319 contains one non-volatile 8-bit register, known as

the Initial Value Register (IVR), and two volatile 8-bit registers,

Wiper Register (WR) and Access Control Register (ACR). The

memory map of ISL22319 is on Table 1. The non-volatile

register (IVR) at address 0, contains initial wiper position and

volatile register (WR) contains current wiper position.

This is the serial clock input of the I2C serial interface. SCL

requires an external pull-up resistor, since it is an open drain

input.

Device Address (A1, A0)

The address inputs are used to set the least significant 2 bits

2

of the 7-bit I C interface slave address. A match in the slave

TABLE 1. MEMORY MAP

address serial data stream must match with the Address

input pins in order to initiate communication with the

ISL22319. A maximum of 4 ISL22319 devices may occupy

ADDRESS

NON-VOLATILE

VOLATILE

2

1

0

—

ACR

2

the I C serial bus.

Reserved

Principles of Operation

IVR

WR

The ISL22319 is an integrated circuit incorporating one DCP

with its associated registers, non-volatile memory and an I C

The non-volatile IVR and volatile WR registers are

accessible with the same address.

2

serial interface providing direct communication between a

host and the potentiometer and memory. The resistor array

is comprised of individual resistors connected in series. At

either end of the array and between each resistor is an

electronic switch that transfers the potential at that point to

the wiper.

The Access Control Register (ACR) contains information

and control bits described below in Table 2.

The VOL bit (ACR[7]) determines whether the access is to

wiper registers WR or initial value registers IVR.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions.

VOL

SHDN

WIP

0

If VOL bit is 0, the non-volatile IVR register is accessible. If

VOL bit is 1, only the volatile WR is accessible. Note, value

is written to IVR register also is written to the WR. The

default value of this bit is 0.

When the device is powered down, the last value stored in

IVR will be maintained in the non-volatile memory. When

power is restored, the contents of the IVR is recalled and

loaded into the WR to set the wiper to the initial value.

The SHDN bit (ACR[6]) disables or enables Shutdown mode.

This bit is logically OR ‘d with SHDN pin. When this bit is 0,

DCP is in Shutdown mode. Default value of SHDN bit is 1.

DCP Description

The DCP is implemented with a combination of resistor

elements and CMOS switches. The physical ends of each

DCP are equivalent to the fixed terminals of a mechanical

The WIP bit (ACR[5]) is read only bit. It indicates that

nonHvolatile write operation is in progress. It is impossible to

write to the WR or ACR while WIP bit is 1.

potentiometer and internally connected to V

and GND.

CC

The RW pin of the DCP is connected to intermediate nodes,

and is equivalent to the wiper terminal of a mechanical

potentiometer. The position of the wiper terminal within the

DCP is controlled by an 7-bit volatile Wiper Register (WR).

When the WR of a DCP contains all zeroes (WR[6:0]= 00h),

its wiper terminal (RW) is closest to GND. When the WR

register of a DCP contains all ones (WR[6:0]= 7Fh), its wiper

terminal (RW) is closest to V . As the value of the WR

increases from all zeroes (0) to all ones (127 decimal), the

wiper moves monotonically from the position closest to GND

2

I C Serial Interface

2

The ISL22319 supports an I C bidirectional bus oriented

protocol. The protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is a master and

the device being controlled is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, the ISL22319

operates as a slave device in all applications.

CC

to the closest to V

.

CC

2

All communication over the I C interface is conducted by

While the ISL22319 is being powered up, the WR is reset to

40h (64 decimal), which locates RW roughly at the center

sending the MSB of each byte of data first.

between V

and GND. After the power supply voltage

CC

becomes large enough for reliable non-volatile memory

FN6310.0

July 3, 2006

9

ISL22319

either master or slave, releases the SDA bus after

Protocol Conventions

transmitting eight bits. During the ninth clock cycle, the

receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (See Figure 13).

Data states on the SDA line must change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (See

Figure 12). On power-up of the ISL22319 the SDA pin is in

the input mode.

The ISL22319 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL22319 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation

2

All I C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL22319 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (See

Figure 12). A START condition is ignored during the

powerHup of the device.

A valid Identification Byte contains 01010 as the five MSBs, and

the following two bits matching the logic values present at pins

A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a

Read operation, and “0” for a Write operation (See Table 3).

2

All I C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (See Figure 12). A STOP condition at the end

of a read operation, or at the end of a write operation places

the device in its standby mode.

TABLE 3. IDENTIFICATION BYTE FORMAT

Logic values at pins A1 and A0 respectively

0

1

0

1

0

A1

A0

R/W

An ACK, Acknowledge, is a software convention used to

indicate a successful data transfer. The transmitting device,

(MSB)

(LSB)

SCL

SDA

START

DATA

STOP

STABLE

CHANGE STABLE

FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS

SCL FROM

MASTER

1

8

9

SDA OUTPUT FROM

TRANSMITTER

HIGH IMPEDANCE

SDA OUTPUT FROM

RECEIVER

START

ACK

FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER

FN6310.0

July 3, 2006

10

ISL22319

WRITE

S

T

A

R

T

SIGNALS FROM

THE MASTER

S

T

O

P

IDENTIFICATION

ADDRESS

BYTE

DATA

BYTE

SIGNAL AT SDA

0 1 0 1 0 A1A0 0

0 0 0 0

SIGNALS FROM

THE SLAVE

A

C

K

A

C

K

A

C

K

FIGURE 14. BYTE WRITE SEQUENCE

S

T

A

R

T

S

T

A

R

T

SIGNALS

FROM THE

MASTER

S

T

O

P

A

C

K

A

C

K

IDENTIFICATION

BYTE WITH

R/W=0

IDENTIFICATION

BYTE WITH

R/W=1

A

C

K

ADDRESS

BYTE

SIGNAL AT SDA

1

0 A1A0 1

0 1 0 1 0A1A0 0

0 0 0 0

0 1 0

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIRST READ

DATA BYTE

LAST READ

DATA BYTE

FIGURE 15. READ SEQUENCE

Write Operation

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte,

and a STOP condition. After each of the three bytes, the

ISL22319 responds with an ACK. At this time, the device

enters its standby state (See Figure 14).

The non-volatile write cycle starts after STOP condition is

determined and it requires up to 20ms delay for the next

non-volatile write.

Read Operation

A Read operation consists of a three byte instruction

followed by one or more Data Bytes (See Figure 15). The

master initiates the operation issuing the following

sequence: a START, the Identification byte with the R/W bit

set to “0”, an Address Byte, a second START, and a second

Identification byte with the R/W bit set to “1”. After each of

the three bytes, the ISL22319 responds with an ACK. Then

the ISL22319 transmits Data Bytes as long as the master

responds with an ACK during the SCL cycle following the

eighth bit of each byte. The master terminates the read

operation (issuing a ACK and STOP condition) following the

last bit of the last Data Byte (See Figure 15).

In order to read back the non-volatile IVR, it is recommended

that the application reads the ACR first to verify the WIP bit

is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat

its reading sequence again.

FN6310.0

July 3, 2006

11

ISL22319

V

CC

V

CC CC

0.1µF

V

CC

Rpu Rpu

SHDN

0.1µF

RW

V

SCL

SDA

A0

OUT

A1

R2

ISL22319

R1

FIGURE 16. TYPICAL APPLICATION DIAGRAM FOR IMPLEMENTING ADJUSTABLE VOLTAGE REFERANCE

Applications Information

The typical application diagram is shown on Figure 16. For

proper operation adding 0.1µF decoupling ceramic capacitor

to V

is recommended. The capacitor value may vary

CC

based on expected noise frequency of the design.

FN6310.0

July 3, 2006

12

ISL22319

Mini Small Outline Plastic Packages (MSOP)

N

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES

MILLIMETERS

E1

E

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.25

0.09

2.95

MAX

1.10

0.15

0.95

0.36

0.20

3.05

NOTES

A

A1

A2

b

0.037

0.002

0.030

0.010

0.004

0.116

0.043

0.006

0.037

0.014

0.008

0.120

-

-B-

0.20 (0.008)

INDEX

AREA

1 2

A

B

C

-

TOP VIEW

4X θ

9

0.25

(0.010)

R1

c

-

R

GAUGE

PLANE

D

3

E1

e

4

SEATING

PLANE

L

0.026 BSC

0.65 BSC

-

-C-

4X θ

L1

A

A2

E

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

-

L

6

SEATING

PLANE

L1

N

0.037 REF

0.95 REF

-

0.10 (0.004)

-A-

C

b

8

7

-H-

A1

e

R

0.003

-

0.07

-

D

0.20 (0.008)

C

R1

0

-

o

5

15

5

15

-

a

SIDE VIEW

C

L

o

0

6

0

6

-

α

E

1

-B-

Rev. 2 01/03

0.20 (0.008)

C

D

END VIEW

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

to be determined at Datum plane

-A -

10. Datums

and

.

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6310.0

July 3, 2006

13


型号：	ISL22319
厂家：	Intersil
描述：	Low Noise, Low Power, I2C Bus, 128 Taps, Wiper Only 低噪声，低功耗， I2C总线， 128个抽头，抽头只
文件：	总13页 (文件大小：384K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL22319 [INTERSIL]

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