ISL23315UFRUZ-TK_技术文档

Single, Low Voltage Digitally Controlled Potentiometer

(XDCP™)

ISL23315

Features

2

• 256 resistor taps

The ISL23315 is a volatile, low voltage, low noise, low power, I C

™

Bus , 256 Taps, single digitally controlled potentiometer (DCP),

2

• I C serial interface

which integrates DCP core, wiper switches and control logic on

a monolithic CMOS integrated circuit.

- No additional level translator for low bus supply

- Two address pins allow up to four devices per bus

The digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

• Wiper resistance: 70Ω typical @ V = 3.3V

CC

• Shutdown Mode - forces the DCP into an end-to-end open

2

I C bus interface. The potentiometer has an associated

circuit and R is shorted to R internally

W

L

volatile Wiper Register (WR) that can be directly written to and

read by the user. The contents of the WR controls the position

of the wiper. When powered on, the ISL23315’s wiper will

always commence at mid-scale (128 tap position).

• Power-on preset to mid-scale (128 tap position)

• Standby current <2.5µA max

• Shutdown current <2µA max

• Power supply

The low voltage, low power consumption, and small package

of the ISL23315 make it an ideal choice for use in battery

operated equipment. In addition, the ISL23315 has a V

- V = 1.7V to 5.5V analog power supply

CC

LOGIC

pin allowing down to 1.2V bus operation, independent from the

value. This allows for low logic levels to be connected

2

- V

LOGIC

= 1.2V to 5.5V I C bus/logic power supply

V

CC

• DCP terminal voltage from 0V to V

CC

directly to the ISL23315 without passing through a voltage

level shifter.

• 10kΩ, 50kΩ or 100kΩ total resistance

• Extended industrial temperature range: -40°C to +125°C

• 10 Ld MSOP or 10 Ld µTQFN packages

• Pb-free (RoHS compliant)

The DCP can be used as a three-terminal potentiometer or as a

two-terminal variable resistor in a wide variety of applications

including control, parameter adjustments, and signal processing.

Applications

• Power supply margining

• RF power amplifier bias compensation

• LCD bias compensation

• Laser diode bias compensation

10000

8000

6000

4000

2000

0

V_REF

-

V_{REF_M}

ISL23315

+

ISL28114

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 2. V

ADJUSTMENT

REF

FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP

POSITION, 10k DCP

December 15, 2010

FN7778.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners

1

ISL23315

Block Diagram

V

CC

LOGIC

R

SCL

SDA

A1

H

POWER-UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

I/O

BLOCK

LEVEL

SHIFTER

WR

VOLATILE

REGISTER

AND

A0

WIPER

CONTROL

CIRCUITRY

R

L

R

W

GND

Pin Configurations

Pin Descriptions

MSOP

µTQFN

SYMBOL

DESCRIPTION

ISL23315

(10 LD MSOP)

TOP VIEW

2

1

10

V

I C bus /logic supply. Range 1.2V to

5.5V

LOGIC

10

9

GND

V

1

2

3

4

5

2

3

1

2

SCL

SDA

Logic Pin - Serial bus clock input

LOGIC

SCL

V

CC

Logic Pin - Serial bus data

input/open drain output

8

RH

RW

RL

SDA

A0

7

4

5

3

4

A0

A1

Logic Pin - Hardwire slave address

2

A1

6

pin for I C serial bus.

Range: V

or GND

LOGIC

ISL23315

Logic Pin - Hardwire slave address

2

(10 LD µTQFN)

TOP VIEW

pin for I C serial bus.

Range: V

or GND

LOGIC

6

7

8

9

5

6

7

8

RL

RW

RH

DCP “low” terminal

DCP wiper terminal

DCP “high” terminal

GND

SCL

1

2

3

4

9

8

7

6

V

Analog power supply.

Range 1.7V to 5.5V

CC

V

SDA

A0

CC

RH

10

9

GND

Ground pin

A1

RW

FN7778.0

December 15, 2010

2

ISL23315

Ordering Information

RESISTANCE

PART NUMBER

OPTION

(kΩ)

TEMP RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

(Note 5)

PART MARKING

ISL23315TFUZ (Notes 1, 3)

ISL23315UFUZ (Notes 1, 3)

ISL23315WFUZ (Notes 1, 3)

3315T

3315U

3315W

100

50

-40 to +125

10 Ld MSOP

M10.118

10 Ld MSOP

M10.118

10

10 Ld MSOP

M10.118

ISL23315TFRUZ-T7A (Notes 2, 4) HB

ISL23315TFRUZ-TK (Notes 2, 4) HB

ISL23315UFRUZ-T7A (Notes 2, 4) HA

ISL23315UFRUZ-TK (Notes 2, 4) HA

ISL23315WFRUZ-T7A (Notes 2, 4) GZ

ISL23315WFRUZ-TK (Notes 2, 4) GZ

NOTES:

100

50

10 Ld 2.1x1.6 µTQFN

L10.2.1x1.6A

50

10

1. Add “-T*” suffix for Tape and Reel option. Please refer to TB347 for details on reel specifications.

2. Please refer to TB347 for details on reel specifications.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin

plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4

termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020

5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23315. For more information on MSL please see techbrief TB363.

FN7778.0

December 15, 2010

3

ISL23315

Absolute Maximum Ratings

Thermal Information

Supply Voltage Range

Thermal Resistance (Typical)

10 Ld MSOP Package (Notes 6, 7). . . . . . .

10 Ld µTQFN Package (Notes 6, 7) . . . . . .

θ

_JA(°C/W)

170

θ

_JC(°C/W)

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

70

90

CC

LOGIC

145

Voltage on Any DCP Terminal Pin. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Wiper current I (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

ESD Rating

Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .6.5kV

CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V

Latch Up

Recommended Operating Conditions

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

(Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125°C

V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V

CC

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V

LOGIC

DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to V

CC

Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

6. θ_JAis measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

7. For θ , the “case temp” location is the center top of the package.

JC

Analog Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise

LOGIC

CC

stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

to R resistance

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

kΩ

R

W option

U option

T option

10

50

TOTAL

H

L

kΩ

100

±2

kΩ

R

to R resistance tolerance

-20

+20

%

H

L

End-to-End Temperature Coefficient

W option

U option

T option

175

85

ppm/°C

V

70

V

, V

RH RL

DCP terminal voltage

Wiper resistance

V

or V to GND

RL

0

V

RH

CC

R

- floating, V = 0V, force I current

RL

70

200

Ω

W

H

W

to the wiper,

= (V - V )/R

TOTAL,

I

W

CC RL

V

= 2.7V to 5.5V

CC

V

= 1.7V

580

22/22/32

< 0.1

120

Ω

pF

CC

C /C /C

W

Terminal capacitance

Leakage on DCP pins

Resistor noise density

See “DCP Macro Model” on page 8

Voltage at pin from GND to V

H

L

I

-0.4

0.4

µA

LkgDCP

Noise

CC

Wiper at middle point, W option

Wiper at middle point, U option

Wiper at middle point, T option

nV Hz

dB

190

220

Feed Thru Digital feed-through from bus to wiper Wiper at middle point

-65

PSRR

Power Supply Reject Ratio

Wiper output change if V change

CC

-75

dB

±10%; wiper at middle point

FN7778.0

December 15, 2010

4

ISL23315

Analog Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise

LOGIC

CC

stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

VOLTAGE DIVIDER MODE (0V @ RL; V @ RH; measured at RW, unloaded)

CC

Integral non-linearity, guaranteed

(Note 13) monotonic

INL

W option

U, T option

W option

U, T option

W option

U, T option

W option

U, T option

-1.0

-0.5

-1

±0.5

±0.15

±0.4

±0.1

-2

+1.0

+0.5

+1

LSB

(Note 9)

LSB

(Note 9)

DNL

Differential non-linearity, guaranteed

LSB

(Note 9)

(Note 12) monotonic

-0.4

-3.5

-2

+0.4

0

LSB

(Note 9)

FSerror

Full-scale error

LSB

(Note 9)

(Note 11)

-0.5

2

0

LSB

(Note 9)

ZSerror

Zero-scale error

0

3.5

2

LSB

(Note 9)

(Note 10)

0

0.4

LSB

(Note 9)

TC

Ratiometric temperature coefficient

W option, Wiper Register set to 80 hex

U option, Wiper Register set to 80 hex

T option, Wiper Register set to 80 hex

From code 0 to FF hex

8

4

ppm/°C

ns

V

(Notes 14)

2.3

Large Signal Wiper Settling Time

-3dB cutoff frequency

300

1200

250

120

f

Wiper at middle point W option

Wiper at middle point U option

Wiper at middle point T option

kHz

cutoff

kHz

RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)

R

Integral non-linearity, Guaranteed

W option; V = 2.7V to 5.5V

CC

-2.0

-1.0

-1

±1

10.5

±0.3

2.1

+2.0

+1.0

+1

MI

(Note 15)

INL

(Note 18) monotonic

W option; V = 1.7V

CC

MI

(Note 15)

U, T option; V = 2.7V to 5.5V

CC

MI

(Note 15)

U, T option; V = 1.7V

CC

MI

(Note 15)

R

Differential non-linearity, Guaranteed

W option; V = 2.7V to 5.5V

CC

±0.4

±0.6

±0.15

±0.35

MI

(Note 15)

DNL

(Note 17) monotonic

W option; V = 1.7V

CC

MI

(Note 15)

U, T option; V = 2.7V to 5.5V

CC

-0.5

+0.5

MI

(Note 15)

U, T option; V = 1.7V

CC

MI

(Note 15)

FN7778.0

December 15, 2010

5

ISL23315

Analog Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise

LOGIC

CC

stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

W option; V = 2.7V to 5.5V

(Note 20)

(Note 8)

(Note 20)

UNITS

R

Offset, wiper at 0 position

0

3

5.5

2

MI

(Note 15)

offset

CC

(Note 16)

W option; V = 1.7V

CC

6.3

0.5

1.1

220

100

75

MI

(Note 15)

U, T option; V = 2.7V to 5.5V

CC

MI

(Note 15)

U, T option; V = 1.7V

CC

MI

(Note 15)

TCR

(Note 19)

Resistance temperature coefficient

W option; Wiper register set between

32 hex and FF hex

ppm/°C

U option; Wiper register set between 32

hex and FF hex

T option; Wiper register set between 32

hex and FF hex

Operating Specifications V = 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise

LOGIC

CC

stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

µA

I

V

supply current (write/read)

V

= 5.5V, V = 5.5V,

CC

200

LOGIC

2

f

= 400 kHz (for I C active read and

SCL

write)

V

= 1.2V, V = 1.7V,

CC

= 400 kHz (for I C active read and

5

µA

LOGIC

2

f

SCL

write)

I

V

supply current (write/read)

V

= 5.5V, V = 5.5V

CC

18

10

1

µA

CC

LOGIC

= 1.2V, V = 1.7V

CC

I

standby current

= V = 5.5V,

CC

LOGIC SB

LOGIC

2

I C interface in standby

V

= 1.2V, V = 1.7V,

0.5

1.5

1

µA

µs

LOGIC

CC

2

I C interface in standby

I

V

standby current

V = V = 5.5V,

LOGIC CC

CC SB

CC

2

I C interface in standby

V

= 1.2V, V = 1.7V,

LOGIC

CC

2

I C interface in standby

shutdown current

V

= V = 5.5V,

1.3

0.4

0.7

0.5

0.4

LOGIC

LOGIC CC

2

I C interface in standby

SHDN

V

= 1.2V, V = 1.7V,

LOGIC

CC

2

I C interface in standby

I

shutdown current

V = V = 5.5V,

LOGIC CC

CC SHDN

CC

2

I C interface in standby

V

= 1.2V, V = 1.7V,

LOGIC

CC

2

I C interface in standby

I

Leakage current, at pins A0, A1, SDA,

SCL

Voltage at pin from GND to V

-0.4

<0.1

1.5

LkgDig

LOGIC

t

Wiper response time

SCL rising edge of the acknowledge bit

after data byte to wiper new position

DCP

FN7778.0

December 15, 2010

6

ISL23315

Operating Specifications V = 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise

LOGIC

CC

stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

µs

tShdnRec DCP recall time from shutdown mode

SCL rising edge of the acknowledge bit

after ACR data byte to wiper recalled

position and RH connection

1.5

V

V ramp rate

Ramp monotonic at any level

0.01

50

V/ms

CC, LOGIC

CC , LOGIC

Ramp

(Note 21)

Serial Interface Specification for SCL, SDA, A0, A1 Unless Otherwise Noted.

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20)

SYMBOL

PARAMETER

Input LOW Voltage

TEST CONDITIONS

UNITS

V

-0.3

0.3 x V

V

IL

LOGIC

+ 0.3

V

Input HIGH Voltage

0.7 x V

LOGIC

V

LOGIC

IH

Hysteresis

SDA and SCL Input Buffer

Hysteresis

V

> 2V

<2V

0.05 x V

LOGIC

0.1 x V

0

V

SDA Output Buffer LOW Voltage

I

= 3mA, V

> 2V

LOGIC

0.4

V

OL

I

= 1.5mA,

0.2 x V

LOGIC

V

<2V

LOGIC

C

SDA, SCL Pin Capacitance

SCL Frequency

10

pF

kHz

ns

f

400

SCL

t

Pulse Width Suppression Time at

SDA and SCL Inputs

Any pulse narrower than the

max spec is suppressed

50

sp

t

SCL Falling Edge to SDA Output

Data Valid

SCL falling edge crossing 30%

900

ns

AA

of V

, until SDA exits the

LOGIC

30% to 70% of V

window

LOGIC

t

Time the Bus Must be Free Before SDA crossing 70% of V

1300

BUF

the Start of a New Transmission

during a STOP condition, to

SDA crossing 70% of V

LOGIC

during the following START

condition

t

Clock LOW Time

Measured at the 30% of

1300

600

ns

LOW

V

crossing

LOGIC

Measured at the 70% of

crossing

t

Clock HIGH Time

HIGH

V

LOGIC

t

START Condition Set-up Time

SCL rising edge to SDA falling

edge; both crossing 70% of

600

SU:STA

V

LOGIC

From SDA falling edge

crossing 30% of V

t

START Condition Hold Time

Input Data Set-up Time

Input Data Hold Time

600

100

0

ns

HD:STA

to SCL

LOGIC

falling edge crossing 70% of

V

LOGIC

From SDA exiting the 30% to

70% of V window, to SCL

t

SU:DAT

HD:DAT

LOGIC

rising edge crossing 30% of

V

LOGIC

From SCL falling edge crossing

70% of V to SDA entering

t

CC

the 30% to 70% of V window

CC

FN7778.0

December 15, 2010

7

ISL23315

Serial Interface Specification for SCL, SDA, A0, A1 Unless Otherwise Noted. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

ns

t

STOP Condition Set-up Time

From SCL rising edge crossing

600

1300

0

SU:STO

70% of V

, to SDA rising

LOGIC

edge crossing 30% of V

LOGIC

t

STOP Condition Hold Time for Read From SDA rising edge to SCL

ns

HD:STO

or Write

falling edge; both crossing

70% of V (Note 11)

CC

t

Output Data Hold Time

From SCL falling edge crossing

DH

30% of V

, until SDA

LOGIC

enters the 30% to 70% of

window.

V

LOGIC

I

= 3mA, V

= 0.5mA, V

> 2V.

< 2V

OL

LOGIC

t

SDA and SCL Rise Time

SDA and SCL Fall Time

From 30% to 70% of V

From 70% to 30% of V

20 + 0.1 x Cb

10

250

400

ns

pF

R

LOGIC

t

F

Cb

Capacitive Loading of SDA or SCL Total on-chip and off-chip

(Note 11)

t

A1, A0 setup time

A1, A0 hold time

Before START condition

After STOP condition

600

ns

SU:A

t

HD:A

NOTES:

8. Typical values are for T = +25°C and 3.3V supply voltages.

A

9. LSB = [V(RW)

255

– V(RW) ]/255. V(RW)

and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental

255 0

0

voltage when changing from one tap to an adjacent tap.

10. ZS error = V(RW) /LSB.

0

11. FS error = [V(RW)

255

– V ]/LSB.

CC

12. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

i

13. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 255

i

0

14.

Max(V(RW) ) – Min(V(RW) )

for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

voltage and Min( ) is the minimum value of the wiper voltage over the temperature range.

6

10

i

----------------------------------------------------------------------------- ---------------------

TC

=

×

V

V(RW (+25°C))

+165°C

– RW |/255. MI is a minimum increment. RW

i

15. MI = |RW

and RW are the measured resistances for the DCP register set to FF hex and 00

0

255

hex respectively.

0

255

16. Roffset = RW /MI, when measuring between RW and RL.

0

Roffset = RW

/MI, when measuring between RW and RH.

255

17. RDNL = (RW – RW )/MI -1, for i = 16 to 255.

i-1

i

18. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 255.

i

0

6

19.

for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the

minimum value of the resistance over the temperature range.

[Max(Ri) – Min(Ri)]

10

+165°C

------------------------------------------------------ ---------------------

TC

=

×

R

Ri(+25°C)

20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

21. It is preferable to ramp up both the V and the V supplies at the same time. If this is not possible it is recommended to ramp-up the V

LOGIC

CC

LOGIC

first followed by the V

.

CC

DCP Macro Model

R

TOTAL

RH

RL

C

L

C

H

C

W

22pF

32pF

RW

FN7778.0

December 15, 2010

8

ISL23315

Timing Diagrams

SDA vs SCL Timing

t

sp

t

R

F

HIGH

LOW

SCL

t

SU:DAT

t

SU:STO

SU:STA

HD:DAT

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

AA

DH

SDA

(OUTPUT TIMING)

A0 and A1 Pin Timing

STOP

START

SCL

CLK 1

SDA

t

HD:A

SU:A

A0, A1

Typical Performance Curves

0.4

0.30

0.2

0

0.15

0

-0.2

-0.4

-0.15

-0.30

0

50

100

150

200

250

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 4. 50k DNL vs TAP POSITION, V = 5V

CC

FIGURE 3. 10k DNL vs TAP POSITION, V = 5V

CC

FN7778.0

December 15, 2010

9

ISL23315

Typical Performance Curves (Continued)

0.30

0.15

0

0.4

0.2

0

-0.15

-0.30

-0.2

-0.4

0

50

100

150

200

250

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 6. 50k INL vs TAP POSITION, V = 5V

CC

FIGURE 5. 10k INL vs TAP POSITION, V = 5V

CC

0.4

0.2

0

0.30

0.15

0

-0.2

-0.4

-0.15

-0.30

0

50

100

150

200

250

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 7. 10k RDNL vs TAP POSITION, V = 5V

CC

FIGURE 8. 50k RDNL vs TAP POSITION, V = 5V

CC

0.6

0.4

0.2

0

0.30

0.15

0

-0.2

-0.4

-0.6

-0.15

-0.30

0

50

100

150

200

250

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 10. 50k RINL vs TAP POSITION, V = 5V

CC

FIGURE 9. 10k RINL vs TAP POSITION, V = 5V

CC

FN7778.0

December 15, 2010

10

ISL23315

Typical Performance Curves (Continued)

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

+125°C

+25°C

-40°C

0

50

100

150

200

250

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, V = 5V

CC

FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, V = 5V

CC

300

250

200

150

100

50

70

60

50

40

30

20

10

0

15

65

115

165

215

15

65

115

165

215

TAP POSITION (DECIMAL)

FIGURE 13. 10k TCv vs TAP POSITION

FIGURE 14. 50k TCv vs TAP POSITION

600

500

400

300

200

100

0

200

150

100

50

0

15

65

115

165

215

65

115

165

215

TAP POSITION (DECIMAL)

FIGURE 16. 50k TCr vs TAP POSITION

FIGURE 15. 10k TCr vs TAP POSITION

FN7778.0

December 15, 2010

11

ISL23315

Typical Performance Curves (Continued)

35

30

25

20

15

10

5

120

90

60

30

0

15

65

115

165

215

15

65

115

165

215

TAP POSITION (DECIMAL)

FIGURE 17. 100k TCv vs TAP POSITION

FIGURE 18. 100k TCr vs TAP POSITION

SCL CLOCK

RW PIN

10mV/DIV

1µs/DIV

20mV/DIV

5µs/DIV

FIGURE 19. WIPER DIGITAL FEED-THROUGH

FIGURE 20. WIPER TRANSITION GLITCH

1V/DIV

1µs/DIV

1V/DIV

0.1s/DIV

WIPER

SCL 9TH CLOCK OF THE

DATA BYTE (ACK)

FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME

FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE

FN7778.0

December 15, 2010

12

ISL23315

Typical Performance Curves (Continued)

1.2

1.0

0.8

0.6

0.4

0.2

0

CH1: 0.5V/DIV, 0.2µs/DIV RH PIN

CH2: 0.2V/DIV, 0.2µs/DIV RW PIN

V

= 5.5V, V

= 5.5V

LOGIC

CC

V

= 1.7V, V

= 1.2V

LOGIC

CC

R

= 10k

TOTAL

-40

-15

10

35

60

85

110

-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP

TEMPERATURE (°C)

FIGURE 24. STANDBY CURRENT vs TEMPERATURE

FIGURE 23. 10k -3dB CUT OFF FREQUENCY

V

LOGIC

Functional Pin Descriptions

Potentiometers Pins

RH AND RL

This is an input pin, that supply internal level translator for serial

bus operation from 1.2V to 5.5V.

Principles of Operation

The ISL23315 is an integrated circuit incorporating one DCP with

The high (R ) and low (R ) terminals of the ISL23315 are

H

L

equivalent to the fixed terminals of a mechanical potentiometer.

R and R are referenced to the relative position of the wiper and

2

its associated registers and an I C serial interface providing

H

L

not the voltage potential on the terminals. With WR set to 255

decimal, the wiper will be closest to R , and with the WR set to 0,

direct communication between a host and the potentiometer.

The resistor array is comprised of individual resistors connected

in series. At either end of the array and between each resistor is

an electronic switch that transfers the potential at that point to

the wiper.

H

the wiper is closest to R .

L

RW

RW is the wiper terminal, and it is equivalent to the movable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the WR register.

The electronic switches on the device operate in a “make before

break” mode when the wiper changes tap positions.

Voltage at any DCP pins, R , R or R , should not exceed V

CC

level at any conditions during power-up and normal operation.

H

L

W

Bus Interface Pins

2

SERIAL DATA INPUT/OUTPUT (SDA)

The V

pin needs to be connected to the I C bus supply

LOGIC

2

The SDA is a bidirectional serial data input/output pin for I C

which allows reliable communication with the wide range of

interface. It receives device address, operation code, wiper

address and data from an I C external master device at the

rising edge of the serial clock SCL, and it shifts out data after

each falling edge of the serial clock.

microcontrollers and independent of the V level. This is

extremely important in systems where the master supply has

lower levels than DCP analog supply.

CC

2

DCP Description

The DCP is implemented with a combination of resistor elements

and CMOS switches. The physical ends of each DCP are

SDA requires an external pull-up resistor, since it is an open drain

input/output.

SERIAL CLOCK (SCL)

equivalent to the fixed terminals of a mechanical potentiometer

(RH and RL pins). The RW pin of the DCP is connected to

intermediate nodes, and is equivalent to the wiper terminal of a

mechanical potentiometer. The position of the wiper terminal

within the DCP is controlled by an 8-bit volatile Wiper Register

(WR). When the WR of a DCP contains all zeroes (WR[7:0]= 00h),

its wiper terminal (RW) is closest to its “Low” terminal (RL). When

the WR register of a DCP contains all ones (WR[7:0]= FFh), its

wiper terminal (RW) is closest to its “High” terminal (RH). As the

value of the WR increases from all zeroes (0) to all ones (255

decimal), the wiper moves monotonically from the position

closest to RL to the position closest to RH. At the same time, the

2

This input is the serial clock of the I C serial interface. SCL

requires an external pull-up resistor, since a master is an open

drain output.

DEVICE ADDRESS (A1, A0)

The address inputs are used to set the least significant 2 bits of

2

the 7-bit I C interface slave address. A match in the slave

address serial data stream must match with the Address input

pins in order to initiate communication with the ISL23315. A

maximum of four ISL23315 devices may occupy the I C serial

2

bus (see Table 3).

FN7778.0

December 15, 2010

13

ISL23315

resistance between RW and RL increases monotonically, while

the resistance between RH and RW decreases monotonically.

indicating START and STOP conditions (see Figure 26). On

power-up of the ISL23315, the SDA pin is in the input mode.

2

While the ISL23315 is being powered up, the WR is reset to 80h

(128 decimal), which locates RW roughly at the center between

All I C interface operations must begin with a START condition,

which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The

ISL23315 continuously monitors the SDA and SCL lines for the

START condition and does not respond to any command until this

condition is met (see Figure 26). A START condition is ignored

during the power-up of the device.

R and R .

L

H

2

The WR can be read or written to directly using the I C serial

interface as described in the following sections.

2

Memory Description

All I C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while SCL is

HIGH (see Figure 26). A STOP condition at the end of a read

operation or at the end of a write operation places the device in

its standby mode.

The ISL23315 contains two volatile 8-bit registers: Wiper Register

(WR) and Access Control Register (ACR). Memory map of ISL23315

is in Table 1. The Wiper Register (WR) at address 0, contains current

wiper position. The Access Control Register (ACR) at address 10h

contains information and control bits described in Table 2.

An ACK (Acknowledge) is a software convention used to indicate

a successful data transfer. The transmitting device, either master

or slave, releases the SDA bus after transmitting eight bits.

During the ninth clock cycle, the receiver pulls the SDA line LOW

to acknowledge the reception of the eight bits of data

(see Figure 27).

TABLE 1. MEMORY MAP

ADDRESS

(hex)

VOLATILE

REGISTER NAME

DEFAULT SETTING

(hex)

10

0

ACR

WR

42

80

The ISL23315 responds with an ACK after recognition of a START

condition followed by a valid Identification Byte, and once again

after successful receipt of an Address Byte. The ISL23315 also

responds with an ACK after receiving a Data Byte of a write

operation. The master must respond with an ACK after receiving

a Data Byte of a read operation.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

BIT #

7

0

6

5

0

4

0

3

0

2

0

1

0

NAME/

VALUE

SHDN

A valid Identification Byte contains 10100 as the five MSBs, and

the following two bits matching the logic values present at pins

A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a

Read operation and “0” for a Write operation (see Table 3).

The SHDN bit (ACR[6]) disables or enables Shutdown mode. When

this bit is 0, i.e. DCP is forced to end-to-end open circuit and RW is

shorted to RL as shown in Figure 25. Default value of the SHDN bit

is 1.

TABLE 3. IDENTIFICATION BYTE FORMAT

RH

LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY

1

0

1

0

A1

A0

R/W

RW

(MSB)

(LSB)

RL

FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE

2

I C Serial Interface

The ISL23315 supports an I C bidirectional bus oriented

2

protocol. The protocol defines any device that sends data onto

the bus as a transmitter and the receiving device as the receiver.

The device controlling the transfer is a master and the device

being controlled is the slave. The master always initiates data

transfers and provides the clock for both transmit and receive

operations. Therefore, the ISL23315 operates as a slave device

in all applications.

2

All communication over the I C interface is conducted by sending

the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line must change only during SCL LOW

periods. SDA state changes during SCL HIGH are reserved for

FN7778.0

December 15, 2010

14

ISL23315

SCL

SDA

START

DATA

STOP

STABLE

CHANGE STABLE

FIGURE 26. VALID DATA CHANGES, START AND STOP CONDITIONS

SCL FROM

MASTER

1

8

9

SDA OUTPUT FROM

TRANSMITTER

HIGH IMPEDANCE

SDA OUTPUT FROM

RECEIVER

START

ACK

FIGURE 27. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

S

T

A

R

T

SIGNALS FROM

THE MASTER

S

T

O

P

IDENTIFICATION

BYTE

ADDRESS

BYTE

DATA

BYTE

SIGNAL AT SDA

1 0 1 0 0 A1A0 0

0 0 0

SIGNALS FROM

THE SLAVE

A

C

K

A

C

K

A

C

K

FIGURE 28. BYTE WRITE SEQUENCE

READ

S

T

A

R

T

S

T

A

R

T

SIGNALS

FROM THE

MASTER

S

T

O

P

A

C

K

A

C

K

IDENTIFICATION

BYTE WITH

R/W = 0

IDENTIFICATION

BYTE WITH

R/W = 1

A

C

K

ADDRESS

BYTE

SIGNAL AT SDA

0

0 A1A0 1

1 0 1 0 0A1A0 0

0 0 0

1 0 1

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIRST READ

DATA BYTE

LAST READ

DATA BYTE

FIGURE 29. READ SEQUENCE

FN7778.0

December 15, 2010

15

ISL23315

Applications Information

Write Operation

A Write operation requires a START condition, followed by a valid

Identification Byte, a valid Address Byte, a Data Byte, and a STOP

condition. After each of the three bytes, the ISL23315 responds

V

Requirements

LOGIC

It is recommended to keep V

normal operation. In a case where turning V

LOGIC

powered all the time during

OFF is

necessary, it is recommended to ground the V pin of the

LOGIC

2

with an ACK. The data is transferred from I C block to the

corresponding register at the 9th clock of the data byte and

device enters its standby state (see Figures 27 and 28).

ISL23315. Grounding the V

pin or both V and V does

LOGIC

CC

not affect other devices on the same bus. It is good practice to

Read Operation

put a 1µF cap in parallel to 0.1µF as close to the V

possible.

pin as

LOGIC

A Read operation consists of a three byte instruction followed by

one or more Data Bytes (see Figure 29). The master initiates the

operation issuing the following sequence: a START, the

Identification byte with the R/W bit set to “0”, an Address Byte, a

second START, and a second Identification byte with the R/W bit

set to “1”. After each of the three bytes, the ISL23315 responds

with an ACK; then the ISL23315 transmits Data Byte. The master

terminates the read operation issuing a NACK (ACK) and a STOP

condition following the last bit of the last Data Byte (see

Figure 29).

V

Requirements and Placement

CC

It is recommended to put a 1µF capacitor in parallel with 0.1µF

decoupling capacitor close to the V pin.

CC

Wiper Transition

When stepping up through each tap in voltage divider mode,

some tap transition points can result in noticeable voltage

transients, or overshoot/undershoot, resulting from the sudden

transition from a very low impedance “make” to a much higher

impedance “break” within a short period of time (<1µs). There

are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,

EFh to FFh, which have higher transient glitch. Note, that all

switching transients will settle well within the settling time as

stated in the datasheet. A small capacitor can be added

externally to reduce the amplitude of these voltage transients.

However, that will also reduce the useful bandwidth of the circuit,

thus may not be a good solution for some applications. It may be

a good idea, in that case, to use fast amplifiers in a signal chain

for fast recovery.

FN7778.0

December 15, 2010

16

ISL23315

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN7778.0

CHANGE

12/15/10

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address

some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product

families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil

product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL23315

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7778.0

December 15, 2010

17

ISL23315

Mini Small Outline Plastic Packages (MSOP)

N

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES

MILLIMETERS

E1

E

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.18

0.09

2.95

MAX

1.10

0.15

0.95

0.27

0.20

3.05

NOTES

A

A1

A2

b

0.037

0.002

0.030

0.007

0.004

0.116

0.043

0.006

0.037

0.011

0.008

0.120

-

-B-

0.20 (0.008)

INDEX

AREA

1 2

A

B

C

-

TOP VIEW

4X θ

9

0.25

(0.010)

R1

c

-

R

GAUGE

PLANE

D

3

E1

e

4

SEATING

PLANE

L

0.020 BSC

0.50 BSC

-

-C-

4X θ

L1

A

A2

E

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

-

L

6

SEATING

PLANE

L1

N

0.037 REF

10

0.95 REF

10

-

0.10 (0.004)

-A-

C

b

7

-H-

A1

e

R

0.003

-

0.07

-

D

0.20 (0.008)

C

R1

θ

-

o

a

SIDE VIEW

5

15

5

15

-

C

L

o

0

6

0

6

-

α

E

1

-B-

Rev. 0 12/02

0.20 (0.008)

C

D

END VIEW

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

-A -

10. Datums

and

to be determined at Datum plane

.

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only

FN7778.0

December 15, 2010

18

ISL23315

Package Outline Drawing

L10.2.1x1.6A

10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 5, 3/10

8.

PIN 1

INDEX AREA

2.10

A

PIN #1 ID

8.

0.05 MIN.

B

1

4

1

4X 0.20 MIN.

0.10 MIN.

10

5

0.80

10X 0.40

10 X 0.20

0.10

6

9

2X

6X 0.50

4

TOP VIEW

(10 X 0.20)

0.10 M C A B

M C

BOTTOM VIEW

SEE DETAIL "X"

(0.05 MIN)

(0.10 MIN.)

MAX. 0.55

PACKAGE

OUTLINE

1

0.10 C

C

(10X 0.60)

SEATING PLANE

0.08 C

(2.00)

SIDE VIEW

0 . 125 REF

(0.80)

(1.30)

C

(6X 0.50 )

(2.50)

0-0.05

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

2. All Dimensions are in millimeters. Angles are in degrees.

Dimensions in ( ) for Reference Only.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Lead width dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Maximum package warpage is 0.05mm.

6. Maximum allowable burrs is 0.076mm in all directions.

7. Same as JEDEC MO-255UABD except:

No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm

Lead Length dim. = 0.45mm max. not 0.42mm.

8. The configuration of the pin #1 identifier is optional, but must be located within

the zone indicated. The pin #1 identifier may be either a mold or mark feature.

FN7778.0

December 15, 2010

19


型号：	ISL23315UFRUZ-TK
厂家：	Intersil
描述：	Single, Low Voltage Digitally Controlled Potentiometer (XDCP?) 单路低电压数字控制电位器（ XDCP ？）转换器电位器电阻器
文件：	总19页 (文件大小：829K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL23315UFRUZ-TK [INTERSIL]

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