ISL26132AVZ-T_技术文档

Low-Noise 24-bit Delta Sigma ADC

ISL26132, ISL26134

Features

The ISL26132 and ISL26134 are complete analog front ends

for high resolution measurement applications. These 24-bit

Delta-Sigma Analog-to-Digital Converters include a very

low-noise amplifier and are available as either two or four

differential multiplexer inputs. The devices offer the same

pinout as the ADS1232 and ADS1234 devices and are

functionally compatible with these devices. The ISL26132 and

ISL26134 offer improved noise performance at 10Sps and

80Sps conversion rates.

• Up to 21.6 Noise-free bits.

• Low Noise Amplifier with Gains of 1x/2x/64x/128x

• RMS noise: 10.2nV @ 10Sps (PGA = 128x)

• Linearity Error: 0.0002% FS

• Simultaneous rejection of 50Hz and 60Hz (@ 10Sps)

• Two (ISL26132) or four (ISL26134) channel differential

input multiplexer

• On-chip temperature sensor (ISL26132)

• Automatic clock source detection

The on-chip low-noise programmable-gain amplifier provides

gains of 1x/2x/64x/128x. The 128x gain setting provides an

input range of ±9.766mVFS when using a 2.5V reference. The

high input impedance allows direct connection of sensors such

as load cell bridges to ensure the specified measurement

accuracy without additional circuitry. The inputs accept signals

100mV outside the supply rails when the device is set for unity

gain.

• Simple interface to read conversions

• +5V Analog, +5 to +2.7V Digital Supplies

• Pb-Free (RoHS Compliant)

• TSSOP packages: ISL26132, 24 pin; ISL26134, 28 pin

Applications

• Weigh Scales

The Delta-Sigma ADC features a third order modulator

providing up to 21.6-bit noise-free performance.

The device can be operated from an external clock source,

crystal (4.9152MHz typical), or the on-chip oscillator.

• Temperature Monitors and Controls

• Industrial Process Control

• Pressure Sensors

The two channel ISL26132 is available in a 24 Ld TSSOP

package and the four channel ISL26134 is available in a 28 Ld

TSSOP package. Both are specified for operation over the

automotive temperature range (-40°C to +105°C).

CAP

AVDD

DVDD

XTALIN/CLOCK

INTERNAL

CLOCK

EXTERNAL

OSCILLATOR

XTALOUT

AIN1+

AIN1-

SDO/RDY

SCLK

AIN2+

AIN2-

PGA

1x/2x/64x/

128x

INPUT

MULTIPLEXER

ADC

AIN3+

AIN3-

ISL26134

Only

AIN4+

AIN4-

PWDN

SPEED

A0 A1/TEMP AGND

GAIN0 GAIN1

DGND

CAP

DGND

VREF+

VREF-

NOTE for A1/TEMP pin: Functions as A1 on ISL26134; Functions as TEMP on ISL26132

FIGURE 1. BLOCK DIAGRAM

September 9, 2011

FN6954.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL26132, ISL26134

Ordering Information

PART NUMBER

(Notes 2, 3)

TEMPERATURE RANGE

PACKAGE

(Pb-free)

PKG. DWG

NUMBER

PART MARKING

26132 AVZ

(°C)

ISL26132AVZ

-40 to +105

24 Ld TSSOP

M24.173

ISL26132AVZ-T (Note 1)

ISL26132AVZ-T7A (Note 1)

ISL26134AVZ

26132 AVZ

26134 AVZ

Evaluation Board

24 Ld TSSOP (Tape & Reel) M24.173

28 Ld TSSOP

M28.173

ISL26134AVZ-T (Note 1)

ISL26134AVZ-T7A (Note 1)

ISL26134AV28EV1Z

NOTES:

28 Ld TSSOP (Tape & Reel) M28.173

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL26132, ISL26134. For more information on MSL please see techbrief

TB363.

TABLE 1. KEY DIFFERENCES OF PARTS

PART NUMBER

ISL26132

NUMBER OF CHANNELS

ON-CHIP TEMPERATURE SENSOR

NUMBER OF PINS

2

4

YES

NO

24

28

ISL26134

Pin Configurations

ISL26132

(24 LD TSSOP)

TOP VIEW

ISL26134

(28 LD TSSOP)

TOP VIEW

DVDD

DGND

1

2

3

4

5

6

7

8

9

24

SDO/RDY

23 SCLK

22

DVDD

1

2

3

4

5

6

7

8

9

28 SDO/RDY

27 SCLK

DGND

XTALIN/CLOCK

XTALOUT

DGND

XTALIN/CLOCK

XTALOUT

DGND

PDWN

26 PDWN

21 SPEED

20 GAIN1

19 GAIN0

18 AVDD

17 AGND

16 VREF+

15 VREF-

14 AIN2+

13 AIN2-

SPEED

25

24 GAIN1

23 GAIN0

22 AVDD

21 AGND

DGND

TEMP

A1

A0

CAP

20

VREF+

CAP 10

AIN1+ 11

AIN1- 12

CAP 10

AIN1+ 11

AIN1- 12

AIN3+ 13

AIN3- 14

19 VREF-

18 AIN2+

17 AIN2-

16 AIN4+

15 AIN4-

FN6954.1

September 9, 2011

2

ISL26132, ISL26134

Pin Descriptions

PIN NUMBER

ANALOG/DIGITAL

NAME

DVDD

ISL26132 ISL26134

INPUT/OUTPUT

DESCRIPTION

Digital Power Supply (2.7V to 5.25V)

Digital Ground

1

2, 5, 6

3

1

2, 5, 6

3

Digital

DGND

Digital

XTALIN/CLOCK

Digital/Digital Input

External Clock Input: typically 4.9152MHz. Tie low to activate

internal oscillator. Can also use external crystal across

XTALIN/CLOCK and XTALOUT pins.

XTALOUT

TEMP

4

7

4

-

Digital

External Crystal connection

Digital Input

On-chip Temperature Diode Enable

A1

A0

-

8

7

8

TABLE 2. INPUT MULTIPLEXER SELECT

ISL26134

ISL26132

A1

0

A0

0

CHANNEL

AIN1

0

1

AIN2

1

0

AIN3

1

AIN4

CAP

AIN1+

AIN1-

AIN3+

AIN3-

AIN4-

AIN4+

AIN2-

AIN2+

VREF-

VREF+

AGND

AVDD

9, 10

11

12

-

9, 10

11

12

13

14

15

16

17

Analog

PGA Filter Capacitor

Analog Input

Analog

Positive Analog Input Channel 1

Negative Analog Input Channel 1

Positive Analog Input Channel 3

Negative Analog Input Channel 3

Negative Analog Input Channel 4

Positive Analog Input Channel 4

Negative Analog Input Channel 2

Positive Analog Input Channel 2

Negative Reference Input

-

13

14

15

16

17

18

19

20

21

22

Positive Reference Input

Analog Ground

Analog

Analog Power Supply 4.75V to 5.25V

GAIN0

GAIN1

19

20

23

24

Digital Input

TABLE 3. GAIN SELECT

GAIN1

GAIN0

GAIN

1

0

1

0

1

0

1

2

64

128

FN6954.1

September 9, 2011

3

ISL26132, ISL26134

Pin Descriptions(Continued)

PIN NUMBER

ANALOG/DIGITAL

NAME

ISL26132

21

ISL26134

INPUT/OUTPUT

DESCRIPTION

SPEED

25

Digital Input

TABLE 4. DATA RATE SELECT

SPEED

DATA RATE

10Sps

0

1

80Sps

PDWN

SCLK

22

23

26

27

Digital Input

Power-Down: Holding this pin low powers down the entire

converter and resets the ADC.

Serial Clock: Clock out data on the rising edge. Also used to

initiate Offset Calibration and Sleep modes. See “Serial Clock

Input (SCLK)” on page 14 for more details.

SDO/RDY

24

28

Digital Output

Dual-Purpose Output:

Data Ready: Indicate valid data by going low.

Data Output: Outputs data, MSB first, on the first rising edge

of SCLK.

Circuit Description

The ISL26132 (2-channel) and ISL26134 (4-channel) devices are

very low noise 24-bit delta-sigma ADCs that include a

programmable gain amplifier and an input multiplexer. The

ISL26132 offers an on-chip temperature measurement

capability.

The ISL26132, ISL26134 provide pin compatibility and output

data compatibility with the ADS1232/ADS1234, and offer the

same conversion rates of 10Sps and 80Sps.

All the features of the ISL26132, ISL26134 are pin-controllable,

while offset calibration, standby mode, and output conversion

data are accessible through a simple 2-wire interface.

The clock can be selected to come from an internal oscillator, an

external clock signal, or crystal (4.9152MHz typical).

FN6954.1

September 9, 2011

4

ISL26132, ISL26134

Absolute Maximum Ratings

Thermal Information

A

to D

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

Thermal Resistance (Typical)

24 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . .

28 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . .

θ

_JA(°C/W)

65

θ

_JC(°C/W)

GND

Analog In to A

Digital In to D

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to D

+0.3V

18

GND

VDD

63

Input Current

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mW

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Momentary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . . .7.5kV

Machine Model (Per JESD22-A115). . . . . . . . . . . . . . . . . . . . . . . . . . 450V

Charged Device Model (Per JESD22-C101) . . . . . . . . . . . . . . . . . . . . . . . . 2kV

Latch-up (Per JEDEC JESD-78B; Class 2, Level A)

Operating Conditions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA @ Room and Hot (+105°C)

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

A

D

to A

to D

GND

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V

VDD

GND

VDD

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

5. For θ , the “case temp” location is taken at the package top center.

JC

Electrical Specifications

V

+ = 5V, V

- = 0V, A

VDD

= 5V, D

VDD

= 5V, A

GND

= D

= 0V, MCLK = 4.9152MHz, and

GND

REF

= -40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C

T

A

MIN

(Note 6)

MAX

(Note 6)

SYMBOL

ANALOG INPUTS

PARAMETER

TEST LEVEL or NOTES

TYP

UNITS

V

Differential Input Voltage Range

±0.5V

/

REF

Gain

Common Mode Input Voltage

Range

Gain = 1, 2

A

- 0.1

A

+ 0.1

V

GND

VDD

Gain = 64, 128

Gain = 1

A

+1.5

A

- 1.5

V

GND

VDD

±20

±40

±1

nA

Differential Input Current

Gain = 2

Gain = 64, 128

SYSTEM PERFORMANCE

Resolution

No Missing Codes

24

Bits

SPS

Internal Osc. SPEED = High

Internal Osc. SPEED = Low

External Osc. SPEED = High

External Osc. SPEED = Low

80

10

Data Rate

fCLK/61440

fCLK/49152

0

Digital Filter Settling Time

Integral Nonlinearity

Full Setting

4

Conversions

INL

Differential Input Gain = 1, 2

Differential Input Gain = 64, 128

±0.0002

±0.0004

±0.001

% of FSR (Note 7)

% of FSR

(Note 7)

Input Offset Error

Input Offset Drift

Gain Error (Note 8)

Gain Drift

Gain = 1

±0.4

±1.5

0.3

ppm of FS

µV/°C

nV/°C

%

Gain = 128

Gain = 1

Gain = 128

Gain = 1

10

±0.007

±0.02

0.5

±0.02

Gain = 128

Gain = 1

%

ppm/°C

Gain = 128

7

FN6954.1

September 9, 2011

5

ISL26132, ISL26134

Electrical Specifications

V

+ = 5V, V

- = 0V, A

VDD

= 5V, D

VDD

= 5V, A

GND

= D

= 0V, MCLK = 4.9152MHz, and

GND

REF

= -40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C (Continued)

T

A

MIN

MAX

SYMBOL

PARAMETER

TEST LEVEL or NOTES

At DC, Gain = 1, ΔV = 1V

(Note 6)

TYP

100

130

100

105

(Note 6)

UNITS

dB

CMRR

PSRR

Common Mode Rejection

85

At DC, Gain = 128, ΔV = 0.1V

External 4.9152MHz Clock

At DC, Gain = 1, ΔV = 1V

dB

50Hz/60Hz Rejection (Note 9)

Power Supply Rejection

dB

82

dB

At DC, Gain = 128, ΔV = 0.1V

100

dB

Input Referred Noise

Noise Free Bits

See “Typical Characteristics” beginning

on page 8

See “Typical Characteristics” beginning

on page 8

VOLTAGE REFERENCE INPUT

VREF

VREF-

VREF+

IREF

Voltage Reference Input

VREF = VREF+ - VREF-

1.5

AVDD

±350

AVDD + 0.1

VREF+ - 1.5

AVDD + 0.1

V

Negative Reference Input

Positive Reference Input

AGND - 0.1

VREF- + 1.5

V

Voltage Reference Input Current

nA

POWER SUPPLY REQUIREMENTS

A

Analog Supply Voltage

Digital Supply Voltage

Analog Supply Current

4.75

2.7

5.0

3.3

7

5.25

8.5

12

V

VDD

D

V

VDD

A

Normal Mode, AVDD = 5, Gain = 1, 2

Normal Mode, AVDD = 5, Gain = 64, 128

Standby Mode

mA

µA

IDD

9

0.2

750

1.5

1

3

Power-Down

2.5

950

26

µA

D

Digital Supply Current

Power Dissipation, Total

Normal Mode, AVDD = 5, Gain = 1, 2

Normal Mode, AVDD = 5, Gain = 64, 128

Standby Mode

µA

Power-Down

26

µA

P

Normal Mode, AVDD = 5, Gain = 1, 2

Normal Mode, AVDD = 5, Gain = 64, 128

Standby Mode

49.6

68

mW

D

0.14

Power-Down

DIGITAL INPUTS

V

0.7 D

V

IH

VDD

V

0.2 D

IL

VDD

V

I

= -1mA

= 1mA

D - 0.4

VDD

V

OH

OL

V

OL

VDD

Input Leakage Current

±10

µA

MHz

External Clock Input Frequency

Serial Clock Input Frequency

0.3

4.9152

1

NOTE:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

7. FSR = Full Scale Range = VREF/Gain

8. Gain accuracy is calibrated at the factory (AVDD = +5V).

9. Specified for word rate equal to 10Sps.

FN6954.1

September 9, 2011

6

ISL26132, ISL26134

Noise Performance

The ISL26132 and ISL26134 provide excellent noise

performance. The noise performance on each of the gain

settings of the PGA at the selected word rates is shown in

Tables 5 and 6.

Resolution in bits decreases by 1-bit if the ADC is operated as a

single-ended input device. Noise measurements are

input-referred, taken with bipolar inputs under the specified

operating conditions, with f

= 4.9152MHz.

CLK

TABLE 5. A

= 5V, V

= 5V, DATA RATE = 10Sps

REF

VDD

RMS NOISE

(nV)

PEAK-TO-PEAK NOISE

(nV) (Note 10)

NOISE-FREE BITS

(Note 11)

GAIN

1

243

148

1604

977

71

21.6

21.3

20.1

19.1

2

64

128

10.8

10.2

67

TABLE 6. A

= 5V, V

= 5V, DATA RATE = 80Sps

REF

VDD

RMS NOISE PEAK-TO-PEAK NOISE NOISE-FREE BITS

GAIN

(nV)

565

285

28.3

27

(nV) (Note 10)

(Note 11)

1

2

3730

20.4

1880

20.3

64

128

187

18.7

178

17.7

NOTES:

10. The peak-to-peak noise number is 6.6 times the rms value. This

encompasses 99.99% of the noise excursions that may occur. This

value best represents the worst case noise that could occur in the

output conversion words from the converter.

11. Noise-Free Bits is defined as: Noise-Free Bits = ln(FSR/peak-to-peak

noise)/ln(2) where FSR is the full scale range of the converter,

VREF/Gain.

FN6954.1

September 9, 2011

7

ISL26132, ISL26134

Typical Characteristics

300

10

GAIN = 1, N = 1024

GAIN = 1

RATE = 10Sps

250

200

150

100

50

STD DEV = 1.635 LSB

VREF = 2.5V

5

0

-5

-10

0

200

400

600

800

1000

-7 -6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

7

OUTPUT CODE (LSB)

TIME (SAMPLES)

FIGURE 2. NOISE AT GAIN = 1, 10Sps

FIGURE 3. NOISE HISTOGRAM AT GAIN = 1, 10Sps

10

5

250

GAIN = 2, N = 1024

RATE = 10Sps

GAIN = 2

RATE = 10Sps

STD DEV = 1.989 LSB

VREF = 2.5V

200

150

100

50

0

-5

-10

0

-8

-6

-4

-2

0

2

4

6

8

200

400

600

800

TIME (SAMPLES)

OUTPUT CODE (LSB)

FIGURE 4. NOISE AT GAIN = 2, 10Sps

FIGURE 5. NOISE HISTOGRAM AT GAIN = 2, 10Sps

20

15

10

5

120

100

80

60

40

20

0

GAIN = 64, N = 1024

RATE = 10Sps

GAIN = 64

RATE = 10Sps

STD DEV = 4.627 LSB

VREF = 2.5V

0

-5

-10

-15

200

400

600

800

-20

-15

-10

-5

0

5

10

15

20

OUTPUT CODE (LSB)

TIME (SAMPLES)

FIGURE 6. NOISE AT GAIN = 64, 10Sps

FIGURE 7. NOISE HISTOGRAM AT GAIN = 64, 10Sps

FN6954.1

September 9, 2011

8

ISL26132, ISL26134

Typical Characteristics(Continued)

50

60

50

40

30

20

10

0

GAIN = 128, N = 1024

RATE = 10Sps

GAIN = 128

RATE = 10Sps

STD DEV = 8.757 LSB

VREF = 2.5V

30

10

-10

-30

-50

-30 -25 -20 -15 -10 -5

0

5

10 15 20 25 30

0

200

400

600

800

1000

TIME (SAMPLES)

OUTPUT CODE (LSB)

FIGURE 8. NOISE AT GAIN = 128, 10Sps

FIGURE 9. NOISE HISTOGRAM AT GAIN = 128, 10Sps

25

20

15

10

5

120

GAIN = 1, N = 1024

RATE = 80Sps

GAIN = 1

RATE = 80Sps

100

80

60

40

20

0

STD DEV = 3.791 LSB

VREF = 2.5V

0

-5

-10

-15

-20

-25

-15

-10

-5

0

5

10

15

0

200

400

600

800

OUTPUT CODE (LSB)

TIME (SAMPLES)

FIGURE 11. NOISE HISTOGRAM AT GAIN = 1, 80Sps

FIGURE 10. NOISE AT GAIN = 1, 80Sps

120

25

15

5

GAIN = 2, N = 1024

RATE = 80Sps

GAIN = 2

RATE = 80Sps

100

80

60

40

20

0

STD DEV = 3.831 LSB

VREF = 2.5V

-5

-15

-25

0

200

400

600

800

-15

-10

-5

0

5

10

15

OUTPUT CODE (LSB)

TIME (SAMPLES)

FIGURE 12. NOISE AT GAIN = 2, 80Sps

FIGURE 13. NOISE HISTOGRAM AT GAIN = 2, 80Sps

FN6954.1

September 9, 2011

9

ISL26132, ISL26134

Typical Characteristics(Continued)

100

50

40

30

20

10

0

GAIN = 64, N = 1024

RATE = 80Sps

GAIN = 64

RATE = 80Sps

STD DEV = 12.15 LSB

VREF = 2.5V

50

0

-50

-100

0

200

400

600

800

1000

-40 -35 -30 -25 -20 -15 -10 -5

0

5 10 15 20 25 30 35 40

TIME (SAMPLES)

OUTPUT CODE (LSB)

FIGURE 14. NOISE AT GAIN = 64, 80Sps

FIGURE 15. NOISE HISTOGRAM AT GAIN = 64, 80Sps

160

120

80

30

GAIN = 128, N = 1024

RATE = 80Sps

GAIN = 128

RATE = 80Sps

25

20

15

10

5

STD DEV = 23.215 LSB

VREF = 2.5V

40

0

-40

-80

-120

-160

-200

0

-80

-60

-40

-20

0

20

40

60

80

0

200

400

600

800

1000

OUTPUT CODE (LSB)

TIME (SAMPLES)

FIGURE 16. NOISE AT GAIN = 128, 80Sps

FIGURE 17. NOISE HISTOGRAM AT GAIN = 128, 80Sps

10000

10

8

NORMAL MODE, PGA = 64.128

NORMAL MODE, PGA = 1, 2

1000

100

10

NORMAL MODE, ALL PGA GAINS

6

4

POWERDOWN MODE

2

0

-40

1

-40

-10

20

50

80

110

-10

20

50

80

110

TEMPERATURE (°C)

FIGURE 19. DIGITAL CURRENT vs TEMPERATURE

FIGURE 18. ANALOG CURRENT vs TEMPERATURE

FN6954.1

September 9, 2011

10

ISL26132, ISL26134

Typical Characteristics(Continued)

10000

1000

100

11.0

10.8

10.6

10.4

10.2

10.0

9.8

WORD RATE = 10Sps

GAIN = 1, 80Sps

64k FFT

25 AVERAGES

9.6

-40

10

0.01

0.1

1

10

-10

20

50

80

110

FREQUENCY (Hz)

TEMPERATURE (°C)

FIGURE 20. TYPICAL WORD RATE vs TEMPERATURE USING

INTERNAL OSCILLATOR

FIGURE 21. NOISE DENSITY vs FREQUENCY AT GAIN = 1, 80Sps

100

GAIN = 128, 80Sps

64k FFT

25 AVERAGES

10

1

0.01

0.1

1

10

FREQUENCY (Hz)

FIGURE 22. NOISE DENSITY vs FREQUENCY AT GAIN = 128, 80Sps

FN6954.1

September 9, 2011

11

ISL26132, ISL26134

The input span of the ADC is ±0.5 VREF/GAIN. For a 5V VREF and

a gain of 1x, the input span will be 5V fully differential as

Functional Description

P-P

shown in Figure 23. Note that input voltages that exceed the

supply rails by more than 100mV will turn on the ESD protection

diodes and degrade measurement accuracy.

Analog Inputs

The analog signal inputs to the ISL26132 connect to a 2-Channel

differential multiplexer and the ISL26134 connect to a 4-Channel

differential multiplexer (Mux). The multiplexer connects a pair of

inputs to the positive and negative inputs (AINx+, AINx-), selected

by the Channel Select Pins A0 and A1 (ISL26134 only). Input

channel selection is shown in Table 7. On the ISL26132, the

TEMP pin is used to select the Temperature Sensor function.

If the differential input exceeds well above the +VE or the -VE FS

(by ~1.5x times) the output code will clip to the corresponding FS

value. Under such conditions, the output data rate will become

1/4th of the original value as the Digital State Machine will

RESET the Delta-Sigma Modulator and the Decimation Filter.

TABLE 7. INPUT CHANNEL SELECTION

Temperature Sensor (ISL26132 only)

CHANNEL SELECT PINS

ANALOG INPUT PINS SELECTED

When the TEMP pin of the ISL26132 is set High, the input

multiplexer is connected to a pair of diodes, which are scaled in

both size and current. The voltage difference measured between

them corresponds to the temperature of the die according to

Equation 1:

A1

0

A0

0

AIN+

AIN1+

AIN2+

AIN3+

AIN4+

AIN-

AIN1-

AIN2-

AIN3-

AIN4-

0

1

(EQ. 1)

∗

V= 102.2mV + (379μV T(°C)) Gain

1

0

1

Note: Valid only for GAIN = 1x or 2x

Where T is the temperature of the die, and Gain = the PGA Gain

Setting.

Whenever the MUX channel is changed (i.e. if any one of the

following inputs - A0/A1, Gain1/0, SPEED is changed), the

digital logic will automatically restart the digital filter and will

cause SDO/RDY to go low only when the output is fully settled.

But if the input itself is suddenly changed, then the user needs to

ignore first four RDY pulses (going low) to get an accurate

measurement of the input signal.

At a temperature of +25°C, the measured voltage will be

approximately 111.7mV. Note that this measurement indicates

only the temperature of the die itself. Applying the result to

correct for the temperature drift of a device external to the

package requires that thermal coupling between the sensor and

the die be taken into account.

1.25V

Low-Noise Programmable Gain Amplifier

(PGA)

3.75

The chopper-stabilized programmable gain amplifier features a

variety of gain settings to achieve maximum dynamic range and

measurement accuracy from popular sensor types with excellent

low noise performance, input offset error, and low drift, and with

minimal external parts count. The GAIN0 and GAIN1 pins allow the

user to select gain settings of 1x, 2x, 64x, or 128x. A block diagram

is shown in Figure 24. The differential input stage provides a gain of

64, which is bypassed when the lower gain settings are selected.

The lower gain settings (1 and 2) will accept inputs with common

mode voltages up to 100mV outside the rails, allowing the device to

accept ground-referred signals. At gain settings of 64 or 128 the

common mode voltage at the inputs is limited to 1.5V inside the

supply rails while maintaining specified measurement accuracy.

2.50

AIN+

1.25

INPUT VOLTAGE RANGE = ±0.5VREF/GAIN

VREF = 5V, GAIN = 1X

3.75

2.50

1.25

AIN-

2.50V

FIGURE 23. DIFFERENTIAL INPUT FOR VREF = 5V, GAIN = 1X

FN6954.1

September 9, 2011

12

ISL26132, ISL26134

CAP

AINx+

+

-

R

INT

A1

R

F1

ADC

R

1

R

F2

-

R

INT

A2

+

AINx-

CAP

FIGURE 24. SIMPLIFIED PROGRAMMABLE GAIN AMPLIFIER BLOCK DIAGRAM

If the ADC is to be operated from a crystal, it should be located

Filtering PGA Output Noise

close to the package pins of the ADC. Note that external loading

capacitors for the crystal are not required as there are loading

capacitors built into the silicon, although the capacitor values are

optimized for operation with a 4.9152MHz crystal.

The programmable gain amplifier, as shown in Figure 24,

includes a passive RC filter on its output. The resistors are

located inside the chip on the outputs of the differential amplifier

stages. The capacitor (nominally a 100nF C0G ceramic or a PPS

film (Polyphenylene sulfide)) for the filter is connected to the two

CAP pins of the chip. The outputs of the differential amplifier

stages of the PGA are filtered before their signals are presented

to the delta-sigma modulator. This filter reduces the amount of

noise by limiting the signal bandwidth and filters the chopping

artifacts of the chopped PGA stage.

The XTALOUT pin is not intended to drive external circuits.

CRYSTAL

XTALIN/

OSCILLATOR

CLOCK

CLOCK DETECT

EN

Voltage Reference Inputs (VREF+, VREF-)

The voltage reference for the ADC is derived from the difference

in the voltages presented to the VREF+ and VREF- pins;

INTERNAL

OSCILLATOR

XTALOUT

VREF = (VREF+ - VREF-). The ADCs are specified with a voltage

reference value of 5V, but a voltage reference as low as 1.5V can

be used. For proper operation, the voltage on the VREF+ pin

should not be greater than AVDD + 0.1V and the voltage on the

VREF- pin should not be more negative than AGND - 0.1V.

MUX

TO ADC

FIGURE 25. CLOCK BLOCK DIAGRAM

Digital Filter Characteristics

Clock Sources

The digital filter inside the ADC is a fourth-order Siinc filter.

Figures 26 and 27 illustrate the filter response for the ADC when

it is operated from a 4.9152MHz crystal. The internal oscillator is

factory trimmed so the frequency response for the filter will be

much the same when using the internal oscillator. The figures

illustrate that when the converter is operated at 10Sps the digital

filter provides excellent rejection of 50Hz and 60Hz line

interference.

The ISL26132, ISL26134 can operate from an internal oscillator,

an external clock source, or from a crystal connected between

the XTALIN/CLOCK and XTALOUT pins. See the block diagram of

the clock system in Figure 25. When the ADC is powered up, the

CLOCK DETECT block determines if an external clock source is

present. If a clock greater than 300kHz is present on the

XTALIN/CLOCK pin, the circuitry will disable the internal oscillator

on the chip and use the external clock as the clock to drive the

chip circuitry. If the ADC is to be operated from the internal

oscillator, the XTALIN/CLOCK pin should be grounded.

FN6954.1

September 9, 2011

13

ISL26132, ISL26134

Serial Clock Input (SCLK)

The serial clock input is provided with hysteresis to minimize

false triggering. Nevertheless, care should be taken to ensure

reliable clocking.

0

-50

DATA RATE = 10SSpPsS

Filter Settling Time and ADC Latency

Whenever the analog signal into the ISL26132, ISL26134

converters is changed, the effects of the digital filter must be

taken into account. The filter takes four data ready periods for

the output code to fully reflect a new value at the analog input. If

the multiplexer control input is changed, the modulator and the

digital filter are reset, and the device uses four data ready

periods to fully settle to yield a digital code that accurately

represents the analog input. Therefore, from the time the control

inputs for the multiplexer are changed until the SDO/RDY goes

low, four data ready periods will elapse. The settling time delay

after a multiplexer channel change is listed in Table 8 for the

converter operating in continuous conversion mode.

-100

-150

0

10 20 30 40 50 60 70 80 90 100

FREQUENCY (Hz)

FIGURE 26. 10Sps: FREQUENCY RESPONSE OUT TO 100Hz

-50

-60

DATA RATE = 10Sps

-70

-80

-90

-100

-110

-120

-130

-140

-150

65

60

45

50

55

FREQUENCY (Hz)

FIGURE 27. 10Sps: 50/60Hz NOISE REJECTION, 45Hz TO 65Hz

TABLE 8. SETTLING TIME

DESCRIPTION

PARAMETER

(f

= 4.9152MHz)

MIN

40

MAX

50

UNITS

µs

CLK

t

A0, A1, SPEED, Gain1, Gain0 change

set-up time

S

t1

Settling time

SPEED = 1

SPEED = 0

54

55

ms

404

405

A0, A1, SPEED, Gain1, Gain0

t

1

SDO/RDY

t

S

FIGURE 28. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE

FN6954.1

September 9, 2011

14

ISL26132, ISL26134

SDO/RDY

FIGURE 29. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE

Conversion Data Rate

Reading Conversion Data from the Serial

Data Output/Ready SDO/RDY Pin

The SPEED pin is used to select between the 10Sps and 80Sps

conversion rates. The 10Sps rate (SPEED = Low) is preferred in

applications requiring 50/60Hz noise rejection. Note that the

sample rate is directly related to the oscillator frequency, as

491,520 clocks are required to perform a conversion at the

10Sps rate, and 61,440 clocks at the 80Sps rate.

When the ADC is powered, it will automatically begin doing

conversions. The SDO/RDY signal will go low to indicate the

completion of a conversion. After the SDO/RDY signal goes low,

the MSB data bit of the conversion word will be output from the

SDO/RDY pin after SCLK is transitioned from a low to a high.

Each subsequent new data bit is also output on the rising edge of

SCLK (see Figure 30). The receiving device should use the falling

edge of SCLK to latch the data bits. After the 24th SCLK, the

SDO/RDY output will remain in the state of the LSB data bit until

a new conversion is completed. At this time, the SDO/RDY will go

high if low and then go low to indicate that a new conversion

word is available. If not all data bits are read from the SDO/RDY

pin prior to the completion of a new conversion, they will be

Output Data Format

The 24-bit converter output word is delivered in two’s

complement format. Input exceeding full scale results in a

clipped output which will not return to in-range values until after

the input signal has returned to the specified allowable voltage

range and the digital filter has settled as discussed previously.

TABLE 9. OUTPUT CODES CORRESPONDING TO INPUT

overwritten. SCLK should be low during time t , as shown in

6

Figure 30, when SDO/RDY is high.

INPUT SIGNAL

OUTPUT CODE (HEX)

7FFFFF

≥ + 0.5V

/GAIN

23

If the user wants the SDO/RDY signal to go high after reading the

24 bits of the conversion data word, a 25th SCLK can be issued.

The 25th SCLK will force the SDO/RDY signal to go high and

remain high until it falls to signal that a new conversion word is

available. Figure 31 illustrates the behavior of the SDO/RDY

signal when a 25th SCLK is used.

REF

(+0.5V

0

/GAIN)/(2 - 1)

000001

REF

000000

23

(-0.5V

/GAIN)/(2 - 1)

FFFFFF

REF

≤ - 0.5V

/GAIN

800000

REF

DATA

DATA READY

NEW DATA READY

MSB

LSB

0

SDO/RDY

23

22

21

t5

t

4

t

6

3

t

2

SCLK

24

1

t

3

t

7

FIGURE 30. OUTPUT DATA WAVEFORMS USING 24 SCLKS TO READ CONVERSION DATA

FN6954.1

September 9, 2011

15

ISL26132, ISL26134

TABLE 10. INTERFACE TIMING CHARACTERISTICS

PARAMETER

DESCRIPTION

MIN

0

TYP

MAX

50

UNITS

ns

t

SDO/RDY Low to first SLK

SCLK pulsewidth, Low or High

SCLK High to Data Valid

Data Hold after SCLK High

Register Update Time

2

3

4

5

6

7

100

ns

0

ns

39

µs

Conversion Period

SPEED = 1

SPEED = 0

12.5

100

ms

DATA

21

DATA READY

NEW DATA READY

SDO/RDY

SCLK

23

22

0

25TH SCLK FORCES

SDO/RDY HIGH

24

25

1

FIGURE 31. OUTPUT DATA WAVEFORMS FOR SDO/RDY POLLING

DATA READY AFTER CALIBRATION

SDO/RDY

SCLK

23

22

21

0

CALIBRATION BEGINS

1

24

25

26

t

8

FIGURE 32. OFFSET CALIBRATION WAVEFORMS

STANDBY MODE

DATA READY

23

22

21

0

SDO/RDY

SCLK

START

CONVERSION

1

24

t

9

t

11

10

FIGURE 33. STANDBY MODE WAVEFORMS

stored and used to digitally remove the offset error from future

conversion words. The SDO/RDY output will fall to indicate the

completion of the offset calibration operation.

Offset Calibration Control

The offset internal to the ADC can be removed by performing an

offset calibration operation. Offset calibration can be initiated

immediately after reading a conversion word with 24 SCLKs by

issuing two additional SCLKs. The offset calibration operation will

begin immediately after the 26th SCLK occurs. Figure 32

illustrates the timing details for the offset calibration operation.

TABLE 11. SDO/RDY DELAY AFTER CALIBRATION

PARAMETER

MIN

108

808

MAX

109

809

UNITS

ms

t

SPEED = 1

SPEED = 0

8

ms

During offset calibration, the analog inputs are shorted internally

and a regular conversion is performed. This conversion generates

a conversion word that represents the offset error. This value is

FN6954.1

September 9, 2011

16

ISL26132, ISL26134

Standby Mode Operation

Performing Offset Calibration After Standby

Mode

The ADC can be put into standby mode to save power. Standby

mode reduces the power to all circuits in the device except the

crystal oscillator amplifier. To enter the standby mode, take the

SCLK signal high and hold it high after SDO/RDY falls. The

converter will remain in standby mode as long as SCLK is held

high. To return to normal operation, take SCLK back low and wait

for the SDO/RDY to fall to indicate that a new conversion has

completed. Figure 33 and Table 12 illustrate the details of

standby mode.

To perform an offset calibration automatically upon returning

from standby, deliver 2 or more additional SCLKs following a

data read cycle, and then set and hold SCLK high. The device will

remain in Standby as long as SCLK remains high. A calibration

cycle will begin once SCLK is brought low again to resume

normal operation. Additional time will be required to perform the

calibration after returning from Standby. Figure 34 and Table 13

illustrate the details of performing offset calibration after

standby mode.

Supply currents are equal in Standby and Power-down modes

unless a Crystal is used. If the Crystal is used, the Crystal

amplifier is turned ON, even in the standby mode.

TABLE 12. STANDBY MODE TIMING

MIN

PARAMETER

DESCRIPTION

MAX

12.44

99.94

UNITS

ms

t

SCLK High after

SDO/RDY Low

SPEED = 1

SPEED = 0

SPEED = 1

SPEED = 0

SPEED = 1

SPEED = 0

0

9

0

t

Standby Mode Delay

12.5

100

50

10

11

t

SDO/RDY falling edge

after SCLK Low

60

400

410

TABLE 13. OFFSET CALIBRATION TIMING AFTER STANDY

PARAMETER

DESCRIPTION

MIN

108

808

MAX

113

813

UNITS

ms

t

SDO/RDY Low after

SCLK Low

SPEED = 1

SPEED = 0

12

ms

STANDBY MODE

DATA READY AFTER CALIBRATION

23

SDO/RDY

SCLK

23

22

21

0

BEGIN

CALIBRATION

1

24

25

t

12

10

FIGURE 34. OFFSET CALIBRATION WAVEFORMS AFTER STANDBY

FN6954.1

September 9, 2011

17

ISL26132, ISL26134

Operation of PDWN

AVDD

DVDD

PDWN must transition from low to high after both power supplies

have settled to specified levels in order to initiate a correct

power-up reset (Figure 35). This can be implemented by an

external controller or a simple RC delay circuit, as shown in

Figure 36.

PDWN

≥10µs

In order to reduce power consumption, the user can assert the

Power-down mode by bringing PDWN Low as shown in Figure 37.

All circuitry is shut down in this mode, including the Crystal

Oscillator. After PDWN is brought High to resume operation, the

reset delay varies depending on the clock source used. While an

external clock source will resume operation immediately, a

circuit utilizing a crystal will incur about a 20 millisecond delay

due to the inherent start-up time of this type of oscillator.

FIGURE 35. POWER-DOWN TIMING RELATIVE TO SUPPLIES

D

VDD

1kΩ

CONNECT TO

PDWN PIN

2.2nF

FIGURE 36. PDWNDELAY CIRCUIT

START

CONVERSION READY

DATA

CLK

SOURCE

WAKEUP

POWER-DOWN

MODE

t

t14

14

PDWN

SDO/RDY

SCLK

t

11

13

FIGURE 37. POWER-DOWN MODE WAVEFORMS

TABLE 14. POWER-DOWN RECOVERY TIMING

PARAMETER

DESCRIPTION

TYP

7.95

0.16

5.6

UNITS

µs

t

Clock Recovery after PDWN Internal Oscillator

13

High

External Clock Source

µs

4.9152MHz Crystal

Oscillator

ms

t

PDWN Pulse Duration

26

µs (min)

14

FN6954.1

September 9, 2011

18

ISL26132, ISL26134

scale output from the load cell will be 10mV. On a gain of 128x

Applications Information

Power-up Sequence – Initialization and

Configuration

The sequence to properly power-up and initialize the device are

as follows. For details on individual functions, refer to their

descriptions.

and sample rate of 10Sps, the converter noise is 67nV . The

P-P

= 149,250 noise free

converter will achieve 10mV/67nV

P-P

counts across its 10mV input signal. This equates to 14,925

counts per mV of input signal. If five output words are averaged

together this can be improved by √5 to yield √5*14925

counts = 33,370 counts per mV of input signal with an effective

update rate of 2 readings per second.

1. A ramp to specified levels

, D

VDD VDD

THERMOCOUPLE MEASUREMENT

2. Apply External Clock

Figure 39 illustrates the ISL26132 in a thermocouple

application. As shown, the 4.096V reference combined with the

PGA gain set to 128x sets the input span of the converter to

±16mV. This supports the K type thermocouple measurement for

temperatures from -270°C at -6.485mV to +380°C at about

16mV.

3. Pull PDWN High to initiate Reset

4. Device begins conversion

5. SDO/RDY goes low at end of first conversion

OPTIONAL ACTIONS

• Perform Offset Calibration

If a higher temperature is preferred, the PGA can be set to 64x to

provide a converter span of ±32mV. The will allow the converter

to support temperature measurement with the K type

thermocouple up to about +765°C.

• Place device in Standby

• Return device from Standby

• Read on-chip Temperature (applicable to ISL26132 only)

In the circuit shown, the thermocouple is referenced to a voltage

dictated by the resistor divider from the +5V supply to ground.

These set the common mode voltage at about 2.5V. The 5M

resistors provide a means for detection of an open thermocouple.

If the thermocouple fails open or is not connected, the bias

through the 5M resistors will cause the input to the PGA to go to

full scale.

Application Examples

WEIGH SCALE SYSTEM

Figure 38 illustrates the ISL26132 connected to a load cell. The

A/D converter is configured for a gain of 128x and a sample rate

of 10Sps. If a load cell with 2mV/V sensitivity is used, the full

5V

3V

0.1µF

18

1

DVDD

GAIN1

VDD

AVDD

20

16

9

VREF+

CAP

19

24

23

22

GAIN0

SDO/RDY

SCLK

GAIN = 128

0.1µF

10

MICRO

CONTROLLER

CAP

-

+

ISL26132

PDWN

4

XTALOUT

11

12

14

AIN+1

AIN-1

AIN+2

AIN-2

3

XTALIN/CLOCK

SPEED

21

8

13

15

A0

7

VREF-

AGND

TEMP

DGND

GND

2, 5, 6

17

FIGURE 38. WEIGH SCALE APPLICATION

FN6954.1

September 9, 2011

19

ISL26132, ISL26134

+5V

+3V

0.1µF

18

1

DVDD

AVDD

20

ISL21009

4.096V

16

GAIN1

GAIN0

VREF+

5M

19

24

23

22

10nF

SDO/RDY

SCLK

MICRO

CONTROLLER

10k

PDWN

11

AIN+1

4

XTALOUT

TYPE K

12

14

13

AIN-1

AIN+2

AIN-2

3

4.9152

MHz

1µF

XTALIN/CLOCK

SPEED

21

8

A0

5M

15

7

VREF-

AGND

TEMP

DGND

2, 5, 6

17

FIGURE 39. THERMOCOUPLE MEASUREMENT APPLICATION

PCB Board Layout and System

Configuration

The ISL26132,ISL26134 ADC is a very low noise converter. To

achieve the full performance available from the device will

require attention to the printed circuit layout of the circuit board.

Care should be taken to have a full ground plane without

impairments (traces running through it) directly under the chip

on the back side of the circuit board. The analog input signals

should be laid down adjacent (AIN+ and AIN- for each channel) to

achieve good differential signal practice and routed away from

any traces carrying active digital signals. The connections from

the CAP pins to the off-chip filter capacitor should be short, and

without any digital signals nearby. The crystal, if used should be

connected with relatively short leads. No active digital signals

should be routed near or under the crystal case or near the

traces, which connect it to the ADC. The AGND and DGND pins of

the ADC should be connected to a common solid ground plane.

All digital signals to the chip should be powered from the same

supply, as that used for DVDD (do not allow digital signals to be

active high unless the DVDD supply to the chip is alive). Route all

active digital signals in a way to keep distance from any analog

pin on the device (AIN, VREF, CAP, AVDD). Power on the AVDD

supply should be active before the VREF voltage is present.

PCB layout patterns for the chips (ISL26132 and ISL26134) are

found on the respective package outline drawings on pages 22,

and 23.

FN6954.1

September 9, 2011

20

ISL26132, ISL26134

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN6954.1

CHANGE

09/08/11

Power Supply Requirements on page 6 - AIDD - Analog Supply Current - Normal Mode, AVDD = 5, Gain = 1,2

changed TYP and MAX from “6, 7.3” to “7, 8.5”

Power Dissipation, Total Normal Mode, AVDD = 5, Gain = 1, 2 changed from “43.3” to “49.6” mW (Max)

08/22/11

FN6954.0

Initial Release.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL26132, ISL26134

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6954.1

September 9, 2011

21

ISL26132, ISL26134

Package Outline Drawing

M24.173

24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 1, 5/10

A

1

3

7.80 ±0.10

SEE DETAIL "X"

13

24

6.40

PIN #1

I.D. MARK

4.40 ±0.10

2

3

0.20 C B A

1

12

+0.05

-0.06

0.15

B

0.65

TOP VIEW

END VIEW

1.00 REF

H

-

0.05

C

+0.15

-0.10

0.90

1.20 MAX

GAUGE

PLANE

SEATING PLANE

0.10 C

0.25

+0.05

-0.06

C B A

0.25

0.10

5

0°-8°

0.60± 0.15

0.05 MIN

0.15 MAX

M

SIDE VIEW

DETAIL "X"

(1.45)

NOTES:

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

3. Dimensions are measured at datum plane H.

(5.65)

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.08mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead

is 0.07mm.

(0.65 TYP)

(0.35 TYP)

6. Dimension in ( ) are for reference only.

TYPICAL RECOMMENDED LAND PATTERN

7. Conforms to JEDEC MO-153.

FN6954.1

September 9, 2011

22

ISL26132, ISL26134

Package Outline Drawing

M28.173

28 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 1, 5/10

A

1

3

9.70± 0.10

SEE DETAIL "X"

15

28

6.40

PIN #1

I.D. MARK

4.40 ± 0.10

2

3

0.20 C B A

1

14

+0.05

-0.06

0.15

B

0.65

TOP VIEW

END VIEW

1.00 REF

H

-

0.05

+0.15

-0.10

0.90

C

GAUGE

PLANE

1.20 MAX

0.25

SEATING PLANE

0.10 C

+0.05

-0.06

0.25

0.10

0°-8°

0.60 ±0.15

5

0.05 MIN

0.15 MAX

C B A

M

SIDE VIEW

DETAIL "X"

(1.45)

NOTES:

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

3. Dimensions are measured at datum plane H.

(5.65)

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.08mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead

is 0.07mm.

(0.35 TYP)

(0.65 TYP)

6. Dimension in ( ) are for reference only.

TYPICAL RECOMMENDED LAND PATTERN

7. Conforms to JEDEC MO-153.

FN6954.1

September 9, 2011

23


型号：	ISL26132AVZ-T
厂家：	Intersil
描述：	Low-Noise 24-bit Delta Sigma ADC 低噪声24位Σ-Δ ADC
文件：	总23页 (文件大小：971K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL26132AVZ-T [INTERSIL]

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