ISL28217FUZ [INTERSIL]
40V Precision Low Power Operational Amplifiers; 40V精密低功耗运算放大器
| 型号： | ISL28217FUZ |
| 厂家： | 
Intersil |
| 描述： | 40V Precision Low Power Operational Amplifiers |
| 文件： | 总33页 (文件大小：1714K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
40V Precision Low Power Operational Amplifiers
ISL28117, ISL28217, ISL28417
Features
The ISL28117, ISL28217 and ISL28417 are a family of very high
precision amplifiers featuring low noise vs power consumption,
• Low Input Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . ±50µV, Max.
• Superb Offset TC . . . . . . . . . . . . . . . . . . . . . . . 0.6µV/°C, Max.
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±1nA, Max.
• Input Bias Current TC. . . . . . . . . . . . . . . . . . . . .±5pA/°C, Max.
• Low Current Consumption . . . . . . . . . . . . . . . . . . . . . . . 440µA
• Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nV/Hz
• Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 40V
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
• Small Package Offerings in Single, Dual and Quad
• Pb-Free (RoHS Compliant)
low offset voltage, low I
current and low temperature drift
BIAS
making them the ideal choice for applications requiring both high
DC accuracy and AC performance. The combination of precision,
low noise, and small footprint provides the user with outstanding
value and flexibility relative to similar competitive parts.
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ISL28117 single and ISL28217 dual are offered in an
8 Ld SOIC, MSOP and TDFN packages. The ISL28417 is offered
in 14 Ld SOIC, 14 Ld TSSOP and 16 Ld QFN packages. All
devices are offered in standard pin configurations and operate
over the extended temperature range from -40°C to +125°C.
Applications
• Precision Instruments
Related Literature
• See AN1508 “ISL281X7SOICEVAL1Z Evaluation Board
User’s Guide”
• Medical Instrumentation
• Spectral Analysis Equipment
• Active Filter Blocks
• See AN1509 “ISL282X7SOICEVAL2Z Evaluation Board
User’s Guide”
• Thermocouples and RTD Reference Buffers
• Data Acquisition
• Power Supply Control
18
V
= ± 15V
S
16
14
12
10
8
C
1
8.2nF
V
+
-
OUTPUT
6
R
R
2
1
V
IN
+
4
1.84k
4.93k
3.3nF
2
C
2
V
-
0
-0.45
-0.30
-0.15
0 0.15
TC (µV/°C)
OS
0.30
0.45
V
SALLEN-KEY LOW PASS FILTER (10kHz)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. V TEMPERATURE COEFFICIENT (V TC)
OS OS
October 13, 2011
FN6632.8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL28117, ISL28217, ISL28417
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
V
(MAX)
PACKAGE
(Pb-Free)
PKG.
DWG. #
OS
(µV)
ISL28117FBBZ
28117 FBZ
50 (B Grade)
100 (C Grade)
70 (B Grade)
150 (C Grade)
75 (B Grade)
150 (C Grade)
50 (B Grade)
100 (C Grade)
8 Ld SOIC
M8.15E
M8.15E
M8.118
M8.118
L8.3x3A
L8.3x3A
M8.15E
M8.15E
ISL28117FBZ
ISL28117FUBZ
ISL28117FUZ
ISL28117FRTBZ
ISL28117FRTZ
ISL28217FBBZ
ISL28217FBZ
28117 FBZ -C
8117Z
8 Ld SOIC
8 Ld MSOP
8 Ld MSOP
8 Ld TDFN
8 Ld TDFN
8 Ld SOIC
8 Ld SOIC
8117Z -C
8117
-C 8117
28217 FBZ
28217 FBZ -C
Coming Soon
ISL28217FUBZ
8217Z
TBD (B Grade)
150 (C Grade)
70 (B Grade)
150 (C Grade)
120 (B Grade)
200 (C Grade)
8 Ld MSOP
8 Ld MSOP
8 Ld TDFN
8 Ld TDFN
14 Ld SOIC
14 Ld SOIC
M8.118
M8.118
L8.3x3A
L8.3x3A
ISL28217FUZ
ISL28217FRTBZ
ISL28217FRTZ
ISL28417FBBZ
ISL28417FBZ
8217Z -C
8217
-C 8217
28417 FBZ
28417 FBZ -C
MDP0027
MDP0027
Coming Soon
ISL28417FVZ
28417 FVZ
-40 to +125
-40 to +125
14 Ld TSSOP
16 Ld QFN
M14.173
L16.4x4
Coming Soon
ISL28417FRZ
28 417FRZ
ISL28117SOICEVAL1Z
ISL28217SOICEVAL2Z
NOTES:
Evaluation Board
Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28117, ISL28217, ISL28417. For more information on MSL please see
techbrief TB363.
October 13, 2011
2
FN6632.8
ISL28117, ISL28217, ISL28417
Pin Configurations
ISL28117
ISL28117
(8 LD TDFN)
TOP VIEW
(8 LD SOIC, MSOP)
TOP VIEW
NC
-IN
+IN
V -
1
2
3
4
8
7
6
5
NC
V+
NC
NC
1
2
3
4
8
7
6
5
+
-
-IN
+IN
V-
V+
V
- +
V
OUT
OUT
NC
NC
ISL28217
(8 LD SOIC, MSOP)
TOP VIEW
ISL28217
(8 LD TDFN)
TOP VIEW
V
_A
1
2
3
4
8
7
6
5
V+
V
OUT
V
_A
V+
8
1
OUT
-IN_A
+IN_A
V -
_B
-
+
OUT
-IN_A
+IN_A
V-
V
_B
OUT
2
3
4
7
6
- +
-IN_B
+IN_B
-IN_B
+ -
+
-
5 +IN_B
ISL28417
(14 LD SOIC, TSSOP)
TOP VIEW
ISL28417
(16 LD QFN)
TOP VIEW
V
_A
14 V
_D
1
2
OUT
OUT
A
D
-IN_A
13
12
-IN_D
-
-
+
+
-
-
15
14
13
16
3
4
5
6
7
+IN_A
V +
+IN_D
-IN_D
+IN_D
-IN_A
1
2
3
12
11 V -
A
D
+IN_C
10
9
+IN_B
-IN_B
11
10
+IN_A
V +
+
B
+
C
-IN_C
V -
8
V
_C
OUT
V
_B
OUT
B
C
9
4
+IN_B
+IN_C
6
7
8
5
October 13, 2011
FN6632.8
3
ISL28117, ISL28217, ISL28417
Pin Descriptions
ISL28117
(8 LD SOIC,
MSOP, TDFN)
ISL28217
(8 LD SOIC,
MSOP, TDFN)
ISL28417
(14 LD SOIC,
TSSOP)
ISL28417
(16 LD QFN)
PIN NAME EQUIVALENT CIRCUIT
DESCRIPTION
3
-
3
5
-
-
3
-
2
+IN
+IN_A
+IN_B
+IN_C
+IN_D
V-
Circuit 1
Amplifier non-inverting input
-
-
5
4
-
10
12
11
-
9
-
-
11
10
-
4
4
-
Circuit 3
Circuit 1
Negative power supply
Amplifier inverting input
2
-IN
-
2
6
-
2
1
-IN_A
-IN_B
-IN_C
-IN_D
V+
-
6
5
-
9
8
-
-
13
4
12
3
7
8
-
Circuit 3
Circuit 2
Positive power supply
Amplifier output
6
-
-
V
OUT
-
1
7
-
1
15
6
V
V
_A
_B
_C
_D
OUT
-
7
OUT
-
-
8
7
V
OUT
-
14
-
14
13, 16
PD
V
OUT
1, 5, 8
PD
-
NC
PD
-
-
No internal connection
PD
-
Thermal Pad - TDFN and QFN
packages only. Connect thermal
pad to ground or most negative
potential.
V+
V+
V+
OUT
V-
500Ω
500Ω
CAPACITIVELY
COUPLED
ESD CLAMP
IN-
IN+
V-
V-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
October 13, 2011
FN6632.8
4
ISL28117, ISL28217, ISL28417
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications V ± 15V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
S
Electrical Specifications V ± 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
S
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input ESD Diode Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Unused Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ISL28117, ISL28217 and ISL28417 SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
License Statement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Characterization vs Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Outline Drawing (M8.15E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package Outline Drawing (M8.118). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing (L8.3x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Outline Drawing (MDP0027). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package Outline Drawing (M14.173). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing (L16.4x4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
October 13, 2011
5
FN6632.8
ISL28117, ISL28217, ISL28417
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....42V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input current for Input Voltage >V+ or <V-. . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration (1 output at a time). . . . . . . . . . . . . . . . Indefinite
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Machine Model (ISL28217 MSOP only). . . . . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5kV
ESD Rating (ISL28417 SOIC)
Thermal Resistance (Typical)
θ
(°C/W)
120
105
155
160
48
43
73
TBD
TBD
θ
(°C/W)
60
50
50
55
7
2
45
TBD
TBD
JA
JC
8 Ld SOIC ISL28117 (Notes 4, 7) . . . . . . . .
8 Ld SOIC ISL28217 (Notes 4, 7) . . . . . . . .
8 Ld MSOP ISL28117 (Notes 4, 7) . . . . . . .
8 Ld MSOP ISL28217 (Notes 4, 7) . . . . . . .
8 Ld TDFN ISL28117 (Notes 5, 6). . . . . . . .
8 Ld TDFN ISL28217 (Notes 5, 6). . . . . . . .
14 Ld SOIC (Notes 5, 7) . . . . . . . . . . . . . . . .
14 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . .+150°C
JMAX
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (T ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. For θ , the “case temp” location is taken at the package top center.
JC
Electrical Specifications V ± 15V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating
S
CM
O
A
temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 8)
TYP
8
(Note 8)
UNIT
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
V
Input Offset Voltage, SOIC Package
ISL28x17 B Grade
ISL28x17 C Grade
ISL28417 B Grade
ISL28417 C Grade
-50
-110
-100
-190
-70
50
110
100
190
70
OS
4
10
10
-120
-110
-160
-200
-70
120
110
160
200
70
T
= -40°C to +85°C
= -40°C to +125°C
A
T
A
Input Offset Voltage, MSOP Package
ISL28117 B Grade
ISL28117 C Grade
ISL28217 C Grade
ISL28117 B Grade
ISL28217 B Grade
ISL28x17 C Grade
-10
4
-150
-150
-250
-150
-250
-75
150
150
250
150
250
75
10
-10
10
10
Input Offset Voltage, TDFN Package
-160
-70
160
70
-140
-150
-250
140
150
250
October 13, 2011
FN6632.8
6
ISL28117, ISL28217, ISL28417
Electrical Specifications V ± 15V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating
S
CM
O
A
temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
TCV
DESCRIPTION
CONDITIONS
(Note 8)
TYP
0.14
0.14
0.2
(Note 8)
UNIT
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
nA
Input Offset Voltage Temperature
Coefficient; SOIC Package
ISL28x17 B Grade
ISL28x17 C Grade
ISL28417 B Grade
ISL28417 C Grade
ISL28117 B Grade
ISL28117 C Grade
ISL28217 C Grade
ISL28117 B Grade
ISL28217 B Grade
ISL28x17 C Grade
-0.6
-0.9
-0.75
-0.9
-0.8
-1
0.6
0.9
0.75
0.9
0.8
1
OS
0.3
Input Offset Voltage Temperature
Coefficient; MSOP Package
0.1
0.14
0.14
0.1
-1
1
Input Offset Voltage Temperature
Coefficient; TDFN Package
-0.9
-0.7
-1
0.9
0.7
1
0.1
0.1
I
Input Bias Current
-1
0.08
1
B
-1.5
-5
1.5
5
nA
TCI
Input Bias Current Temperature
Coefficient
1
pA/°C
B
I
Input Offset Current
-1.5
-1.85
-3
0.08
1.5
1.85
3
nA
nA
pA/°C
pA/°C
V
OS
TCI
Input Offset Current Temperature
Coefficient
0.42
0.45
OS
ISL28417 SOIC B and C Grade
Guaranteed by CMRR test
-4.0
-13
4.0
13
V
Input Voltage Range
CM
CMRR
Common-Mode Rejection Ratio
V
V
V
= -13V to +13V
120
120
120
120
130
13.5
13.2
13.3
13.1
145
145
dB
dB
dB
dB
dB
V
CM
PSRR
Power Supply Rejection Ratio
= ±2.25V to ±20V
S
A
Open-Loop Gain
= -13V to +13V, R = 10kΩ to ground
143
VOL
O
L
V
Output Voltage High
R
R
R
R
= 10kΩ to ground
= 2kΩ to ground
= 10kΩ to ground
= 2kΩ to ground
13.7
OH
L
L
L
L
V
13.55
-13.7
-13.55
0.44
43
V
V
V
Output Voltage Low
-13.5
-13.2
-13.3
-13.1
0.53
0.68
V
OL
V
V
V
I
Supply Current/Amplifier
mA
mA
mA
V
S
I
Short-Circuit
SC
V
Supply Voltage Range
Guaranteed by PSRR
± 2.25
± 20
SUPPLY
AC SPECIFICATIONS
GBWP Gain Bandwidth Product
Voltage Noise V
A
= 1k, R = 2kΩ
1.5
0.25
10
8.2
8
MHz
V
L
e
0.1Hz to 10Hz
f = 10Hz
µV
P-P
nVp-p
P-P
e
e
e
e
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
n
n
n
n
f = 100Hz
f = 1kHz
f = 10kHz
8
October 13, 2011
FN6632.8
7
ISL28117, ISL28217, ISL28417
Electrical Specifications V ± 15V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating
S
CM
O
A
temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
in
DESCRIPTION
Current Noise Density
Total Harmonic Distortion
CONDITIONS
(Note 8)
TYP
0.1
(Note 8)
UNIT
pA/√Hz
%
f = 1kHz
1kHz, G = 1, V = 3.5V
THD + N
, R = 2kΩ
0.0009
0.0005
O
RMS
L
1kHz, G = 1, V = 3.5V
, R = 10kΩ
%
O
RMS
L
TRANSIENT RESPONSE
SR Slew Rate, V
20% to 80%
A
= 11, R = 2kΩ, V = 4V
0.5
V/µs
ns
OUT
t , t ,
V
L
O
P-P
Rise Time
A
= 1,
V
= 50mV ,
P-P
130
r
f
V
OUT
Small Signal
10% to 90% of V
RL = 10kΩ to V
OUT
CM
Fall Time
90% to 10% of V
A
= 1,
V
= 50mV , RL = 10kΩ to V
130
21
ns
µs
µs
µs
µs
V
OUT P-P CM
OUT
t
Settling Time to 0.1%
10V Step; 10% to V
A
= -1,
= -1,
= -1,
= -1,
V
= 10V , RL = 5kΩ to V
P-P CM
s
V
OUT
OUT
OUT
OUT
OUT
Settling Time to 0.01%
10V Step; 10% to V
A
V
= 10V , RL = 5kΩ to V
P-P CM
24
V
OUT
Settling Time to 0.1%
4V Step; 10% to V
A
V
V
= 4V , RL = 5kΩ to V
P-P CM
13
18
V
OUT
Settling Time to 0.01%
4V Step; 10% to V
A
= 4V , RL = 5kΩ to V
P-P CM
V
OUT
t
Output Positive Overload Recovery Time
Output Negative Overload Recovery Time
A
= -100, V = 0.2
V
V
RL = 2kΩ to V
5.6
µs
µs
OL
V
IN
P-P,
P-P,
CM
A
= -100, V = 0.2
IN
RL = 2kΩ to V
10.6
V
CM
Electrical Specifications V ± 5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating
S
CM
O
A
temperature range, -40°C to +125°C.
MAX
MIN
PARAMETER
DESCRIPTION
CONDITIONS
TYP
8
(Note 8)
UNIT
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
(Note 8)
V
Input Offset Voltage, SOIC Package
ISL28x17 B Grade
ISL28x17 C Grade
ISL28417 B Grade
ISL28417 C Grade
-50
-110
-100
-190
-70
50
OS
110
100
190
70
4
10
10
-120
-110
-160
-200
-70
120
110
160
200
70
T
= -40°C to +85°C
= -40°C to +125°C
A
T
A
Input Offset Voltage, MSOP Package
ISL28117 B Grade
ISL28117 C Grade
ISL28217 C Grade
ISL28117 B Grade
ISL28217 B Grade
ISL28x17 C Grade
-10
4
-150
-150
-250
-150
-250
-75
150
150
250
150
250
75
10
-10
10
10
Input Offset Voltage, TDFN Package
-160
-70
160
70
-140
-150
-250
140
150
250
October 13, 2011
FN6632.8
8
ISL28117, ISL28217, ISL28417
Electrical Specifications V ± 5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating
S
CM
O
A
temperature range, -40°C to +125°C. (Continued)
MAX
MIN
PARAMETER
TCV
DESCRIPTION
CONDITIONS
TYP
0.14
0.14
0.2
(Note 8)
UNIT
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
nA
(Note 8)
Input Offset Voltage Temperature
Coefficient; SOIC Package
ISL28x17 B Grade
ISL28x17 C Grade
ISL28417 B Grade
ISL28417 C Grade
ISL28117 B Grade
ISL28117 C Grade
ISL28217 C Grade
ISL28117 B Grade
ISL28217 B Grade
ISL28x17 C Grade
-0.6
-0.9
-0.75
-0.9
-0.8
-1
0.6
0.9
0.75
0.9
0.8
1
OS
0.3
Input Offset Voltage Temperature
Coefficient; MSOP Package
0.1
0.14
0.14
0.1
-1
1
Input Offset Voltage Temperature
Coefficient; TDFN Package
-0.9
-0.7
-1
0.9
0.7
1
0.1
0.1
I
Input Bias Current
-1
0.18
1
B
-1.5
-5
1.5
5
nA
TCI
Input Bias Current Temperature
Coefficient
1
pA/°C
B
I
Input Offset Current
-1.5
-1.85
-3
0.3
1.5
1.85
3
nA
nA
pA/°C
pA/°C
V
OS
TCI
Input Offset Current Temperature
Coefficient
0.42
0.45
OS
ISL28417 SOIC B and C Grade
-4.0
-3
4.0
3
V
Input Voltage Range
CM
CMRR
Common-Mode Rejection Ratio
V
V
V
= -3V to +3V
120
120
120
120
130
3.5
145
145
dB
dB
dB
dB
dB
V
CM
PSRR
Power Supply Rejection Ratio
= ±2.25V to ±5V
S
A
Open-Loop Gain
= -3.0V to +3.0V, R = 10kΩ to ground
143
3.7
VOL
O
L
V
Output Voltage High
R
R
R
R
= 10kΩ to ground
= 2kΩ to ground
= 10kΩ to ground
= 2kΩ to ground
OH
L
L
L
L
3.2
V
3.3
3.55
-3.7
V
3.1
V
V
Output Voltage Low
-3.5
-3.2
-3.3
-3.1
0.53
0.68
V
OL
V
-3.55
0.44
43
V
V
I
Supply Current/Amplifier
Short-Circuit
mA
mA
mA
S
I
SC
AC SPECIFICATIONS
GBWP Gain Bandwidth Product
A = 1k, R = 2kΩ
1.5
0.25
12
MHz
V
L
e
Voltage Noise
0.1Hz to 10Hz
f = 10Hz
µV
P-P
np-p
e
e
e
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
nV/√Hz
nV/√Hz
nV/√Hz
n
n
n
f = 100Hz
f = 1kHz
8.6
8
October 13, 2011
FN6632.8
9
ISL28117, ISL28217, ISL28417
Electrical Specifications V ± 5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating
S
CM
O
A
temperature range, -40°C to +125°C. (Continued)
MAX
MIN
PARAMETER
DESCRIPTION
Voltage Noise Density
Current Noise Density
TRANSIENT RESPONSE
SR Slew Rate, V
t , t , Small Signal Rise Time
CONDITIONS
TYP
8
(Note 8)
UNIT
(Note 8)
e
f = 10kHz
f = 1kHz
nV/√Hz
pA/√Hz
n
in
0.1
20% to 80%
A =11, R = 2kΩ, V = 4V
0.5
V/µs
ns
OUT
V
L
O
P-P
A
= 1,
V
= 50mV ,
P-P
130
r
f
V
OUT
10% to 90% of V
RL = 10kΩ to V
OUT
CM
Fall Time
90% to 10% of V
A
= 1,
V
= 50mV ,
P-P
130
12
19
7
ns
µs
µs
µs
µs
V
OUT
RL = 10kΩ to V
OUT
CM
t
Settling Time to 0.1%
4V Step; 10% to V
A
= -1,
V
= 4V
,
P-P
s
V
OUT
RL = 5kΩ to V
OUT
Settling Time to 0.01%
4V Step; 10% to V
CM
= 4V
A
= -1,
V
,
P-P
V
OUT
RL = 5kΩ to V
OUT
Output Positive Overload Recovery Time
CM
A = -100, V = 0.2V
V
t
OL
IN
P-P
P-P
RL = 2kΩ to V
CM
Output Negative Overload Recovery Time
A
= -100, V = 0.2V
IN
5.8
V
RL = 2kΩ to V
CM
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, unless otherwise specified.
S
CM
L
140
140
V
= ±15V
S
V
= ±5V
S
ISL28217FBBZ
ISL28217FBBZ
120
100
80
60
40
20
0
120
100
80
60
40
20
0
-50
-30
-10
10
(µV)
30
50
-50
-30
-10
10
(µV)
30
50
V
V
OS
OS
FIGURE 4. V DISTRIBUTION FOR GRADE B
OS
FIGURE 3. V DISTRIBUTION FOR GRADE B
OS
October 13, 2011
FN6632.8
10
ISL28117, ISL28217, ISL28417
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
300
250
200
150
100
50
300
V
= ± 5V
S
V
= ± 15V
S
ISL28217FBZ
ISL28217FBZ
250
200
150
100
50
0
0
-100
-60
-20
20
60
100
-100
-60
-20
20
60
100
V
(µV)
V
(µV)
OS
OS
FIGURE 5. V DISTRIBUTION FOR GRADE C
OS
FIGURE 6. V DISTRIBUTION FOR GRADE C
OS
18
16
14
12
10
8
100
V
= ± 15V
S
V
= ± 15V
S
50
0
6
-50
-100
4
2
0
-0.45
-0.30
-0.15
0 0.15
TC (µV/°C)
OS
0.30
0.45
-50
0
50
100
150
V
TEMPERATURE (°C)
FIGURE 7. V RANGE vs TEMPERATURE
OS
FIGURE 8. TCV vs NUMBER OF AMPLIFIERS
OS
100
50
16
14
12
10
8
V
= ±5V
V
S
= ± 5V
S
0
6
-50
4
2
-100
0
-0.45
-0.30
-0.15
0
0.15
0.30
0.45
-50
0
50
100
150
V
TC (µV/°C)
TEMPERATURE (°C)
OS
FIGURE 9. V RANGE vs TEMPERATURE
OS
FIGURE 10. TCV vs NUMBER OF AMPLIFIERS
OS
October 13, 2011
FN6632.8
11
ISL28117, ISL28217, ISL28417
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
500
400
300
200
100
0
70
V
= ± 15V
V
= ±15V
S
S
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
I
0.5
1.5
2.5
3.5 MORE
-50
0
50
100
150
150
150
+TC (pA/°C)
TEMPERATURE (°C)
B
FIGURE 11. I + RANGE vs TEMPERATURE
FIGURE 12. TCI + vs NUMBER OF AMPLIFIERS
B
B
70
500
400
300
200
100
0
V
= ± 15V
S
V = ±15V
S
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
-50
0
50
100
I -TC (pA/°C)
TEMPERATURE (°C)
B
FIGURE 13. I - RANGE vs TEMPERATURE
B
FIGURE 14. TCI - vs NUMBER OF AMPLIFIERS
B
80
70
60
50
40
30
20
10
0
500
400
300
200
100
0
V
= ±5V
V
S
= ± 5V
S
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
-50
0
50
100
I +TC(pA/°C)
TEMPERATURE (°C)
B
FIGURE 15. I + RANGE vs TEMPERATURE
B
FIGURE 16. TCI + vs NUMBER OF AMPLIFIERS
B
October 13, 2011
FN6632.8
12
ISL28117, ISL28217, ISL28417
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
90
500
400
300
200
100
0
V
= ± 5V
V
= ±5V
S
S
80
70
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
-50
0
50
100
150
I -TC(pA/°C)
TEMPERATURE (°C)
B
FIGURE 17. I - RANGE vs TEMPERATURE
B
FIGURE 18. TCI - vs NUMBER OF AMPLIFIERS
B
90
80
70
60
50
40
30
20
10
0
500
400
300
200
100
0
V
= ±15V
V
S
= ± 15V
S
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
TCI
0.5
1.5
2.5
3.5
-50
0
50
100
150
(pA/°C)
TEMPERATURE (°C)
OS
FIGURE 19. I RANGE vs TEMPERATURE
OS
FIGURE 20. I TC vs NUMBER OF AMPLIFIERS
OS
100
90
80
70
60
50
40
30
20
10
0
500
400
300
200
100
0
V
= ±5V
V
S
= ± 5V
S
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
TCI
0.5
1.5
2.5
3.5
-50
0
50
100
150
(pA/°C)
TEMPERATURE (°C)
OS
FIGURE 21. I RANGE vs TEMPERATURE
OS
FIGURE 22. I TC vs NUMBER OF AMPLIFIERS
OS
October 13, 2011
FN6632.8
13
ISL28117, ISL28217, ISL28417
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
0.7
0.6
0.5
0.4
0.3
20000
V
= ±13V
O
±15V
±2.25V
15000
10000
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 23. SUPPLY CURRENT PER AMP vs TEMPERATURE
FIGURE 24. AV vs TEMPERATURE
OL
-140
-130
-135
-140
-145
-150
-155
-160
V
= ±13V
CM
V
= ±2.25V TO ±20V
S
-145
-150
-155
-50
0
50
100
150
-50
0
50
TEMPERATURE (°C)
100
150
TEMPERATURE (°C)
FIGURE 25. PSRR vs TEMPERATURE
FIGURE 26. CMRR vs TEMPERATURE
60
55
50
45
40
35
30
25
60
55
50
45
40
35
30
25
I
+ @ ±15V
SC
I
- @ ±15V
SC
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 27. POSITIVE SHORT CIRCUIT CURRENT vs TEMPERATURE
FIGURE 28. NEGATIVE SHORT CIRCUIT CURRENT vs TEMPERATURE
October 13, 2011
FN6632.8
14
ISL28117, ISL28217, ISL28417
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
100
100
80
60
40
20
0
V
= ±5V
S
80
60
40
20
0
V
= ±15V
S
+125°C
+125°C
+25°C
-40°C
+25°C
-40°C
-20
-40
-60
-20
-40
-60
-5
-3
-1
1
3
5
-15
-10
-5
0
5
10
15
V
(V)
VCM (V)
CM
FIGURE 29. INPUT V vs INPUT COMMON MODE VOLTAGE,
OS
FIGURE 30. INPUT V vs INPUT COMMON MODE VOLTAGE,
OS
V
= ±15
V = ±5V
S
S
-13.2
-13.4
-13.6
-13.8
-14.0
-14.2
-14.4
14.4
14.2
14.0
13.8
13.6
13.4
13.2
V
R
= ±15V
= 10kΩ
S
V
= ±15V
S
L
R
= 10kΩ
L
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 31. V
vs TEMPERATURE
FIGURE 32. V vs TEMPERATURE,
OL
OH
-13.2
-13.4
-13.6
-13.8
-14.0
-14.2
-14.4
14.4
14.2
14.0
13.8
13.6
13.4
13.2
V
R
= ±15V
= 2kΩ
V
R
= ±15V
= 2kΩ
S
S
L
L
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 33. V vs TEMPERATURE
OH
FIGURE 34. V vs TEMPERATURE
OL
October 13, 2011
FN6632.8
15
ISL28117, ISL28217, ISL28417
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
CM
S
L
250
200
150
100
50
100
V
= ±18.2V
S
AV = 1
0
10
-50
-100
-150
-200
-250
V+ = 36.4V
= 10, R = 100k
R
g
f
AV = 10,000
1
0
1
2
3
4
5
6
7
8
9
10
1
10
100
1k
10k
100k
TIME (s)
FREQUENCY (Hz)
FIGURE 35. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
FIGURE 36. INPUT NOISE VOLTAGE SPECTRAL DENSITY
1
200
180
160
140
V
= ±18.2V
S
AV = 1
PHASE
120
100
80
60
40
20
0
GAIN
-20
-40
-60
R
C
= 10k
L
= 10pF
L
SIMULATION
-80
0.1
-100
1
10
100
1k
10k
100k
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 37. INPUT NOISE CURRENT SPECTRAL DENSITY
FIGURE 38. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R = 10kΩ,
L
C = 10pF
L
220
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
40
20
V
= ±2.5V
S
V
= ±5V
S
PHASE
V
= ±15V
S
GAIN
0
60
-20
-40
-60
R
C
= 10k
L
R
C
= INF
L
L
40
= 100pF
L
= 10pF
SIMULATION
20
-80
SIMULATION
-100
0
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 39. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R = 10kΩ,
FIGURE 40. CMRR vs FREQUENCY, V = ±2.25, ±5V, ±15V
S
L
C = 100pF
L
October 13, 2011
FN6632.8
16
ISL28117, ISL28217, ISL28417
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
120
110
100
90
80
70
60
50
40
30
20
10
0
70
R
= 100, R = 100k
f
g
AV = 1000
AV = 100
AV = 10
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
g
PSRR+ AND PSRR- V = ±2.25V
S
V
C
R
= ±20V
= 4pF
= 10k
S
L
L
R
C
= INF
= 4pF
L
L
V
= 50mV
P-P
OUT
AV = +1
= 1V
V
R
= 10k, R = 100k
f
CM
P-P
g
AV = 1
PSRR+ AND PSRR- V = ±15V
S
R
= OPEN, R = 0
f
g
-10
-10
10k
10
100
1k
100k
1M
10M
10M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 41. PSRR vs FREQUENCY, V = ±5V, ±15V
FIGURE 42. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
S
2
4
2
R
= 10k
L
1
0
R = R = 100k
f
g
0
-1
-2
-3
-4
-5
-6
-7
-8
-2
-4
-6
-8
-10
R = R = 10k
f g
R
= 4.99k
= 1k
L
R = R = 1k
f
g
R
L
R = R = 100
f
g
V
= ±20V
= 10k
S
V
= ±20V
= 4pF
R
= 499
S
L
R
L
L
C
L
C
= 4pF
-12
-14
-16
AV = +1
AV = +2
R
= 100
100k
L
V
= 50mV
P-P
OUT
V
= 50mV
OUT
P-P
10k
FREQUENCY (Hz)
10
100
1k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 43. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE
R /R
FIGURE 44. GAIN vs FREQUENCY vs R
L
f
g
12
10
8
2
1
V
= ±2.25V
S
V
= ±2.5V
= 10k
S
R
L
V
= ±5V
S
AV = +1
= 50mV
0
V
OUT
P-P
6
-1
-2
-3
-4
-5
-6
-7
-8
4
V
= ±15V
S
2
C = 0.01µF
L
C
= 47pF
L
V
= ±20V
S
0
-2
-4
-6
-8
C
= 100pF
C
R
= 4pF
= 10k
L
L
L
C
= 4pF
C
= 270pF
L
L
AV = +1
C
= 470pF
L
V
= 50mV
OUT
P-P
C
= 1000pF
10k
L
10
100
1k
100k
1M
10M
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
FREQUENCY (Hz)
FIGURE 45. GAIN vs FREQUENCY vs C
FIGURE 46. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
L
October 13, 2011
FN6632.8
17
ISL28117, ISL28217, ISL28417
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
180
160
140
120
100
80
2.4
2.0
1.6
1.2
0.8
0.4
0
V
= ±15V, RL = 2k, 10k
= ±5V, RL = 2k, 10k
S
V
= ±15V
S
R -DRIVER CH. = OPEN
V
L
S
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
R -RECEIVING CH. = 10k
L
60
C
= 4pF
L
CL = 4pF
AV = +1
40
AV = +1
V
= 4V
V
= 1V
OUT
P-P
20
SOURCE
P-P
1k
0
10
100
10k
100k
1M
10M
0
10
20
30
40
50
60
70
80
90 100
FREQUENCY (Hz)
TIME (µs)
FIGURE 47. CROSSTALK, V = ±15V
FIGURE 48. LARGE SIGNAL TRANSIENT RESPONSE vs R V = ±5V,
L S
S
±15V
14
12
10
8
0.04
0
60
50
40
30
20
10
0
INPUT
-0.04
-0.08
-0.12
-0.16
-0.20
-0.24
-0.28
OUTPUT @ VS = ±15V
V
= ±15V
S
R
C
= 2k
RL = 10k
CL = 4pF
AV = +1
L
L
6
= 4pF
AV = -100
4
R = 100k, R = 1k
f
g
V
= 50mV
P-P
OUT
V
= 200mV
P-P
IN
2
0
OUTPUT @ V = ±5V
S
-2
-10
0
10
20
30
40
50
60
70
80
90 100
0
5
10
15
20
TIME (µs)
25
30
35
40
TIME (µs)
FIGURE 49. SMALL SIGNAL TRANSIENT RESPONSE, V = ±5V, ±15V
FIGURE 50. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
= ±5V, ±15V
S
V
S
0.24
0.20
0.16
0.12
0.08
0.04
0
4
80
70
60
50
40
30
20
10
0
V
R
= ±15V
= 10k
S
L
2
OUTPUT @ V = ±5V
S
AV = 1
= 50mV
0
V
OUT
P-P
R
C
= 2k
-2
-4
-6
-8
-10
-12
L
L
= 4pF
AV = -100
R = 100k, R = 1k
f
g
V
= 200mV
P-P
IN
INPUT
80
OUTPUT @ V = ±15V
S
-0.04
-0.08
0
10
20
30
40
50
60
70
90 100
1
10
100
1k
10k
TIME (µs)
CAPACITANCE (pF)
FIGURE 51. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
= ±5V, ±15V
FIGURE 52. % OVERSHOOT vs LOAD CAPACITANCE, V = ±15V
S
V
S
October 13, 2011
FN6632.8
18
ISL28117, ISL28217, ISL28417
Applications Information
V+
Functional Description
The ISL28117, ISL28217 and ISL28417 are single, dual and
quad, low noise precision op amps. Both devices are fabricated
in a new precision 40V complementary bipolar DI process. A
super-beta NPN input stage with input bias current cancellation
provides low input bias current (180pA typical), low input offset
voltage (13µV typical), low input noise voltage (8nV/√Hz), and
low 1/f noise corner frequency (~8Hz). These amplifiers also
feature high open loop gain (18kV/mV) for excellent CMRR
500Ω
V
OUT
500Ω
V
R
IN
L
V-
FIGURE 53. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
(145dB) and THD+N performance (0.0005% @ 3.5V
into 2kΩ). A complimentary bipolar output stage enables high
capacitive load drive without external compensation.
, 1kHz
RMS
The series resistors limit the high feed-through currents that can
occur in pulse applications when the input dV/dT exceeds the
0.5V/µs slew rate of the amplifier. Without the series resistors, the
input can forward-bias the anti-parallel diodes causing current to
flow to the output resulting in severe distortion and possible diode
failure. Figure 48 provides an example of distortion free large signal
Operating Voltage Range
The devices are designed to operate over the 4.5V (±2.25V) to
40V (±20V) range and are fully characterized at 10V (±5V) and
30V (±15V). The Power Supply Rejection Ratio typically exceeds
140dB over the full operating voltage range and 120dB
minimum over the -40°C to +125°C temperature range. The
worst case common mode input voltage range over temperature
is 2V to each rail. With ±15V supplies, CMRR performance is
typically >130dB over-temperature. The minimum CMRR
performance over the -40°C to +125°C temperature range is
>120dB for power supply voltages from ±5V (10V) to ±15V (30V).
response using a 4V input pulse with an input rise time of <1ns.
P-P
The series resistors enable the input differential voltage to be equal
to the maximum power supply voltage (40V) without damage.
In applications where one or both amplifier input terminals are at
risk of exposure to high voltages beyond the power supply rails,
current limiting resistors may be needed at the input terminal to
limit the current through the power supply ESD diodes to
20mA max.
Input Performance
Output Current Limiting
The super-beta NPN input pair provides excellent frequency
response while maintaining high input precision. High NPN beta
(>1000) reduces input bias current while maintaining good
frequency response, low input bias current and low noise. Input
bias cancellation circuits provide additional bias current
reduction to <1nA, and excellent temperature stabilization.
Figures 11 through 18 show the high degree of bias current
stability at ±5V and ±15V supplies that is maintained across the
-40°C to +125°C temperature range. The low bias current TC
also produces very low input offset current TC, which reduces DC
input offset errors in precision, high impedance amplifiers.
The output current is internally limited to approximately ±45mA
at +25°C and can withstand a short circuit to either rail as long
as the power dissipation limits are not exceeded. This applies to
only 1 amplifier at a time for the dual op amp. Continuous
operation under these conditions may degrade long term
reliability. Figures 27 and 28 show the current limit variation with
temperature.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28117, ISL28217 and ISL28417 are immune to
output phase reversal, even when the input voltage is 1V beyond
the supplies.
The +25°C maximum input offset voltage (V ) for the “B” grade is
OS
50µV and 100µV for the “C” grade. Input offset voltage temperature
coefficients (V TC) are a maximum of ±0.6µV/°C for the “B” and
OS
±0.9µV/°C for the “C” grade. Figures 3 through 6 show the typical
gaussian-like distribution over the ±5V to ±15V supply range and over
Unused Channels
the full temperature range. The V temperature behavior is smooth
OS
The ISL28217 is a dual op-amp. If the application only requires
one channel, the user must configure the unused channel to
prevent it from oscillating. The unused channel oscillates if the
input and output pins are floating. This results in higher than
expected supply currents and possible noise injection into the
channel being used. The proper way to prevent this oscillation is
to short the output to the inverting input and ground the positive
input, as shown in Figure 54.
(Figures 7 through 10) maintaining constant TC across the entire
temperature range.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, series connected
500Ω current limiting resistors and an anti-parallel diode pair
across the inputs (Figure 53).
-
+
FIGURE 54. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
October 13, 2011
FN6632.8
19
ISL28117, ISL28217, ISL28417
Power Dissipation
License Statement
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
temperature (T
) for all applications to determine if power
JMAX
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
(EQ. 1)
T
= T
+ θ xPD
MAX JA MAXTOTAL
JMAX
The Licensee may not sell, loan, rent, or license the macro-
model, in whole, in part, or in modified form, to anyone outside
the Licensee’s company. The Licensee may modify the macro-
model to suit his/her specific applications, and the Licensee may
make copies of this macro-model for use within their company
only.
where:
• P
is the sum of the maximum power dissipation of
DMAXTOTAL
each amplifier in the package (PD
)
MAX
• PD
PD
for each amplifier can be calculated using Equation 2:
MAX
V
OUTMAX
R
L
------------------------
= V × I
+ (V - V ) ×
OUTMAX
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
(EQ. 2)
MAX
S
qMAX
S
where:
• T
= Maximum ambient temperature
MAX
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
• θ = Thermal resistance of the package
JA
• PD
= Maximum power dissipation of 1 amplifier
MAX
• V = Total supply voltage
S
• I
qMAX
= Maximum quiescent supply current of 1 amplifier
= Maximum output voltage swing of the application
• V
OUTMAX
ISL28117, ISL28217 and ISL28417 SPICE
Model
Figure 55 shows the SPICE model schematic and Figure 56
shows the net list for the ISL28117, ISL28217 and ISL28417
SPICE model for a Grade “B” part. The model is a simplified
version of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC
parameters are VOS, IOS, total supply current and output voltage
swing. The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 6. The AVOL is adjusted
for 155dB with the dominate pole at 0.02Hz. The CMRR is set
(210dB, f = 10Hz). The input stage models the actual device to
cm
present an accurate AC representation. The model is configured
for ambient temperature of +25°C.
Figures 57 through 67 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Closed Loop Gain vs RL, Large Signal Step Response, Open Loop
Gain Phase and Simulated CMRR vs Frequency.
October 13, 2011
FN6632.8
20
ISL28117, ISL28217, ISL28417
.
V++
V++
R3
R4
IEE1
4
5
96E-6
4.45k
4.45k
4
5
CASCODE
CASCODE
Q4
6
7
Q5
3
D1
DX
C4
2
2pF
SUPERB
SUPERB
Vin-
V5
V
-
Q1 Q2
IN
C5
2pF
R1
8
5E11
24
25
EOS
C6
1.2pF
1
IOS
Mirror
Vc
D12
DN
0.1V
R17
VCM
+
-
+
-
Vmid
Q3
0.3nA
9
+
-
IEE
R2
200E-6
290
In+
VOS
5E11
En
13E-6
V
+
IN
V--
VCM
Voltage Noise
Input Stage
V++
V++
D2
DX
D4
DX
G1
G3
G5
L1
13
10
4
15.9159E
+
+
+
-
+
-
+
-
R5
1
R7
C2
R9
V1
V3
17
400pF
2.1E3
R11
1
1.86V
1.86V
1.99e10
-
-
5
11
Vc
Vg
Vmid
Vg
Vc
R12
1
R6
1
R8
R10
C3
Vmid
G4
G6
G2
2.1E3
1.99e10
400pF
18
+
-
+
-
-
+
-
+
-
+
V4
V2
L2
1.86V
1.86V
12
14
VCM
15.9159E
D5
DX
D3
DX
V--
V--
VCM
ST
nd
Mid Supply Ref
Common Mode Gain Stage
1
Gain Stage
2
Gain Stage
V++
D8
DX
D9
DX
G7
V+
V+
+
-
+
E2
R15
90
-
-
+
22
23
V5
DX
DX
D6
20
21
ISY
0.44mA
V
OUT
VOUT
1.12V
Vg
V6
D7
1.12V
R16
90
V-
G8
-
+
+
-
+
-
-
+
D10
DY
D11
DY
-
E3
V-
+
V--
G9
G10
Supply Isolation Stage
Output Stage
FIGURE 55. SPICE SCHEMATIC
October 13, 2011
FN6632.8
21
ISL28117, ISL28217, ISL28417
* source ISL28117_SPICEmodel
R_R7
R_R8
C_C2
C_C3
D_D4
D_D5
V_V3
V_V4
*
VG V++ 1.99e10
* Revision B, November 20th 2009 LaFontaine
* Model for Grade B Noise, supply currents, 210dB
f=10Hz CMRR, 155dB f=0.02Hz AOL, SR = 0.5V/µsec
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
V-- VG 1.99e10
VG V++ 4e-10
V-- VG 4e-10
13 V++ DX
V-- 14 DX
13 VG 1.86
VG 14 1.86
*
*
*
*
*
|
|
|
|
|
-input
*Mid supply Ref
|
|
|
|
+Vsupply
R_R9
R_R10
I_ISY
E_E2
E_E3
*
VMID V++ 2.1E3
|
|
|
-Vsupply
V-- VMID 2.1E3
V+ V- DC 0.44E-3
V++ 0 V+ 0 1
|
|
output
|
.subckt ISL28117subckt Vin+ Vin-V+ V- VOUT
V-- 0 V- 0 1
* source ISL28107subckt
*
*Common Mode Gain Stage with Zero
*Voltage Noise
G_G5
G_G6
R_R11
R_R12
L_L1
L_L2
*
V++ VC VCM VMID 3.162277
V-- VC VCM VMID 3.162277
E_En
IN+ VIN+ 25 0 1
25 0 290
R_R17
D_D12
V_V7
VC 17
18 VC
1
1
24 25 DN
24 0 0.1
17 V++ 15.9159E-3
18 V-- 15.9159E-3
*
*Input Stage
I_IOS
C_C6
IN+ VIN- DC 0.08E-9
IN+ VIN- 1.2E-12
VCM VIN- 5e11
IN+ VCM 5e11
2 VIN- 1 SuperB
3 8 1 SuperB
*Output Stage with Correction Current Sources
G_G7
G_G8
G_G9
G_G10
D_D6
D_D7
D_D8
D_D9
D_D10
D_D11
V_V5
V_V6
R_R15
R_R16
*
VOUT V++ V++ VG 1.11e-2
V-- VOUT VG V-- 1.11e-2
22 V-- VOUT VG 1.11e-2
23 V-- VG VOUT 1.11e-2
VG 20 DX
R_R1
R_R2
Q_Q1
Q_Q2
Q_Q3
V-- 1 7 Mirror
4 6 2 Cascode
5 6 3 Cascode
4 V++ 4.45e3
21 VG DX
Q_Q4
V++ 22 DX
Q_Q5
V++ 23 DX
R_R3
V-- 22 DY
R_R4
5 V++ 4.45e3
V-- 23 DY
C_C4 VIN- 0 2e-12
C_C5 8 0 2e-12
20 VOUT 1.12
VOUT 21 1.12
D_D1
I_IEE
I_IEE1
V_VOS
E_EOS
*
6 7 DX
VOUT V++ 9E1
1 V-- DC 200e-6
V++ 6 DC 96e-6
9 IN+ 8e-6
V-- VOUT 9E1
.model SuperB npn
8 9 VC VMID 1
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
*1st Gain Stage
G_G1
G_G2
R_R5
R_R6
D_D2
D_D3
V_V1
V_V2
*
V++ 11 4 5 8.129384e-2
.model Cascode npn
V-- 11 4 5 8.129384e-2
11 V++ 1
+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140
+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f
+ kf=0 af=0
V-- 11
1
10 V++ DX
V-- 12 DX
10 11 1.86
11 12 1.86
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
*2nd Gain Stage
G_G3
G_G4
V++ VG 11 VMID 2.83e-3
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28117subckt
V-- VG 11 VMID 2.83e-3
FIGURE 56. SPICE NET LIST
October 13, 2011
FN6632.8
22
ISL28117, ISL28217, ISL28417
Characterization vs Simulation Results
100
100
10
1
V
= ±18.2V
S
AV = 1
10
1.0
1.0
10
100
1.0k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 57. CHARACTERIZED INPUT NOISE VOLTAGE
FIGURE 58. SIMULATED INPUT NOISE VOLTAGE
70
60
70
60
50
40
30
20
10
0
R
= 100, R = 100k
f
R
= 100, R = 100k
f
AV = 1000
AV = 100
AV = 10
g
g
AV = 1000
AV = 100
AV = 10
R
= 1k, R = 100k
f
g
R
= 1k, R = 100k
f
g
V
C
R
V
= ±20V
= 4pF
= 10k
V
= ±15V
S
L
S
40
20
C
= 4pF
L
R
V
= 10k
L
L
= 50mV
= 50mV
OUT
P-P
OUT
P-P
R
= 10k, R = 100k
f
R
= 10k, R = 100k
f
g
g
AV = 1
AV = 1
0
R
= OPEN, R = 0
f
g
R
= OPEN, R = 0
f
g
-10
10
-10
10k
10
100
1k
100k
1M
10M
100
1.0k
10k
100k
1.0M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 59. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY
FIGURE 60. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
2
1
R
= 10k
R = 10k
L
L
1
0
0
-2
-4
-6
-8
R
= 4.99k
L
-1
-2
-3
-4
-5
-6
-7
-8
R
= 1k
R
= 4.99k
L
L
R
= 1k
L
V
= ±15V
= 4pF
V
= ±20V
= 4pF
S
R
= 499
S
L
R
= 499
L
C
C
L
L
AV = +1
= 50mV
AV = +1
= 50mV
R
=100
100k
L
R
= 100
V
L
V
OUT
P-P
OUT
P-P
10
100
1k
10k
100k
1M
10M
10
100
1.0k
10k
1.0M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 61. CHARACTERIZED CLOSED LOOP GAIN vs R
FIGURE 62. SIMULATED CLOSED LOOP GAIN vs R
L
L
October 13, 2011
FN6632.8
23
ISL28117, ISL28217, ISL28417
Characterization vs Simulation Results(Continued)
3
2.4
2.0
1.6
1.2
0.8
0.4
0
2
INPUT
V
= ±15V, RL =10k
S
OUTPUT
1
0
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
-1
-2
-3
CL = 4pF
AV = +1
C
= 4pF
L
AV = +1
V
= 4V
OUT
P-P
V
= 4V
OUT
P-P
0
20
40
60
80
100
0
10
20
30
40
50
60
70
80
90 100
TIME (µs)
TIME (µs)
FIGURE 64. SIMULATED LARGE SIGNAL 10V STEP RESPONSE
FIGURE 63. CHARACTERIZED LARGE SIGNAL TRANSIENT
RESPONSE vs R
V
= ±15V
L
S
200
160
200
180
160
140
120
100
80
PHASE
120
60
80
PHASE
40
20
0
GAIN
40
GAIN
-20
-40
-60
-80
-100
R
C
= 10k
L
0
= 10pF
L
SIMULATION
-40
1.0m 10m 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 65. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
FIGURE 66. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
250
200
150
100
50
1m 10m 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 67. SIMULATED CMRR vs FREQUENCY
October 13, 2011
FN6632.8
24
ISL28117, ISL28217, ISL28417
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN6632.8
CHANGE
10/11/11
Figure 27 added “Positive” to Short Circuit Current title
Figure 28 added “Negative” to Short Circuit Current title
Figure 36 y axis label units changed from (nV/ÖHz) to (nV/√Hz)
Figure 37 y axis label units changed from pA/Öhz to pA/√Hz
Figure 31, 33 changed from VOUT vs Temperature to VOH vs Temperature
Figure 32, 34 changed from VOUT vs Temperature to VOL vs Temparature
Table of Contents on page 5 updated to list all package outline drawings
Changed POD M14.15 to MDP0027
Changed TCIos for ISL28417 SOIC grade B and C on pages 7 and 9 from ±3.5pA/C to ±4.0pA/C
10/7/11
1. Pg 2 Ordering Information:
a.Added ordering information rows for ISL28417FBBZ (B grade) and ISL28417FBZ (C grade).
b. Add Table of Contents
2. Pg 5 Abs Max and Thermal Information Tables:
a. Added HBM, MM, and CDM ESD levels for the ‘417
b. Added θ and θ values for the 14 Ld SOIC
JA JC
3. Pg 6 ±15V electrical Specs
a. Added ISL28417 B & C grade VOS and limits
b. Added ISL28417 B & C grade TCVOS and limits
c. Added ISL28417 B & C grade TCIOS and limits
4. Pg 7
a. Converted AVOL limits and units from 3kV/mV Min and 14kV/mV typ to 130dB and 143dB respectively
5. Pg 8 ±5V electrical Specs
a. Added ISL28417 B & C grade VOS and limits
6. Pg 9
a. Added ISL28417 B & C grade TCVOS and limits
b. Added ISL28417 B & C grade TCIOS and limits
c. Converted AVOL limits and units from 3kV/mV Min and 14kV/mV Typ to 130dB and 143dB respectively
7. Pg 17 Applications Information
a. Added Unused Channels paragraph and Figure 54.
7/12/11
FN6632.7
1. Releasing ISL28217FUZ MSOP Grade C package. Remove 'Coming Soon' from Order Information Table
2. Page 5, added: Machine Model (ISL28217 MSOP only). . . . . 300V
3. Under Electrical Spec ±15V and ±5V tables, changed Typical Rise Time and Fall Time from: Rise Time 100ns,
Fall Time 120ns, to: Rise Time 130ns, Fall Time 130ns.
4. Under Electrical Spec ±15V and ±5V table for Vos and TCVos, added in row for ISL28217 MSOP Grade C
package. Added Vos and TCVos limits for 25C and Full Temp.
5. For Typical performance curves for Vos Histograms, added note that histogram is based on ISL28217FBBZ for
Grade B figures and ISL28217FBZ for Grade C figures. (Figures 3-6, added part number label to graph below Vs)
6. Under Electrical Spec ±15V and ±5V tables, changed TYP for Open Loop Gain from 18,000V/mV to
14,000V/mV
12/2/10
FN6632.6
1. Updated “Ordering Information” table on page 2. Removed Coming Soon for ISL28117FRTBZ and
ISL28117FUBZ parts. Added in the Vos (MAX) numbers in those rows (75 and 70 respectively).
2. Corrected part marking in “Ordering Information” table on page 2 for ISL28117FRTZ from 8117 -C to -C 8117
3. Corrected part marking in “Ordering Information” table on page 2 for ISL28217FRTZ from 8217 -C to -C 8217
4. Updated Tape & Reel note in “Ordering Information” table on page 2 from "Add "-T7", "-T7A" or "-T13" suffix
for tape and reel." to new standard "Add "-T*" suffix for tape and reel." The "*" covers all possible tape and reel
options
5. Updated “Electrical Specifications” Table for “V ” on page 6 and “TCVOS” on page 7
OS
a. Added data row for Offset Voltage; MSOP Grade B Package; ISL28117
b. Added data row for Offset Voltage; TDFN Grade B Package; ISL28117
c. Added data row for Input Offset Voltage Temperature Coefficient; MSOP Grade B Package; ISL28117
d. Added data row for Input Offset Voltage Temperature Coefficient; TDFN Grade B Package; ISL28117
6. Removed "Temperature data established by characterization" from common conditions of spec table.
Removed note "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested." from Min Max columns of
spec table. Replaced with new standard note in Min Max columns, “Compliance to datasheet limits is assured
by one or more methods: production test, characterization and/or design.”
October 13, 2011
FN6632.8
25
ISL28117, ISL28217, ISL28417
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev. (Continued)
DATE
REVISION
FN6632.5
CHANGE
8/31/10
1. General changes:
a. Added in Quad devices to the datasheet for SOIC, TSSOP and QFN packages.
b. Added in TDFN packages for single and dual devices.
c. Added in new VOS and TCVOS limits for TDFN packages
d. Added Tja and Tjc Notes for TDFN Package which are “direct attach (Tja) ” and “bottom (Tjc)”
2. Specific changes:
a. Added in ISL28417 to title and front page info on page 1
b. Added in ISL28117FRTZ, ISL28117FRTBZ, ISL28217FRTZ, ISL28217FRTBZ, ISL28417FBZ, ISL28417FVZ,
and ISL28417FRZ packages to Ordering information on page 2 and page 2. Added in -T7 and -T7A tape and
reel extensions where applicable.
c. Added in TDFN, 14 Ld SOIC, 14 Ld TSSOP and 16 Ld QFN to pin configurations on page 3 and page 3.
d. Updated Pin Descriptions tables with new added in packages on page 4.
e. Abs Max Table added in thermal packaging info for TDFN packages on page 6.
f. Electrical Specifications Table - Added two new line items for VOS spec. TDFN package ISL28217 Grade B
limits ±70uV 25C and ±140uV full temp. TDFN package ISL28x17 Grade C limits ±150uV 25C and ±250uV full
temp on page 6 and page 8.
g. Electrical Specifications Table - Added two new line items for TCVOS spec. TDFN package ISL28217 Grade B
limits ±0.7uV/C full temp. TDFN package ISL28x17 Grade C limits ±1uV/C on page 7 and page 9.
h. Added in PODs for L8.3x3A, M14.15, M14.173, and L16.4x4
3/18/10
FN6632.4
1. Updated “Ordering Information” on page 2 by adding two rows for MSOP packages ISL28117FUBZ and
ISL28117FUZ, which are scheduled to release Q2 2010. Added Pinout accordingly.
2. Added POD for MSOP M8.118 to the end of datasheet
3. In “Ordering Information” on page 2, Separated each part number with it's own specific -T7 and -T13 suffix
and removed “Add “-T7” or “-T13” suffix for Tape and Reel.” from Note 1.
4. Updated ±15 and ±5V Electrical Specification table with the following edits:
A) Separated VOS specs for SOIC and MSOP Grade C packages. Added new VOS specs for MSOP Grade C
package.
B) Separated TCVOS specs for SOIC and MSOP Grade C packages. Added new TCVOS specs for MSOP Grade C
package.
5. Added “Thermal Information” on page 6 for ISL28117 MSOP package.
3/3/10
Added “Related Literature” on page 1.
Added Evaluation Boards to “Ordering Information” on page 2.
Added Theta JC values to “Thermal Information” on page 6. Added applicable Theta JC Note 7.
Updated Theta JA for ISL28217 8 Ld SOIC from 115°C/W to 105°C/W.
1/21/10
Part marking in “Ordering Information” on page 2 changed as follows:
ISL28117FBBZ changed from "28117 FBZ -B" to "28117 FBZ"
ISL28117FBZ changed from "28117 FBZ" to "28117 FBZ -C"
ISL28217FBBZ changed from "28217 FBZ -B" to "28217 FBZ"
ISL28217FBZ changed from "28217 FBZ" to "28217 FBZ -C"
12/24/09
11/25/09
On page 10: Changed label in Figure 3 from “V = +5V” to “V = ±5V”
S S
On page 10: Changed label in Figure 4 from “V = +15V” to “V = ±15V”
S
S
Changed Typical VOS spec from “13” to “8” (B Grade), “19” to “4” (C Grade), IB from “0.18” to “0.08, IOS from
“0.3” to “0.08”. Edited Spice Schematic - L1 from “95.4957” to “15.9159E”, R1 from “6k” to 1, R9 from “1” to
“2.1E3”, R10 from “1” to “2.1E3, R12 from “6k” to “1”, L2 from “95.4957” to “15.9159E”. Edited Spice Net List
- Changed Revision from “A” to “B”, Date change from “October 29th 2009” to “November 20th 2009”, added
after AOL “SR = 0.5V/µsec, Input Stage changed in I_IOS from “0.3E-9” to 0.08E-9”, V_VOS “13e-6” to
“8e-6”, Mid supply Ref R_R9 and R_R10 changed “1” to “2.1E3”, Common Mode Gain Stage with Zero change
in G_G5 and G_G6 “5.27046e-15” to “3.162277”, R_R11 and R_R12 “6.3” to “1”, L_L1 and L_L2 “95.4957” to
“15.9159E-3”
11/12/09
FN6632.3
Updated Typical Performance Curves Figure 5, 7, 9, 11, 13, 15, 17 and 19. Added Spice Model and license
statement. Replaced typical application schematic .
October 13, 2011
FN6632.8
26
ISL28117, ISL28217, ISL28417
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev. (Continued)
DATE
REVISION
FN6632.2
CHANGE
10/16/09
On page 2 “Ordering Information”, changed the following:
a) corrected part marking for ISL28117FBBZ from "28117 -B FBZ" to "28117 FBZ -B". Corrected part marking
for ISL28217FBBZ from "28217-B FBZ" to "28217 FBZ -B"
B) Updated package outline drawing to most recent revision (no changes were made to package dimensions;
land pattern was added and dimensions were moved from table onto drawing)
c) Added "Add “-T7” or “-T13” suffix for tape and reel." to the tape and reel Note 1.
d) added Note 3 callout to all parts (Note 3 reads: "For Moisture Sensitivity Level (MSL), please see device
information page for ISL28117, ISL28217. For more information on MSL please see techbrief TB363.")
e) removed "Coming Soon" from ISL28117FBBZ, ISL28117FBZ & ISL28217FBBZ devices
10/08/09
FN6632.1
1. Removed “very” from “...low noise..” 1st sentence, page 1.
2. Removed “Low” from 6th bullet under features, page 1.
3. Modified typical characteristics curves to show conservative performance. Specific channel designations
removed. On temperature curves, changed formatting to indicate range from typical value. Changes include:
a. Removed former Figures 1, 3, 5, 7, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29, 30, 33, 34, 37 & 38 (all
Channel A curves)
b. Replaced former Figures 19, 20, 23, 24, 27, 28, 31, 32, 35, 36, 39 & 40 with new Figures 9 thru 20 (all
“conservative channels”)
c. Added Figures 30, 31, 32
4. Updated TCVos histogram on page 1 to match TCVos histogram Figure 6 on page 7 (same graphic)
5. Added temp labels to Figures 28 & 29
09/03/09
FN6632.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL28117, ISL28217, ISL28417
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
October 13, 2011
27
FN6632.8
ISL28117, ISL28217, ISL28417
Package Outline Drawing (M8.15E)
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
October 13, 2011
FN6632.8
28
ISL28117, ISL28217, ISL28417
Package Outline Drawing (M8.118)
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.036
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
October 13, 2011
FN6632.8
29
ISL28117, ISL28217, ISL28417
Package Outline Drawing (L8.3x3A)
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
( 1.95)
3.00
A
B
( 8X 0.50)
(1.50)
6
PIN 1
INDEX AREA
( 2.90 )
(4X)
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
0.10 C
2X 1.950
C
6X 0.65
0.75 ±0.05
0.08 C
1
PIN #1
INDEX AREA
6
SIDE VIEW
1.50 ±0.10
5
8
C
0 . 2 REF
4
8X 0.30 ±0.05
0.10 M C A B
8X 0.30 ± 0.10
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
7.
October 13, 2011
FN6632.8
30
ISL28117, ISL28217, ISL28417
Small Outline Package Family (SO)
Package Outline Drawing (MDP0027)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
0.010
A1
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
October 13, 2011
FN6632.8
31
ISL28117, ISL28217, ISL28417
Package Outline Drawing (M14.173)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
October 13, 2011
FN6632.8
32
ISL28117, ISL28217, ISL28417
Package Outline Drawing (L16.4x4)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08
4X 1.95
0.65
12X
4.00
A
6
B
13
16
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
1
12
2 . 10 ± 0 . 15
9
4
0.15
(4X)
5
8
0.10 M C A B
TOP VIEW
+0.15
-0.10
16X 0 . 60
4
0.28 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
1.00 MAX
BASE PLANE
( 3 . 6 TYP )
SEATING PLANE
0.08
C
SIDE VIEW
(
2 . 10 )
( 12X 0 . 65 )
5
( 16X 0 . 28 )
( 16 X 0 . 8 )
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
October 13, 2011
FN6632.8
33
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