ISL28413 [INTERSIL]
Single, Dual, Quad General Purpose Micropower, RRIO Operational Amplifier; 单，双，四核通用微功耗， RRIO运算放大器
| 型号： | ISL28413 |
| 厂家： | 
Intersil |
| 描述： | Single, Dual, Quad General Purpose Micropower, RRIO Operational Amplifier |
| 文件： | 总21页 (文件大小：1159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single, Dual, Quad General Purpose Micropower,
RRIO Operational Amplifier
ISL28113, ISL28213, ISL28413 Features
• Low Current Consumption . . . . . . . . . . . . .130µA
• Wide Supply Range. . . . . . . . . . . . . 1.8V to 5.5V
• Gain Bandwidth Product . . . . . . . . . . . . . . 2MHz
• Input Bias Current . . . . . . . . . . . . . . 20pA, Max.
• Operating Temperature Range . ..-40°C to +125°C
• Packages
- ISL28113 (Single) . . . . . . . . . SC70-5, SOT23-5
- ISL28213 (Dual) . . . . . . . . . . . . . MSOP8, SO8
- ISL28413 (Quad). . . . . . . . . SOIC14, TSSOP14
The ISL28113, ISL28213, and ISL28413 are single,
dual, and quad channel general purpose micropower,
rail-to-rail input and output operational amplifiers with
supply voltage range of 1.8V to 5.5V. Key features are
a low supply current of 130µA maximum per channel
at room temperature, a low bias current and a wide
input voltage range, which enables the ISL28x13
devices to be excellent general purpose op-amps for a
wide range of applications.
The ISL28113 is available in the SC70-5 and SOT23-5
packages, the ISL28213 is in the MSOP8, SO8 packages,
and the ISL28413 is in the TSSOP14, SOIC14 packages.
All devices operate over the extended temperature range
of -40°C to +125°C.
Applications*(see page 15)
• Power Supply Control/Regulation
• Process Control
• Signal Gain/Buffers
• Active Filters
• Current Shunt Sensing
• Trans-impedance Amps
Typical Application
RF
100kΩ
LOAD
RIN-
+5V
IN-
-
VOUT
V+
ISL28x13
RSENSE
10kΩ
V-
RIN+
IN+
+
10kΩ
GAIN = 10
RREF+
100kΩ
VREF
SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER
December 22, 2009
FN6728.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL28113, ISL28213, ISL28413
Ordering Information
PART NUMBER
(Note 2)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28113FEZ-T7 (Note 1)
BJA
5 Ld SC-70
P5.049
P5.049
ISL28113FEZ-T7A (Note 1)
ISL28113FHZ-T7 (Note 1)
ISL28113FHZ-T7A (Note 1)
ISL28213FUZ
BJA
5 Ld SC-70
5 Ld SOT-23
5 Ld SOT-23
8 Ld MSOP
8 Ld MSOP
8 Ld SOIC
BCYA
BCYA
8213Z
8213Z
MDP0038
MDP0038
M8.118A
M8.118A
M8.15E
ISL28213FUZ-T7 (Note 1)
ISL28213FBZ
28213 FBZ
28213 FBZ
28213 FBZ
28413 FVZ
28413 FVZ
28413 FVZ
28413 FBZ
28413 FBZ
28413 FBZ
ISL28213FBZ-T7 (Note 1)
ISL28213FBZ-T13 (Note 1)
ISL28413FVZ
8 Ld SOIC
M8.15E
8 Ld SOIC
M8.15E
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
MDP0044
MDP0044
MDP0044
MDP0027
MDP0027
MDP0027
ISL28413FVZ-T7 (Note 1)
ISL28413FVZ-T13 (Note 1)
ISL28413FBZ
ISL28413FBZ-T7 (Note 1)
ISL28413FBZ-T13 (Note 1)
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28113, ISL28213, ISL28413. For more
information on MSL please see techbrief TB363.
Pin Configurations
ISL28113
(5 LD SC-70)
TOP VIEW
ISL28113
(5 LD SOT-23)
TOP VIEW
ISL28213
(8 LD MSOP, 8 LD SOIC)
TOP VIEW
V +
S
V +
S
1
2
8
7
V +
IN+
1
2
3
5
4
OUT
1
2
3
5
OUT_A
IN-_A
IN+_A
S
OUT_B
IN-_B
IN+_B
V -
S
V -
S
OUT
IN-
IN-
IN+
4
3
4
6
5
V -
S
FN6728.3
December 22, 2009
2
ISL28113, ISL28213, ISL28413
Pin Configurations(Continued)
ISL28413
(14 LD TSSOP, 14 LD SOIC)
TOP VIEW
OUT_A
IN-_A
IN+_A
1
2
3
4
5
6
7
14 OUT_D
13 IN-_D
12 IN+_D
V +
11 V -
S
S
IN+_B
IN-_B
OUT_B
10 IN+_C
9
8
IN-_C
OUT_C
Pin Descriptions
PIN NUMBER
TSSOP14,
PIN NAME SC70-5 SOT23-5 MSOP8, SO8 14 LD SOIC
DESCRIPTION
Output
V+
OUT
V-
OUT
4
1
OUT_A
OUT_B
OUT_C
OUT_D
1
7
1
7
8
14
CIRCUIT 1
V -
S
2
2
4
11
Negative supply voltage
V
CAPACITIVELY
TRIGGERED
ESD CLAMP
V-
CIRCUIT 2
IN+
1
3
3
4
Positive Input
Negative Input
V+
IN+
V-
IN+_A
IN+_B
IN+_C
IN+_D
3
5
3
5
10
12
IN-
IN-
IN-_A
IN-_B
IN-_C
IN-_D
2
6
2
6
9
13
CIRCUIT 3
See Circuit 2
V +
5
5
8
4
Positive supply voltage
S
FN6728.3
December 22, 2009
3
ISL28113, ISL28213, ISL28413
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . 20mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.5V
Input Voltage. . . . . . . . . . . . . . . . . .V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 4000V
Machine Model
ISL28113, ISL28213 . . . . . . . . . . . . . . . . . . . . . . 350V
ISL28413. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . 2000V
Thermal Resistance (Typical)
θ
JA (°C/W)
θ
JC (°C/W)
5 Ld SC-70 (Notes 4, 5). . . . . . . .
5 Ld SOT-23 (Notes 4, 5) . . . . . . .
8 Ld MSOP (Notes 4, 5) . . . . . . . .
8 Ld SO Package (Notes 4, 5). . . .
14 Ld TSSOP Package (Notes 4, 5)
14 Ld SOIC Package (Notes 4, 5) .
Ambient Operating Temperature Range. . . . -40°C to +125°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
250
225
180
126
120
90
N/A
N/A
100
90
40
50
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
JA
TB379 for details.
5. For θ , the “case temp” location is the top of the package.
JC
Electrical Specifications V + = 5V, V - = 0V, R = Open, V
= V /2, T = +25°C, unless otherwise specified.
S A
Boldface limits apply over the operating temperature range, -40°C to +125°C,
unless otherwise specified.
S
S
L
CM
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 6)
TYP
0.5
2
(Note 6)
UNIT
DC SPECIFICATIONS
V
Input Offset Voltage
-5
5
6
mV
mV
OS
-6
TCV
Input Offset Voltage
Temperature Coefficient
-40°C to +125°C
10
µV/°C
OS
I
I
Input Offset Current
Input Bias Current
1
3
30
20
pA
pA
pA
pA
pA
V
OS
B
ISL28113
-20
-100
-20
100
20
ISL28213, ISL28413
3
-50
50
Common Mode Input
Voltage Range
- 0.1V
+5.1V
12
Z
C
Input Impedance
Input Capacitance
10
Ω
pF
dB
dB
dB
dB
V
IN
1
72
IN
CMRR
Common Mode Rejection Ratio VCM = -0.1V to 5.1V
70
PSRR
Power Supply Rejection Ratio Vs =1.8V to 5.5V
71
70
V
V
V
Output Voltage Swing, High
Output Voltage Swing, Low
Supply Voltage
R = 10kΩ
4.985
4.993
OH
OL
+
L
4.98
V
R
= 10kΩ
13
15
20
5.5
mV
mV
V
L
1.8
FN6728.3
December 22, 2009
4
ISL28113, ISL28213, ISL28413
Electrical Specifications V + = 5V, V - = 0V, R = Open, V
= V /2, T = +25°C, unless otherwise specified.
S A
Boldface limits apply over the operating temperature range, -40°C to +125°C,
unless otherwise specified.
S
S
L
CM
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
µA
I
Supply Current per Amplifier R = OPEN
90
130
S
L
170
µA
I
I
Output Source Short Circuit
Current
R = 10Ω to V-
-22
16
mA
SC+
SC-
L
Output Sink Short Circuit
Current
R = 10Ω to V+
mA
L
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
V
= ±2.5V
2
MHz
S
A = 100, R = 100kΩ,
V
F
L
R
V
= 1kΩ, R = 10kΩ to
G
CM
e
e
V
Peak-to-Peak Input Noise
Voltage
V
= ±2.5V
14
55
5
µV
P-P
N
P-P
S
f = 0.1Hz to 10Hz
Input Noise Voltage Density
Input Noise Current Density
Differential Input Capacitance
V
= ±2.5V
nV/√(Hz)
fA/√(Hz)
N
S
f = 1kHz
V = ±2.5V
S
i
N
f = 1kHz
C
V
= ±2.5V
1.0
1.3
pF
pF
in
S
f = 1MHz
Common Mode Input
Capacitance
TRANSIENT RESPONSE
SR Slew Rate 20% to 80% V
V
= 0.5V to 4.5V
1
V/µs
ns
OUT
Rise Time, t 10% to 90%
OUT
= ±2.5V
S
t , t , Small Signal
V
100
115
r
f
r
A = +1, V
= 0.05V
,
P-P
V
OUT
Fall Time, t 10% to 90%
f
ns
R = 0Ω, R = 10kΩ,
F
L
L
C = 15pF
t
Settling Time to 0.1%, 4V
Step
V = ±2.5V
S
7.5
µs
s
P-P
A = +1, R = 0Ω,
V
F
R = 10kΩ, C = 1.2pF
L
L
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
FN6728.3
December 22, 2009
5
ISL28113, ISL28213, ISL28413
Typical Performance Curves V = ±2.5V, V = 0V, R = Open, unless otherwise
S
CM
L
specified.
50
40
10,000
V
A
= ±2.5V
= 1
+
V
30
20
1000
10
0
-10
-20
-30
-40
-50
100
10
SIMULATION
-20
-40
0
20
40
60
80
100 120 140
1
10
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
FIGURE 2. INPUT NOISE VOLTAGE SPECTRAL
DENSITY
FIGURE 1. INPUT BIAS CURRENT vs TEMPERATURE
120
100
80
20
120
100
80
20
0
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-20
GAIN
GAIN
60
60
-40
40
40
20
0
-60
20
-80
0
-100
-120
-140
-160
-180
V
R
C
= ±0.9V
= 100k
= 10pF
V
R
C
= ±2.5V
= 100k
= 10pF
+
L
-20
-40
-60
-80
+
L
-20
-40
-60
-80
PHASE
PHASE
L
L
SIMULATION
SIMULATION
0.1
1
10
100
1k
10k 100k 1M 10M 100M
0.1
1
10
100
1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 4. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
R = 100kΩ, C = 100F, V = ±2.5V
FIGURE 3. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
R = 100kΩ, C = 10pF, V = ±0.9V
L
L
S
L
L
S
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
PSRR- V = ±2.5V
S
PSRR- V = ±0.9V
S
PSRR+ V = ±0.9V
S
PSRR+ V = ±2.5V
S
R
C
= INF
= 4pF
= +1
L
L
A
V
SIMULATION
V
= 100mV
CM
P-P
100
1k
10k
100k
1M
10M
0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. CMRR vs FREQUENCY, V = ±2.5
S
FIGURE 6. PSRR vs FREQUENCY, V = ±0.9V, ±2.5V
S
FN6728.3
December 22, 2009
6
ISL28113, ISL28213, ISL28413
Typical Performance Curves V = ±2.5V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
70
60
50
40
30
20
10
0
1
0
R
= 100, R = 100k
f
g
A
= 1000
V
-1
-2
-3
-4
-5
R
= 1k, R = 100k
f
g
A
= 100
= 10
V
= ±2.5V
= 4pF
= 10k
V
+
L
L
C
V
V
= 10mV
= 50mV
OUT
P-P
R
OUT
OUT
P-P
V
= 50mV
OUT
P-P
A
V
V
= 100mV
P-P
V
= ±2.5V
= 4pF
= +1
V
= 200mV
= 500mV
S
OUT
P-P
R
A
= 10k, R = 100k
f
-6
g
C
V
L
OUT
P-P
-7
= 1
A
V
V
V
= 1V
P-P
OUT
-8
R
= 10k
L
R
= OPEN, R = 0
f
g
-10
-9
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE vs CLOSED LOOP
GAIN
FIGURE 8. FREQUENCY RESPONSE vs V
OUT
6
5
1
0
4
3
C
= 1004pF
-1
L
R
= 49.9k
L
-2
-3
-4
-5
-6
-7
-8
-9
C
= 474pF
L
R
= 10k
L
2
C
= 224pF
L
1
R
= 4.99k
L
0
V
C
= ±2.5V
= 4pF
= +1
R
= 1k
+
C
= 104pF
-1
-2
-3
-4
V
= ±2.5V
= 10k
= +1
L
L
S
L
R
A
V
L
C
= 26pF
= 4pF
L
R
= 499
L
A
V
V
OUT
C
= 50mV
V
= 50mV
L
P-P
OUT
P-P
R
= 100
L
10k
1k
100k
FREQUENCY (Hz)
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 10. GAIN vs FREQUENCY vs C
FIGURE 9. GAIN vs FREQUENCY vs R
L
L
1
0
140
120
100
80
-1
-2
-3
-4
-5
-6
-7
-8
-9
V
= ±2.5V
S
60
R -DRIVER = INF
V
= ±2.5V
L
S
R -RECEIVER = 10k
L
C
= 4pF
= 10k
= +1
L
L
V
= ±1.75V
= ±1.25V
= ±0.9V
40
S
C
A
= 4pF
= +1
R
A
V
L
V
V
S
V
V
20
= 50mV
V
= 1V
S
OUT
P-P
SOURCE
P-P
0
10
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 12. CROSSTALK, V = ±2.5V
FIGURE 11. GAIN vs FREQUENCY vs SUPPLY
VOLTAGE
S
FN6728.3
December 22, 2009
7
ISL28113, ISL28213, ISL28413
Typical Performance Curves V = ±2.5V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
30
3
V
= ±2.5V
S
20
2
1
10
V
= ±2.5V
V
= ±0.9V
S
S
R
C
= 10k
= 15pF
= +1
L
L
0
0
R
C
= 10k
= 15pF
= +1
L
L
A
OUT
V
-10
-20
-30
-1
-2
-3
V
= 50mV
P-P
A
OUT
V
V
= RAIL
0
200 400 600 800 1000 1200 1400 1600 1800 2000
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
TIME (ms)
FIGURE 14. LARGE SIGNAL TRANSIENT RESPONSE vs
R V = ±0.9V, ±2.5V
FIGURE 13. SMALL SIGNAL TRANSIENT RESPONSE,
V = ±2.5V
L
S
S
0.5
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
3.0
2.5
2.0
1.5
1.0
0.5
0
INPUT
OUTPUT @ V = ±2.5V
S
0
R
C
= INF
= 15pF
=10
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
L
L
OUTPUT @ V =±0.9V
S
A
V
R
C
= INF
= 15pF
=10
L
L
R = 9.09k, R = 1k
f
g
A
V
OUTPUT @ V =±0.9V
S
R = 9.09k, R = 1k
f
g
OUTPUT @ V = ±2.5V
S
INPUT
-0.1
-0.5
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TIME (ms)
TIME (ms)
FIGURE 15. NEGATIVE OUTPUT OVERLOAD
FIGURE 16. POSITIVE OUTPUT OVERLOAD
RESPONSE TIME, V = ±0.9V, ±2.5V
RESPONSE TIME, V = ±0.9V, ±2.5V
S
S
90
V
L
= ±2.5V
S
R
A
= 10k
= 1
80
70
60
50
40
30
20
10
0
V
V
= 50mV
OUT
P-P
10
100
1k
10k
CAPACITANCE (pF)
FIGURE 17. % OVERSHOOT vs LOAD CAPACITANCE, V = ±2.5V
S
FN6728.3
December 22, 2009
8
ISL28113, ISL28213, ISL28413
Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load, power supply
Applications Information
Functional Description
The ISL28113, ISL28213 and ISL28413 are single, dual
and quad, CMOS rail-to-rail input, output (RRIO)
conditions and ambient temperature conditions. It is
therefore important to calculate the maximum junction
micropower operational amplifiers. They are designed to
operate from single supply (1.8V to 5.5V) or dual supply
(±0.9V to ±2.75V). The parts have an input common
mode range that extends 100mV above and below the
power supply voltage rails. The output stage can swing to
within 15mV of the supply rails with a 10kΩ load.
temperature (T ) for all applications to determine if
JMAX
power supply voltages, load conditions, or package type
need to be modified to remain in the safe operating area.
These parameters are related using Equation 1:
(EQ. 1)
T
= T
+ θ xPD
MAX JA MAXTOTAL
JMAX
Input ESD Diode Protection
where:
• P
All input terminals have internal ESD protection diodes
to both positive and negative supply rails, limiting the
input voltage to within one diode beyond the supply
rails. They also contain back-to-back diodes across the
input terminals (see “Pin Descriptions - Circuit 1” on
page 3). For applications where the input differential
voltage is expected to exceed 0.5V, an external series
resistor must be used to ensure the input currents
never exceed 20mA (see Figure 18).
is the sum of the maximum power
DMAXTOTAL
dissipation of each amplifier in the package (PD
)
MAX
• PD
for each amplifier can be calculated using
MAX
Equation 2:
V
OUTMAX
----------------------------
PD
= V × I
+ (V - V
) ×
MAX
S
qMAX
S
OUTMAX
(EQ. 2)
R
L
where:
• T
MAX
= Maximum ambient temperature
-
• θ = Thermal resistance of the package
JA
V
R
OUT
IN
V
R
IN
+
• PD
= Maximum power dissipation of 1 amplifier
L
MAX
• V = Total supply voltage
S
• I
qMAX
= Maximum quiescent supply current of 1
amplifier
FIGURE 18. INPUT CURRENT LIMITING
Although the amplifier is fully protected, high input slew
rates that exceed the amplifier slew rate (±1V/µs) may
cause output distortion.
• V
= Maximum output voltage swing of the
OUTMAX
application
• R = Load resistance
L
Output Phase Reversal
ISL28113, ISL28213 and ISL28413 SPICE
Model
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28113, ISL28213
and ISL28413 are immune to output phase reversal,
even when the input voltage is 1V beyond the supplies.
Figure 20 shows the SPICE model schematic and
Figure 21 shows the net list for the SPICE model. The
model is a simplified version of the actual device and
simulates important AC and DC parameters. AC
parameters incorporated into the model are: 1/f and
flatband noise, Slew Rate, CMRR, Gain and Phase. The
DC parameters are IOS, total supply current and output
voltage swing. The model uses typical parameters given
in the “Electrical Specifications” Table beginning on
page 4. The AVOL is adjusted for 85dB with the
dominate pole at 100Hz. The CMRR is set 72dB,
f = 35kHz). The input stage models the actual device to
present an accurate AC representation. The model is
configured for ambient temperature of +25°C.
Unused Channels
If the application requires less than all amplifiers one
channel, the user must configure the unused channel(s)
to prevent it from oscillating. The unused channel(s) will
oscillate if the input and output pins are floating. This will
result in higher than expected supply currents and
possible noise injection into the channel being used. The
proper way to prevent this oscillation is to short the
output to the inverting input and ground the positive
input (as shown in Figure 19).
Figures 22 through 31 show the characterization vs
simulation results for the Noise Voltage, Closed Loop
Gain vs Frequency, Large Signal 5V Step Response,
CMRR and Open Loop Gain Phase.
-
+
FIGURE 19. PREVENTING OSCILLATIONS IN
UNUSED CHANNELS
FN6728.3
December 22, 2009
9
ISL28113, ISL28213, ISL28413
LICENSE STATEMENT
The information in this SPICE model is protected under
the United States copyright laws. Intersil Corporation
hereby grants users of this macro-model hereto referred
to as “Licensee”, a nonexclusive, nontransferable licence
to use this model as long as the Licensee abides by the
terms of this agreement. Before using this macro-model,
the Licensee should read this license. If the Licensee
does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to
anyone outside the Licensee’s company. The Licensee
may modify the macro-model to suit his/her specific
applications, and the Licensee may make copies of this
macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND
WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED
OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with
or arising out of the use of this macro-model. Intersil
reserves the right to make changes to the product and
the macro-model without prior notice.
FN6728.3
December 22, 2009
10
ISL28113, ISL28213, ISL28413
En
Vin+
R21
800E3
Voltage Noise Stage
28
V++
V9
DN
D13
29
+
I2
V1
G1A
5E-3
R10
1E9
1E-6V
0.00035V
2
-
+
-
RA1
1
En
R1
R2
10
9
8
DX
D1
Vc
M16
M17
1.0004 1.0004
3
R9
100
14
R22
5E11
4
5
+
-
+
R5
10
R6
10
Vmid
1
-
15
4
DX
D2
CinDiff
1.02pF
R3
10
R4
10
6
11
12
EOS
R23
5E11
RA2
In+
5
R7
1
R8
1
G2A
M14
M15
Vc
Vmid
1
-
+
7
13
Vin-
IOS
+
Cin1
Cin2
I1
5E-3
1E-6V
25E-12
1.26pF 1.26pF
V2
-
V--
V--
VCM
V++
ST
1
Gain Stage
Input Stage
V++
318.329E3
R13
D3
D5
DX
G5
G1
G3
L1
DX
17
19
4
4.5474
+
+
+
-
+
-
+
-
R11
1
V3
V5
21
C2
R15
1E6
0.61V
-
-
5.0nF
0.604V
Vmid
5
16
Vc
Vg
Vg
Vc
R16
1E6
Vmid
R12
1
C3
Vmid
G4
G6
G2
E4
0.604V
22
5.0nF
+
+
-
+
-
+
-
+
V4
V6
+
-
+
L2
-
0.61V
-
-
R14
18
20
4.5474
D6
D4
DX
318.329E3
V--
V--
DX
VCM
VCM
ST
nd
Mid Supply Ref
Common Mode Gain Stage
1
Gain Stage (Cont)
2
Gain Stage
V++
G7
C4
D9
DX
D10
DX
G11
V+
10pF
V+
+
-
+
-
+
E2
R19
50
-
-
+
26
27
V7
R17
5305.32
DX
DX
D7
D8
24
25
ISY
V
OUT
Vg
VOUT
0.08V
90uA
23
V8
Vmid
V-
0.08V
R20
50
R18
G12
5305.32
-
+
+
-
+
-
-
+
D11
DY
-
+
D12
DY
-
E3
V-
+
C3
10pF
V--
G9
G10
G8
Pole Stage
Supply Isolation Stage
Output Stage
FIGURE 20. SPICE SCHEMATIC
FN6728.3
December 22, 2009
11
ISL28113, ISL28213, ISL28413
* source ISL28113_SPICEmodel
*2nd Gain Stage
* Revision C, LaFontaine October 9th 2009
* Model for Noise, supply currents, CMRR 72dB f=35kHz ,AVOL 85dB
f=100Hz
* SR = 1.0V/us, GBWP 2MHz, 2nd pole 3MHz Output voltage clamp
and short ckt I limit
G_G3
G_G4
V_V5
V_V6
D_D5
D_D6
R_R13
R_R14
C_C2
C_C3
*
V++ VG 16 VMID 24.893e-3
V-- VG 16 VMID 24.893e-3
19 VG .604
VG 20 .604
19 V++ DX
*Copyright 2009 by Intersil Corporation
V-- 20 DX
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
VG V++ 318.329e3 TC=0,0
V-- VG 318.329e3 TC=0,0
VG V++ 5E-09 TC=0,0
V-- VG 5E-09 TC=0,0
* Connections:
+input
*
*
*
*
|
|
|
|
|
-input
|
|
|
|
+Vsupply
*Mid supply Ref
|
|
|
-Vsupply
|
|
E_E4
E_E2
E_E3
I_ISY
*
VMID V-- V++ V-- 0.5
V++ 0 V+ 0 1
V-- 0 V- 0 1
output
|
VOUT
*
.subckt ISL28113subckt
* source ISL28113_DS rev1
*
Vin+ Vin- V+
V-
V+ V- DC 90e-6
*Common Mode Gain Stage with Zero
*Voltage Noise
G_G5
G_G6
E_EOS
R_R15
R_R16
R_R22
R_R23
L_L1
L_L2
*
*Pole Satge
G_G7
G_G8
V++ VC VCM VMID 2.5118E-10
V-- VC VCM VMID 2.5118E-10
1 EN VC VMID 1
VC 21 1e6 TC=0,0
22 VC 1e6 TC=0,0
EN VCM 5e11 TC=0,0
VCM VIN- 5e11 TC=0,0
21 V++ 4.5474
E_En
D_D13
V_V9
VIN+ EN 28 0 1
29 28 DN
29 0 .00035
R_R21
*
28 0 800E3 TC=0,0
*Input Stage
M_M14
M_M15
M_M16
M_M17
3 1 5 5 NCHANNELMOSFET
4 VIN- 6 6 NCHANNELMOSFET
11 VIN- 9 9 PMOSISIL
22 V-- 4.5474
12 1 10 10 PMOSISIL
I_I1
7 V-- DC 5e-3
V++ 23 VG VMID 188.49e-6
V-- 23 VG VMID 188.49e-6
23 V++ 5305.32 TC=0,0
V-- 23 5305.32 TC=0,0
23 V++ 10e-12 TC=0,0
V-- 23 10e-12 TC=0,0
I_I2
V++ 8 DC 5e-3
I_IOS
G_G1A
G_G2A
V_V1
V_V2
R_R1
R_R2
R_R3
R_R4
R_R5
R_R6
R_R7
R_R8
R_RA1
R_RA2
C_CinDif
C_Cin1
C_Cin2
*
VIN- 1 DC 25e-12
V++ 14 4 3 1404
V-- 14 11 12 1404
V++ 2 1e-6
R_R17
R_R18
C_C4
C_C5
*
13 V-- 1e-6
3 2 1.0004 TC=0,0
4 2 1.0004 TC=0,0
5 7 10 TC=0,0
7 6 10 TC=0,0
9 8 10 TC=0,0
8 10 10 TC=0,0
13 11 1 TC=0,0
13 12 1 TC=0,0
14 V++ 1 TC=0,0
V-- 14 1 TC=0,0
VIN- EN 1.02E-12 TC=0,0
V-- EN 1.26e-12 TC=0,0
V-- VIN- 1.26e-12 TC=0,0
*Output Stage with Correction Current Sources
G_G9
G_G10
G_G11
G_G12
V_V7
V_V8
D_D7
D_D8
D_D9
D_D10
D_D11
D_D12
R_R19
R_R20
26 V-- VOUT 23 0.02
27 V-- 23 VOUT 0.02
VOUT V++ V++ 23 0.02
V-- VOUT 23 V-- 0.02
24 VOUT .08
VOUT 25 .08
23 24 DX
25 23 DX
V++ 26 DX
V++ 27 DX
V-- 26 DY
V-- 27 DY
VOUT V++ 50 TC=0,0
V-- VOUT 50 TC=0,0
*1st Gain Stage
G_G1
G_G2
V_V3
V_V4
D_D1
D_D2
D_D3
D_D4
R_R9
R_R10
R_R11
R_R12
*
V++ 16 15 VMID 334.753e-3
V-- 16 15 VMID 334.753e-3
17 16 .61
16 18 .61
15 VMID DX
VMID 15 DX
17 V++ DX
V-- 18 DX
15 14 100 TC=0,0
15 VMID 1e9 TC=0,0
16 V++ 1 TC=0,0
V-- 16 1 TC=0,0
.model pmosisil pmos (kp=16e-3 vto=-0.6)
.model NCHANNELMOSFET nmos (kp=3e-3 vto=0.6)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28113subckt
FIGURE 21. SPICE NET LIST
FN6728.3
December 22, 2009
12
ISL28113, ISL28213, ISL28413
Characterization vs Simulation Results
(A) AC sims.dat (active)
10
10,000
V
A
= ±2.5V
= 1
+
V
1000
1.0
100
10
100
1.0
10
100
1.0k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 23. SIMULATED INPUT NOISE VOLTAGE
FIGURE 22. CHARACTERIZED INPUT NOISE VOLTAGE
(A) AC sims.dat (active)
70
70
R
= 100, R = 100k
f
g
A
= 1000
V
60
40
20
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
g
A
= 100
= 10
V
= ±2.5V
= 4pF
= 10k
V
+
L
L
C
R
V
= 50mV
OUT
P-P
A
V
R
= 10k, R = 100k
f
g
A
= 1
V
0
R
= OPEN, R = 0
f
g
-10
-10
10
100
1.0k
10k
100k
1.0M
10M 100M
1k
10k
FREQUENCY (Hz)
100k
1M
10M
100M
10
100
FREQUENCY (Hz)
FIGURE 24. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
FIGURE 25. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
(A) AC sims.dat (active)
3
3
V
OUT
V
= ±2.5V
= ±0.9V
2
1
2
1
S
V
= ±2.5V
S
V
V
IN
S
-0
-1
-2
-3
0
R = 10k
L
C
A
V
= 15pF
= +1
OUT
L
V
R
= 10k
-1
-2
-3
L
L
C
= 15pF
= +10
= RAIL
A
V
V
= RAIL
OUT
0
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
30
TIME (µs)
TIME (ms)
FIGURE 27. SIMULATED LARGE SIGNAL TRANSIENT
RESPONSE vs R , V = ±0.9V, ±2.5V
FIGURE 26. CHARACTERIZED LARGE SIGNAL
TRANSIENT RESPONSE vs R ,
L
S
L
V = ±0.9V, ±2.5V
S
FN6728.3
December 22, 2009
13
ISL28113, ISL28213, ISL28413
Characterization vs Simulation Results(Continued)
(A) AC sims.dat (active)
200
160
120
80
120
100
80
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
GAIN
60
40
20
0
V
R
= ±2.5V
= 100k
= 10pF
+
L
-20
-40
-60
-80
PHASE
40
C
L
SIMULATION
0
0.01 0.1
1.0
10
100 1.0k 10k 100k 1.0M 10M 100M
FREQUENCY (Hz)
0.1
1
10
100
1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 28. SIMULATED (DESIGN) OPEN-LOOP GAIN,
PHASE vs FREQUENCY
FIGURE 29. SIMULATED (SPICE) OPEN-LOOP GAIN,
PHASE vs FREQUENCY
(A) AC sims.dat (active)
80
80
70
60
50
40
30
20
60
40
20
0
10
SIMULATION
0
0.01 0.1
1.0
10 100 1.0k 10k 100k 1.0M 10M 100M
FREQUENCY (Hz)
0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 31. SIMULATED (SPICE) CMRR
FIGURE 30. SIMULATED (DESIGN) CMRR
FN6728.3
December 22, 2009
14
ISL28113, ISL28213, ISL28413
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
Web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
12/16/09
FN6728.3
Removed “Coming Soon” from MSOP package options in the “Ordering
Information” on page 2.
Updated the Theta JA for the MSOP package option from 170°C/W to 180°C/W
on page 4.
11/17/09
11/12/09
10/26/09
FN6728.2
FN6728.1
FN6728.0
Removed “Coming Soon” from SC70 and SOT-23 package options in the
“Ordering Information” on page 2.
Changed theta Ja to 250 from 300. Added license statement (page 10) and
reference in spice model (page 12).
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL28113, ISL28213, ISL28413
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
FN6728.3
December 22, 2009
15
ISL28113, ISL28213, ISL28413
Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e1
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.043
0.004
0.039
0.012
0.010
0.009
0.009
0.085
0.094
0.053
MIN
0.80
0.00
0.80
0.15
0.15
0.08
0.08
1.85
1.80
1.15
MAX
1.10
0.10
1.00
0.30
0.25
0.22
0.20
2.15
2.40
1.35
NOTES
5
1
4
A
A1
A2
b
0.031
0.000
0.031
0.006
0.006
0.003
0.003
0.073
0.071
0.045
-
-
-
-
E
C
L
C
E1
L
2
3
b
b1
c
e
6
6
3
-
C
L
c1
D
0.20 (0.008) M
C
C
C
L
E
E1
e
3
-
SEATING
PLANE
0.0256 Ref
0.0512 Ref
0.010 0.018
0.65 Ref
1.30 Ref
0.26 0.46
A2
A1
A
e1
L
-
-C-
4
-
L1
L2
0.017 Ref.
0.420 Ref.
0.15 BSC
0.10 (0.004)
C
0.006 BSC
o
o
o
o
0
8
0
8
-
α
N
b
WITH
5
5
5
PLATING
b1
R
0.004
0.004
-
0.10
0.15
-
R1
0.010
0.25
c
c1
Rev. 3 7/07
NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
GAUGE PLANE
SEATING
PLANE
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
L
C
α
L2
L1
4X θ1
VIEW C
0.4mm
0.75mm
2.1mm
0.65mm
TYPICAL RECOMMENDED LAND PATTERN
FN6728.3
December 22, 2009
16
ISL28113, ISL28213, ISL28413
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
SOT23-5
6
4
N
SYMBOL
SOT23-6
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
6
TOLERANCE
MAX
A
A1
A2
b
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
5
±0.05
E1
E
±0.15
2
3
±0.05
0.15
2X
C
D
c
±0.06
1
2
3
0.20
2X
C
D
Basic
5
e
E
Basic
E1
e
Basic
0.20
C
A-B
D
M
B
b
NX
Basic
e1
L
Basic
±0.10
L1
N
Reference
Reference
Rev. F 2/07
0.15
2X
C
A-B
1
3
D
NOTES:
C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
A2
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
A1
0.10
NX
C
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
(L1)
H
A
GAUGE
PLANE
0.25
c
+3°
-0°
L
0°
FN6728.3
December 22, 2009
17
ISL28113, ISL28213, ISL28413
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
A
3.0±0.1
8
0.25 CAB
4.9±0.15
DETAIL "X"
0.18 ± 0.05
3.0±0.1
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
GAUGE
PLANE
H
C
0.25
SEATING PLANE
0.10 ± 0.05
0.33 +0.07/ -0.08
0.08 C AB
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
1. Dimensions are in millimeters.
4.40
3.00
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
0.65
0.40
4. Plastic interlead protrusions of 0.25mm max per side are not
included.
1.40
5. Dimensions “D” and “E1” are measured at Datum Plane “H”.
6. This replaces existing drawing # MDP0043 MSOP 8L.
TYPICAL RECOMMENDED LAND PATTERN
FN6728.3
December 22, 2009
18
ISL28113, ISL28213, ISL28413
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN6728.3
December 22, 2009
19
ISL28113, ISL28213, ISL28413
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN6728.3
December 22, 2009
20
ISL28113, ISL28213, ISL28413
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
0.25 M C A B
D
A
(N/2)+1
MILLIMETERS
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
2X
1
(N/2)
c
N/2 LEAD TIPS
B
D
TOP VIEW
E
Basic
E1
e
±0.10
Basic
0.05
H
e
L
±0.15
C
L1
Reference
Rev. F 2/07
SEATING
PLANE
NOTES:
0.10 M C A B
b
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
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FN6728.3
December 22, 2009
21
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