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ISL3034E [INTERSIL]

4-Channel And 6-Channel High Speed, Auto-direction Sensing Logic Level Translators; 4通道和6通道高速，自动方向感应逻辑电平转换器
ISL3034E
型号： ISL3034E
厂家： Intersil    Intersil
描述：

4-Channel And 6-Channel High Speed, Auto-direction Sensing Logic Level Translators
4通道和6通道高速，自动方向感应逻辑电平转换器

转换器 电平转换器
文件： 总16页 (文件大小：501K)
中文：  中文翻译
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ISL3034E, ISL3035E, ISL3036E  
®
Data Sheet  
March 31, 2009  
FN6492.0  
4-Channel And 6-Channel High Speed,  
Auto-direction Sensing Logic Level  
Translators  
Features  
• Best-In-Class ESD Protection: ±15kV IEC61000-4-2 ESD  
Protection on ALL Input, Output, and I/O Lines  
The ISL3034E, ISL3035E, ISL3036E 4- and 6-channel  
bi-directional, auto-direction sensing, level translators  
provide the required level shifting in multi-voltage systems at  
data transfer rates up to 100Mbps. The auto-direction  
sensing feature makes the ISL3034E, ISL3035E, ISL3036E  
ideally suited for memory-card level translation (or for  
generic four to six channel level translation) especially if  
• 100Mbps Guaranteed Data Rate  
• Four (ISL3036) or Six (ISL3034, ISL3035) Bi-directional  
Channels  
• Auto-direction Sensing Eliminates Direction Control Logic  
Pins  
• Enable Input (ISL3034E, ISL3036E) for Logic Control of  
Low Power SHDN Mode  
bit-by-bit direction control is desired. The V  
and V supply  
L
CC  
voltages set the logic levels on either side of the device.  
Logic signals present on the IC’s V side appear as higher  
• Clock Return Output (ISL3035E)  
L
voltage logic signals on the IC’s V  
side and vice versa.  
• Compatible with 4mA Input Drivers or Larger  
CC  
The ISL3035E features a CLK_RET output that returns the  
same clock signal applied to the CLK_V input, but with  
• +1.35V ≤ V ≤ +3.2V and +2.2V ≤ V  
≤ +3.6V Supply  
L
CC  
L
Voltage Range  
timing that mimics the data returning from the I/OV  
CC  
inputs.  
• Pb-Free (RoHS Compliant)  
The ISL3034E, ISL3035E, ISL3036E operate at full speed  
with external input drivers that source as little as 4mA output  
current. Each I/O channel is pulled up to V  
• 16Ld µTQFN (2.6mmx1.8mm), 16 Ld TQFN (3mmx3mm),  
and 14 Ld QFN (3.5mmx3.5mm) Packages  
or V by an  
CC  
L
internal 30µA current source, allowing the ISL3034E,  
ISL3035E, ISL3036E to be driven by either push-pull or  
open-drain drivers.  
Applications  
• Simplifies the Interface Between Two Logic ICs Operating  
at Different Supply Voltages  
The ISL3034E and ISL3036E include an enable (EN) input  
that when driven low places the IC into a low-power  
shutdown mode, with all I/O lines tri-stated. All versions  
feature an automatic shutdown mode, that places the part in  
• SD Card and MiniSD Card Level Translation  
• MMC (Multi Media Card) Level Translation  
• Memory Stick Card Level Translation  
the same shutdown state when V  
is less than V . The  
L
CC  
and I/OV during shutdown are chosen by  
states of I/OV  
CC  
L
selecting the appropriate product (see Table 1).  
Typical Operating Circuit  
+1.8V  
+3.3V  
The ISL3034E, ISL3035E, ISL3036E operate with V  
CC  
0.1µF  
0.1µF 1µF  
voltages from +2.2V to +3.6V and V voltages from +1.35V  
L
to +3.2V, making them ideal for data transfer between  
low-voltage microcontrollers or ASICs and higher voltage  
components.  
V
V
L
CC  
+1.8V  
+3.3V  
SD CARD  
ISL3035E  
SYSTEM  
CONTROLLER  
DAT3  
DAT2  
DAT1  
DAT0  
CMD  
I/OV  
I/OV  
DAT3  
L
L
L
L
L
CC  
CC  
CC  
CC  
CC  
CC  
TABLE 1. SUMMARY OF FEATURES  
I/OV  
I/OV  
I/OV  
I/OV  
I/OV  
DAT2  
DAT1  
DAT0  
CMD  
I/OV  
I/OV  
I/OV  
DATA  
RATE  
NUMBER  
OF  
I/OV  
CC  
SHDN  
STATE  
PART  
EN  
I/OV SHDN  
L
NUMBER (Mbps) CHANNELS PIN?  
STATE  
CLOCK  
CLOCK_IN  
CLK_V CLK_V  
L
CLOCK  
ISL3034E  
ISL3035E  
ISL3036E  
100  
100  
100  
6
6
4
YES  
16.5kΩ  
16.5kΩ  
CLK_RET  
GND  
to V  
to V  
L
CC  
NO  
75kΩ to V  
High  
Impedance  
L
GND  
GND  
YES  
16.5kΩ  
16.5kΩ  
to V  
to V  
L
CC  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2009. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
ISL3034E, ISL3035E, ISL3036E  
Ordering Information  
PART  
NUMBER  
PART  
MARKING  
TEMP. RANGE  
(°C)  
PACKAGE  
(Pb-free)  
PKG.  
DWG. #  
ISL3034EIRTZ (Note 1)  
ISL3034EIRTZ-T (Notes 1, 3)  
ISL3034EIRUZ-T (Notes 2, 3)  
ISL3035EIRTZ (Note 1)  
ISL3035EIRTZ-T (Notes 1, 3)  
ISL3035EIRUZ-T (Notes 2, 3)  
ISL3036EIRZ-T (Notes 1, 3)  
ISL3036EIRUZ-T (Notes 2, 3)  
NOTES:  
34TZ  
34TZ  
GAE  
35TZ  
35TZ  
GAF  
36EZ  
GAK  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
16 Ld TQFN  
L16.3x3A  
16 Ld TQFN  
16 Ld µTQFN  
16 Ld TQFN  
16 Ld TQFN  
16 Ld µTQFN  
14 Ld QFN  
L16.3x3A  
L16.2.6x1.8A  
L16.3x3A  
L16.3x3A  
L16.2.6x1.8A  
L14.3.5x3.5  
L16.2.6x1.8A  
16 Ld µTQFN  
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte  
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil  
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-  
020.  
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu  
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products  
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
3. Please refer to TB347 for details on reel specifications.  
Pinouts  
ISL3034E  
(16 LD TQFN)  
TOP VIEW  
ISL3034E  
(16 LD µTQFN)  
TOP VIEW  
I/OV 1  
L
1
2
3
4
12 I/OV 6  
L
I/OV 1  
L
I/OV 6  
L
1
2
3
4
12  
V
L
11  
10  
9
EN  
THERMAL  
PAD  
V
L
EN  
I/OV 2  
L
I/OV 5  
L
11  
10  
9
I/OV 3  
L
I/OV 4  
L
I/OV 2  
L
I/OV 5  
L
I/OV 4  
L
I/OV 3  
L
FN6492.0  
March 31, 2009  
2
ISL3034E, ISL3035E, ISL3036E  
Pinouts (Continued)  
ISL3035E  
(16 LD TQFN)  
TOP VIEW  
ISL3035E  
(16 LD µTQFN)  
TOP VIEW  
I/OV 1  
L
1
2
3
4
12 CLK_V  
L
I/OV 1  
L
CLK_V  
1
2
3
4
12  
L
V
L
11  
10  
9
CLK_RET  
THERMAL  
PAD  
V
L
CLK_RET  
11  
10  
9
I/OV 2  
L
I/OV 5  
L
I/OV 2  
L
I/OV 5  
L
I/OV 3  
L
I/OV 4  
L
I/OV 4  
L
I/OV 3  
L
ISL3036E  
(14 LD QFN)  
TOP VIEW  
ISL3036E  
(16 LD µTQFN)  
TOP VIEW  
1
14  
2
3
4
5
6
13 I/OV  
1
2
3
4
I/OV 1  
CC  
L
I/OV 1  
L
I/OV  
I/OV  
I/OV  
I/OV  
1
2
3
4
1
2
3
4
12  
CC  
CC  
CC  
CC  
12  
11  
10  
9
I/OV 2  
I/OV  
I/OV  
I/OV  
NC  
L
CC  
CC  
CC  
I/OV 2  
L
THERMAL  
PAD  
11  
10  
9
I/OV 3  
L
I/OV 3  
L
I/OV 4  
L
I/OV 4  
L
NC  
7
8
Pin Descriptions  
NAME  
FUNCTION  
NOTES  
V
V
V
power supply, +2.2V to +3.6V. Decouple V to ground with a 0.1µF capacitor.  
For normal operation, V  
For normal operation, V  
> V .  
L
CC  
CC  
CC  
CC  
V
logic supply, +1.35V to +3.2V. Decouple V to ground with a 0.1µF capacitor.  
> V .  
L
L
L
L
CC  
GND  
EN  
Ground Pin  
±15kV IEC61000 ESD Protected Enable Input. Logic “0” puts the device in shutdown. Logic ISL3034E and ISL3036E only  
“1” enables the device.  
I/OV  
x
±15kV IEC61000 ESD Protected Input/Output channel referenced to V  
.
CC  
CC  
CLK_V  
±15kV IEC61000 ESD Protected Input/Output clock channel referenced to V  
.
CC  
ISL3035E only  
CC  
I/OV x  
±15kV IEC61000 ESD Protected Input/Output channel referenced to V .  
L
L
CLK_V  
IEC61000 ESD Protected Input clock channel referenced to V .  
ISL3035E only  
ISL3035E only  
L
L
CLK_RET IEC61000 ESD Protected Output clock channel referenced to V .  
L
FN6492.0  
March 31, 2009  
3
ISL3034E, ISL3035E, ISL3036E  
Absolute Maximum Ratings  
Thermal Information  
(All voltages referenced to GND.)  
Thermal Resistance (Typical)  
θ
(°C/W)  
θ
(°C/W)  
JC  
JA  
V
, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V  
CC  
L
14 Ld QFN Package (Notes 4, 5). . . . .  
16 Ld TQFN Package (Notes 4, 5). . . .  
16 Ld µTQFN Package (Note 4) . . . . .  
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C  
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . see link below  
http://www.intersil.com/pbfree/Pb-FreeReflow.asp  
46  
74  
93  
6
10  
44  
I/OV _, CLK_V . . . . . . . . . . . . . . . . . . . . -0.3V to (V  
I/OV _, CLK_V , CLK_RET. . . . . . . . . . . . . . . -0.3V to (V + 0.3V)  
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V  
Short-Circuit Duration I/OV _, I/OV _, CLK_V  
+ 0.3V)  
CC CC CC  
L
L
L
,
CC  
L
CC  
CLK_RET to GND. . . . . . . . . . . . . . . . . . . . . . . . . . Continuous  
Operating Conditions  
Operating Temperature Range . . . . . . . . . . . . . . . . -40°C to +85°C  
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and  
result in failures not covered by warranty.  
NOTES:  
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air, and with “direct attach” features for  
JA  
the QFN and TQFN. See Tech Brief TB379 for details.  
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.  
JC  
Electrical Specifications  
V
V
= +2.2V to +3.6V, V = +1.35V to +3.2V, EN = V , unless otherwise noted. Typical values are at  
L L  
CC  
CC  
= +3.3V, V = +1.8V and T = +25°C. (Note 6).  
L
A
TEMP  
(°C)  
MIN  
(Note 8) TYP  
MAX  
(Note 8) UNITS  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
POWER SUPPLIES  
V
V
V
Supply Range  
V
(Note 6)  
(Note 6)  
Full  
Full  
Full  
Full  
Full  
1.35  
-
-
3.2  
3.6  
30  
V
L
L
Supply Range  
V
2.2  
V
CC  
CC  
CC  
Quiescent Supply Current  
I
I/OV  
I/OV  
= V , I/OV = V  
CC  
-
-
-
18  
12  
-
µA  
µA  
µA  
CC  
CC  
CC  
L
L
L
V Quiescent Supply Current  
I
= V , I/OV = V  
CC  
18  
L
VL  
L
V
Shutdown Supply Current  
I
EN = GND or V > V + 0.7V; ISL3034E and  
L CC  
2.5  
CC  
CCSD  
ISL3036E Only  
V
> V  
+ 0.7V; ISL3035E Only  
CC  
Full  
Full  
-
-
-
-
2.5  
4
µA  
µA  
L
V Shutdown Supply Current  
I
EN = GND or V > V  
L
+ 0.7V; ISL3034E and  
CC  
L
LSD  
ISL3036E Only  
V
> V  
+ 0.7V; ISL3035E Only  
Full  
Full  
-
-
-
4
2
µA  
µA  
L
CC  
I/OV , CLK_V  
CC  
Tri-State  
I
V > V  
+ 0.7V, V = 0V or V , ISL3035E Only  
CC  
0.1  
CC  
LKG  
L
CC  
O
Leakage Current  
EN Input Current  
I
ISL3034E and ISL3036E Only  
Full  
Full  
-
1
µA  
V
IN_EN  
V
High  
- V  
Shutdown Threshold  
Shutdown Threshold  
V
_
V
rising  
-0.2  
0.05V  
L
0.7  
L
CC  
CC  
TH H  
CC  
V
- V  
V
V
falling  
Full  
Full  
Full  
-0.2  
10  
0.1V  
L
0.7  
23  
V
L
TH_L  
CC  
Low  
I/OV , I/OV Pull-up  
R
EN = GND; ISL3034E and ISL3036E Only  
16.5  
75  
kΩ  
kΩ  
CC  
L
PU_SD1  
PU_SD2  
Resistance During Shutdown  
I/OV , CLK_V CLK_RET  
L ,  
R
V
> (V + 0.7V); ISL3035E Only  
CC  
45  
105  
L
L
Pull-up Resistance During  
Shutdown  
I/OV , CLK_V , CLK_RET Pull-  
up Current  
I
EN = V , I/OV = GND  
Full  
Full  
Full  
20  
20  
-
-
-
75  
75  
-
µA  
µA  
kΩ  
L_  
L
VL_PU  
L
L
I/OV  
CC_  
, CLK_V  
Pull-up  
I
EN = V , I/OV  
= GND  
CC  
CC  
VCC_PU  
L
Current  
I/OV to I/OV  
DC Resistance  
R
ON  
3
L
CC  
FN6492.0  
March 31, 2009  
4
ISL3034E, ISL3035E, ISL3036E  
Electrical Specifications  
V
V
= +2.2V to +3.6V, V = +1.35V to +3.2V, EN = V , unless otherwise noted. Typical values are at  
CC  
CC  
L
L
= +3.3V, V = +1.8V and T = +25°C. (Note 6). (Continued)  
L
A
TEMP  
(°C)  
MIN  
(Note 8) TYP  
MAX  
(Note 8) UNITS  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
ESD PROTECTION  
All Input and I/O Pins From Pin to  
GND  
IEC61000-4-2 Air-Gap Discharge  
IEC61000-4-2 Contact Discharge  
Human Body Model  
25  
25  
25  
25  
25  
-
-
-
-
-
±15  
>±9  
-
-
-
-
-
kV  
kV  
kV  
kV  
V
±15  
All Pins  
HBM, per JEDEC  
>±12  
±1300  
Machine Model, per JEDEC  
LOGIC-LEVEL THRESHOLDS  
I/OV , CLK_V Input Voltage  
High Threshold  
V
(Note 7)  
(Note 7)  
(Note 7)  
(Note 7)  
Full  
Full  
Full  
Full  
-
0.15  
-
-
-
-
-
V
L
- 0.2  
-
V
V
V
V
L
L
IHL  
I/OV , CLK_V Input Voltage  
V
L
L
ILL  
Low Threshold  
I/OV , CLK_V  
CC  
High Threshold  
Input Voltage  
Input Voltage  
V
V
- 0.4  
CC  
CC  
IHC  
I/OV , CLK_V  
CC  
V
0.2  
-
CC  
ILC  
Low Threshold  
EN Input Voltage High Threshold  
EN Input Voltage Low Threshold  
V
Full  
Full  
Full  
-
-
-
-
V
- 0.4  
L
V
V
V
IH  
V
0.4  
-
-
IL  
I/OV , CLK_RET Output Voltage  
L
High  
V
I
I
I
I
= 20µA, I/OV  
≥ V  
- 0.4V  
2/3 V  
OHL  
OH  
OL  
OH  
OL  
CC  
CC  
L
I/OV , CLK_RET Output Voltage  
L
Low  
V
= 20µA, I/OV  
≤ 0.2V  
Full  
Full  
Full  
-
-
-
-
1/3 V  
-
V
V
V
OLL  
CC  
L
I/OV , CLK_V  
CC  
Voltage High  
Output  
Output  
V
= 20µA, I/OV ≥ V - 0.2V  
2/3 V  
-
CC  
CC  
OHC  
L
L
CC  
I/OV , CLK_V  
CC  
V
= 20µA, I/OV ≤ 0.15V  
1/3 V  
OLC  
L
CC  
Voltage Low  
RISE/FALL TIME ACCELERATOR STAGE  
Accelerator Pulse Duration  
On falling edge  
On rising edge  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
-
-
-
-
-
-
-
-
-
-
3
3
-
-
-
-
-
-
-
-
-
-
ns  
ns  
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
I/OV , CLK_RET Output  
L
Accelerator Source Impedance  
V
V
V
V
V
V
V
V
= 1.62V  
= 3.2V  
11  
6
L
L
I/OV , CLK_V  
CC  
Output  
= 2.2V  
= 3.6V  
9
CC  
Accelerator Source Impedance  
CC  
CC  
8
I/OV , CLK_RET Output  
L
Accelerator Sink Impedance  
= 1.62V  
= 3.2V  
9
L
8
L
I/OV , CLKV  
CC  
Output  
= 2.2V  
= 3.6V  
10  
9
CC  
CC  
CC  
Accelerator Sink Impedance  
TIMING CHARACTERISTICS (R  
= 150Ω, Input rise/fall time ≤ 1ns)  
SOURCE  
I/OV , CLK_V  
CC  
Rise Time  
t
R
= 150Ω, C  
= 10pF, C  
= 10pF, C  
I/OVCC  
= 10pF,  
Full  
-
-
3.2  
ns  
CC  
RVCC  
S
I/OVCC  
CLK_VCC  
push-pull drivers  
I/OV , CLK_V  
CC  
Fall Time  
t
R
= 150Ω, C  
= 150Ω, C  
= 10pF  
≥ 1.35V  
≥ 1.62V  
Full  
Full  
Full  
-
-
-
-
-
-
3.2  
4
ns  
ns  
ns  
CC  
FVCC  
S
CLK_VCC  
I/OV , CLK_RET Rise Time  
t
R
C
= 15pF,  
V
V
L
RVL  
S
I/OVL  
L
L
= 15pF, push-pull drivers  
CLK_RET  
3.5  
FN6492.0  
March 31, 2009  
5
ISL3034E, ISL3035E, ISL3036E  
Electrical Specifications  
V
V
= +2.2V to +3.6V, V = +1.35V to +3.2V, EN = V , unless otherwise noted. Typical values are at  
CC  
CC  
L
L
= +3.3V, V = +1.8V and T = +25°C. (Note 6). (Continued)  
L
A
TEMP  
(°C)  
MIN  
(Note 8) TYP  
MAX  
(Note 8) UNITS  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
I/OV , CLK_RET Fall Time  
t
R
C
= 150Ω, C  
= 15pF,  
V
V
V
V
≥ 1.35V  
≥ 1.62V  
≥ 1.35V  
≥ 1.62V  
Full  
Full  
Full  
Full  
-
-
-
-
-
-
-
-
4
ns  
ns  
ns  
ns  
L
FVL  
S
I/OVL  
L
L
L
L
= 15pF  
CLK_RET  
3.5  
7.5  
6.5  
I/OV , CLK_V  
CC  
Propagation  
t
R
C
= 150Ω, C  
= 10pF,  
= 10pF, push-pull  
CC  
PDVCC  
S
I/OVCC  
Delay (Driving I/OV , CLK_V )  
L
L
CLK_VCC  
drivers  
t
Channel-to-Channel  
t
V
V
≥ 1.35V  
≥ 1.62V  
Full  
Full  
Full  
-
-
-
-
-
-
1.3  
1
ns  
ns  
ns  
PDVCC  
SKEWC  
L
L
Skew (Note 9)  
I/OV , CLK_RET Propagation  
t
R = 150Ω, C  
S I/OVL  
= 15pF, C  
CLK_RET  
= 15pF,  
6.5  
L
PDVL  
Delay (Driving I/OV  
,
push-pull drivers  
CC  
CLK_V  
)
CC  
t
Channel-to-Channel Skew  
t
V
V
≥ 1.35V  
≥ 1.62V  
Full  
Full  
25  
-
-
-
-
-
1.3  
0.8  
-
ns  
ns  
µs  
PDVL  
SKEWL  
L
L
(Note 9)  
Delay from EN High to I/OV  
Active  
t
R = 1MΩ, C  
LOAD I/OVCC  
ISL3036E)  
= 10pF (ISL3034E and  
1.5  
CC  
L
EN-VCC  
Delay from EN High to I/OV  
Active  
t
R
= 1MΩ, C  
I/OVL  
= 15pF (ISL3034E and  
25  
-
1.5  
-
µs  
EN-VL  
LOAD  
ISL3036E)  
Maximum Data Rate  
D.R.  
Push-pull operation,  
V
V
≥ 1.35V  
≥ 1.62V  
Full  
Full  
85  
-
-
-
-
Mbps  
Mbps  
1.35  
L
L
R
C
C
C
= 150Ω,  
= 10pF, C  
SOURCE  
D.R.  
100  
1.6  
= 15pF,  
I/OVCC  
I/OVL  
= 10pF,  
= 15pF  
CLK_VCC  
CLK_RET  
NOTES:  
6. V must be less than or equal to V  
- 0.2V during normal operation. However, V can be greater than V during start-up and shutdown  
CC  
L
CC  
L
conditions and the part will not latch-up nor be damaged.  
7. Input thresholds are referenced to the boost circuit.  
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization  
and are not production tested.  
9. Delta between all I/OV channel prop delays, or delta between all I/OV  
L
channel prop delays, all channels tested at the same test conditions.  
CC  
Test Circuits and Waveforms  
V
L
V
L
I/OV  
I/OV  
L
50%  
50%  
EN  
0V  
V
V
CC  
L
t
t
PLH  
PHL  
V
OH  
90%  
90%  
I/OV  
I/OV  
50%  
10%  
CC  
50%  
10%  
L
CC  
V
OL  
150Ω  
t
t
RVCC  
FVCC  
C
SIGNAL  
L
GENERATOR  
t
= t  
or t  
PLH PHL  
PDVCC  
FIGURE 1A. TEST CIRCUIT  
FIGURE 1B. MEASUREMENT POINTS  
FIGURE 1. I/OV  
OUTPUT PROPAGATION DELAY AND TRANSITION TIMES (PUSH - PULL)  
CC  
FN6492.0  
March 31, 2009  
6
ISL3034E, ISL3035E, ISL3036E  
Test Circuits and Waveforms (Continued)  
V
L
V
CC  
I/OV  
CC  
50%  
50%  
EN  
0V  
PHL  
V
V
L
CC  
t
t
PLH  
V
OH  
90%  
90%  
I/OV  
50%  
10%  
I/OV  
I/OV  
50%  
10%  
L
CC  
L
V
OL  
150Ω  
t
t
RVL  
FVL  
C
SIGNAL  
GENERATOR  
L
t
= t  
or t  
PLH PHL  
PDVL  
FIGURE 2A. TEST CIRCUIT  
FIGURE 2B. MEASUREMENT POINTS  
FIGURE 2. I/OV OUTPUT PROPAGATION DELAY AND TRANSITION TIMES (PUSH - PULL)  
L
V
L
EN  
50%  
EN  
SIGNAL  
0V  
V
V
V
GENERATOR  
CC  
L
t
ENL  
1MΩ  
V
V
CC  
I/OV  
I/OV  
CC  
CC  
CC  
L
I/OV  
CC  
50%  
OUTPUT LOW  
GND  
GND  
SW1  
SW2  
V
OL  
OH  
t
ENH  
PARAMETER  
SW1  
SW2  
V
OUTPUT HIGH  
50%  
t
GND  
V
ENL  
CC  
GND  
I/OV  
CC  
t
V
CC  
ENH  
0V  
t
= t  
OR t  
ENL ENH  
EN-VCC  
FIGURE 3B. MEASUREMENT POINTS  
FIGURE 3A. TEST CIRCUIT  
FIGURE 3. I/OV  
OUTPUT ENABLE TIMES  
CC  
V
CC  
EN  
50%  
EN  
SIGNAL  
0V  
V
V
V
GENERATOR  
L
CC  
t
ENL  
1MΩ  
V
L
V
I/OV  
L
I/OV  
L
CC  
L
I/OV  
50%  
OUTPUT LOW  
L
GND  
GND  
SW1  
SW2  
V
OL  
t
ENH  
PARAMETER  
SW1  
SW2  
V
OH  
OUTPUT HIGH  
50%  
t
GND  
V
L
ENL  
I/OV  
L
t
V
GND  
ENH  
L
0V  
t
= t  
OR t  
ENL ENH  
EN-VL  
FIGURE 4B. MEASUREMENT POINTS  
FIGURE 4. I/OV OUTPUT ENABLE TIMES  
FIGURE 4A. TEST CIRCUIT  
L
FN6492.0  
March 31, 2009  
7
ISL3034E, ISL3035E, ISL3036E  
V
L
Application Information  
HIGH V  
TH  
DETECT  
Overview  
#
#
The ISL3034E, ISL3035E, ISL3036E are 100Mbps,  
bi-directional voltage level translating ICs for multi-supply  
voltage systems. These products shift lower voltage levels  
LOW V  
TH  
DETECT  
V
V
CC  
L
on one interface side (supplied by V ) to a higher voltage  
EN  
L
level on the other interface side (supplied by V ), or vice  
CC  
I/OV  
I/OV  
CC  
L
versa. V  
of the I/OV pins tracks the V supply, while V  
OH  
L
L
OH  
V
CC  
of the I/OV  
CC  
pins tracks the V  
supply.  
CC  
HIGH V  
TH  
DETECT  
These ICs feature bit-by-bit auto-direction sensing to  
increase flexibility, and to eliminate the need for direction  
control pins. On chip pull-up current sources in the active  
#
#
LOW V  
TH  
DETECT  
mode, and pull-up resistors in SHDN mode, eliminate the  
need for most external bus resistors. Drivers interfacing with  
these level translators may be open-drain or push-pull types,  
and all three versions may also be used for unidirectional  
level shifting.  
# ONE-SHOT AND LEVEL SHIFTER  
FIGURE 5. ONE CHANNEL SIMPLIFIED SCHEMATIC  
open-drain type driver. Once the one-shot - and thus the  
accelerator - times out (approximately 3ns to 4ns), the large  
output drivers tri-state and the pins are weakly held in the  
The three versions share the same architecture, but the  
ISL3034E is a general purpose 6-Channel version, while the  
6-Channel ISL3035E specifically targets SD Card and other  
memory card applications. The 4-channel ISL3036 targets  
nibble and byte based applications, as well as 4-wire SPI  
interfaces. Power supply ranges allow level shifting between  
last state by the small NMOS transistor between I/OV and  
L
I/OV  
(for a low) or by the small current sources (for a  
CC  
high). In this static state, the I/O pins are easily overdriven by  
the next transition from an external driver. Having large  
pull-up and pull-down devices in the accelerator (vs just an  
active pull-up) nearly eliminates the concern about the  
external driver’s output impedance, and that impedance’s  
1.5V, 1.8V, and 2.5V powered devices on the V side to  
L
2.5V, and 3.3V devices on the V  
side.  
CC  
effect on V , fall times and data rate.  
OL  
Principles of Operation  
The weak pull-up current sources on each I/O pin and the  
NMOS pass transistors, remain ON whenever the IC is  
enabled. If a channel’s external driver tri-states, the weak  
pull-up currents either keep the I/O pins high, or if the last  
state was a low the current sources pull the I/O pins high. In  
the latter case, each channel’s accelerators will once again  
When enabled, these level shifters detect transitions on an  
I/O pin, and drive the appropriate logic level on the  
corresponding I/O pin on the other “side”. If the transition  
was low-to-high, the channel shifts the voltage up to V  
(for  
CC  
transitions on an I/OV pin) or down to V (for transitions on  
L
L
an I/OV  
pin), and then drives the shifted level on the other  
CC  
fire when either the I/OV or the I/OV  
voltage crosses the  
L
CC  
side. The ISL3035E enables whenever V > V + 200mV,  
CC  
while the ISL3034E and ISL3036E enable if EN = 1 AND  
> V + 200mV.  
L
accelerator’s high threshold level.  
Auto Direction Sensing  
V
CC  
L
Each level translator channel independently and  
automatically determines the direction of data transfer  
without any external control signals. As described earlier, a  
transition on either of the channel’s I/O pins momentarily  
defines that pin as an input, which then translates and drives  
that input signal to the channel’s corresponding pin on the  
other port (now the output). After a brief period of active  
driving, both I/O pins return to their weak “hold” mode, where  
the next transition on either I/O pin determines the direction  
for the next transfer.  
Upon detecting a transition on either I/O pin, that channel’s  
accelerator circuitry actively drives the opposite side’s  
(output) pin to GND or the output’s supply rail, and then turns  
off. Weak hold circuitry then maintains the logic state until  
the input is 3-stated, or until another active transition occurs  
on either I/O pin for that channel. Figure 5 shows the  
simplified block diagram of one level shifting channel. The  
accelerator circuitry comprises high and low threshold  
detectors, one shots with level shifters and large output  
drivers. A transition on one of the I/OV or I/OV  
pins  
L
CC  
Auto sensing saves valuable processor GPIO pins (three  
[CLK, CMD, DAT] for SD Card applications, or six for the  
general purpose hex case), and simplifies the software  
associated with the peripheral interface.  
momentarily defines that pin as an input. When the high or  
low threshold is crossed, a one-shot fires either the PMOS or  
NMOS driver, respectively, on the opposite side (effectively  
the output). These drivers are large enough to quickly drive  
the output node to its respective supply or to GND. Note that  
this transition on the “output” trips the transition detector on  
that pin, firing its accelerator, which feeds back to the “input”  
to help reinforce slow transitions, such as those from an  
Using Open Drain Drivers  
These level translators’ accelerator based architecture  
works equally well when driven by push-pull or open drain  
type drivers (e.g., for the CMD line initialization in MMC  
FN6492.0  
March 31, 2009  
8
ISL3034E, ISL3035E, ISL3036E  
applications). The low static pull-up current is easily  
respectively. Both products include SHDN mode 16.5kΩ  
overdriven by an active pull-down, and the feedback nature  
of the accelerators (i.e., the accelerator firing in one direction  
also triggers the accelerator in the opposite direction) aids  
the passive pull-up once the input signal passes the  
pull-ups on the I/OV  
and I/OV pins.  
CC L  
ISL3035E  
+1.8V  
+3.3V  
accelerator’s high threshold. The pull-up current and load  
capacitance set the input signal rise time, and thus the  
maximum data rate. For slow data rates the internal pull-up  
current may suffice, but higher data rates - or more heavily  
loaded signal lines - may require an external pull-up resistor.  
1
µF  
0.1µF  
0.1µF  
1µF  
+1.8V  
+3.3V  
SD CARD  
V
V
L
CC  
SYSTEM  
ISL3035E  
CONTROLLER  
HOST  
DAT3  
I/OV  
I/OV  
I/OV  
I/OV  
I/OV  
I/OV  
DAT3  
DAT2  
DAT1  
DAT0  
CMD  
L_  
L_  
L_  
L_  
L_  
CC_  
CC_  
CC_  
CC_  
CC_  
DAT2  
DAT1  
DAT0  
CMD  
I/OV  
I/OV  
I/OV  
I/OV  
Using External Bus Resistors  
As mentioned earlier, these level translators incorporate I/O  
pin pull-up current sources when enabled, and I/O pin  
pull-up resistors in SHDN (except for the ISL3035E’s I/OV  
pins). Therefore, external pull-up or pull-down resistors  
CC  
CLK_V  
CC  
CLOCK  
CLOCK  
CLOCK_IN  
GND  
CLK_V  
L
shouldn’t be necessary, and aren’t recommended, unless  
using high-speed open drain signaling.  
CLK_RET  
GND  
Power Supplies  
GND  
WIDE SUPPLY RANGE  
These ICs operate from a wide range of supply voltages.  
V is designed to connect to the supply of 1.5V, 1.8V, and  
L
FIGURE 6. ISL3035E IN AN SD CARD APPLICATION  
2.5V powered devices, while V  
is targeted for 2.5V, and  
CC  
The ISL3035E specifically targets memory card applications,  
and Figure 6 illustrates its use in an SD Card application.  
Instead of six general purpose channels, the ISL3035E  
features five general purpose channels and one dedicated  
CLK channel. In memory card applications, the CLK channel  
is a unidirectional signal driven by the host controller and  
used by the memory card to synchronize data reads and  
writes. The ISL3035E’s CLK channel is unique in that the  
3.3V components. Remember that V must be greater  
than V for proper operation.  
L
CC  
POWER SUPPLY SEQUENCING  
Either V  
CC  
or V may be powered up first, but the IC  
L
remains in SHDN until V  
exceeds V by as much as  
CC  
L
200mV. V may exceed V  
by as much as 4V without  
L
CC  
causing any damage.  
host CLK applied to the CLK_V pin routes to the memory  
L
I/O PIN INPUT THRESHOLDS VS SUPPLY VOLTAGE  
card via the CLK_V  
pin, but it also loops back to the host  
CC  
Even though the “Electrical Specification” table on page 4  
on the CLK_RET pin. This CLK_RET signal better mimics  
the timing of “read” data returned from the memory card (see  
Figure 21 for signal timing), so using CLK_RET as the host’s  
input CLK improves the CLK to data timing relationship.  
shows the I/O pin input thresholds (V , V ) with a fixed  
IH IL  
delta from the supplies or GND, the thresholds are better  
represented as a percentage of the supplies. The typical  
I/OV  
and CLK_V  
V
runs about 55% to 60% of V  
,
CC  
CC IH  
CC  
CLK_RET is strictly an output, and CLK_V is strictly an  
L
while the corresponding V runs about 33% of V . The  
IL CC  
input. If an ISL3035E application needs a sixth I/O channel  
typical I/OV and CLK_V V runs about 60% to 70% of V ,  
IH  
L
L
L
then the user needs to connect CLK_V and CLK_RET  
while the corresponding V runs about 25% to 35% of V .  
L
IL  
L
together. Connected this way, the combination channel has the  
same architecture as the other I/O channels. Both CLK_RET  
Low Power SHDN Mode  
This family of level translators features a low power SHDN  
mode that tri-states all the I/O and output pins, considerably  
reduces current consumption, and enables any pull-up  
resistors on a port’s I/O pins (see Table 1). The ISL3034E  
and ISL3036E enter the SHDN mode when the EN input  
and CLK_V have equivalent pull-up current sources and  
L
SHDN pull-up resistors, so connecting these two pins together  
doubles the pull-up current in either mode.  
The bit-by-bit auto direction control eliminates the need for  
GPIO signals to control the flow of data on the CMD and  
DAT lines.  
switches low, or automatically when the V  
voltage drops  
below the V voltage. The ISL3035 has no enable pin, so it  
CC  
L
enters SHDN only if V  
drops below V . The V supply  
L L  
CC  
The ISL3035E has no enable pin, so it only enters the low  
powers the EN circuitry.  
power SHDN mode when V  
drops below V . There are no  
L
CC  
SHDN pull-up resistors on the I/OV  
and CLK_V  
pins,  
CC  
CC  
ISL3034E and ISL3036E  
but there are 75kΩ pull-ups on the I/OV , CLK_V , and  
CLK_RET pins.  
L
L
The ISL3034E and ISL3036E are general purpose level  
translators featuring an enable pin, and six or four channels,  
FN6492.0  
March 31, 2009  
9
ISL3034E, ISL3035E, ISL3036E  
configuration (power applied). The IEC61000 standard’s  
Best-in-Class ESD Protection  
lower current limiting resistor coupled with the larger charge  
storage capacitor yields a test that is much more severe than  
the HBM test. The extra ESD protection built into these  
devices’ pins allows the design of equipment meeting level 4  
criteria without the need for additional board level protection.  
All pins on these devices include class 3 (>12kV) Human  
Body Model (HBM) ESD protection structures, but the input  
and I/O pins incorporate advanced structures allowing  
them to survive ESD events in excess of ±15kV HBM and  
±15kV to IEC61000-4-2. The I/OV  
pins are particularly  
CC  
vulnerable to ESD damage because they typically connect  
to an exposed port on the exterior of the finished product.  
Simply touching the port pins, or connecting a memory  
card, can cause an ESD event that might destroy  
unprotected ICs. These new ESD structures protect the  
device whether or not it is powered up and without  
degrading the level shifting performance. This built-in ESD  
protection eliminates the need for board level protection  
structures (e.g., transient suppression diodes) and the  
associated, undesirable capacitive load they present. To  
ensure the full benefit of the built-in ESD protection,  
connect the IC’s GND pin directly to a low impedance GND  
plane.  
AIR-GAP DISCHARGE TEST METHOD  
For this test method, a charged probe tip moves toward the  
IC pin until the voltage arcs to it. The current waveform  
delivered to the IC pin depends on approach speed,  
humidity, temperature, etc., so it is difficult to obtain  
repeatable results. All the EN, CLK, and I/O pins withstand  
±15kV air-gap discharges, relative to GND.  
CONTACT DISCHARGE TEST METHOD  
During the contact discharge test, the probe contacts the  
tested pin before the probe tip is energized, thereby  
eliminating the variables associated with the air-gap  
discharge. The result is a more repeatable and predictable  
test, but equipment limits prevent testing devices at voltages  
higher than ±9kV. Devices in this family survive ±9kV contact  
discharges (relative to the GND pin) on the EN, CLK, and I/O  
pins.  
IEC61000-4-2 Testing  
The IEC61000 test method applies to finished equipment,  
rather than to an individual IC. Therefore, the pins most likely  
to suffer an ESD event are those that are exposed to the  
outside world (typically I/OV  
pins in memory card  
Layout and Decoupling Considerations  
CC  
applications) but the ISL3034E, ISL3035E, and ISL3036E  
feature IEC61000 ESD protection on all logic and I/O pins  
These level translators’ high data rates and fast signal  
transitions require that the accelerators have high transient  
currents. Thus, short, low inductance supply traces and  
decoupling within 1/8th inch of the IC are imperative with  
very low impedance GND return paths.  
(both I/OV and I/OV , as well as CLK pins). Unlike HBM  
L
CC  
and MM methods which only test each pin-to-pin  
combination without applying power, IEC61000 testing is  
also performed with the IC in its typical application  
Typical Performance Curves  
V
= 3.3V, V = 1.8V, C = 15pF, R = 150Ω, Data Rate = 100Mbps, push-pull driver,  
SOURCE  
= +25°C; Unless Otherwise Specified.  
CC  
L
L
T
A
2.5  
25  
V
= 1.8V  
V
= 3.6V  
L
CC  
SWITCHING 6 I/OV INPUTS  
L
2.0  
1.5  
1.0  
0.5  
0
20  
15  
10  
5
SWITCHING 6 I/OV  
INPUTS  
CC  
SWITCHING 4 I/OV INPUTS  
L
SWITCHING 4 I/OV  
CC  
INPUTS  
SWITCHING 1 I/OV INPUT  
L
SWITCHING 1 I/OV  
INPUT  
2.1  
CC  
0
2.2  
2.4  
2.6  
2.8  
3.0  
3.2  
3.4  
3.6  
1.3  
1.5  
1.7  
1.9  
2.3  
2.5  
2.7  
2.9  
3.1 3.2  
V
SUPPLY VOLTAGE (V)  
V SUPPLY VOLTAGE (V)  
CC  
L
FIGURE 7. V SUPPLY CURRENT vs V  
L
SUPPLY VOLTAGE  
FIGURE 8. V SUPPLY CURRENT vs V SUPPLY VOLTAGE  
L L  
CC  
FN6492.0  
March 31, 2009  
10  
ISL3034E, ISL3035E, ISL3036E  
Typical Performance Curves  
V
= 3.3V, V = 1.8V, C = 15pF, R = 150Ω, Data Rate = 100Mbps, push-pull driver,  
SOURCE  
= +25°C; Unless Otherwise Specified. (Continued)  
CC  
L
L
T
A
35  
16  
V
= 1.8V  
V
= 3.6V  
L
CC  
14  
12  
10  
8
30  
25  
20  
15  
10  
5
SWITCHING 6 I/OV INPUTS  
L
SWITCHING 6 I/OV  
INPUTS  
CC  
SWITCHING 4 I/OV INPUTS  
L
SWITCHING 4 I/OV  
INPUTS  
CC  
6
4
SWITCHING 1 I/OV  
INPUT  
2.1  
CC  
SWITCHING 1 I/OV INPUT  
L
2
0
2.2  
0
1.3  
2.4  
2.6  
2.8  
3.0  
3.2  
3.4  
3.6  
1.5  
1.7  
1.9  
2.3  
2.5  
2.7  
2.9  
3.1 3.2  
V
SUPPLY VOLTAGE (V)  
V SUPPLY VOLTAGE (V)  
CC  
L
FIGURE 9. V  
SUPPLY CURRENT vs V  
SUPPLY  
FIGURE 10. V  
SUPPLY CURRENT vs V SUPPLY VOLTAGE  
CC L  
CC  
CC  
VOLTAGE  
2.50  
2.45  
2.40  
2.35  
2.30  
2.25  
2.20  
2.15  
2.10  
2.05  
2.00  
7
SWITCHING 1 I/OV  
INPUT  
SWITCHING 1 I/OV INPUT  
CC  
L
6
5
4
3
2
1
0
I
CC  
I
L
I
CC  
I
L
-40  
-15  
10  
35  
60  
85  
-40  
-15  
10  
35  
60  
85  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 11. SUPPLY CURRENT vs TEMPERATURE  
FIGURE 12. SUPPLY CURRENT vs TEMPERATURE  
18  
40  
35  
16  
14  
12  
10  
8
SWITCHING 6 I/OV INPUTS  
L
SWITCHING 6 I/OV  
SWITCHING 4 I/OV  
INPUTS  
CC  
30  
25  
20  
15  
10  
5
SWITCHING 4 I/OV INPUTS  
L
INPUTS  
CC  
6
4
SWITCHING 1 I/OV INPUT  
SWITCHING 1 I/OV  
INPUT  
20  
L
CC  
2
0
0
10  
15  
20  
25  
30  
35  
10  
15  
25  
30  
35  
CAPACITIVE LOAD (pF)  
SUPPLY CURRENT vs I/OV  
CAPACITIVE LOAD (pF)  
FIGURE 14. V  
CAPACITIVE  
CC  
FIGURE 13. V SUPPLY CURRENT vs I/OV CAPACITIVE  
CC  
LOAD  
L
L
LOAD  
FN6492.0  
March 31, 2009  
11  
ISL3034E, ISL3035E, ISL3036E  
Typical Performance Curves  
V
= 3.3V, V = 1.8V, C = 15pF, R = 150Ω, Data Rate = 100Mbps, push-pull driver,  
SOURCE  
= +25°C; Unless Otherwise Specified. (Continued)  
CC  
L
L
T
A
1.8  
2.1  
SWITCHING I/OV INPUT  
L
SWITCHING I/OV  
INPUT  
CC  
1.7  
t
1.9  
1.7  
1.5  
1.3  
1.1  
0.9  
FVCC  
1.6  
t
RVL  
1.5  
t
t
RVCC  
FVL  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
10  
15  
20  
25  
30  
35  
10  
15  
20  
25  
30  
35  
CAPACITIVE LOAD (pF)  
CAPACITIVE LOAD (pF)  
FIGURE 15. RISE/FALL TIME vs I/OV  
CAPACITIVE LOAD  
FIGURE 16. RISE/FALL TIME vs I/OV CAPACITIVE LOAD  
CC  
L
3.4  
4.2  
SWITCHING I/OV  
INPUT  
CC  
SWITCHING I/OV INPUT  
L
4.0  
3.8  
3.6  
3.4  
3.2  
3.0  
3.2  
3.0  
2.8  
2.6  
2.4  
t
PLH  
t
PLH  
t
PHL  
t
PLH  
t
PHL  
10  
15  
20  
25  
30  
35  
10  
15  
20  
25  
30  
35  
CAPACITIVE LOAD (pF)  
CAPACITIVE LOAD (pF)  
FIGURE 17. PROPAGATION DELAY vs I/OV  
CAPACITIVE  
FIGURE 18. PROPAGATION DELAY vs I/OV CAPACITIVE  
CC  
L
LOAD  
LOAD  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
2.0  
1.5  
1.0  
0.5  
0
2.0  
1.5  
1.0  
0.5  
0
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
C
= 15pF  
C
= 35pF  
L
L
0
TIME (4ns/DIV)  
TIME (4ns/DIV)  
FIGURE 19. I/OV  
CC  
OUTPUT WAVEFORMS (100Mbps)  
FIGURE 20. I/OV OUTPUT WAVEFORMS (100Mbps)  
L
FN6492.0  
March 31, 2009  
12  
ISL3034E, ISL3035E, ISL3036E  
Typical Performance Curves  
V
= 3.3V, V = 1.8V, C = 15pF, R = 150Ω, Data Rate = 100Mbps, push-pull driver,  
SOURCE  
= +25°C; Unless Otherwise Specified. (Continued)  
CC  
L
L
T
A
2
1
0
Die Characteristics  
SUBSTRATE AND TQFN/QFN THERMAL PAD  
POTENTIAL (POWERED UP):  
3.0  
2.5  
2.0  
1.5  
1.0  
GND  
TRANSISTOR COUNT:  
C
= 35pF  
L
0.5  
ISL3034E, ISL3035E - 2600  
ISL3036E - 2000  
0
2.0  
C
= 15pF  
L
1.5  
1.0  
0.5  
0
PROCESS:  
Si Gate BiCMOS  
TIME (4ns/DIV)  
FIGURE 21. ISL3035E CLOCK WAVEFORMS (100Mbps)  
FN6492.0  
March 31, 2009  
13  
ISL3034E, ISL3035E, ISL3036E  
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)  
L16.2.6x1.8A  
D
A
B
E
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE  
MILLIMETERS  
6
INDEX AREA  
SYMBOL  
MIN  
0.45  
NOMINAL  
MAX  
0.55  
NOTES  
N
A
A1  
A3  
b
0.50  
-
2X  
0.10 C  
1 2  
-
-
0.05  
-
2X  
0.10 C  
0.127 REF  
-
TOP VIEW  
0.15  
2.55  
1.75  
0.20  
0.25  
2.65  
1.85  
5
D
2.60  
-
0.10 C  
E
1.80  
-
C
A
0.05 C  
SEATING PLANE  
e
0.40 BSC  
-
K
0.15  
0.35  
0.45  
-
0.40  
0.50  
16  
4
-
0.45  
0.55  
-
A1  
L
-
SIDE VIEW  
L1  
N
-
2
e
Nd  
Ne  
θ
3
PIN #1 ID  
L1  
K
1 2  
4
3
NX L  
0
-
12  
4
5
NX b  
16X  
Rev. 5 2/09  
(DATUM B)  
(DATUM A)  
NOTES:  
0.10 M C A B  
0.05 M C  
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.  
2. N is the number of terminals.  
BOTTOM VIEW  
3. Nd and Ne refer to the number of terminals on D and E side,  
respectively.  
4. All dimensions are in millimeters. Angles are in degrees.  
5. Dimension b applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
C
L
(A1)  
6. The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
NX (b)  
5
L
e
7. Maximum package warpage is 0.05mm.  
8. Maximum allowable burrs is 0.076mm in all directions.  
9. JEDEC Reference MO-255.  
SECTION "C-C"  
TERMINAL TIP  
C C  
10. For additional information, to assist with the PCB Land Pattern  
Design effort, see Intersil Technical Brief TB389.  
3.00  
1.80  
1.40  
0.90  
1.40  
2.20  
0.40  
0.20  
0.20  
0.40  
0.50  
10  
LAND PATTERN  
FN6492.0  
March 31, 2009  
14  
ISL3034E, ISL3035E, ISL3036E  
Package Outline Drawing  
L14.3.5x3.5  
14 LEAD QUAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (QFN)  
Rev 0, 2/08  
2x 2.0  
3.50  
A
6
PIN 1  
8x 0.50  
INDEX AREA  
6
B
PIN #1 INDEX AREA  
2
6
1
7
3.50  
2.05 ± 0 . 15  
2x 1.50  
8
14  
(4X)  
0.15  
13  
9
0.10 M  
C A B  
TOP VIEW  
+
0.07  
4
16X 0.23  
- 0.05  
VIEW “A-A”  
14x 0.40 ± 0.10  
BOTTOM VIEW  
( 2.00 )  
(8x 0.50)  
SEE DETAIL "X"  
C
0.10  
C
0 . 90 ± 0.1  
BASE PLANE  
SEATING PLANE  
0.08  
( 3.30 TYP )  
C
( 2x 1.5 )  
(
2.05)  
SIDE VIEW  
( 14x 0.23 )  
( 14 x 0.60)  
5
C
0 . 2 REF  
TYPICAL RECOMMENDED LAND PATTERN  
0 . 00 MIN.  
0 . 05 MAX.  
DETAIL “X”  
NOTES:  
1. Dimensions are in millimeters.  
Dimensions in ( ) for Reference Only.  
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.  
3.  
Unless otherwise specified, tolerance : Decimal ± 0.05  
4. Lead width dimension applies to the metallized terminal and is  
measured between 0.15mm and 0.30mm from the terminal tip.  
Tiebar shown (if present) is a non-functional feature.  
5.  
6.  
The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
FN6492.0  
March 31, 2009  
15  
ISL3034E, ISL3035E, ISL3036E  
Thin Quad Flat No-Lead Plastic Package (TQFN)  
Thin Micro Lead Frame Plastic Package (TMLFP)  
)
2X  
L16.3x3A  
0.15  
E1/2  
A2  
C A  
D
A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE  
9
D/2  
MILLIMETERS  
D1  
SYMBOL  
MIN  
NOMINAL  
MAX  
0.80  
0.05  
0.80  
NOTES  
D1/2  
A
A1  
A2  
A3  
b
0.70  
0.75  
-
2X  
N
0.15 C  
B
-
-
-
-
6
INDEX  
AREA  
-
9
1
2
3
E/2  
9
0.20 REF  
9
E1  
E
B
0.18  
1.35  
1.35  
0.23  
0.30  
1.65  
1.65  
5, 8  
D
3.00 BSC  
-
2X  
D1  
D2  
E
2.75 BSC  
9
0.15 C  
B
2X  
1.50  
7, 8, 10  
TOP VIEW  
SIDE VIEW  
0.15 C  
A
3.00 BSC  
-
0
4X  
E1  
E2  
e
2.75 BSC  
9
A
/ /  
0.10 C  
0.08 C  
C
1.50  
7, 8, 10  
0.50 BSC  
-
A1  
A3  
SEATING PLANE  
k
0.20  
0.30  
-
0.40  
16  
4
-
-
9
L
0.50  
8
5
NX b  
N
2
0.10 M C A B  
4X P  
D2  
D2  
8
7
Nd  
Ne  
P
3
NX k  
(DATUM B)  
4
3
2
N
-
-
-
0.60  
12  
9
4X P  
θ
-
9
1
2
(DATUM A)  
Rev. 0 6/04  
(Ne-1)Xe  
REF.  
3
E2  
6
NOTES:  
INDEX  
AREA  
7
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.  
2. N is the number of terminals.  
E2/2  
8
NX L  
8
N
e
3. Nd and Ne refer to the number of terminals on each D and E.  
4. All dimensions are in millimeters. Angles are in degrees.  
9
CORNER  
OPTION 4X  
(Nd-1)Xe  
REF.  
5. Dimension b applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
BOTTOM VIEW  
A1  
6. The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
NX b  
5
7. Dimensions D2 and E2 are for the exposed pads which provide  
improved electrical and thermal performance.  
SECTION "C-C"  
C
L
C
8. Nominal dimensions are provided to assist with PCB Land  
Pattern Design efforts, see Intersil Technical Brief TB389.  
L
9. Features and dimensions A2, A3, D1, E1, P & θ are present when  
Anvil singulation method is used and not present for saw  
singulation.  
L
L
10  
L1  
10  
L1  
e
e
10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2  
and D2 MAX dimension.  
C
C
TERMINAL TIP  
FOR ODD TERMINAL/SIDE  
FOR EVEN TERMINAL/SIDE  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
16  

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