ISL43L120_06 [INTERSIL]
Ultra Low ON-Resistance, Single Supply, Dual SPST Analog Switches; 超低导通电阻，单电源，双路SPST模拟开关
| 型号： | ISL43L120_06 |
| 厂家： | 
Intersil |
| 描述： | Ultra Low ON-Resistance, Single Supply, Dual SPST Analog Switches |
| 文件： | 总11页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL43L120, ISL43L121, ISL43L122
®
Data Sheet
June 23, 2006
FN6091.2
Ultra Low ON-Resistance, Single Supply,
Dual SPST Analog Switches
Features
• Low ON Resistance (R
)
ON
The Intersil ISL43L120, ISL43L121, ISL43L122 devices are
low ON-resistance, low voltage, bidirectional, precision, dual
single-pole/single-throw (SPST) analog switches designed
to operate from a single +1.65V to +3.6V supply. Targeted
applications include battery powered equipment that benefit
- V+ = 3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.16Ω
- V+ = 1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26Ω
• R
Matching Between Channels. . . . . . . . . . . . 0.005Ω
Flatness Over Signal Range . . . . . . . . . . . . . . 0.008Ω
ON
ON
• R
from low R
(0.16Ω), low power consumption (0.12µW)
ON
and fast switching speeds (t
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V
= 13ns, t
= 13ns).
ON
OFF
• Low Power Consumption (P ). . . . . . . . . . . . . . . . . <0.12µW
D
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This family of parts may be used to
switch in additional functionality while reducing ASIC design
risk. The ISL43L12X are offered in an 8 Ld MSOP package,
alleviating board space limitations.
• Fast Switching Action (V+ = 3.0V)
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns
ON
OFF
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kV
• 1.8V Logic Compatible (+3V Supply)
• Available in 8-Ld thin DFN and 8-Ld MSOP Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
The ISL43L120, ISL43L121, ISL43L122 are dual single-
pole/single-throw (SPST) devices. The ISL43L120 has two
normally open (NO) switches; the ISL43L121 has two
normally closed (NC) switches; the ISL43L122 has one
normally open (NO) and one normally closed (NC) switch
and can be used as an SPDT.
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
Table 1 summarizes the performance of this family.
- Pagers
- Laptops, Notebooks, Palmtops
TABLE 1. FEATURES AT A GLANCE
• Portable Test and Measurement
• Medical Equipment
ISL43L120
ISL43L121
ISL43L122
NUMBER OF
SWITCHES
2
2
2
• Audio and Video Switching
SW 1/SW 2
NO/NO
0.26Ω
NC/NC
0.26Ω
NO/NC
0.26Ω
1.8V R
ON
1.8V t /t
ON OFF
30ns/25ns
0.16Ω
30ns/25ns
0.16Ω
30ns/25ns
0.16Ω
3V R
ON
3V t /t
13ns/13ns
13ns/13ns
13ns/13ns
ON OFF
PACKAGES
8Ld 3x3 TDFN, 8Ld MSOP
Related Literature
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”.
Application Note AN557 “Recommended Test Procedures
for Analog Switches”.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL43L120, ISL43L121, ISL43L122
Pinouts (Note 1)
ISL43L120 (MSOP, TDFN)
ISL43L122 (MSOP, TDFN)
ISL43L121 (MSOP, TDFN)
TOP VIEW
TOP VIEW
TOP VIEW
COM
V+
V+
V+
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
COM
COM
1
1
2
NO
NC
IN
2
NO
IN
1
IN
2
1
1
IN
2
IN
COM
IN
1
COM
GND
1
2
2
1
COM
2
GND
NC
NC
GND
NO
2
2
NOTE:
1. Switches Shown for Logic “0” Input.
Ordering Information
Truth Table
TEMP.
RANGE
(°C)
ISL43L120
ISL43L121
SW 1, 2
ON
ISL43L122
PART
PART
PKG.
DWG. #
LOGIC
SW 1, 2
OFF
SW 1
SW 2
ON
NUMBER*
MARKING
PACKAGE
0
1
OFF
ON
ISL43L120IU L120
ISL43L120IR L10
ISL43L121IU L121
ISL43L121IR L11
ISL43L122IU L122
ISL43L122IR L12
-40 to 85 8 Ld MSOP
M8.118
ON
OFF
OFF
-40 to 85 8 Ld 3x3 TDFN L8.3x3A
-40 to 85 8 Ld MSOP M8.118
-40 to 85 8 Ld 3x3 TDFN L8.3x3A
-40 to 85 8 Ld MSOP M8.118
-40 to 85 8 Ld 3x3 TDFN L8.3x3A
NOTE: Logic “0” ≤ 0.5V. Logic “1” ≥ 1.4V with a 3V Supply.
Pin Descriptions
PIN
FUNCTION
System Power Supply Input (+1.65V to +3.6V)
Ground Connection
ISL43L120IUZ L120Z
(Note)
-40 to 85 8 Ld MSOP
(Pb-free)
M8.118
V+
GND
IN
ISL43L120IRZ L10Z
(Note)
-40 to 85 8 Ld 3x3 TDFN L8.3x3A
(Pb-free)
Digital Control Input
COM
NO
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
ISL43L121IUZ L121Z
(Note)
-40 to 85 8 Ld MSOP
(Pb-free)
M8.118
ISL43L121IRZ L11Z
(Note)
-40 to 85 8 Ld 3x3 TDFN L8.3x3A
(Pb-free)
NC
ISL43L122IUZ L122Z
(Note)
-40 to 85 8 Ld MSOP
(Pb-free)
M8.118
ISL43L122IRZ L12Z
(Note)
-40 to 85 8 Ld 3x3 TDFN L8.3x3A
(Pb-free)
*Add “-T” suffix for tape and reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN6091.2
June 23, 2006
2
ISL43L120, ISL43L121, ISL43L122
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
IN (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
NO, NC (Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . 300mA
Peak Current, IN, NO, NC, or COM
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
JA
8 Ld 3x3 TDFN Package . . . . . . . . . . . . . . . . . . . . .
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
110
190
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . 500mA
ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>8kV
Operating Conditions
Temperature Range
ISL43L12XIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless Otherwise Specified
= 1.4V, V
= 0.5V (Note 4, 6),
INL
INH
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C)
(NOTE 5)
TYP
(NOTE 5) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
V+
0.25
0.3
0.02
0.04
0.06
0.07
3
V
Ω
ON Resistance, R
V+ = 2.7V, I
= 100mA, V
or V
= 0V to V+
= Voltage at
= 0V to V+,
= 3V, 0.3V
0.17
ON
COM
See Figure 4
NO
NO
NO
NC
NC
NC
Full
25
-
-
Ω
R
Matching Between Channels, V+ = 2.7V, I
= 100mA, V
Note 8
or V
or V
-
0.005
Ω
ON
∆R
COM
Max R
ON,
ON
Full
25
-
-
Ω
R
Flatness, R
V+ = 2.7V, I = 100mA, V
COM
-
0.008
Ω
ON
Flat(ON)
Note 9
Full
25
-
-
-
-
-
-
Ω
NO or NC OFF Leakage Current,
or I
V+ = 3.3V, V
= 0.3, 3V, V
or V
NC
-3
-60
-3
-80
nA
nA
nA
nA
COM
NO
I
NO(OFF)
NC(OFF)
Full
25
60
COM ON Leakage Current,
V+ = 3.3V, V
= 0.3V, 3V, or V
or V
= 0.3V, 3V
NC
3
COM
NO
I
COM(ON)
Full
80
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 50Ω, C = 35pF,
25
Full
25
-
-
-
-
-
-
15
-
25
30
25
30
-
ns
ns
ns
ns
pC
dB
ON
NO
NC
L
L
V
= 0 to 2.7V, See Figure 1, Note 7
IN
Turn-OFF Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 50Ω, C = 35pF,
15
-
OFF
NO
NC
L
L
V
= 0 to 2.7V, See Figure 1, Note 7
IN
Full
25
Charge Injection, Q
OFF Isolation
C
= 1.0nF, V = 0V, R = 0Ω, See Figure 2
-125
62
L
G
G
R = 50Ω, C = 5pF, f = 100kHz, V
= 1 V
See
See
25
-
L
L
COM
RMS,
Figure 3
Crosstalk (Channel-to-Channel)
R = 50Ω, C = 5pF, f = 100kHz, V
= 1 V
25
25
-
-
-94
-
-
dB
pF
L
L
COM
RMS,
Figure 5
NO or NC OFF Capacitance, C
f = 1MHz, V
or V
NC
= V = 0V, See Figure 6
COM
182
OFF
NO
FN6091.2
June 23, 2006
3
ISL43L120, ISL43L121, ISL43L122
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless Otherwise Specified (Continued)
= 1.4V, V
= 0.5V (Note 4, 6),
INL
INH
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C)
(NOTE 5)
TYP
(NOTE 5) UNITS
COM OFF Capacitance,
f = 1MHz, V
f = 1MHz, V
or V
= V
= 0V, See Figure 6
25
-
182
-
pF
NO
NO
NC
COM
C
COM(OFF)
COM ON Capacitance, C
or V
= V
= 0V, See Figure 6
25
-
290
-
pF
COM(ON)
NC
COM
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
1.65
-
-
-
3.6
30
V
Positive Supply Current, I+
V+ = 1.65V to 3.6V, V = 0V or V+, all channels on or
IN
off
-
-
nA
nA
Full
750
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.5
-
V
V
INL
Input Voltage High, V
1.4
-0.5
INH
Input Current, I , I
INH INL
V+ = 3.3V, V = 0V or V+ (Note 7)
IN
0.5
µA
NOTES:
4. V = input voltage to perform proper function.
IN
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Guaranteed but not tested.
8. R
matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron
ON
value.
9. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2.0V, GND = 0V, V
Unless Otherwise Specified
= 1.0V, V
= 0.4V (Note 4, 6),
INL
INH
TEMP
(°C)
MIN
(NOTE 5)
MAX
(NOTE 5) UNITS
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
V+
0.35
0.4
-
V
Ω
ON Resistance, R
V+ = 1.8V, I
COM
Figure 4, Note 7
= 100mA, V
or V = 0V to V+, See
NO NC
0.26
ON
Full
25
-
-
Ω
R
Matching Between Channels, V+ = 1.8V, I
COM
= 100mA, V
NO
or V
= Voltage at
or V = 0V to V+,
NC
-
0.005
Ω
ON
∆R
NC
Max R
Note 8
ON
ON,
Full
25
-
0.005
-
Ω
R
Flatness, R
V+ = 1.8V, I
Note 9
= 100mA, V
-
0.074
-
Ω
ON
FLAT(ON)
COM
NO
Full
25
-
0.082
-
Ω
NO or NC OFF Leakage Current,
or I
V+ = 2.0V, V
COM
= 0.3V, 1.8V, V
NO
or V
NC
= 1.8V, 0.3V
-3
-60
-3
-80
-
-
-
-
3
nA
nA
nA
nA
I
NO(OFF)
NC(OFF)
Full
25
60
3
COM ON Leakage Current,
V+ = 2.0V, V
= 0.3V, 1.8V, or V
or V
= 0.3V,
NC
COM
NO
I
1.8V
COM(ON)
Full
80
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 1.65V, V
or V
= 1.0V, R =50Ω, C = 35pF,
25
Full
25
-
-
-
-
-
30
-
40
45
35
40
-
ns
ns
ns
ns
pC
ON
NO
NC
L
L
V
= 0 to 1.65V, See Figure 1, Note 7
IN
Turn-OFF Time, t
V+ = 1.65V, V
or V
= 1.0V, R =50Ω, C = 35pF,
25
-
OFF
NO
NC
L
L
V
= 0 to 1.65V, See Figure 1, Note 7
IN
Full
25
Charge Injection, Q
C
= 1.0nF, V = 0V, R = 0Ω, See Figure 2
-80
L
G
G
FN6091.2
June 23, 2006
4
ISL43L120, ISL43L121, ISL43L122
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2.0V, GND = 0V, V
Unless Otherwise Specified (Continued)
= 1.0V, V
= 0.4V (Note 4, 6),
INL
INH
TEMP
(°C)
MIN
(NOTE 5)
MAX
(NOTE 5) UNITS
PARAMETER
OFF Isolation
Crosstalk (Channel-to-Channel)
TEST CONDITIONS
R = 50Ω, C = 5pF, f = 100kHz, V
TYP
62
= 1 V See
RMS,
25
25
25
25
-
-
-
-
-
-
-
-
dB
dB
pF
pF
L
L
COM
Figure 3 and Figure 5
-94
182
182
NO or NC OFF Capacitance, C
COM OFF Capacitance,
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V, See Figure 6
= 0V, See Figure 6
OFF
NO
NO
NC
COM
COM
NC
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
or V
= V
= 0V, See Figure 6
25
-
290
-
pF
COM(ON)
NO
NC
COM
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 1.65V to 3.6V, V = 0V or V+, all channels on or
IN
off
25
-
-
-
-
30
nA
nA
Full
750
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.4
-
V
V
INL
Input Voltage High, V
1.0
-0.5
INH
Input Current, I
, I
V+ = 2.0V, V = 0V or V+ (Note 7)
IN
0.5
µA
INH INL
Test Circuits and Waveforms
V+
V+
t < 5ns
r
t < 5ns
f
C
LOGIC
INPUT
50%
0V
NO
0V
t
V
OFF
OUT
NO or NC
IN
SWITCH
INPUT
COM
SWITCH
INPUT
V
V
OUT
90%
90%
R
50Ω
C
35pF
LOGIC
INPUT
L
L
GND
SWITCH
OUTPUT
t
ON
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
------------------------------
V
= V
OUT
(NO or NC)
R
+ R
(ON)
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
SWITCH
OUTPUT
∆V
OUT
V
R
OUT
G
COM
NO or NC
GND
V
OUT
V+
0V
ON
ON
LOGIC
INPUT
V
OFF
G
IN
C
L
LOGIC
INPUT
Q = ∆V
x C
L
OUT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
FN6091.2
June 23, 2006
5
ISL43L120, ISL43L121, ISL43L122
Test Circuits and Waveforms (Continued)
V+
V+
C
C
R
= V /100mA
1
ON
SIGNAL
GENERATOR
NO or NC
NO or NC
V
NX
IN
1mA
0V or V+
X
0V or V+
IN
V
1
COM
COM
ANALYZER
GND
GND
R
L
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FIGURE 4. R
TEST CIRCUIT
ON
V+
C
V+
C
SIGNAL
GENERATOR
50Ω
NO1 or NC1
COM1
NO or NC
IN
1
IN
0V or V+
X
0V or V+
0V or V+
IN
2
IMPEDANCE
ANALYZER
COM
NO2 or NC2
GND
COM2
ANALYZER
NC
GND
R
L
FIGURE 5. CROSSTALK TEST CIRCUIT
FIGURE 6. CAPACITANCE TEST CIRCUIT
Supply Sequencing and Overvoltage Protection
Detailed Description
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 7). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
The ISL43L12X family of devices are bidirectional, single
pole/single throw (SPST) analog switches that offer precise
switching capability from a single 1.65V to 3.6V supply with
low on-resistance (0.16Ω) and high speed operation
(t
= 13ns, t = 13ns). The device is especially well
ON
OFF
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(2.7µW max), low leakage currents (80nA max), and the tiny
TDFN and MSOP packaging. The ultra low on-resistance and
R
flatness provide very low insertion loss and distortion to
ON
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 7). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
application that require signal reproduction.
FN6091.2
June 23, 2006
6
ISL43L120, ISL43L121, ISL43L122
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low R switch, so two small signal
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2V to 3.6V (see Figure 14). At 3.6V
ON
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 7). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
the V level is about 1.27V. This is still below the 1.8V
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
IH
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
OPTIONAL PROTECTION
DIODE
In 50Ω systems, signal response is reasonably flat even past
20MHz with a -3dB bandwidth of 175MHz (see Figure 15).
The frequency response is very consistent over a wide V+
range, and for varying analog signal levels.
V+
OPTIONAL
PROTECTION
RESISTOR
IN
V
X
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 16 details the high Off Isolation and Crosstalk
rejection provided by this family. At 100kHz, Off Isolation is
about 62dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
V
NO or NC
COM
GND
OPTIONAL PROTECTION
DIODE
FIGURE 7. OVERVOLTAGE PROTECTION
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Power-Supply Considerations
The ISL43L12x construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL43L12X 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
The minimum recommended supply voltage is 1.65V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and on-
resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
FN6091.2
June 23, 2006
7
ISL43L120, ISL43L121, ISL43L122
Typical Performance Curves T = 25°C, Unless Otherwise Specified
A
0.26
0.24
0.22
0.2
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
V+ = 3V
= 100mA
I
= 100mA
COM
I
COM
V+ = 1.8V
85°C
25°C
0.18
0.16
0.14
0.12
V+ = 2.7V
V+ = 3V
V+ = 3.6V
-40°C
0
0.5
1
1.5
(V)
2
2.5
3
0
1
2
3
4
V
V
(V)
COM
COM
FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
50
0.3
V+ = 1.8V
= 100mA
I
COM
0
-50
V+ = 3V
85°C
0.25
0.2
-100
-150
-200
-250
V+ = 1.8V
25°C
-40°C
0.15
0.1
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
V
(V)
V
(V)
COM
COM
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 11. CHARGE INJECTION vs SWITCH VOLTAGE
50
80
70
60
50
40
30
20
10
0
40
85°C
30
85°C
25°C
-40°C
25°C
20
10
0
-40°C
1
1.5
2
2.5
V+ (V)
3
3.5
4
4.5
1.5
2
2.5
3
3.5
4
4.5
1
V+ (V)
FIGURE 12. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 13. TURN - OFF TIME vs SUPPLY VOLTAGE
FN6091.2
June 23, 2006
8
ISL43L120, ISL43L121, ISL43L122
Typical Performance Curves T = 25°C, Unless Otherwise Specified (Continued)
A
1.8
V+ = 3V
0
1.6
1.4
1.2
1
GAIN
-20
PHASE
0
V
INH
20
40
60
80
100
V
INL
0.8
0.6
0.4
0.2
R
= 50Ω
= 0.2V to 2V
L
V
IN
P-P P-P
1
1.5
2
2.5
3
3.5
4
4.5
1M
10M
100M
FREQUENCY (Hz)
600M
V+ (V)
FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 15. FREQUENCY RESPONSE
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
20
30
40
50
60
70
80
90
V+ = 3V
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
114
ISOLATION
PROCESS:
Submicron CMOS
CROSSTALK
-100
-110
100
110
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 16. CROSSTALK AND OFF ISOLATION
FN6091.2
June 23, 2006
9
ISL43L120, ISL43L121, ISL43L122
Thin Dual Flat No-Lead Plastic Package (TDFN)
2X
L8.3x3A
0.15
C A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
0.15
C B
SYMBOL
MIN
0.70
NOMINAL
0.75
MAX
0.80
NOTES
A
A1
A3
b
-
-
0.25
2.20
1.40
0.02
0.05
-
E
0.20 REF
0.30
-
6
0.35
2.40
1.60
5, 8
INDEX
AREA
D
3.00 BSC
2.30
-
D2
E
7, 8, 9
TOP VIEW
B
3.00 BSC
1.50
-
E2
e
7, 8, 9
// 0.10
0.08
C
0.65 BSC
-
-
A
C
k
0.25
0.20
-
-
L
0.30
0.40
8
C
SIDE VIEW
A3
SEATING
PLANE
N
8
2
Nd
4
3
D2
D2/2
2
7
8
Rev. 3 11/04
(DATUM B)
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
1
6
INDEX
AREA
NX k
E2
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM A)
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
e
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8
(Nd-1)Xe
REF.
M
0.10
C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
9. Compliant to JEDEC MO-WEEC-2 except for the “L” min
dimension.
C
L
(A1)
NX (b)
5
L1
10
L
e
SECTION "C-C"
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
FN6091.2
June 23, 2006
10
ISL43L120, ISL43L121, ISL43L122
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6091.2
June 23, 2006
11
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