ISL45042IR [INTERSIL]
LCD Module Calibrator; 液晶显示模块校准器
| 型号： | ISL45042IR |
| 厂家： | 
Intersil |
| 描述： | LCD Module Calibrator |
| 文件： | 总7页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL45042
®
Data Sheet
June 21, 2005
FN6072.3
LCD Module Calibrator
Features
• 128-Step Adjustable Sink Current Output
The VCOM voltage of an LCD panel needs to be adjusted to
remove flicker. This part provides a digital interface to control
the sink-current output that attaches to an external voltage
divider. The increase in output sink current lowers the
voltage on the external divider, which is applied to an
external VCOM buffer amplifier. Once the desired VCOM
setting is obtained, the settings can be stored in the non-
volatile memory, which would then be automatically recalled
during every power-up.
• 2.6V to 3.6V Logic Supply Voltage Operating Range
• 4.5V to 20V Analog Supply Voltage Range
• Rewritable EEPROM for storing the optimum VCOM value
• Output Adjustment Enable/Disable Control
• Output Guaranteed Monotonic Over Temperature
• Two Pin Adjustment, Programming and Enable
• Ultra Thin 8-Pin 3mm x 3mm DFN (0.8mm max)
• Pb-Free Plus Anneal Available (RoHS Compliant)
The VCOM adjustment and non-volatile memory
programming is through a single interface pin. An additional
pin is used to prevent programming.
An external resistor attaches to the SET pin, and sets the
full-scale sink current that determines the lowest voltage of
the external voltage divider.
Applications
• LCD Panels
The ISL45042 is available in an 8-pin 3mm x 3mm Thin DFN
package with a maximum thickness of 0.8mm for ultra thin
LCD panel design.
Ordering Information
TEMP.
PKG.
PART NO.
ISL45042IR
ISL45042IR-T
RANGE (°C)
PACKAGE
DWG. #
Pinout
-40 to 85 8 Ld 3x3 Thin DFN
L8.3x3A
L8.3x3A
ISL45042 (THIN DFN)
-40 to 85 8 Ld 3x3 Thin DFN
Tape and Reel
TOP VIEW
OUT
AVDD
N/C
1
2
3
4
8
7
6
5
SET
CE
ISL45042IRZ
(Note)
-40 to 85 8 Ld 3x3 Thin DFN
(Pb-free)
L8.3x3A
L8.3x3A
CTL
ISL45042IRZ-T
(Note)
-40 to 85 8 Ld 3x3 Thin DFN
Tape and Reel (Pb-free)
GND
V
DD
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL45042
Pin Descriptions
PIN
FUNCTION
OUT
Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink
current divided by 128. See SET pin function description for the maxim adjustable sink current setting.
AVDD
N/C
High-Voltage Analog Supply. Bypass to GND with 0.1µF capacitor.
No Connect. Not internally connected.
GND
Ground connection.
V
System power supply input. Bypass to GND with 0.1µF capacitor.
DD
CTL
Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments
the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high
transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage
at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter.
See EEPROM Programming section for details.
CE
Counter Enable Pin. Connect CE to V
to enable counting of the internal counter. Connect CE to GND to inhibit counting.
DD
SET
Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the
OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.
Block Diagram
ISL45042
IBIAS
CE
AVDD
IOUT
SET
UP
DWN
CTL
ANALOG DCP AND
CURRENT OUTPUT
BLOCK
DIGITAL INTERFACE
WITH THRESHOLD
SENSORS
PWRUP
POR
UP/DOWN COUNTER
WITH PRESET
LATCHES
PRGM
READ
PRGM MEMORY
POR
EEPROM
OR
NVL MEMORY
PRGM
GND
V
DD
FN6072.3
2
June 21, 2005
ISL45042
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 1)
8 Ld Thin DFN Package. . . . . . . . . . . . . . . . . . . . . .
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Erase/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,000
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 years @ 85°C
V
to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4V
θ
DD
JA
90(°C/W)
Input Voltages to GND
SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V
Output Voltages to GND
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
ESD Rating
HBM for Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75kV
HBM for CTL to GND (no EEPROM Content Disruption). . . . .8kV
Operating Conditions
Temperature Range
ISL45042IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
Electrical Specifications Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, R
= 24.9kΩ; Unless Otherwise Specified.
SET
Typicals are at T = 25°C
A
TEMP
PARAMETER
SYMBOL
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
V
Supply Range
Supply Current
V
For Programming
For Operation
CE = V
0 to 85
Full
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.6
3.6
50
20
23
3
V
V
DD
DD
DD
2.6
V
I
Full
-
µA
µA
mA
mA
V
DD
DD
CE = GND
Full
-
Program (Charge Pump Current) (Note 5)
Read (Note 5)
0 to 85
Full
-
-
AVDD Supply Range
AVDD
IAVDD
Full
4.5
-
20
20
AVDD Supply Current
(Note 3)
Full
µA
V
CTL High Voltage
CTL
2.6V < V
2.6V < V
< 3.6V
< 3.6V
Full
0.7*V
0.8*V
IH
CTL
DD
DD
DD
DD
DD
DD
CTL Low Voltage
Full
0.2*V
0.3*V
V
IL
CTL High Rejected Pulse Width
CTL Low Rejected Pulse Width
CTL High Minimum Pulse Width
CTL Low Minimum Pulse Width
CTL
CTL
Full
20
20
-
-
-
µs
µs
µs
µs
µs
IHRPW
ILRPW
IHMPW
ILMPW
Full
CTL
CTL
Full
200
200
10
Full
-
CTL Minimum Time Between
Counts
CTL
Full
-
MTC
CTL Input Current
ICTL
CTL = GND
Full
Full
Full
Full
Full
Full
Full
-
-
-
-
-
-
10
µA
µA
pF
V
CTL = V
(Note 5)
10
DD
CTL Input Capacitance
CE Input Low Voltage
CTL
10
-
-
CAP
CE
2.6V < V
2.6V < V
(Note 5)
2.6V < V
< 3.6V
< 3.6V
0.4
IL
DD
DD
CE Input High Voltage
CE
1.6
1
-
-
-
V
IH
CE Minimum Start Up Time
CTL EEPROM Program Voltage
CE
-
ms
V
ST
CTL
< 3.6V, (Note 2)
4.9
-
15.75
PROM
DD
FN6072.3
3
June 21, 2005
ISL45042
Electrical Specifications Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, R
= 24.9kΩ; Unless Otherwise Specified.
SET
Typicals are at T = 25°C (Continued)
A
TEMP
PARAMETER
SYMBOL
CTL
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
CTL EEPROM Programming
Signal Time
>4.9V
Full
200
-
-
µs
PT
Programming Time
EE Write Cycles
P
Full
25
100
-
ms
Cycles
Bits
LSB
LSB
LSB
µA
T
EE
Guaranteed by Design
(Note 4)
1000
-
WC
SET Voltage Resolution
SET Differential Nonlinearity
SET Zero-Scale Error
SET Full-Scale Error
SET Current
SET
SET
Full
Full
Full
Full
Full
Full
Full
Full
7
-
-
VR
DN
Monotonic Over Temperature
-
-
±1
±2
±8
120
200
45
-
SET
-
-
ZSE
FSE
SET
-
-
-
ISET
SET
Through R
(Note 5)
-
SET
SET External Resistance
To GND, AVDD = 20V (Note 5)
To GND, AVDD = 4.5V (Note 5)
10
2.25
-
-
-
kΩ
ER
kΩ
AVDD to SET Voltage Attenuation
AVDD to
SET
1:20
V/V
OUT Settling Time
OUT Voltage Range
OUT
to ±0.5 LSB Error Band (Note 5)
Full
Full
-
20
-
-
µs
ST
V
(Note 5)
VSET +
0.5V
13
V
OUT
OUT Voltage Drift
NOTES:
OUT
(Note 5)
25 to 55
-
-
10
mV
VD
2. CTL signal only needs to be greater than 4.9V to program EEPROM.
3. Tested at AVDD = 20V.
4. The Counter value is set to mid-scale ±4 LSB’s in the Production.
5. Simulated and Determined via Design and NOT Directly Tested.
The adjustment of the output and the programming of the
non-volatile memory are provided on one pin, while the
counter enable (CE) is provided on a separate pin. The
output is adjusted via the CTL pin either by counting up with
a mid to low transition, or by counting down with a mid to
high transition. Once the minimum or maximum value is
reached on the 128-steps, the device will not overflow or
underflow beyond that minimum or maximum value. An
increment of the counter will increase the output sink
current, which will lower the voltage on the external voltage
divider. A decrement of the counter will decrease the output
sink current, which will raise the voltage on the external
voltage divider.
Application Information
This device provides the ability to reduce the flicker of an
LCD panel by adjustment of the VCOM voltage during
production test and alignment. A 128-step resolution is
provided under digital control, which adjusts the sink current
of the output. The output is connected to an external voltage
divider, so that the device will have the capability to reduce
the voltage on the output by increasing the output sink
current.
AVDD
AVDD
ISL45042
R
1
Once the desired output level is obtained, the part can store
its setting using the non-volatile memory in the device. (See
the Non-volatile programming section for detailed
information.)
-
+
OUT
SET
R
2
R
SET
The output adjustment can also be prevented from changing
by pulling down the counter enable pin.
FIGURE 1. OUTPUT CONNECTION CIRCUIT EXAMPLE
FN6072.3
4
June 21, 2005
ISL45042
AVDD
R
R
a
AVDD
ISL45042
OUT
AVDD
R
VCOM
-
+
1
VCOM
b
-
+
SET
R
2
R
c
R
= Ra
R
SET
1
2
R
R
= Rb + Rc
= (Ra(Rb + Rc)) / 20Rb
SET
FIGURE 2. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042
To avoid unintentional adjustment, the ISL45042 guarantees
to reject CTL pulses shorter than 20µs.
Adjustable Sink Current Output
The device provides an output sink current which lowers the
voltage on the external voltage divider. The equations that
control the output are given below. See Figure 1.
To avoid the possibility of a false pulse (since the internal
comparators come up in an unknown state) the very first
CTL pulse is ignored. See Figure 4 for the timing
Setting
AVDD
IOUT = --------------------X----------------------------
information.
128
20(RSET)
.
R2
Setting
R1
ISL45042
----------------------
VOUT =
VAVDD 1 – --------------------X----------------------------
1kΩ
R1 + R2
128
20(RSET)
CTL
0.01µF
NOTE: Where setting is an integer between 1 and 128.
Replacing Existing Mechanical Potentiometer
Circuits
Figure 2 shows the common adjustment mechanical circuits
and equivalent replacement with the ISL45042.
FIGURE 3. EXTERNAL ESD PROTECTION ON CTL PIN
TABLE 1. TRUTH TABLE
INPUT
CE
Hi
OUTPUT
ICC
7-Bit UP/DOWN Counter
CTL
Mid to Hi
Mid to Lo
X
VDD
VDD
SET
MEMORY
The counter sets the level to the digital potentiometer and is
connected to the non-volatile memory. When the part is
programmed, the counter setting is loaded into the
non-volatile memory. This value will be loaded from the
non-volatile memory into the counter during power-on. The
counter will not exceed its maximum level and will hold that
value during subsequent increment requests on the CTL pin.
The counter will not exceed its minimum level and will hold
that value during subsequent decrement requests on the
CTL pin.
Decrement
Increment
No Change
Normal
Normal
Lower
X
X
X
Hi
VDD
Lo
VDD
>4.9V
X
X
VDD
No Change Increased Program
Read Increased Read
X
0 to VDD
NOTE: ‘CE’ should be disabled (pulled low) before powering the
device down to assure that the glitches and transients will not cause
unwanted EEPROM overwriting.
NOTE: In case where CE is tied to VDD, CTL pin should be tied to
ground (pulled low) when the programming is finished (should not
move the counter as the first pulse after programming is ignored),
and before the power-down. This will assure that no glitches or
transients on CTL input would cause unwanted counter movements.
CTL Pin
CTL should have a noise filter to reduce bouncing or noise
on the input that could cause unwanted counting when the
CE pin is high. The board should have an additional ESD
protection circuit, with a series 1kΩ resistor and a shunt
0.01µF capacitor connected on the CTL pin. (See Figure 3)
In order to increment the setting, pulse CTL low for more
than 200µs. The output sink current increases and lowers
the VCOM lever by one least-significant bit (LSB). On the
other hand, to decrement the setting, pulse CTL high for
more than 200µs. The output sink current will decrease, and
the VCOM level will increase by one LSB.
FN6072.3
5
June 21, 2005
ISL45042
CTL
CE
IHRPW
ST
CTL
MTC
CTL HIGH
CTL
V
/2
DD
CTL LOW
CTL
CTL
ILMPW
IHMPW
CTL
ILRPW
CE
COUNTER
OUTPUT
UNDEF.
78
79
7A
7B
7A
VCOM
FIGURE 4. VCOM ADJUSTMENT
Non-Volatile Memory (EEPROM)
Programming
When the CTL pin exceeds 4.9V, the non-volatile
programming cycle will be activated. The CTL signal needs
to remain above 4.9V for more than 200µs. The level and
timing needed to program the non-volatile memory is given
below. It then takes a maximum of 100ms for the
programming to be completed inside the device (see P
specification in Electrical Specification Table).
T
CTL VOLTAGE
>200µs
4.9V
CTL
PT
TIME
FIGURE 5. EEPROM PROGRAMMING
FN6072.3
6
June 21, 2005
ISL45042
Thin Dual Flat No-Lead Plastic Package (TDFN)
2X
L8.3x3A
0.15
C A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
NOMINAL
0.75
0.15
C B
SYMBOL
MIN
0.70
MAX
0.80
NOTES
A
A1
A3
b
-
-
0.25
2.20
1.40
0.02
0.05
-
E
0.20 REF
0.30
-
6
0.35
2.40
1.60
5, 8
INDEX
AREA
D
3.00 BSC
2.30
-
D2
E
7, 8, 9
TOP VIEW
SIDE VIEW
B
3.00 BSC
1.50
-
E2
e
7, 8, 9
// 0.10
0.08
C
0.65 BSC
-
-
A
C
k
0.25
0.20
-
-
L
0.30
0.40
8
C
A3
SEATING
N
8
2
PLANE
Nd
4
3
D2
D2/2
2
7
8
Rev. 3 11/04
(DATUM B)
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
1
6
INDEX
NX k
E2
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
AREA
(DATUM A)
5. Dimension b applies to the metallized terminal and is measured
E2/2
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
e
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
8
improved electrical and thermal performance.
(Nd-1)Xe
REF.
M
0.10
C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
9. Compliant to JEDEC MO-WEEC-2 except for the “L” min
C
dimension.
L
(A1)
NX (b)
5
L1
10
L
e
SECTION "C-C"
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6072.3
7
June 21, 2005
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