ISL54048_技术文档

ISL54048, ISL54049

®

Data Sheet

March 20, 2007

FN6469.0

Ultra Low ON-Resistance, +1.65V to +4.5V,

Single Supply, Dual SPST Analog Switch

Features

• ON-Resistance (r

)

ON

The Intersil ISL54048 and ISL54049 devices are low ON-

resistance, low voltage, bidirectional, dual single-pole/single-

throw (SPST) analog switches designed to operate from a

single +1.65V to +4.5V supply. Targeted applications include

- V+ = +4.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29Ω

- V+ = +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33Ω

- V+ = +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55Ω

• r

Matching Between Channels . . . . . . . . . . . . . . . . . 0.06Ω

Flatness Across Signal Range . . . . . . . . . . . . . . . . 0.03Ω

ON

battery powered equipment that benefit from low r

(0.29Ω)

= 20ns). The

ON

and fast switching speeds (t

ON

= 40ns, t

OFF

• r

digital logic input is 1.8V logic-compatible when using a single

+3V supply.

• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V

• Low Power Consumption (P ). . . . . . . . . . . . . . . <0.45μW

D

Cell phones, for example, often face ASIC functionality

limitations. The number of analog input or GPIO pins may be

limited and digital geometries are not well suited to analog

switch performance. This part may be used to “mux-in”

additional functionality while reducing ASIC design risk. The

ISL54048 and ISL54049 are offered in a small form factor

package, alleviating board space limitations.

• Fast Switching Action (V+ = +4.3V)

- t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns

ON

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns

OFF

• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV

• 1.8V Logic Compatible (+3V supply)

• Low ICC Current when VinH is not at the V+ Rail

• Available in 10 Ld 1.8mmx1.4mmx0.5mm μTQFN

• Pb-free plus anneal available (RoHS compliant)

The ISL54048 has two normally open (NO) SPST switches

and the ISL54049 has two normally closed (NC) SPST

switches.

TABLE 1. FEATURES AT A GLANCE

ISL54048, ISL54049

Applications

• Battery powered, Handheld, and Portable Equipment

- Cellular/mobile Phones

Number of Switches

SW

2

SPST

- Pagers

4.3V r

ON

0.29Ω

- Laptops, Notebooks, Palmtops

4.3V t /t

ON OFF

40ns/20ns

0.33Ω

• Portable Test and Measurement

• Medical Equipment

3V r

ON

• Audio and Video Switching

3V t /t

50ns/27ns

0.55Ω

ON OFF

1.8V r

ON

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

1.8V t /t

70ns/54ns

ON OFF

10 Ld 1.8mmx1.4mmx0.5mm

Package

μTQFN

• Application Note AN557 “Recommended Test Procedures

for Analog Switches”

Ordering Information

PART NUMBER (Note)

PART MARKING

TEMP. RANGE (°C)

PACKAGE (Pb-Free)

PKG. DWG. #

L10.1.8x1.4A

ISL54048IRUZ-T

B

C

-40 to +85

10 Ld 1.8x1.4x0.5 μTQFN

Tape and Reel

ISL54049IRUZ-T

-40 to +85

10 Ld 1.8x1.4x0.5 μTQFN

L10.1.8x1.4A

Tape and Reel

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL54048, ISL54049

Pinouts (Note 1)

ISL54048

(10 LD μTQFN)

TOP VIEW

ISL54049

(10 LD μTQFN)

TOP VIEW

N.C.

7

GND

6

NC2

7

GND

6

N.C.

IN1

8

9

5

NC1

IN1

IN2

8

5

IN2

4

COM2

NO2

9

COM2

N.C. 10

10

3

COM1

3

COM1

2

1

V+

NO1

V+

N.C.

NOTE:

1. Switches Shown for Logic “0” Input.

Truth Table

LOGIC

ISL54048

OFF

ISL54049

0

1

ON

OFF

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

Pin Descriptions

FUNCTION

System Power Supply Input (+1.65V to +4.5V)

Ground Connection

V+

GND

IN

Digital Control Input

COM

NOx

NCx

NC

Analog Switch Common Pin

Analog Switch Normally Open Pin

Analog Switch Normally Closed Pin

No Connect

FN6469.0

March 20, 2007

2

ISL54048, ISL54049

Absolute Maximum Ratings

Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V

Input Voltages

NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)

Output Voltages

COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)

Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA

ESD Rating:

Thermal Resistance (Typical)

θ

(°C/W)

143

JA

10 Ld μTQFN Package (Note 3) . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(Lead Tips Only)

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .>8kV

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . .>500V

Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . >1.4kV

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.

3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications - 4.3V Supply

Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V

Unless Otherwise Specified

= 1.6V, V

= 0.5V (Notes 4),

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

-

V+

V

Ω

ON-Resistance, r

V+ = 3.9V, I

= 100mA, V

or V = 0V to V+,

NC

-

0.30

0.35

0.06

0.08

0.03

0.04

-

ON

COM

(See Figure 4)

NO

Full

25

-

Ω

r

Matching Between Channels,

V+ = 3.9V, I

COM

= 100mA, V

NO

or V = Voltage at max

NC

-

Ω

ON

Δr

r

(Note 7)

ON

ON,

Full

25

-

Ω

r

Flatness, r

FLAT(ON)

V+ = 3.9V, I

(Note 6)

= 100mA, V

or V = 0V to V+,

NC

-

Ω

ON

COM

NO

Full

25

-

Ω

NO or NC OFF Leakage Current,

or I

V+ = 4.5V, V

COM

= 0.3V, 3V, V

NO

or V

NC

= 3V, 0.3V

-100

-195

-100

-195

100

195

100

195

nA

I

NO(OFF)

NC(OFF)

Full

25

-

COM ON Leakage Current,

V+ = 4.5V, V

= 0.3V, 3V, or V

or V = 0.3V,

NC

-

COM

3V, or floating

NO

I

COM(ON)

Full

-

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 3.9V, V

or V

= 3.0V, R =50Ω, C = 35pF,

25

Full

25

-

40

50

-

ns

pC

dB

ON

NO

(See Figure 1)

NC

L

Turn-OFF Time, t

V+ = 3.9V, V

= 3.0V, R =50Ω, C = 35pF,

20

OFF

NO

(See Figure 1)

L

Full

25

30

Charge Injection, Q

OFF Isolation

C

R

= 1.0nF, V = 0V, R = 0Ω, See Figure 2

170

62

L

G

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

,

25

L

COM

RMS

(See Figure 3)

Crosstalk (Channel-to-Channel)

Total Harmonic Distortion

R

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

25

-

-85

-

dB

%

L

COM

(See Figure 5)

f = 20Hz to 20kHz, V

= 2V

, R = 600Ω

P-P

0.005

COM

L

FN6469.0

March 20, 2007

3

ISL54048, ISL54049

Electrical Specifications - 4.3V Supply

Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V

Unless Otherwise Specified (Continued)

= 1.6V, V

= 0.5V (Notes 4),

(NOTE 5)

INH

INL

TEMP (NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

NO or NC OFF Capacitance, C

f = 1MHz, V

or V

= V

= 0V, (See Figure 6)

25

-

62

-

pF

OFF

NO

NC

COM

COM ON Capacitance, C

25

176

COM(ON)

NC

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

25

1.65

4.5

0.1

1

V

Positive Supply Current, I+

V+ = +4.5V, V = 0V or V+

IN

-

μA

Full

25

Positive Supply Current, I+

V+ = +4.2V, V = 2.85V

IN

12

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.5

-

V

INL

Input Voltage High, V

1.6

-0.5

INH

Input Current, I

, I

V+ = 4.5V, V = 0V or V+

IN

0.5

μA

INH INL

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

Unless Otherwise Specified

= 1.4V, V

= 0.5V (Notes 4),

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

-

0.35

-

V+

0.5

0.7

0.07

0.08

0.15

-

V

Ω

ON-Resistance, r

V+ = 2.7V, I

= 100mA, V

or V

= 0V to V+,

= Voltage at

= 0V to V+,

ON

COM

(See Figure 4)

NO

NC

Full

25

Ω

r

Matching Between Channels,

V+ = 2.7V, I

COM

= 100mA, V

or V

0.06

-

Ω

ON

Δr

NO

NC

max r , (Note 7)

ON

Full

25

Ω

r

Flatness, r

FLAT(ON)

V+ = 2.7V, I

(Note 6)

= 100mA, V

or V

NC

0.03

-

Ω

ON

COM

NO

Full

25

Ω

NO or NC OFF Leakage Current,

or I

V+ = 3.3V, V

= 0.3V, 3V, V

NO

or V

NC

= 3V, 0.3V

0.9

30

0.8

30

nA

COM

I

NO(OFF)

NC(OFF)

Full

25

-

COM ON Leakage Current,

V+ = 3.3V, V

or floating

= 0.3V, 3V, or V

or V

= 0.3V, 3V,

NC

-

COM

NO

I

COM(ON)

Full

-

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 2.7V, V

or V

= 1.5V, R = 50Ω, C = 35pF,

25

Full

25

-

50

60

27

35

94

62

-

ns

pC

dB

ON

NO

(See Figure 1)

NC

L

Turn-OFF Time, t

V+ = 2.7V, V

= 1.5V, R = 50Ω, C = 35pF,

L L

OFF

NO

(See Figure 1)

Full

25

Charge Injection, Q

OFF Isolation

C

R

= 1.0nF, V = 0V, R = 0Ω, (See Figure 2)

G G

L

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

,

25

L

COM

RMS

(See Figure 3)

Crosstalk (Channel-to-Channel)

Total Harmonic Distortion

R

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

25

-

-85

-

dB

L

COM

RMS

(See Figure 5)

f = 20Hz to 20kHz, V

= 2V , R = 600Ω

P-P

25

-

0.005

65

-

%

pF

COM

L

NO or NC OFF Capacitance, C

f = 1MHz, V

or V

= V

= 0V, (See Figure 6)

OFF

NO

NC

COM

COM ON Capacitance, C

or V

= V

181

COM(ON)

FN6469.0

March 20, 2007

4

ISL54048, ISL54049

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

Unless Otherwise Specified (Continued)

= 1.4V, V

= 0.5V (Notes 4),

(NOTE 5)

INH

INL

TEMP (NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+

V+ = +3.6V, V = 0V or V+

IN

25

-

0.01

0.52

-

μA

Full

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

25

-

0.5

-

V

INL

Input Voltage High, V

1.4

-0.5

INH

Input Current, I

, I

V+ = 3.3V, V = 0V or V+

IN

Full

0.5

μA

INH INL

Electrical Specifications - 1.8V Supply

Test Conditions: V+ = +1.65V to +2V, GND = 0V, V

Unless Otherwise Specified

= 1.0V, V

= 0.4V (Note 4),

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

-

0.7

-

V+

0.8

V

Ω

ON-Resistance, r

V+ = 1.65V, I

= 100mA, V

or V

= 0V to V+,

NC

ON

COM

(See Figure 4)

NO

Full

-

0.85

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 1.65V, V

or V

= 1.0V, R =50Ω, C = 35pF,

25

Full

25

-

70

80

-

ns

pC

pF

ON

NO

(See Figure 1)

NC

L

Turn-OFF Time, t

V+ = 1.65V, V

= 1.0V, R =50Ω, C = 35pF,

54

OFF

NO

(See Figure 1)

L

Full

25

65

Charge Injection, Q

C

= 1.0nF, V = 0V, R = 0Ω, (See Figure 2)

42

L

G

NO

G

NO or NC OFF Capacitance, C

f = 1MHz, V

or V

= V

= 0V, (See Figure 6)

25

70

OFF

NC

COM

COM ON Capacitance, C

or V

= V

25

186

COM(ON)

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

25

-

0.4

-

V

INL

Input Voltage High, V

1.0

-0.5

INH

Input Current, I , I

INH INL

V+ = 2.0V, V = 0V or V+

IN

Full

0.5

μA

NOTES:

4. V = input voltage to perform proper function.

IN

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

7. r

matching between channels is calculated by subtracting the channel with the highest max r

value from the channel with lowest max r

ON ON

ON

value, between Nx1 and Nx2.

FN6469.0

March 20, 2007

5

ISL54048, ISL54049

Test Circuits and Waveforms

V+

C

V+

t < 5ns

r

t < 5ns

f

LOGIC

INPUT

50%

0V

V

OUT

t

NX1 OR NX2

OFF

SWITCH

INPUT

COM

SWITCH

INPUT

V

Nx1

0V

IN

V

OUT

90%

C

L

35pF

R

50Ω

LOGIC

INPUT

L

GND

SWITCH

OUTPUT

t

ON

Logic input waveform is inverted for switches that have the opposite

logic sense.

Repeat test for all switches. C includes fixture and stray

L

capacitance.

r

L

----------------------------

V

= V

OUT

(NO or NC)

R

+ r

(ON)

L

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

V+

C

V

R

OUT

G

COM

NX1 OR NX2

GND

SWITCH

OUTPUT

ΔV

OUT

V

OUT

V

G

IN

C

L

V+

0V

ON

LOGIC

INPUT

LOGIC

INPUT

OFF

Q = ΔV

x C

L

OUT

Repeat test for all switches.

FIGURE 2B. TEST CIRCUIT

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2. CHARGE INJECTION

V+

C

V+

C

SIGNAL

GENERATOR

r

= V /100mA

1

ON

NX1 OR NX2

V

NX

IN

0V or V+

100mA

IN

V

1

COM

GND

ANALYZER

COM

GND

R

L

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

Repeat test for all switches.

FIGURE 3. OFF ISOLATION TEST CIRCUIT

FIGURE 4. r

TEST CIRCUIT

ON

FN6469.0

March 20, 2007

6

ISL54048, ISL54049

Test Circuits and Waveforms (Continued)

V+

C

SIGNAL

GENERATOR

50Ω

NX1 OR NX2

COM

NX1 OR NX2

IN

1

0V or V+

IN

0V or V+

IMPEDANCE

ANALYZER

COM

GND

NX1 OR NX2

COM

ANALYZER

N.C.

GND

R

L

Repeat test for all switches.

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

FIGURE 5. CROSSTALK TEST CIRCUIT

FIGURE 6. CAPACITANCE TEST CIRCUIT

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

Detailed Description

The ISL54048 and ISL54049 are bidirectional, dual single

pole/single throw (SPST) analog switches that offer precise

switching capability from a single 1.65V to 4.5V supply with

low on-resistance (0.29Ω) and high speed operation

purpose of using a low r

switch. Connecting schottky

ON

diodes to the signal pins (as shown in Figure 7) will shunt the

fault current to the supply or to ground thereby protecting the

switch. These schottky diodes must be sized to handle the

expected fault current.

(t

= 40ns, t = 20ns). The devices are especially well

ON

OFF

suited for portable battery powered equipment due to their

low operating supply voltage (1.65V), low power

Power-Supply Considerations

consumption (4.5µW max), low leakage currents (195nA max)

and the tiny µTQFN package. The ultra low ON-resistance

The ISL54048 and ISL54049 construction is typical of most

single supply CMOS analog switches, in that they have two

supply pins: V+ and GND. V+ and GND drive the internal

CMOS switches and set their analog voltage limits. Unlike

switches with a 4V maximum supply voltage, the ISL54048

and ISL54049 4.7V maximum supply voltage provides plenty

of room for the 10% tolerance of 4.3V supplies, as well as

room for overshoot and noise spikes.

and r

flatness provide very low insertion loss and distortion

ON

to applications that require signal reproduction.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. All I/O pins contain

ESD protection diodes from the pin to V+ and to GND (see

Figure 7). To prevent forward biasing these diodes, V+ must

be applied before any input signals, and the input signal

voltages must remain between V+ and GND.

The minimum recommended supply voltage is 1.65V. It is

important to note that the input signal range, switching times,

and ON-resistance degrade at lower supply voltages. Refer

to “Electrical Specifications” on page 3 and the Typical

Performance Curves on page 8 for details.

If these conditions cannot be guaranteed, then precautions

must be implemented to prohibit the current and voltage at

the logic pin and signal pins from exceeding the maximum

ratings of the switch. The following two methods can be used

to provided additional protection to limit the current in the

event that the voltage at a signal pin or logic pin goes below

ground or above the V+ rail.

OPTIONAL

SCHOTTKY

DIODE

V+

OPTIONAL

PROTECTION

RESISTOR

IN

V

X

V

NX

COM

Logic inputs can be protected by adding a 1kΩ resistor in

series with the logic input (see Figure 7). The resistor limits

the input current below the threshold that produces

permanent damage, and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

GND

OPTIONAL

SCHOTTKY

DIODE

FIGURE 7. OVERVOLTAGE PROTECTION

FN6469.0

March 20, 2007

7

ISL54048, ISL54049

V+ and GND also power the internal logic and level shiftiers.

An OFF switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal

feedthrough from a switch’s input to its output. Off isolation is

the resistance to this feedthrough, while crosstalk indicates

the amount of feedthrough from one switch to another.

Figure 21 details the high off isolation and crosstalk rejection

provided by this part. At 100kHz, off isolation is about 62dB

in 50Ω systems, decreasing approximately 20dB per decade

as frequency increases. Higher load impedances decrease

off isolation and crosstalk rejection due to the voltage divider

action of the switch OFF impedance and the load

impedance.

The level shiftiers convert the input logic levels to switched

V+ and GND signals to drive the analog switch gate

terminals.

This family of switches cannot be operated with bipolar

supplies because the input switching point becomes

negative in this configuration.

Logic-Level Thresholds

This switch family are 1.8V logic compatible (0.5V and 1.4V)

over a supply range of 2.7V to 4.5V (see Figure 17). At 2.7V,

the V level is about 0.53V. This is still above the 1.8V logic

IL

guaranteed low output maximum level of 0.5V, but noise

margin is reduced.

Leakage Considerations

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND. One of

these diodes conducts if any analog signal exceeds V+ or

GND.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

the digital input signals from GND to V+ with a fast transition

time minimizes power dissipation.

Virtually all the analog leakage current comes from the ESD

diodes to V+ or GND. Although the ESD diodes on a given

signal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biased by either

V+ or GND and the analog signal. This means their leakages

will vary as the signal varies. The difference in the two diode

leakages to the V+ and GND pins constitutes the analog-

signal-path leakage current. All analog leakage current flows

between each pin and one of the supply terminals, not to the

other switch terminal. This is why both sides of a given

switch can show leakage currents of the same or opposite

polarity. There is no connection between the analog signal

paths and V+ or GND.

The ISL54048 and ISL54049 have been designed to

minimize the supply current whenever the digital input

voltage is not driven to the supply rails (0V to V+). For

example, driving the device with 2.85V logic (0V to 2.85V)

while operating with a 4.2V supply the device draws only

12µA of current (see Figure 15 for VIN = 2.85V).

Frequency Performance

In 50Ω systems, the ISL54048 and ISL54049 have a -3dB

bandwidth of 120MHz (see Figure 20). The frequency

response is very consistent over a wide V+ range, and for

varying analog signal levels.

Typical Performance Curves T = +25°C, Unless Otherwise Specified

A

0.3

0.29

0.28

0.27

0.26

0.25

0.35

I

= 100mA

COM

I

= 100mA

COM

0.34

0.33

0.32

0.31

0.30

0.29

0.28

V+ = 2.7V

V+ = 3.9V

V+ = 3V

V+ = 4.3V

V+ = 3.3V

V+ = 4.5V

3

0

1

2

4

5

0

0.5

1.0

1.5

2.0

(V)

2.5

3.0

3.5

V

COM

V

(V)

COM

FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FN6469.0

March 20, 2007

8

ISL54048, ISL54049

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

0.70

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.35

0.30

0.25

0.20

V+ = 4.3V

= 100mA

I

= 100mA

COM

I

COM

+85°C

+25°C

V+ = 1.65V

V+ = 1.8V

V+ = 2V

-40°C

0

1

2

V

3

4

5

0

0.5

1.0

COM

1.5

2.0

V

(V)

COM

FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE

0.40

V+ = 3.3V

COM

V+ = 2.7V

COM

I

= 100mA

I

= 100mA

+85°C

+25°C

-40°C

0.35

0.30

0.25

0.20

+85°C

+25°C

-40°C

0.35

0.30

0.25

0

0.5

1.0

1.5

(V)

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

(V)

2.5

3.0

3.5

V

COM

FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE

FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE

0.60

200

V+ = 1.8V

+85°C

V+ = 4.2V

I

= 100mA

COM

0.55

0.50

0.45

0.40

0.35

0.30

0.25

SWEEPING BOTH LOGIC INPUTS

+25°C

-40°C

150

100

50

0

0.5

1.0

1.5

2.0

1

2

3

4

5

V

(V)

V

AND V (V)

IN2

COM

IN1

FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE

FIGURE 15. SUPPLY CURRENT vs VLOGIC VOLTAGE

FN6469.0

March 20, 2007

9

ISL54048, ISL54049

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

200

150

100

50

V

INH

V+ = 4.3V

V+ = 3V

V

INL

V+ = 1.8V

0

-50

-100

0

1

2

3

4

5

1.5

2.0

2.5

3.0

V+ (V)

3.5

4.0

4.5

V

(V)

COM

FIGURE 16. CHARGE INJECTION vs SWITCH VOLTAGE

FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE

250

200

150

+85°C

+25°C

100

50

0

150

+25°C

-40°C

100

-40°C

1.5

25

1.0

2.0

2.5

3.0

3.5

4.0

4.5

1.5

2.0

2.5

3.0

3.5

4.0

4.5

V+ (V)

FIGURE 18. TURN-ON TIME vs SUPPLY VOLTAGE

FIGURE 19. TURN-OFF TIME vs SUPPLY VOLTAGE

-10

-20

-30

-40

-50

-60

-70

-80

-90

10

20

30

40

50

60

70

80

90

V+ = 3.0V

V+ = 4.3V

0

GAIN

-20

ISOLATION

0

PHASE

20

40

60

80

CROSSTALK

R

= 50Ω

= 0.2V

-100

-110

100

110

L

V

to 2V

P-P P-P

IN

1M

10M

100M

300M

1k

10k

100k

1M

10M

100M 500M

FREQUENCY (Hz)

FIGURE 20. FREQUENCY RESPONSE

FIGURE 21. CROSSTALK AND OFF ISOLATION

FN6469.0

March 20, 2007

10

ISL54048, ISL54049

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

114

PROCESS:

Submicron CMOS

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6469.0

March 20, 2007

11

ISL54048, ISL54049

Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)

L10.1.8x1.4A

D

A

B

10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC

PACKAGE

6

MILLIMETERS

INDEX AREA

N

E

SYMBOL

MIN

0.45

NOMINAL

MAX

0.55

NOTES

2X

0.10 C

A

A1

A3

b

0.50

-

1

2

2X

0.10 C

-

0.05

-

TOP VIEW

0.127 REF

-

0.15

1.75

1.35

0.20

1.80

1.40

0.40 BSC

0.40

0.50

10

0.25

1.85

1.45

5

D

-

0.10 C

C

E

-

A

0.05 C

SEATING PLANE

e

-

A1

L

0.35

0.45

0.55

-

SIDE VIEW

L1

N

-

2

Nd

Ne

θ

2

3

(DATUM A)

PIN #1 ID

NX L

3

5

NX b

10X

1

2

0

-

12

4

L1

0.10 M C A B

Rev. 3 6/06

0.05 M C

NOTES:

(DATUM B)

5

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

7

e

3. Nd and Ne refer to the number of terminals on D and E side,

respectively.

BOTTOM VIEW

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

C

L

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

(A1)

NX (b)

5

L

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

SECTION "C-C"

e

TERMINAL TIP

C C

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.

2.20

1.00

0.60

1.00

0.50

1.80

0.40

0.20

0.40

10

LAND PATTERN

FN6469.0

March 20, 2007

12


型号：	ISL54048
厂家：	Intersil
描述：	Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPST Analog Switch 超低导通电阻， + 1.65V至+ 4.5V单电源，双路SPST模拟开关开关
文件：	总12页 (文件大小：327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL54048 [INTERSIL]

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