ISL54057IRUZ-T_技术文档

ISL54057

®

Data Sheet

September 29, 2006

FN6379.0

Ultra Low ON-Resistance, Low-Voltage,

Single Supply, Differential 4 to 1 Analog

Multiplexer

Features

• Pb-Free Plus Anneal Available (RoHS Compliant)

• ON Resistance (R

)

ON

The Intersil ISL54057 device contains precision, bidirectional,

analog switches configured as a differential 4-channel

multiplexer/demultiplexer, designed to operate from a single

+1.6V to +3.6V supply. The devices have an inhibit pin to

simultaneously open all signal paths.

- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.41Ω

- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.61Ω

• R

Matching Between Channels. . . . . . . . . . . . . . . . 0.09Ω

ON

• R

Flatness Across Signal Range . . . . . . . . . . . . . . 0.07Ω

ON

ON resistance is 0.41Ω with a +3V supply and 0.61Ω with a

single +1.8V supply. Each switch can handle rail to rail

analog signals. The off-leakage current is only 4nA max at

+25°C or 35nA max at +85°C with a +3.3V supply.

• Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V

• Low Power Consumption (PD). . . . . . . . . . . . . . . . . <0.18µW

• Fast Switching Action (V = +3V)

S

- t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27ns

ON

All digital inputs are 1.8V logic-compatible when using a

single +3V supply.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18ns

OFF

• Break-Before-Make

The ISL54057 is a differential 4 to 1 multiplexer device that is

offered in a 16 Ld 2.6x1.8x0.5mm µTQFN package.

• High Current Handling Capacity (300mA Continuous)

• Available in 16 Ld 2.6x1.8x0.5mm µTQFN

• 1.8V CMOS-Logic Compatible (+3V Supply)

Table 1 summarizes the performance of this family.

TABLE 1. FEATURES AT A GLANCE

ISL54057

Applications

Configuration

3V R

Diff 4:1 Mux

0.41Ω

• Battery Powered, Handheld, and Portable Equipment

- Cellular/Mobile Phones

ON

3V t /t

27ns/18ns

ON OFF

- Pagers

1.8V R

0.61Ω

- Laptops, Notebooks, Palmtops

ON

1.8V t /t

34ns/26ns

ON OFF

• Portable Test and Measurement

• Medical Equipment

Packages

16 Ld 2.6x1.8x0.5mm µTQFN

• Audio and Video Switching

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

• Application Note AN557 “Recommended Test Procedures

for Analog Switches”

Ordering Information

PART NUMBER (NOTE)

PART MARKING

TEMP. RANGE (°C)

PACKAGE

PKG. DWG. #

ISL54057IRUZ-T

GAB

-40 to +85

16 Ld Thin µQFN Tape and Reel (Pb-free) L16.2.6x1.8A

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination

finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-

free peak reflow temperatures that meet or exceed the

Pb-free requirements of IPC/JEDEC J STD-020C.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL54057

Pinouts (Note 1)

ISL54057

(16 LD µTQFN)

TOP VIEW

B2

ADD1

V+

A0

A2

ADD0

GND

N.C.

NOTE:

1. 2.6mm x 1.8mm x 0.5mm

Truth Table

Pin Descriptions

ISL54057

ADD1

FUNCTION

INH

1

ADD0

SWITCH ON

NONE

V+

System Power Supply Input (1.6V to 3.6V)

No Connect. Not internally connected.

Ground Connection

X

0

1

X

0

1

0

1

N.C.

GND

INH

0

A0, B0

0

A1, B1

Digital Control Input. Connect to GND for Normal

Operation. Connect to V+ to turn all switches off.

0

A2, B2

COMA Analog Switch Channel A Output

COMB Analog Switch Channel B Output

A0-A3 Analog Switch Channel A Input

B0-B3 Analog Switch Channel B Input

ADDx Address Input Pin

0

A3, B3

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V, with a 3V supply.

X = Don’t Care.

FN6379.0

September 29, 2006

2

ISL54057

Absolute Maximum Ratings

Thermal Information

o

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V

Input Voltages

INH, Ax, Bx, ADDx (Note 2) . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V

Output Voltages

COMx (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V

Continuous Current NO or COM . . . . . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO or COM

Thermal Resistance (Typical, Note 3)

θ

( C/W)

JA

µTQFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . .

93

Maximum Junction Temperature (Plastic Package) . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(Lead Tips Only)

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA

ESD Rating

Operating Conditions

Temperature Range

ISL54057IRUZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV

MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300V

CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Signals on Ax, Bx, COMx, ADDx, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current

ratings.

3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications: 3V Supply

Test Conditions: V

(Notes 4, 8), Unless Otherwise Specified

= +2.7V to +3.3V, GND = 0V, V

= 1.4V, V

= 0.5V

SUPPLY

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

Full

25

0

-

V+

0.75

0.8

0.2

0.15

4

V

Ω

ANALOG

ON Resistance, R

V+ = 2.7V, I

= 100mA, V

V

AX or BX

= 0V to V+

= Voltage at

= 0V t0 V+

-

0.43

ON

COM

(See Figure )

Full

25

-

Ω

R

Matching Between Channels, V+ = 2.7V, I

V

AX or BX

-

0.09

Ω

ON

∆R

COM

max R , Note 6

ON

Full

25

-

Ω

R

Flatness, R

V+ = 2.7V, I

(Note 7)

V

AX or BX

-

0.07

Ω

ON

FLAT(ON)

COM

Full

25

-

Ω

Ax or Bx OFF Leakage Current,

or I

V+ = 3.3V, V

= 0.3V, 3V, V

V

= 3V, 0.3V

-4

-35

-8.5

-60

nA

COM

AX or BX

I

Ax(OFF)

Bx(OFF)

Full

25

35

COM ON Leakage Current,

V+ = 3.3V, V

= V

V

= 0.3V, 3V

8.5

60

AX or BX

I

COM(ON)

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V , V

Full

1.4

-

V

INH ADDH

Input Voltage Low, V , V

0.5

INL ADDL

, I , I

Input Current, I

INH INL ADDH

,

V+ = 3.3V, V

= V

= 0V or V+

ADD

-0.5

µA

INH

I

ADDL

DYNAMIC CHARACTERISTICS

Inhibit Turn-ON Time, t

V+ = 2.7V, V

(See Figure 1)

V

= 1.5V, R = 50Ω, C = 35pF

25

Full

25

-

27

37

18

28

29

40

4

-

ns

pF

ON

Ax or Bx

L

Inhibit Turn-OFF Time, t

OFF

V+ = 2.7V, V

See Figure 1

V

= 1.5V, R = 50Ω, C = 35pF,

Ax or Bx L L

Full

25

Address Transition Time, t

V+ = 2.7V, V

(See Figure 1)

V

= 1.5V, R = 50Ω, C = 35pF

TRANS

BBM

AX or BX L L

Full

25

Break-Before-Make Time, t

V+ = 3.3V, V

V

= 1.5V, R = 50Ω, C = 35pF

L L

AX or BX

(See Figure 2)

Full

25

1

Ax or Bx OFF Capacitance, C

OFF

f = 1MHz, V

V

= V

= 0V (See Figure )

= 0V (See Figure 6)

44

149

201

AX or BX

COM

COM OFF Capacitance, C

V

AX or BX

25

OFF

COM ON Capacitance, C

V

AX or BX

25

COM(ON)

FN6379.0

September 29, 2006

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ISL54057

Electrical Specifications: 3V Supply

Test Conditions: V

= +2.7V to +3.3V, GND = 0V, V

= 1.4V, V

= 0.5V

SUPPLY

(Notes 4, 8), Unless Otherwise Specified (Continued)

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

= 50Ω, C = 35pF, f = 100kHz

(°C)

MIN

TYP

65

MAX

UNITS

dB

OFF Isolation

R

25

-

L

(See Figures 3 and 5)

Crosstalk, Note 9

25

-100

dB

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

25

1.6

3.6

0.05

1.1

V

Positive Supply Current, I+

NOTES:

V+ = 3.3V, V

, V

INH ADD

= 0V or V+, Switch On or Off

-

µA

Full

4. V = Input voltage to perform proper function.

IN

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. R

R

matching between channels is calculated by subtracting the channel with the highest max R

value.

value from the channel with lowest max

ON

7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

8. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.

9. Between any two switches.

Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, V

= 1V, V

= 0.4V (Note 4, 8),

INL

INH

Unless Otherwise Specified

TEMP

(°C)

MIN

(NOTE 5)

MAX

(NOTE 5) UNITS

PARAMETER

TEST CONDITIONS

TYP

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

Full

25

0

-

V+

V

Ω

ANALOG

ON Resistance, R

V+ = 1.8V, I

= 10.0mA, V

V = 1.0V

AX or BX

0.61

-

0.85

ON

COM

(See Figure 4)

Full

25

0.9

R

Matching Between Channels, V+ = 1.8V, I

V = 1.0V

AX or BX

0.11

0.12

0.19

-

ON

∆R

COM

(Note 6)

ON)

Full

25

R

Flatness, R

V+ = 1.8V, I

V = 0V, 0.9V,

AX or BX

ON

FLAT(ON)

COM

1.6V (Note 7)

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V , V

Full

1

-

V

INH ADDH

Input Voltage Low, V , V

0.4

0.5

INL ADDL

, I , I

Input Current, I

INH INL ADDH

,

V+ = 1.8V, V

, V

INH ADD

= 0V or V+

-0.5

µA

I

ADDL

DYNAMIC CHARACTERISTICS

Inhibit Turn-ON Time, t

V+ = 1.8V, V

(See Figure 1)

V

= 1.0V, R = 50Ω, C = 35pF

25

Full

25

-

34

45

26

37

35

46

9

-

ns

ON

Ax or Bx

L

Inhibit Turn-OFF Time, t

OFF

V+ = 1.8V, V

V

= 1.0V, R = 50Ω, C = 35pF

L L

Ax or Bx

(See Figure 1)

Full

25

Address Transition Time, t

V+ = 1.8V, V

V

= 1.0V, R = 50Ω, C = 35pF

L L

TRANS

BBM

AX or BX

(See Figure 1)

Full

25

Break-Before-Make Time, t

V+ = 1.8V, V

V

= 1.0V, R = 50Ω, C = 35pF

L L

AX or BX

(See Figure 2A)

FN6379.0

September 29, 2006

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ISL54057

Test Circuits and Waveforms

V+

C

V+

t < 5ns

r

t < 5ns

f

LOGIC

INPUT

50%

0V

V+

A0, B0

V

t

OUT

ON

A1,A2,B1,

B2,A3,B3

COMA

COMB

INH

V

VA0, VB0

OUT

ADD0-1

GND

90%

C

35pF

L

R

50Ω

LOGIC

INPUT

L

SWITCH

OUTPUT

0V

t

OFF

Logic input waveform is inverted for switches that have the opposite

logic sense.

Repeat test for other switches. C includes fixture and stray

L

capacitance.

R

L

------------------------------

V

= V

OUT

(NO or NC)

R

+ R

(ON)

L

FIGURE 1A. INHIBIT t /t

ON OFF

MEASUREMENT POINTS

FIGURE 1B. INHIBIT t /t

TEST CIRCUIT

ON OFF

V+

0V

t < 5ns

r

t < 5ns

f

LOGIC

INPUT

V+

50%

C

t

TRANS

V

V+

A0, B0

V

OUT

A1,A2,B1,

B2,A3,B3

OUT

VA0, VB0

COMA,

COMB

90%

SWITCH

OUTPUT

ADD0-1

INH

GND

C

35pF

L

R

50Ω

L

LOGIC

INPUT

10%

VA3, VB3

0V

t

TRANS

Logic input waveform is inverted for switches that have the opposite

logic sense.

Repeat test for other switches. C includes fixture and stray

L

capacitance.

R

L

------------------------------

V

= V

OUT

(NO or NC)

R

+ R

(ON)

L

FIGURE 1D. ADDRESS t

TRANS

TEST CIRCUIT

FIGURE 1C. ADDRESS t

MEASUREMENT POINTS

TRANS

FIGURE 1. SWITCHING TIMES

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September 29, 2006

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ISL54057

Test Circuits and Waveforms (Continued)

V+

t < 5ns

r

C

t < 5ns

f

C

V+

0V

LOGIC

INPUT

V

OUT

A0-A3

B0-B3

COMA

COMB

V+

C

R

L

ADD0-1

50Ω

35pF

90%

SWITCH

OUTPUT

V

OUT

LOGIC

INPUT

0V

t

GND INH

BBM

Repeat test for other switches. C includes fixture and stray

L

capacitance.

FIGURE 2A. t

BBM

MEASUREMENT POINTS

FIGURE 2B. t

TEST CIRCUIT

BBM

FIGURE 2. BREAK-BEFORE-MAKE TIME

V+

10nF

C

SIGNAL

GENERATOR

R

= V /100mA

1

ON

Ax or Bx

V

X

0V or V+

100mA

0V or V+

ADD1

ADD0

V

1

ADD1

ADD0

Channel

Select

Channel

Select

COMA or

COMB

ANALYZER

COMx

GND INH

GND

INH

R

L

Off-Isolation is measured between COM and “Off” NO terminal on

each switch.

Signal direction through switch is reversed and worst case values

are recorded.

FIGURE 4. R

TEST CIRCUIT

ON

FIGURE 3. OFF ISOLATION TEST CIRCUIT

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September 29, 2006

6

ISL54057

Test Circuits and Waveforms (Continued)

V+

C

V+

C

0V or V+

SIGNAL

GENERATOR

50Ω

Ax or Bx

A

COM

x

A

0V or V+

ADD1

ADD0

ADD1

ADD0

IMPEDANCE

ANALYZER

Channel

Select

Channel

Select

COMA or COMB

INH

B

N.C.

x

GND

ANALYZER

COM

B

GND INH

R

L

Crosstalk is measured between adjacent channels with one channel

ON and the other channel OFF.

Signal direction through switch is reversed and worst case values

are recorded.

FIGURE 6. CAPACITANCE TEST CIRCUIT

FIGURE 5. CROSSTALK TEST CIRCUIT

Logic inputs can be protected by adding a 1kΩ resistor in

series with the logic input (see Figure 7). The resistor limits

the input current below the threshold that produces

permanent damage, and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

Detailed Description

The ISL54057 analog switch offer precise switching

capability from a single 1.6V to 3.6V supply with low

on-resistance (0.41Ω) and high speed operation

(t

= 27ns, t = 18ns). The devices are especially well

ON

OFF

suited to portable battery powered equipment thanks to the

low operating supply voltage (1.6V), low power consumption

(0.17µW), low leakage currents (60nA max) , and the tiny

µTQFN package. The ultra low on-resistance and Ron

flatness provide very low insertion loss and distortion to

applications that require signal reproduction.

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

purpose of using a low R

switch. Connecting schottky

ON

diodes to the signal pins as shown in Figure 7 will shunt the

fault current to the supply or to ground thereby protecting the

switch. These schottky diodes must be sized to handle the

expected fault current.

Supply Sequencing And Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. All I/O pins contain

ESD protection diodes from the pin to V+ and to GND (see

Figure 7). To prevent forward biasing these diodes, V+ must

be applied before any input signals, and the input signal

voltages must remain between V+ and GND.

OPTIONAL

SCHOTTKY

DIODE

V+

OPTIONAL

INH

PROTECTION

RESISTOR

or

ADD

X

If these conditions cannot be guaranteed, then precautions

must be implemented to prohibit the current and voltage at

the logic pin and signal pins from exceeding the maximum

ratings of the switch. The following two methods can be used

to provided additional protection to limit the current in the

event that the voltage at a signal pin or logic pin goes below

ground or above the V+ rail.

Ax or Bx

V

COMX

GND

OPTIONAL

SCHOTTKY

DIODE

FIGURE 7. OVERVOLTAGE PROTECTION

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September 29, 2006

7

ISL54057

The frequency response is very consistent over a wide V+

Power-Supply Considerations

range, and for varying analog signal levels.

The ISL54057 construction is typical of most CMOS analog

switches, in that they have two supply pins: V+ and GND. V+

and GND drive the internal CMOS switches and set their

analog voltage limits. Unlike switches with a 4V maximum

supply voltage, the ISL54057 4.7V maximum supply voltage

provides plenty of room for the 10% tolerance of 3.6V

supplies, as well as room for overshoot and noise spikes.

An OFF switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal feed

through from a switch’s input to its output. Off Isolation is the

resistance to this feed through, while Crosstalk indicates the

amount of feed through from one switch to another.

Figure 11 details the high Off Isolation and Crosstalk

rejection provided by this family. At 100kHz, Off Isolation is

about 65dB in 50Ω systems, decreasing approximately 20dB

per decade as frequency increases. Higher load

The minimum recommended supply voltage is 1.6V but the

part will operate with a supply below 1.5V. It is important to

note that the input signal range, switching times, and

on-resistance degrade at lower supply voltages. Refer to the

electrical specification tables and Typical Performance

curves for details.

impedances decrease Off Isolation and Crosstalk rejection

due to the voltage divider action of the switch OFF

impedance and the load impedance.

Leakage Considerations

V+ and GND power the internal logic (thus setting the digital

switching point) and level shifters. The level shifters convert

the logic levels to switched V+ and V- signals to drive the

analog switch gate terminals.

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND.

One of these diodes conducts if any analog signal exceeds

V+ or GND.

Logic-Level Thresholds

Virtually all the analog leakage current comes from the ESD

diodes to V+ or GND. Although the ESD diodes on a given

signal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biased by either

V+ or GND and the analog signal. This means their leakages

will vary as the signal varies. The difference in the two diode

leakages to the V+ and GND pins constitutes the analog-

signal-path leakage current. All analog leakage current flows

between each pin and one of the supply terminals, not to the

other switch terminal. This is why both sides of a given

switch can show leakage currents of the same or opposite

polarity. There is no connection between the analog signal

paths and V+ or GND.

This device is 1.8V CMOS compatible (0.5V and 1.4V) over

a supply range of 2.7V to 3.6V. At 2.7V the V level is about

IL

0.54V. This is still above the 1.8V CMOS guaranteed low

output maximum level of 0.5V but noise margin is reduced.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

the digital input signals from GND to V+ with a fast transition

time minimizes power dissipation.

High-Frequency Performance

In 50Ω systems, signal response is reasonably flat even past

10MHz with a -3dB bandwidth of 70MHz (see Figure 12).

Typical Performance Curves T = +25°C, Unless Otherwise Specified

A

0.8

0.7

0.6

0.5

0.4

0.3

0.5

0.45

0.4

V+ = 3V

= 100mA

I

= 100mA

COM

I

V+ = 1.65V

COM

+85°C

+25°C

-40°C

V+ = 1.8V

0.35

0.3

V+ = 2.7V

V+ = 3V

V+ = 3.6V

2

0.25

0

0.5

1

1.5

(V)

2

2.5

3

0

1

3

4

V

(V)

COM

FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE

FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

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September 29, 2006

8

ISL54057

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

0

-10

-20

-30

450

-50

-60

-70

-80

10

20

30

40

50

60

70

80

90

0.7

0.65

0.6

V+ = 1.8V

= 100mA

V+ = 3V

I

COM

+85°C

+25°C

-40°C

0.55

0.5

ISOLATION

0.45

0.4

CROSSTALK

10M

-90

100

110

0.35

0

0.5

1

1.5

2

-100

V

(V)

COM

1k

10k

100k

1M

100M 500M

FREQUENCY (Hz)

FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE

FIGURE 11. CROSSTALK AND OFF ISOLATION

Die Characteristics

V+ = 3V

GAIN

0

SUBSTRATE POTENTIAL (POWERED UP):

GND

-10

TRANSISTOR COUNT:

228

0

PHASE

PROCESS:

20

40

60

80

Submicron CMOS

R

= 50Ω

= 0.2V

L

100

V

to 2V

IN

P-P P-P

0.1

1

10

FREQUENCY (MHz)

FIGURE 12. FREQUENCY RESPONSE

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6379.0

September 29, 2006

9

ISL54057

Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)

L16.2.6x1.8A

D

A

B

16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

6

INDEX AREA

SYMBOL

MIN

0.45

NOMINAL

MAX

0.55

NOTES

N

E

A

A1

A3

b

0.50

-

2X

0.10 C

1 2

-

0.05

-

2X

0.10 C

0.127 REF

-

TOP VIEW

0.15

2.55

1.75

0.20

2.60

1.80

0.40 BSC

0.40

0.50

16

0.25

2.65

1.85

5

D

-

0.10 C

E

-

C

A

0.05 C

SEATING PLANE

e

-

L

0.35

0.45

0.55

-

A1

L1

N

-

SIDE VIEW

2

Nd

Ne

θ

4

3

e

4

3

PIN #1 ID

L1

1 2

0

-

12

4

NX L

Rev. 4 8/06

NOTES:

5

NX b

16X

(DATUM B)

(DATUM A)

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

0.10 M C A B

0.05 M C

3. Nd and Ne refer to the number of terminals on D and E side,

respectively.

BOTTOM VIEW

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

C

L

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

(A1)

NX (b)

5

L

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

e

SECTION "C-C"

TERMINAL TIP

C C

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.

3.00

1.80

1.40

0.90

1.40

2.20

0.40

0.20

0.40

0.50

10

LAND PATTERN

FN6379.0

September 29, 2006

10


型号：	ISL54057IRUZ-T
厂家：	Intersil
描述：	Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer 超低导通电阻，低电压，单电源，差分4：1模拟多路复用器复用器
文件：	总10页 (文件大小：265K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL54057IRUZ-T [INTERSIL]

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