ISL54206AEVAL1Z_技术文档

MP3/USB 2.0 High Speed Switch with Negative

Signal Handling

ISL54206A

Features

• High Speed (480Mbps) and Full Speed (12Mbps)

Signaling Capability per USB 2.0

The Intersil ISL54206A dual SPDT (Single Pole/Double

Throw) switches combine low distortion audio and

accurate USB 2.0 high speed data (480Mbps) signal

switching in the same low voltage device. When operated

with a 2.7V to 3.6V single supply, these analog switches

allow audio signal swings below-ground, allowing the use

of a common USB and audio headphone connector in

Personal Media Players and other portable battery

powered devices.

• Low Distortion Negative Signal Capability

• Control Pin to Open all Switches and Enter Low

Power State

• Low Distortion Headphone Audio Signals

- THD+N at 20mW into 32Ω Load. . . . . . . <0.1%

• Cross-talk Audio Channels (20Hz to 20kHz) . . -110dB

The ISL54206A logic control pins are 1.8V compatible,

which allows for control via a standard µcontroller. With a

• Single Supply Operation (V ) . . . . . 2.5V to 5.5V

DD

• -3dB Bandwidth USB Switches. . . . . . . . . 630MHz

• Available in µTQFN and TDFN Packages

• Pb-Free (RoHS Compliant)

V

voltage in the range of 2.7V to 3.6V, the IN pin

DD

voltage can exceed the V

rail allowing for the USB 5V

DD

voltage from a computer to directly drive the IN pin

V

BUS

to switch between the audio and USB signal sources in

the portable device. The part has an audio enable control

pin to open all the switches and put the part in a low

power state.

• Compliant with USB 2.0 Short Circuit Requirements

Without Additional External Components

Applications*(see page 17)

• MP3 and Other Personal Media Players

• Cellular/Mobile Phones

• PDA’s

The ISL54206A is available in a small 10 Ld

2.1mmx1.6mm ultra-thin µTQFN package and a 10 Ld

3mmx3mm TDFN package. It operates over a

temperature range of -40°C to +85°C.

• Audio/USB Switching

Related Literature*(see page 17)

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”.

• Application Note AN1337 “ISL54206AEVAL1Z

Evaluation Board User’s Manual”.

Application Block Diagram

V

DD

µCONTROLLER

ISL54206A

CTRL

IN

VBUS

LOGIC

USB

HIGH-SPEED

4MΩ

D-

COM-

TRANSCEIVER

D+

L

COM+

CODEC

R

GND

NOTE: The L and R 50kΩ resistors to ground are not shown.

September 30, 2010

FN6515.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL54206A

Pin Configurations (Note 1)

ISL54206A

(10 LD µTQFN)

TOP VIEW

ISL54206A

(10 LD TDFN)

TOP VIEW

PD

10

VDD

IN

CTRL

D-

10

9

1

2

4M

LOGIC

VDD

IN

9

D-

LOGIC

CONTROL

1

2

3

4

CONTROL

COM -

D+

3

4

5

8

7

6

D+

8

7

6

COM +

GND

L

COM -

L

R

COM +

R

50k

5

NOTE:

1. ISL54206A Switches shown for IN = Logic “0” and CTRL = Logic “1”.

Truth Table

Pin Descriptions

ISL54206A

IN

0

CTRL L, R

D+, D-

OFF

PIN NO. NAME

FUNCTION

0

1

X

OFF

ON

1

2

VDD Power Supply

IN Digital Control Input

0

OFF

1

OFF

ON

3

COM- Voice and Data Common Pin

COM+ Voice and Data Common Pin

GND Ground Connection

IN: Logic “0” when ≤0.5V, Logic “1” when ≥1.4V with 2.7V to

3.6V supply.

CTRL: Logic “0” when ≤0.5V or Floating, Logic “1” when ≥1.4V

with 2.7V to 3.6V supply.

4

5

6

R

L

Audio Right Input

Audio Left Input

7

8

D+ USB Differential Input

D- USB Differential Input

CTRL Digital Control Input (Audio Enable)

9

10

-

PD

Thermal Pad. Tie to Ground or Float

(TDFN package only)

FN6515.2

September 30, 2010

2

ISL54206A

Ordering Information

PART NUMBER

(Note 5)

PART

MARKING

TEMP. RANGE

PACKAGE

(Pb-Free)

PKG.

DWG. #

(°C)

ISL54206AIRTZ (Note 3)

06AZ

-40 to +85

10 Ld 3mmx3mm TDFN

10 Ld 3mmx3mm TDFN (Tape and Reel)

L10.3x3A

ISL54206AIRTZ-T (Notes 2, 3) 06AZ

ISL54206AIRUZ-T (Notes 2, 4) FU

10 Ld 2.1mmx1.6mm µTQFN (Tape and Reel) L10.2.1x1.6A

ISL54206AEVAL1Z

NOTES:

Evaluation Board

2. Please refer to TB347 for details on reel specifications.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach

materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54206A. For more information on MSL please

see techbrief TB363.

FN6515.2

September 30, 2010

3

ISL54206A

Absolute Maximum Ratings

Thermal Information

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.0V

Input Voltages

Thermal Resistance (Typical)

θ_JA(°C/W) θ_JC(°C/W)

10 Ld µTQFN (Notes 7, 8) . . . . . . .

10 Ld TDFN (Notes 9, 10) . . . . . . .

Maximum Junction Temperature (Plastic Package). . +150°C

Maximum Storage Temperature Range . . . -65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

145

55

90

16

D+, D-, L, R (Note 6). . . . . . . . . . - 2V to ((V ) + 0.3V)

DD

IN (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . -2V to 5.5V

CTRL (Note 6). . . . . . . . . . . . . . . -0.3 to ((V ) + 0.3V)

DD

Output Voltages

COM-, COM+ (Note 6) . . . . . . . . . . -2V to ((V ) + 0.3V)

DD

Continuous Current (Audio Switches) . . . . . . . . . . ±150mA

Peak Current (Audio Switches)

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . -40°C to +85°C

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . ±300mA

Continuous Current (USB Switches) . . . . . . . . . . . . ±40mA

Peak Current (USB Switches)

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . ±100mA

ESD Rating:

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >7kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >400V

Charged Device Model . . . . . . . . . . . . . . . . . . . . .>1.4kV

Latch-up Tested per JEDEC; Class II Level A . . . . . . at 85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

6. Signals on D+, D-, L, R, COM-, COM+, CTRL, IN exceeding V

maximum current ratings.

or GND by specified amount are clamped. Limit current to

DD

7. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief

JA

TB379 for details.

8. For θ , the “case temp” location is taken at the package top center.

JC

9. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”

JA

features. See Tech Brief TB379.

10. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V

= +3.3V, GND = 0V, V

= 1.4V,

= 0.5V, (Note 11), unless

DD

INH

V

= 0.5V, V

= 1.4V, V

INL

CTRLH

CTRLL

otherwise specified. Boldface limits apply over the operating

temperature range, -40°C to +85°C.

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 12, 15) TYP (Notes 12, 15) UNITS

ANALOG SWITCH CHARACTERISTICS

Audio Switches (L, R)

Analog Signal Range,

V

= 3.0V, IN = 0.5V, CTRL = 1.4V

Full

25

-1.5

-

1.5

V

Ω

DD

V

ANALOG

ON-Resistance, r

V

= 5.0V, IN = 0V, CTRL = V , I

= 40mA,

-

2.47

2.50

2.87

-

ON

DD DD COMx

V or V = -0.85V to 0.85V, (See Figure 3)

L

R

V

= 4.2V, IN = 0V, CTRL = V , I

= 40mA,

DD

DD COMx

V or V = -0.85V to 0.85V, (See Figure 3)

L

R

V

= 2.85V, IN = 0V, CTRL = V , I

= 40mA,

COMx

DD

DD COMx

V or V = -0.85V to 0.85V, (See Figure 3)

L

R

V

= 3.0V, IN = 0.5V, CTRL = 1.4V, I

25

Full

25

-

2.65

4.0

5.5

Ω

DD

V or V = -0.85V to 0.85V, (See Figure 3)

L

R

-

0.02

-

R

Matching Between

V

= 3.0V, IN = 0.5V, CTRL = 1.4V, I = 40mA,

COMx

0.13

0.16

ON

Channels, Δr

DD

V or V = Voltage at max r

over signal range of

ON

L

R

ON

Full

-0.85V to 0.85V, (Note 14)

R

Flatness, R

V

= 3.0V, IN = 0.5V, CTRL = 1.4V, I

= 40mA,

25

-

0.03

-

0.05

Ω

ON

FLAT(ON)

DD

COMx

V or V = -0.85V to 0.85V, (Note 13)

L

R

Full

0.07

FN6515.2

September 30, 2010

4

ISL54206A

Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V

= +3.3V, GND = 0V, V

= 1.4V,

= 0.5V, (Note 11), unless

DD

INH

V

= 0.5V, V

= 1.4V, V

INL

CTRLH

CTRLL

otherwise specified. Boldface limits apply over the operating

temperature range, -40°C to +85°C. (Continued)

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 12, 15) TYP (Notes 12, 15) UNITS

Discharge Pull-Down

V

= 3.6V, IN = 0V, CTRL = 3.6V, V

or

25

-

50

-

kΩ

DD

COM-

Resistance, R , R

= -0.85V, 0.85V, V or V = -0.85V,

L

R

COM+

L R

0.85V, V

and V = floating, Measure current

D-

D+

through the discharge pull-down resistor and

calculate resistance value.

USB Switches (D+, D-)

Analog Signal Range,

V

= 3.6V, IN = 1.4V, CTRL = 1.4V

Full

= 1mA, +25

0

-

V

Ω

DD

V

ANALOG

ON-Resistance, r

V

= 5.0V, IN = V , CTRL = V , I

or V = 5V (See Figure 4)

D-

17.7

19.5

26

-

ON

DD DD DD COMx

V

D+

V

= 4.2V, IN = V , CTRL = V , I

DD DD COMx

-

DD

V

or V = 4.2V (See Figure 4)

D+

D-

V

= 2.85V, IN = V , CTRL = V , I

DD COMx

-

DD

V

or V = 2.85V (See Figure 4)

D+

D-

V

= 3.3V, IN = 1.4V, CTRL = 1.4V, I

= 1mA, +25

Full

-

23.5

30

35

Ω

DD

COMx

V

or V = 3.3V (See Figure 4)

D+

D-

-

4.6

-

ON-Resistance, r

V

= 3.6V, IN = 1.4V, CTRL = 1.4V, I = 40mA,

COMx

25

Full

25

5

ON

DD

V

or V = 0V to 400mV (See Figure 4)

D+

D-

6.5

0.5

0.55

r

Matching Between

V

= 3.6V, IN = 1.4V, CTRL = 1.4V, I

= 40mA,

over signal range

0.06

-

ON

Channels, Δr

DD COMx

V

or V = Voltage at max R

ON

D+ D- ON

Full

of 0V to 400mV, (Note 14)

r

Flatness, R

FLAT(ON)

V

= 3.6V, IN = 1.4V, CTRL = 1.4V,

25

-

0.4

-

0.6

Ω

ON

DD

I

= 40mA, V

D+

or V = 0V to 400mV,

D-

COMx

(Note 13)

Full

1.0

OFF Leakage Current,

or I

V

= 3.6V, IN = 0V, CTRL = 3.6V, V

or

25

-10

-

10

nA

DD

COM-

I

= 0.5V, 0V, V

or V = 0V, 0.5V, V and

D+(OFF)

D-(OFF)

COM+

D+

D-

L

Full

-70

70

V = float

R

ON Leakage Current, I

Dx

V

= 3.3V, IN = 3.3V, CTRL = 0V or 3.3V, V

25

-30

8

-

30

nA

DD

or V = 2.0V, V

D+

,V

, V and V = float

D-

COM- COM+

L

R

Full

-300

300

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V

= 2.7V, R = 50Ω, C = 10pF, (See Figure 1) 25

-

67

48

18

-

ns

ON

DD

L

Turn-OFF Time, t

= 2.7V, R = 50Ω, C = 10pF, (See Figure 1) 25

L L

OFF

Break-Before-Make Time

= 2.7V, R = 50Ω, C = 10pF, (See Figure 2) 25

L

Delay, t

Skew, t

D

V

= 3.3V, IN = 3.3V, CTRL = 0V or 3.3V,

25

-

50

-

ps

SKEW

DD

L

R = 45Ω, C = 10pF, t = t = 750ps at

480Mbps, (Duty Cycle = 50%) (See Figure 7)

L

R

F

Total Jitter, t

V

= 3.3V, IN = 3.3V, CTRL = 0V or 3.3V,

25

-

210

250

-

ps

dB

J

DD

L

R = 45Ω, C = 10pF, t = t = 750ps at 480Mbps

L

R

F

Propagation Delay, t

V

= 3.3V, IN = 3.3V, CTRL = 0V or 3.3V,

DD

PD

R = 45Ω, C = 10pF, (See Figure 7)

L

Crosstalk

(Channel-to-Channel),

R to COM-, L to COM+

V

= 3.3V, IN = 0V, CTRL = 3.3V, R = 32Ω,

-110

DD

L

f = 20Hz to 20kHz, V or V = 0.707V

(2V ), (See Figure 6)

P-P

R L

RMS

Total Harmonic Distortion f = 20Hz to 20kHz, V

DD

= 3.0V, IN = 0V, CTRL = 3V,

25

-

0.06

630

6

-

%

MHz

pF

V or V = 0.707V

(2V ), R = 32Ω

L

R

RMS

P-P

L

USB Switch -3dB

Bandwidth

Signal = 0dBm, 0.2V offset, R = 50Ω,C = 5pF

DC L L

D+/D- OFF Capacitance,

f = 1MHz, V

DD

D- D+

= 3.3V, IN = 0V, CTRL = 3.3V,

= 0V, (See Figure 5)

C

, C

V

or V

= V

D+(OFF)

D-(OFF)

COMx

FN6515.2

September 30, 2010

5

ISL54206A

Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V

= +3.3V, GND = 0V, V

= 1.4V,

= 0.5V, (Note 11), unless

DD

INH

V

= 0.5V, V

= 1.4V, V

INL

CTRLH

CTRLL

otherwise specified. Boldface limits apply over the operating

temperature range, -40°C to +85°C. (Continued)

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

= 3.3V, IN = 0V, CTRL = 0V or

(°C) (Notes 12, 15) TYP (Notes 12, 15) UNITS

L/R OFF Capacitance,

f = 1MHz, V

DD

25

-

9

-

pF

C

, C

3.3V, V or V = V

= 0V, (See Figure 5)

LOFF ROFF

L

R

COMx

COM ON Capacitance,

, C

f = 1MHz, V

= 3.3V, IN = 3.0V, CTRL = 0V or

10

DD

C

3.3V, V or V

= V = 0V, (See Figure 5)

COMx

COM-(ON)

POWER SUPPLY CHARACTERISTICS

Power Supply Range, V

COM+(ON)

D-

D+

Full

25

2.5

-

6

-

5.5

8

V

DD

Positive Supply Current,

V

= 3.6V, IN = 0V or 3.6V, CTRL = 3.6V

-

µA

DD

I

DD

Full

25

10

-

Positive Supply Current,

V

= 4.2V, IN = 0V or 4.2V, CTRL = 4.2V

= 5.0V, IN = 0V or 5.0V, CTRL = 5.0V

= 3.6V, IN = 0V, CTRL = 0V or float

6

DD

I

DD

Positive Supply Current,

25

-

8

-

µA

I

DD

Positive Supply Current,

(Low Power State)

25

-

4

25

-

nA

I

DD

Full

150

DIGITAL INPUT CHARACTERISTICS

Voltage Low, V

, V

CTRLL

V

= 2.7V to 3.6V

Full

-

0.5

V

INL

DD

Voltage High, V

,

1.4

-

INH

V

CTRLH

Input Current, I

, I

V

= 3.6V, IN = 0V, CTRL = 0V

= 3.6V, IN = 3.6V, CTRL = 0V

= 3.6V, IN = 0V, CTRL = 3.6V

Full

-50

-2

20

1.1

4

50

2

nA

µA

MΩ

INL CTRLL DD

V

INH

DD

CTRLH

CTRL Pull-Down Resistor,

-

R

CTRL

NOTES:

11. V

= Input voltage to perform proper function.

LOGIC

12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data

sheet.

13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal

range.

14. R

ON

matching between channels is calculated by subtracting the channel with the highest max r value from the channel with

ON

lowest max R

value, between L and R or between D+ and D-.

ON

15. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established

by characterization and are not production tested.

FN6515.2

September 30, 2010

6

ISL54206A

Test Circuits and Waveforms

C

VDD

tr <20ns

tf <20ns

LOGIC

INPUT

50%

0V

CTRL

VINPUT

SWITCH

INPUT

VOUT

tOFF

AUDIO or USB

COMx

SWITCH

INPUT

VINPUT

0V

IN

VOUT

90%

CL

10pF

RL

50Ω

VIN

GND

SWITCH

OUTPUT

tON

Logic input waveform is inverted for switches that have the

opposite logic sense.

Repeat test for all switches. C includes fixture and stray

L

capacitance.

R

L

-----------------------

L

V

= V

OUT

(INPUT)

R

+ r

ON

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

VDD

C

VDD

0V

LOGIC

INPUT

CTRL

D- or D+

VOUT

VINPUT

COMx

L or R

VOUT

0V

CL

RL

90%

SWITCH

OUTPUT

50Ω

10pF

IN

tD

GND

VIN

Repeat test for all switches. C includes fixture and stray

L

capacitance.

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2B. TEST CIRCUIT

FIGURE 2. BREAK-BEFORE-MAKE TIME

VDD

C

R

= V1/100mA

R

= V1/40mA

ON

CTRL

L OR R

CTRL

D- OR D+

VD- OR D+

VL OR R

VDD

IN

0V

IN

V1

40mA

100mA

COMx

GND

Repeat test for all switches.

FIGURE 3. AUDIO R

Repeat test for all switches.

FIGURE 4. USB R

TEST CIRCUIT

ON

FN6515.2

September 30, 2010

7

ISL54206A

Test Circuits and Waveforms(Continued)

VDD

C

VDD

C

CTRL

L OR R

AUDIO OR USB

SIGNAL

GENERATOR

32Ω

COMx

IN

IMPEDANCE

ANALYZER

0V

0V or

VDD

COMx

GND

R OR L

COMx

ANALYZER

NC

GND

RL

Repeat test for all switches.

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

FIGURE 5. CAPACITANCE TEST CIRCUIT

FIGURE 6. AUDIO CROSSTALK TEST CIRCUIT

VDD

C

tri

90%

50%

10%

CTRL

DIN+

tskew_i

DIN-

VDD

15.8Ω

IN

90%

50%

OUT+

D+

D-

COM+

10%

DIN+

DIN-

45Ω

143Ω

15.8Ω

CL

tfi

tro

OUT-

COM-

90%

45Ω

143Ω

10%

90%

50%

tskew_o

50%

OUT+

OUT-

GND

|tro - tri| Delay Due to Switch for Rising Input and Rising Outpu

|tfo - tfi| Delay Due to Switch for Falling Input and Falling Outpu

|tskew_0| Change in Skew through the Switch for Output Signa

|tskew_i| Change in Skew through the Switch for Input Signals

10%

tf0

FIGURE 7A. MEASUREMENT POINTS

FIGURE 7B. TEST CIRCUIT

FIGURE 7. SKEW TEST

FN6515.2

September 30, 2010

8

ISL54206A

Application Block Diagrams

VDD

µCONTROLLER

ISL54206A

LOGIC

CTRL

VBUS

IN

USB

HIGH-SPEED

TRANSCEIVER

4MΩ

D-

COM-

D+

50kΩ

L

COM+

R

CODEC

GND

LOGIC CONTROL VIA MICRO-PROCESSOR

VDD

µCONTROLLER

ISL54206A

CTRL

IN

VBUS

22kΩ

LOGIC

4MΩ

USB

HIGH-SPEED

TRANSCEIVER

4MΩ

D-

COM-

D+

50kΩ

L

COM+

R

CODEC

GND

LOGIC CONTROL VIA VBUS VOLTAGE FROM COMPUTER OR USB HUB

The ISL54206A was specifically designed for MP3

players, cell phones and other personal media player

applications that need to combine the audio headphone

jack and the USB data connector into a single shared

connector, thereby saving space and component cost.

Typical application block diagrams of this functionality is

shown above.

Detailed Description

The ISL54206A device is a dual single pole/double throw

(SPDT) analog switch device that can operate from a

single DC power supply in the range of 2.5V to 5.5V. It

was designed to function as a dual 2 to 1 multiplexer to

select between USB differential data signals and audio L

and R stereo signals. It comes in tiny µTQFN and TDFN

packages for use in MP3 players, PDAs, cell phones, and

other personal media players.

The ISL54206A has a single logic control pin (IN) that

selects between the audio switches and the USB

switches. This pin can be driven Low or High to switch

between the audio CODEC drivers and USB transceiver of

the MP3 player or cellphone. The ISL54206A also

contains a logic control pin (CTRL) that when driven Low

while IN is Low, opens all switches and puts the part into

The part consists of two 3Ω audio switches and two 5Ω

USB switches. The audio switches can accept signals that

swing below ground. They were designed to pass audio

left and right stereo signals, that are ground referenced,

with minimal distortion. The USB switches were designed

to pass high-speed USB differential data signals with

minimal edge and phase distortion.

a low power state, drawing typically 1nA of I

current.

DD

A detailed description of the two types of switches is

provided in the following sections. The USB transmission

FN6515.2

September 30, 2010

9

ISL54206A

and audio playback are intended to be mutually exclusive

operations.

Note: Whenever the USB switches are ON, the audio

drivers of the CODEC need to be at AC or DC ground or

floating to keep from interfering with the data

transmission.

Audio Switches

The two audio switches (L, R) are 3Ω switches that can

pass signals that swing below ground by as much as

1.5V. They were designed to pass ground reference

stereo signals with minimal insertion loss and very low

distortion. Crosstalk between the audio switches over the

audio band is < -110dB.

USB Switch Cell Off-Isolation

Due to the unique internal architecture of the

ISL54206A part, the USB switch cell has limited off-

isolation to a negative signal at the COM side of the

part.

Over a signal range of ±1V (0.707V

>2.7V, these switches have an extremely low R

) with V

RMS

DD

ON

When driving an audio signal into the L and R inputs a

small negative voltage will appear at the D- and D+

lines as the audio signal transitions below ground. With

a USB transceiver connected at the D-/D+ pins and

with a 32W headphone connected at the COM pins

Table 1 shows the negative voltage generated at the

D-/D+ lines as you increase the audio amplitude

across the headphone load.

resistance variation. They can pass ground referenced

audio signals with very low distortion (<0.06% THD+N)

when delivering 15.6mW into a 32Ω headphone speaker

load. See Figures 8, Figures 9, Figures 10, and

Figures 11 THD+N performance curves.

These switches are uni-directional switches. The audio

drivers should be connected at the L and R side of the

switch (pin 7 and pin 8) and the speaker loads should be

connected at the COM side of the switch (pin 3 and

pin 4).

TABLE 1.

D-/D+ VOLTAGE (V)

AUDIO SIGNAL

AMPLITUDE

+25°C

-0.22

-0.24

-0.3

+85°C

-0.27

-0.3

The audio switches are active (turned ON) whenever the

IN voltage is ≤0.5V and the CTRL voltage to ≥1.4V.

800mV

880mV

P-P

Note: Whenever the audio switches are ON, the USB

transceivers need to be in the high impedance state or

static high or low state.

1.08V

2V

-0.34

-0.44

-0.5

-0.41

-0.47

-0.83

P-P

USB Switches

The two USB switches (D+, D-) are bidirectional switches

that can pass rail-to-rail signals. When powered with a

2.25V

4V

P-P

-0.85

P-P

3.6V supply, these switches have a nominal r

over the signal range of 0V to 400mV with a r

ON

of 4.6Ω

flatness

ON

The USB specification (USB Specification Rev 2.0,

Chapter 7, Section 7.1.1) states that a USB transceiver

must be able to tolerate a -1V signal at its D-/D+

differential inputs. The data in the table shows that the

-1V level is never exceeded during audio operation and

should have no impact on the long-term reliability of

the USB transceiver.

of 0.4Ω. The r

switches over this signal range is only 0.06Ω ensuring

matching between the D+ and D-

ON

minimal impact by the switches to USB high speed signal

transitions. As the signal level increases, the r

resistance increases. At signal level of 3.3V the switch

ON

resistance is nominally 23Ω.

The USB switches were specifically designed to pass USB

2.0 high-speed (480Mbps) differential signals typically in

the range of 0V to 400mV. They have low capacitance

and high bandwidth to pass the USB high-speed signals

with minimum edge and phase distortion to meet USB

2.0 high speed signal quality specifications. See

high-speed eye diagram Figure 15.

ISL54206A Operation

The following discussion discusses using the ISL54206A

in the typical application shown in the block diagrams

on page 9.

V

SUPPLY

DD

The DC power supply connected at VDD (pin 1) provides

the required bias voltage for proper switch operation.

The part can operate with a supply voltage in the range

of 2.5V to 5.5V.

The USB switches can also pass USB full-speed signals

(12Mbps) with minimal distortion and meet all the USB

requirements for USB 2.0 full-speed signaling. See the

full-speed eye diagrams, Figures 12 thru 14.

In a typical USB/Audio application for portable battery

The maximum signal range for the USB switches is from

powered devices, the V voltage will come from a

battery or an LDO and be in the range of 2.7V to 3.6V.

For best possible USB full-speed operation (12Mbps), it is

DD

-1.5V to V . The signal voltage at D- and D+ should not

DD

be allowed to exceed the V

DD

voltage rail or go below

ground by more than -1.5V.

recommended that the V

voltage be ≥2.5V in order to

get a USB data signal level above 2.5V.

DD

The USB switches are active (turned ON) whenever the

IN voltage is ≥1.4V.

FN6515.2

September 30, 2010

10

ISL54206A

LOGIC CONTROL

and will drive the IN pin low and put the part back into

the Audio or Low Power Mode.

The state of the ISL54206A device is determined by the

voltage at the IN pin (pin 2) and the CTRL pin (pin 10).

Refer to “Truth Table” on page 2. These logic pins are

Low Power Mode

If the IN pin = Logic “0” and CTRL pin = Logic “0,” the

part will be in the Low Power mode. In the Low Power

mode, the audio switches and the USB switches are OFF

(high impedance). In this state, the device draws

typically 1nA of current.

1.8V logic compatible when V

3.6V and can be controlled by a standard µprocessor.

is in the range of 2.7V to

DD

The CTRL pin is internally pulled low through a 4MΩ

resistor to ground and can be left floating or tri-stated by

the µprocessor. The CTRL control pin is only active when

IN is logic “0”.

USING THE COMPUTER V

THE “IN” PIN

VOLTAGE TO DRIVE

BUS

The IN pin does not have an internal pull-down resistor

and must not be allowed to float. It must be driven High

or Low.

External IN Pull-Down Resistor

Rather than using a microprocessor to control the IN

logic pin you can directly drive the IN pin using the V

voltage from the computer or USB hub. In order to do

this, you must connect an external resistor from the IN

pin to ground.

BUS

The voltage at the IN pin can exceed the V

as much as 2.55V. This allows the V

BUS

voltage by

voltage from a

DD

computer or USB hub (4.4V to 5.25V) to drive the IN pin

while the V voltage is in the range of 2.7V to 3.6V. An

DD

external pull-down resistor is required from the IN pin to

When a headphone or nothing is connected at the

common connector, the external pull-down will pull the

IN pin low putting the ISL54206A in the Audio mode or

Low Power mode depending on the condition of the CTRL

pin.

ground when directly driving the IN pin with the

computer VBUS voltage. See “USING THE COMPUTER

VBUS VOLTAGE TO DRIVE THE “IN” PIN” on page 11.

Logic Control Voltage Levels

When a USB cable is connected at the common

connector, the voltage at the IN pin will be driven to 5V

and the part will automatically go into the USB mode.

IN = Logic “0” (Low) when IN ≤0.5V

IN = Logic “1” (High) when IN ≥1.4V

CTRL = Logic “0” (Low) when ≤0.5V or floating.

CTRL = Logic “1” (High) when ≥1.4V

When the USB cable is disconnected from the common

connector, the voltage at the IN pin will be pulled low by

the pull-down resistor and return to the Audio Mode or

Low Power Mode depending on the condition of the CTRL

pin.

Audio Mode

If the IN pin = Logic “0” and CTRL pin = Logic “1,” the part

will be in the Audio mode. In Audio mode, the L (left) and R

(right) 3Ω audio switches are ON and the D- and D+ 5Ω

USB switches are OFF (high impedance).

Note: The voltage at the IN pin can exceed the V

DD

voltage by as much as 2.55V. This allows the V

BUS

voltage from a computer or USB hub (4.4V to 5.25V) to

When nothing is plugged into the common connector or a

headphone is plugged into the common connector, the

µprocessor will sense that there is no voltage at the

VBUS pin of the connector and will drive and hold the IN

control pin of the ISL54206A low. As long as the

CTRL = Logic “1,” the ISL54206A part will be in the audio

mode and the audio drivers of the media player can drive

the headphones and play music.

drive the IN pin while the V

2.7V to 3.6V.

voltage is in the range of

DD

External IN Series Resistor

The ISL54206A contains a clamp circuit between IN and

VDD. Whenever the IN voltage is greater than the V

DD

voltage by more than 2.55V, current will flow through

this clamp circuitry into the V

power supply bus.

DD

USB Mode

During normal USB operation, V

DD

is in the range of 2.7V

voltage from computer or USB

If the IN pin = Logic “1” and CTRL pin = Logic “0” or

Logic “1” the part will go into USB mode. In USB mode,

the D- and D+ 5Ω switches are ON and the L and R 3Ω

audio switches are OFF (high impedance).

to 3.6V and IN (V

BUS

hub) is in the range of 4.4V to 5.25V, the clamp circuit is

not active and no current will flow through the clamp into

the V

supply.

DD

When a USB cable from a computer or USB hub is

connected at the common connector, the µprocessor will

sense the presence of the 5V VBUS and drive the IN pin

voltage high. The ISL54206A part will go into the USB

mode. In USB mode, the computer or USB hub

transceiver and the MP3 player or cell phone USB

transceiver are connected and digital data will be able to

be transmitted back and forth.

In a USB application, the situation can exist where the

voltage from the computer could be applied at the

V

BUS

IN pin before the V

voltage is up to its normal

DD

operating voltage range and current will flow through the

clamp into the V power supply bus. This current could

DD

be quite high when V

is OFF or at 0V and could

DD

potentially damage other components connected in the

circuit. In the application circuit, a 22kΩ resistor has

been put in series with the IN pin to limit the current to a

safe level during this situation.

When the USB cable is disconnected, the µprocessor will

sense that the 5V VBUS voltage is no longer connected

FN6515.2

September 30, 2010

11

ISL54206A

It is recommended that a current limiting resistor in the

Note: No external resistor is required in applications

range of 10kΩ to 50kΩ be connected in series with the IN

pin. It will have minimal impact on the logic level at the

IN pin during normal USB operation and protect the

where the voltage at the IN pin will not exceed V

more than 2.55V.

by

DD

circuit during the time V

to its normal operating voltage.

is present before V is up

BUS

DD

Typical Performance Curves T = +25°C, Unless Otherwise Specified

A

0.4

0.3

0.2

0.1

0

0.11

0.10

0.09

0.08

0.07

0.06

0.05

0.04

R

V

= 32Ω

= 0.707V

R

V

= 32Ω

LOAD

= 3V

LOAD

DD

RMS

3V

P-P

V

= 2.6V

DD

2.5V

V

= 2.7V

P-P

DD

V

= 3.6V

20k

DD

2V

P-P

V

DD

= 3V

1V

P-P

20

200

FREQUENCY (Hz)

2k

20

200

FREQUENCY (Hz)

2k

20k

FIGURE 9. THD+N vs SIGNAL LEVELS vs FREQUENCY

FIGURE 8. THD+N vs SUPPLY VOLTAGE vs

FREQUENCY

0.5

R

= 32Ω

R

= 32Ω

LOAD

FREQ = 1kHz

= 3V

LOAD

FREQ = 1kHz

= 3V

V

DD

0.4

0.3

0.2

0.1

0

0.4

0.3

0.2

0.1

0

10

20

30

40

50

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

OUTPUT POWER (mW)

OUTPUT VOLTAGE (V

)

P-P

FIGURE 10. THD+N vs OUTPUT VOLTAGE

FIGURE 11. THD+N vs OUTPUT POWER

FN6515.2

September 30, 2010

12

ISL54206A

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

V

= 5.5V

DD

TIME SCALE (10ns/DIV)

FIGURE 12. EYE PATTERN: 12MBps WITH SWITCHES IN THE SIGNAL PATH

FN6515.2

September 30, 2010

13

ISL54206A

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

V

= 3.3V

DD

TIME SCALE (10ns/DIV)

FIGURE 13. EYE PATTERN: 12MBps WITH SWITCHES IN THE SIGNAL PATH

FN6515.2

September 30, 2010

14

ISL54206A

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

V

= 2.5V

DD

TIME SCALE (10ns/DIV)

FIGURE 14. EYE PATTERN: 12MBps WITH SWITCHES IN THE SIGNAL PATH

FN6515.2

September 30, 2010

15

ISL54206A

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

V

= 3.3V

DD

TIME SCALE (0.2ns/DIV.)

FIGURE 15. EYE PATTERN: 480MBps USB SIGNAL WITH SWITCHES IN THE SIGNAL PATH

1

0

Die Characteristics

USB SWITCH

SUBSTRATE AND TDFN THERMAL PAD

POTENTIAL (POWERED UP):

-1

-2

-3

-4

GND

TRANSISTOR COUNT:

98

PROCESS:

Submicron CMOS

R

V

= 50Ω

L

= 0.2V

to 2V

P-P

IN

P-P

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 16. FREQUENCY RESPONSE

FN6515.2

September 30, 2010

16

ISL54206A

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to

web to make sure you have the latest Rev.

DATE

REVISION

CHANGE

09/24/2010 FN6515.2 Added section titled “USB Switch Cell Off-Isolation” to page 10.

06/15/2010 FN6515.1 On page 1:

Added "The L and R 50kΩ resistors to ground are not shown." to “Application Block Diagram”. Removed

(2) 50kΩ resistors, which were tied to L and R next to "CODEC" block

Updated Pb-free bullet in “Features”

On page 2:

Added PD to “Pin Descriptions” table

Updated Pb-free notes in “Ordering Information” per new verbiage based on lead finish. Added TB347

link to ordering information for reel specifications.

On page 4:

Added Latch up to Abs Max Ratings

Added Theta JC to “Thermal Information”. Changed 10 Ld µTQFN Theta JA from 130 to 145. Changed

10 Ld TDFN Theta JA from 110 to 55. Added applicable Theta JC notes.

Added standard over temp note to common conditions of spec table (Boldface limits apply..)

On page 5:

Changed “ON Leakage Current, I ” room temp and full temp limits from:

Dx

Room temp MIN/TYP/MAX: from -10/2/10nA to -30/8/30nA

Full temp MIN/MAX: from -75/75nA to -300/300nA

On page 6:

Changed “Positive Supply Current, IDD (Low Power State)” room temp and full temp limits from:

Room temp TYP/MAX: from 1/7nA to 4/25nA

Full temp: removed MAX of 140nA. Added TYP of 150nA

On page 4 to page 6:

Updated standard over-temp Note 15 in MIN/MAX columns of the Electrical Specifications table.

On page 18:

Updated POD L10.2.1X1.6A to most recent revision. Changes were:

Convert to new format by moving dimensions from table onto drawing

Corrected leadframe thickness in Detail x from 0.2 REF to 0.125 REF

Corrected Note 4 to read "...between 0.15mm and 0.30mm...", it previously read "...between .015mm

and 0.30mm..."

Corrected the word "indentifier" in Note 8 to read "identifier".

On page 19:

Updated POD L10.3x3A to most recent revision. Changes were to add Typical Recommended Land

Pattern & convert to new format by moving dimensions from table onto drawing (no dimension

changes)

06/25/2007 FN6515.0 Initial Release.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The

Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,

handheld products, and notebooks. Intersil's product families address power management and analog signal

processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device

information page on intersil.com: ISL54206A

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications

at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6515.2

September 30, 2010

17

ISL54206A

Package Outline Drawing

L10.2.1x1.6A

10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 5, 3/10

8.

PIN 1

INDEX AREA

2.10

A

PIN #1 ID

8.

0.05 MIN.

B

1

4

1

4X 0.20 MIN.

0.10 MIN.

10

5

0.80

10X 0.40

10 X 0.20

0.10

6

9

2X

6X 0.50

4

TOP VIEW

(10 X 0.20)

0.10 M C A B

M C

BOTTOM VIEW

SEE DETAIL "X"

(0.05 MIN)

(0.10 MIN.)

MAX. 0.55

PACKAGE

OUTLINE

1

0.10 C

C

(10X 0.60)

SEATING PLANE

0.08 C

(2.00)

SIDE VIEW

0 . 125 REF

(0.80)

(1.30)

C

(6X 0.50 )

(2.50)

0-0.05

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

2. All Dimensions are in millimeters. Angles are in degrees.

Dimensions in ( ) for Reference Only.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Lead width dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Maximum package warpage is 0.05mm.

6. Maximum allowable burrs is 0.076mm in all directions.

7. Same as JEDEC MO-255UABD except:

No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm

Lead Length dim. = 0.45mm max. not 0.42mm.

8. The configuration of the pin #1 identifier is optional, but must be located within

the zone indicated. The pin #1 identifier may be either a mold or mark feature.

FN6515.2

September 30, 2010

18

ISL54206A

Package Outline Drawing

L10.3x3A

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 5, 3/10

2.0 REF

8X 0.50 BSC

6

3.00

A

PIN 1

INDEX AREA

B

1

5

6

10X 0 . 30

PIN 1

INDEX AREA

3.00

1.50

0.15

(4X)

C

A B

0.10

0.05

M

10

5

10 X 0.25

4

TOP VIEW

( 2.30 )

2.30

BOTTOM VIEW

0 .80 MAX

SEE DETAIL "X"

0.10 C

C

(2.90)

SEATING PLANE

0.08 C

(1.50)

SIDE VIEW

(10 X 0.50)

5

0 . 2 REF

C

( 8X 0 .50 )

( 10X 0.25 )

0 . 00 MIN.

0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

Angular ±2.50°

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm).

7.

FN6515.2

September 30, 2010

19


型号：	ISL54206AEVAL1Z
厂家：	Intersil
描述：	MP3/USB 2.0 High Speed Switch with Negative Signal Handling MP3 / USB 2.0高速开关，可处理负信号处理开关
文件：	总19页 (文件大小：1564K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL54206AEVAL1Z [INTERSIL]

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