ISL5861/2IA [INTERSIL]
12-bit, +3.3V, 130/210+MSPS, High Speed D/A Converter; 12位， + 3.3V ，二百一分之一百三十○ + MSPS ，高速D / A转换器
| 型号： | ISL5861/2IA |
| 厂家： | 
Intersil |
| 描述： | 12-bit, +3.3V, 130/210+MSPS, High Speed D/A Converter |
| 文件： | 总13页 (文件大小：687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL5861
®
Data Sheet
August 2004
FN6008.2
12-bit, +3.3V, 130/210+MSPS, High Speed
D/A Converter
Features
• Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS
• Low Power . . . . . 103mW with 20mA Output at 130MSPS
• Adjustable Full Scale Output Current. . . . . 2mA to 20mA
• +3.3V Power Supply
The ISL5861 is a 12-bit, 130/210+MSPS (Mega Samples
Per Second), CMOS, high speed, low power, D/A (digital to
analog) converter, designed specifically for use in high
performance communication systems such as base
transceiver stations utilizing 2.5G or 3G cellular protocols.
• 3V LVCMOS Compatible Inputs
This device complements the ISL5x61 family of high speed
converters, which include 10, 12, and 14-bit devices.
• Excellent Spurious Free Dynamic Range
(73dBc to Nyquist, f = 130MSPS, f
= 10MHz)
S
OUT
Ordering Information
• UMTS Adjacent Channel Power =70dB at 19.2MHz
• EDGE/GSM SFDR = 90dBc at 11MHz in 20MHz Window
TEMP.
PART
NUMBER
RANGE
( C)
PKG.
DWG. # SPEED
CLOCK
o
• Pin compatible, 3.3V, Lower Power Replacement For The
AD9752 and HI5860
PACKAGE
ISL5861IB
-40 to 85 28 Ld SOIC
M28.3
M28.3
130MHz
130MHz
• Pb-free available
ISL5861IBZ
(See Note)
-40 to 85 28 Ld SOIC
(Pb-free)
Applications
ISL5861IA
-40 to 85 28 Ld TSSOP M28.173 130MHz
• Cellular Infrastructure - Single or Multi-Carrier: IS-136,
IS-95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
ISL5861IAZ
(See Note)
-40 to 85 28 Ld TSSOP M28.173 130MHz
(Pb-free)
• BWA Infrastructure
ISL5861/2IB
-40 to 85 28 Ld SOIC
M28.3
M28.3
210MHz
210MHz
• Medical/Test Instrumentation
• Wireless Communication Systems
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
ISL5861/2IBZ
(See Note)
-40 to 85 28 Ld SOIC
(Pb-free)
ISL5861/2IA
-40 to 85 28 Ld TSSOP M28.173 210MHz
ISL5861/2IAZ
(See Note)
-40 to 85 28 Ld TSSOP M28.173 210MHz
(Pb-free)
ISL5861EVAL1
25
SOIC Evaluation Platform 210MHz
Pinout
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
ISL5861
TOP VIEW
1
2
CLK
28
D11 (MSB)
D10
D9
27 DV
DD
3
26 DCOM
25 NC
D8
4
5
24 AV
DD
D7
6
23 COMP
22 IOUTA
21 IOUTB
D6
D5
7
D4
8
D3
9
20
ACOM
10
11
12
13
19 NC
D2
18 FSADJ
17 REFIO
16 REFLO
15 SLEEP
D1
D0 (LSB)
DCOM
DCOM 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2004, All Rights Reserved
1
ISL5861
Typical Applications Circuit
ISL5861
ONE CONNECTION
DCOM ACOM
(25, 19) NC
(15) SLEEP
(16) REFLO
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11 (MSB) (1)
D10 (2)
D9 (3)
(17) REFIO
0.1µF
D8 (4)
D7 (5)
(18) FSADJ
D6 (6)
1.91kΩ
R
SET
1:1, Z1:Z2
D5 (7)
(22) IOUTA
(21) IOUTB
D4 (8)
(50Ω)
50Ω
D3 (9)
REPRESENTS
ANY 50Ω LOAD
D2 (10)
D1 (11)
D0 (LSB) (12)
(23) COMP
(20) ACOM
CLK (28)
DCOM (26, 13, 14)
0.1µF
50Ω
FERRITE
BEAD
BEAD
(24) AV
DD
DV
DD
(27)
+
+
10µH
10µH
+3.3V (V
DD
)
10µF
0.1µF
0.1µF
10µF
Functional Block Diagram
IOUTA IOUTB
CASCODE
(LSB) D0
D1
CURRENT
SOURCE
INPUT
LATCH
D2
D3
D4
7 LSBs
31 MSB
SWITCH
MATRIX
38
38
+
D5
SEGMENTS
D6
D7
D8
UPPER
5-BIT
D9
D10
D11
DECODER
COMP
CLK
INT/EXT
VOLTAGE
BIAS
GENERATION
REFERENCE
REFLO REFIO
FSADJ SLEEP
2
ISL5861
Pin Descriptions
PIN NO.
PIN NAME
DESCRIPTION
1-12
D11 (MSB) Through Digital Data Bit 11, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
D0 (LSB)
15
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin
has internal 20µA active pulldown current.
16
17
REFLO
REFIO
Connect to analog ground to enable internal 1.2V reference or connect to AV to disable internal reference.
DD
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
18
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current
= 32 x V .
/R
FSADJ SET
19, 25
21
NC
No Connect. These should be grounded, but can be left disconnected.
IOUTB
The complementary current output of the device. Full scale output current is achieved when all input bits are
set to binary 0.
22
IOUTA
COMP
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
Connect 0.1µF capacitor to ACOM.
Analog Supply (+3.0V to +3.6V).
Connect to Analog Ground.
Connect to Digital Ground.
Digital Supply (+3.0V to +3.6V).
Clock Input.
24
20
AV
DD
ACOM
DCOM
26, 13, 14
27
DV
DD
28
CLK
3
ISL5861
Absolute Maximum Ratings
Thermal Information
o
Digital Supply Voltage DV
to DCOM . . . . . . . . . . . . . . . . . . +3.6V
to ACOM. . . . . . . . . . . . . . . . . . +3.6V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
DD
Analog Supply Voltage AV
JA
DD
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
110
Grounds, ACOM TO DCOM. . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DV
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV
o
+ 0.3V
+ 0.3V
DD
DD
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
o
Analog Output Current (I
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
OUT
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications AV = DV = +3.3V, V
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values
A
DD
DD
REF
o
o
T
= -40 C TO 85 C
A
PARAMETER
SYSTEM PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12
-1.25
-1
-
-
Bits
LSB
LSB
Integral Linearity Error, INL
Differential Linearity Error, DNL
“Best Fit” Straight Line (Note 7)
(Note 7)
±0.5
±0.5
+1.25
+1
Offset Error, I
IOUTA (Note 7)
(Note 7)
-0.006
-
+0.006 % FSR
OS
Offset Drift Coefficient
0.1
-
ppm
o
FSR/ C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
With External Reference (Note 7)
-3
-3
-
±0.5
±0.5
±50
+3
+3
-
% FSR
% FSR
ppm
Full Scale Gain Drift
o
FSR/ C
With Internal Reference (Note 7)
(Note 3)
-
±100
-
ppm
FSR/ C
o
Full Scale Output Current, I
2
-
-
20
mA
V
FS
Output Voltage Compliance Range
-1.0
1.25
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
Maximum Clock Rate, f
Output Rise Time
Output Fall Time
ISL5861/2IA, ISL5861/2IB
ISL5861IA, ISL5861IB
Full Scale Step
210
250
150
1.5
1.5
10
-
-
-
-
-
-
-
MHz
MHz
ns
CLK
130
CLK
-
-
-
-
-
Full Scale Step
ns
Output Capacitance
Output Noise
pF
IOUTFS = 20mA
IOUTFS = 2mA
50
pA/√Hz
pA/√Hz
30
AC CHARACTERISTICS (Using Figure 13 with R
DIFF
= 50Ω and R
= 50Ω, Full Scale Output = -2.5dBm)
LOAD
Spurious Free Dynamic Range,
SFDR Within a Window
f
= 210MSPS, f
= 210MSPS, f
= 130MSPS, f
= 80.8MHz, 30MHz Span (Notes 4, 7)
-
-
-
73
80
85
-
-
-
dBc
dBc
dBc
CLK
OUT
OUT
OUT
f
= 40.4MHz, 30MHz Span (Notes 4, 7)
= 20.2MHz, 20MHz Span (Notes 4, 7)
CLK
f
CLK
4
ISL5861
o
Electrical Specifications AV = DV = +3.3V, V
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values (Continued)
A
DD
DD
REF
o
o
T
= -40 C TO 85 C
A
PARAMETER
TEST CONDITIONS
MIN
TYP
51
60
62
-
MAX
UNITS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Spurious Free Dynamic Range,
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 210MSPS, f
= 210MSPS, f
= 200MSPS, f
= 200MSPS, f
= 130MSPS, f
= 130MSPS, f
= 130MSPS, f
= 130MSPS, f
= 130MSPS, f
= 130MSPS, f
= 100MSPS, f
= 80.8MHz (Notes 4, 7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SFDR to Nyquist (f
/2)
CLK
= 40.4MHz (Notes 4, 7, 9)
o
= 20.2MHz, T = 25 C (Notes 4, 7)
60
58
-
o
o
= 20.2MHz, T = -40 C to 85 C (Notes 4, 7)
= 50.5MHz (Notes 4, 7)
57
62
69
73
77
-
= 40.4MHz (Notes 4, 7)
-
= 20.2MHz (Notes 4, 7)
-
= 10.1MHz (Notes 4, 7)
-
o
= 5.05MHz, T = 25 C (Notes 4, 7)
70
68
-
o
o
= 5.05MHz, T = -40 C to 85 C (Notes 4, 7)
= 40.4MHz (Notes 4, 7)
60
63
69
70
76
68
73
77
65
= 80MSPS, f
= 80MSPS, f
= 80MSPS, f
= 80MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 30.3MHz (Notes 4, 7)
= 20.2MHz (Notes 4, 7)
= 10.1MHz (Notes 4, 7, 9)
= 5.05MHz (Notes 4, 7)
= 20.2MHz (Notes 4, 7)
= 10.1MHz (Notes 4, 7)
= 5.05MHz (Notes 4, 7)
-
OUT
OUT
OUT
OUT
OUT
OUT
OUT
-
-
-
-
-
-
Spurious Free Dynamic Range,
= 210MSPS, f
OUT
= 28.3MHz to 45.2MHz, 2.1MHz Spacing,
-
SFDR in a Window with Eight Tones
50MHz Span (Notes 4, 7, 9)
f
= 130MSPS, f =17.5MHz to 27.9MHz, 1.3MHz Spacing,
-
-
-
-
-
68
75
77
90
70
-
-
-
-
-
dBc
dBc
dBc
dBc
dB
CLK
OUT
35MHz Span (Notes 4, 7)
f
= 80MSPS, f
= 10.8MHz to 17.2MHz, 811kHz Spacing,
CLK
OUT
15MHz Span (Notes 4, 7)
f
= 50MSPS, f
= 6.7MHz to 10.8MHz, 490kHz Spacing,
CLK
OUT
10MHz Span (Notes 4, 7)
Spurious Free Dynamic Range,
f
= 78MSPS, f = 11MHz, in a 20MHz Window, RBW=30kHz
CLK
OUT
SFDR in a Window with EDGE or GSM (Notes 4, 7, 9)
Adjacent Channel Power Ratio,
ACPR with UMTS
f
= 76.8MSPS, f = 19.2MHz, RBW=30kHz (Notes 4, 7, 9)
OUT
CLK
VOLTAGE REFERENCE
Internal Reference Voltage, V
Pin 18 Voltage with Internal Reference
1.2
1.23
±40
0
1.3
V
FSADJ
o
Internal Reference Voltage Drift
-
-
-
-
ppm/ C
Internal Reference Output Current
Sink/Source Capability
Reference is not intended to be externally loaded
µA
Reference Input Impedance
-
-
1
-
-
MΩ
Reference Input Multiplying Bandwidth (Note 7)
1.0
MHz
DIGITAL INPUTS D11-D0, CLK
Input Logic High Voltage with
3.3V Supply, V
(Note 3)
(Note 3)
2.3
-
3.3
0
-
V
V
IH
Input Logic Low Voltage with
3.3V Supply, V
1.0
+25
IL
Sleep Input Current, I
-25
-
µA
IH
5
ISL5861
o
Electrical Specifications AV = DV = +3.3V, V
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values (Continued)
A
DD
DD
REF
o
o
T
= -40 C TO 85 C
A
PARAMETER
TEST CONDITIONS
MIN
-20
-10
-
TYP
MAX
+20
+10
-
UNITS
µA
Input Logic Current, I
-
-
IH, IL
IH, IL
Clock Input Current, I
µA
Digital Input Capacitance, C
5
pF
IN
TIMING CHARACTERISTICS
Data Setup Time, t
See Figure 15
See Figure 15
See Figure 15
-
-
-
1.5
1.5
1
-
-
-
ns
ns
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
Clock
Period
CLK Pulse Width, t
, t
See Figure 15 (Note 3)
2
-
-
ns
PW1 PW2
POWER SUPPLY CHARACTERISTICS
AV
DV
Power Supply
Power Supply
(Note 8)
2.7
3.3
3.3
27.5
10
3.6
3.6
28.5
-
V
DD
(Note 8)
2.7
V
DD
Analog Supply Current (I
AVDD
)
3.3V, IOUTFS = 20mA
3.3V, IOUTFS = 2mA
3.3V (Note 5)
3.3V (Note 6)
-
mA
mA
mA
mA
mA
mW
mW
mW
-
Digital Supply Current (I
)
-
3.7
6.5
1.5
103
110
45
5
DVDD
-
8
Supply Current (I
) Sleep Mode
3.3V, IOUTFS = Don’t Care
3.3V, IOUTFS = 20mA (Note 5)
3.3V, IOUTFS = 20mA (Note 6)
3.3V, IOUTFS = 2mA (Note 5)
Single Supply (Note 7)
-
-
AVDD
Power Dissipation
-
111
120
-
-
-
Power Supply Rejection
NOTES:
-0.125
-
+0.125 %FSR/V
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
ratio should be 32.
(typically 625µA). Ideally the
SET
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was
used at different clock rates, producing different output frequencies but at the same ratio to the clock rate.
5. Measured with the clock at 130MSPS and the output frequency at 5MHz.
6. Measured with the clock at 200MSPS and the output frequency at 20MHz.
7. See “Definition of Specifications”.
8. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in
analog output current may be necessary to maintain spectral performance.
9. See Typical Performance Plots.
6
ISL5861
Typical Performance (+3.3V Supply, Using Figure 13 with R
= 100Ω and R
= 50Ω)
LOAD
DIFF
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
FIGURE 1. EDGE AT 11MHz, 78MSPS CLOCK
FIGURE 2. EDGE AT 11MHz, 78MSPS CLOCK
(75dBc -NYQUIST, 6dB PAD)
(91+dBc @ ∆f = +6MHz)
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
FIGURE 3. GSM AT 11MHz, 78MSPS CLOCK
FIGURE 4. GSM AT 11MHz, 78MSPS CLOCK
(75dBc - NYQUIST, 9dB PAD)
(90+dBc @ ∆f = +6MHz, 3dB PAD)
FIGURE 5. FOUR EDGE CARRIERS AT 12.4-15.6MHz, 800kHz
SPACING, 78MSPS (71dBc - 20MHz WINDOW)
FIGURE 6. FOUR GSM CARRIERS AT 12.4-15.6MHz, 78MSPS
(73dBc - 20MHz WINDOW, 6dB PAD)
7
ISL5861
Typical Performance (+3.3V Supply, Using Figure 13 with R
= 100Ω and R
= 50Ω) (Continued)
LOAD
DIFF
SPECTRAL MASK
UMTS TDD
P>43dBm BTS
FIGURE 7. UMTS AT 19.2MHz, 76.8MSPS (70dB 1stACPR,
70dB 2ndACPR)
FIGURE 8. ONE TONE AT 10.1MHz, 80MSPS CLOCK (71dBc -
NYQUIST, 6dB PAD)
FIGURE 9. ONE TONE AT 40.4MHz, 210MSPS CLOCK
(61dBc - NYQUIST, 6dB PAD)
FIGURE 10. EIGHT TONES (CREST FACTOR=8.9) AT 37MHz,
210MSPS CLOCK, 2.1MHz SPACING
(65dBc - NYQUIST)
FIGURE 11. TWO TONES (CkHzF=6) AT 8.5MHz, 50MSPS
CLOCK, 500kHz SPACING (82dBc - 10MHz
WINDOW, 6dB PAD)
FIGURE 12. FOUR TONES (CF=8.1) AT 14MHz, 80MSPS
CLOCK, 800kHz SPACING (70dBc - NYQUIST,
6dB PAD)
8
ISL5861
Reference Input Multiplying Bandwidth, is defined as the
Definition of Specifications
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is 0.707
(-3dB) of its original value.
Adjacent Channel Power Ratio, ACPR, is the ratio of the
average power in the adjacent frequency channel (or offset)
to the average power in the transmitted frequency channel.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency window.
EDGE, Enhanced Data for Global Evolution, a TDMA
standard for cellular applications which uses 200kHz BW, 8-
PSK modulated carriers.
Total Harmonic Distortion, THD, is the ratio of the RMS
value of the fundamental output signal to the RMS sum of
the first five harmonic components.
Full Scale Gain Drift, is measured by setting the data inputs
to be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied
UMTS, Universal Mobile Telecommunications System, a
W-CDMA standard for cellular applications which uses
3.84MHz modulated carriers.
from T
to T . It is defined as the maximum deviation
MIN
MAX
from the value measured at room temperature to the value
measured at either T or T . The units are ppm of FSR
(full scale range) per C.
MIN
MAX
Detailed Description
o
The ISL5861 is a 12-bit, current out, CMOS, digital to analog
converter. The maximum update rate is at least 210+MSPS
and can be powered by a single power supply in the
recommended range of +3.0V to +3.6V. Operation with clock
rates higher than 210MSPS is possible; please contact the
factory for more information. It consumes less than 120mW
of power when using a +3.3V supply, the maximum 20mA of
output current, and the data switching at 210MSPS. The
architecture is based on a segmented current source
arrangement that reduces glitch by reducing the amount of
current switching at any one time. In previous architectures
that contained all binary weighted current sources or a
binary weighted resistor ladder, the converter might have a
substantially larger amount of current turning on and off at
certain, worst-case transition points such as midscale and
quarter scale transitions. By greatly reducing the amount of
current switching at these major transitions, the overall glitch
of the converter is dramatically reduced, improving settling
time, transient problems, and accuracy.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through R
SET
).
GSM, Global System for Mobile Communication, a TDMA
standard for cellular applications which uses 200kHz BW,
GMSK modulated carriers.
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either T
The units are ppm per C.
or T
.
MAX
MIN
o
Offset Drift, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage at IOUTA
through a known resistance as the temperature is varied
from T
to T . It is defined as the maximum deviation
MIN
MAX
Digital Inputs and Termination
from the value measured at room temperature to the value
measured at either T or T . The units are ppm of FSR
(full scale range) per degree C.
The ISL5861 digital inputs are guaranteed to 3V LVCMOS
levels. The internal register is updated on the rising edge of
the clock. To minimize reflections, proper termination should
be implemented. If the lines driving the clock and the digital
inputs are long 50Ω lines, then 50Ω termination resistors
should be placed as close to the converter inputs as possible
connected to the digital ground plane (if separate grounds
are used). These termination resistors are not likely needed
as long as the digital waveform source is within a few inches
of the DAC. For pattern drivers with very high speed edge
rates, it is recommended that the user consider series
termination (50-200Ω) prior to the DAC’s inputs in order to
reduce the amount of noise.
MIN
MAX
o
Offset Error, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage of IOUTA
through a known resistance. Offset error is defined as the
maximum deviation of the IOUTA output current from a value
of 0mA.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed does not violate the
compliance range.
Power Supply Rejection, is measured using a single power
supply. The nominal supply voltage is varied ±10% and the
change in the DAC full scale output is noted.
9
ISL5861
Power Supply
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH
INTERNAL REFERENCE AND RSET=1.91KΩ
Separate digital and analog power supplies are
recommended. The allowable supply range is +2.7V to
+3.6V. The recommended supply range is +3.0 to 3.6V
(nominally +3.3V) to maintain optimum SFDR. However,
operation down to +2.7V is possible with some degradation
in SFDR. Reducing the analog output current can help the
SFDR at +2.7V. The SFDR values stated in the table of
specifications were obtained with a +3.3V supply.
INPUT CODE (D11-D0)
11 11111 11111
IOUTA (mA)
IOUTB (mA)
20
10
0
0
10 00000 00000
10
20
00 00000 00000
Analog Output
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
Ground Planes
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane.
compliance range of -1.0V to 1.25V. R
(the impedance
OUT
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equation is:
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AV
and DV . Also, the layout should be designed
DD
DD
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
V
= I
OUT
X R .
OUT
OUT
DV
and to the analog ground for AV . Additional filtering
DD
DD
The most effective method for reducing the power
consumption is to reduce the analog output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.23V with a ±40ppm/ C drift coefficient over the
o
Differential Output
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(16) selects the reference. The internal reference can be
selected if pin 16 is tied low (ground). If an external reference
is desired, then pin 16 should be tied high (the analog supply
voltage) and the external reference driven into REFIO, pin
17. The full scale output current of the converter is a function
IOUTA and IOUTB can be used in a differential-to-single-
ended arrangement to achieve better harmonic rejection.
With R
= 50Ω and R =50Ω, the circuit in Figure 13
DIFF
LOAD
will provide a 500mV (-2.5dBm) signal at the output of the
transformer if the full scale output current of the DAC is set to
20mA (used for the electrical specifications table). Values of
R
= 100Ω and R =50Ω were used for the typical
DIFF
LOAD
performance curves. The center tap in Figure 13 must be
grounded.
of the voltage reference used and the value of R
. I
SET OUT
should be within the 2mA to 20mA range, though operation
below 2mA is possible, with performance degradation.
In the circuit in Figure 14, the user is left with the option to
ground or float the center tap. The DC voltage that will exist
at either IOUTA or IOUTB if the center tap is floating is
If the internal reference is used, V
will equal
FSADJ
approximately 1.2V (pin 18). If an external reference is used,
will equal the external reference. The calculation for
IOUT
x (R //R ) V because R is DC shorted by the
DC
A
B
DIFF
V
FSADJ
transformer. If the center tap is grounded, the DC voltage is
0V. Recommended values for the circuit in Figure 14 are
I
(Full Scale) is:
OUT
I
(Full Scale) = (V
/R X 32.
R =R =50Ω, R
DIFF
=100Ω, assuming R =50Ω. The
LOAD
OUT
FSADJ SET)
A
B
performance of Figure 13 and Figure 14 is basically the
same, however leaving the center tap of Figure 14 floating
allows the circuit to find a more balanced virtual ground,
theoretically improving the even order harmonic rejection,
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91kΩ R
resistor, then the input coding to output current will resemble
SET
the following:
10
ISL5861
Propagation Delay
R
= 0.5 x (R
// R
)
DIFF
EQ
LOAD
AT EACH OUTPUT
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
V
= (2 x IOUTA x R )V
EQ
OUT
1:1
IOUTB
PIN 21
PIN 22
R
R
DIFF
LOAD
IOUTA
ISL5861
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form. The form can be found by doing an ‘entire
site search’ at www.intersil.com on the words ‘DAC
R
REPRESENTS THE
LOAD
LOAD SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
Testdrive’. Or, send a request to the technical support center.
R
= 0.5 x (R
// R
// R ), WHERE R =R
EQ
LOAD
DIFF
A
A
B
AT EACH OUTPUT
R
A
V
= (2 x IOUTA x R )V
EQ
OUT
IOUTB
IOUTA
PIN 21
R
R
DIFF
LOAD
PIN 22
ISL5861
R
B
R
REPRESENTS THE
LOAD
LOAD SEEN BY THE TRANSFORMER
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Timing Diagram
t
t
PW2
PW1
50%
CLK
t
t
t
SU
SU
SU
W
t
t
t
HLD
HLD
HLD
D11-D0
W
W
W
0
3
1
2
t
t
PD
OUTPUT=W
PD
0
I
OUT
OUTPUT=W
OUTPUT=W
1
-1
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
11
ISL5861
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
0.7125 17.70
3
-A-
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
µ
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
12
ISL5861
Thin Shrink Small Outline Plastic Packages (TSSOP)
M28.173
N
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
-
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.386
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
9.80
4.50
NOTES
A
A1
A2
b
-
1
2
3
0.002
0.031
0.0075
0.0035
0.378
0.169
0.05
0.80
0.19
0.09
9.60
4.30
-
L
-
0.25
0.05(0.002)
SEATING PLANE
A
0.010
A2
9
-A-
D
c
-
D
3
-C-
E1
e
4
α
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
28
28
7
o
o
o
o
NOTES:
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
Rev. 0 6/98
JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
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