ISL59117 [INTERSIL]
Triple Channel Video Driver with LPF; 三通道视频驱动器与低通滤波器
| 型号： | ISL59117 |
| 厂家： | 
Intersil |
| 描述： | Triple Channel Video Driver with LPF |
| 文件： | 总10页 (文件大小：366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL59117
®
Data Sheet
September 21, 2006
FN6278.0
Triple Channel Video Driver with LPF
Features
The ISL59117 is a triple channel reconstruction filter with a
-3dB roll-off frequency of 9MHz. Operating from single
supplies ranging from +2.5V to +3.6V and drawing only
3.9mA quiescent current, the ISL59117 is ideally suited for
low power, battery-operated applications. Additionally,
enable pins shut the part down in under 14ns.
• 3rd order 9MHz reconstruction filter
• 40V/µs slew rate
• Low supply current = 3.9mA
• Power-down current less than 1µA
• Supplies from 2.5V to 3.6V
• Rail-to-rail output
The ISL59117 is designed to meet the needs for very low
power and bandwidth required in battery-operated
communication, instrumentation, and modern industrial
applications such as video on demand, cable set-top boxes,
MP3 players, and HDTV. The ISL59117 is offered in a
space-saving chipscale package guaranteed to a 0.57mm
maximum height constraint and specified for operation from
-40°C to +85°C temperature range.
• CSP package
• Pb-free plus anneal available (RoHS compliant)
Applications
• Video amplifiers
• Portable and handheld products
• Communications devices
• Video on demand
• Cable set-top boxes
• Satellite set-top boxes
• MP3 players
Pinout
ISL59117 (WLCSP)
TOP VIEW
1
2
3
A
B
C
• HDTV
• Personal video recorder
C
GND
EN
C
OUT
IN
Block Diagram
CVBS
IN
CVBS
OUT
+
-
65mV
-
Y
C
9MHz
9MHz
9MHz
+
x2
x2
x2
Y
OUT
IN
IN
IN
5µA
Y
V
Y
OUT
IN
DD
500mV
65mV
-
+
C
OUT
+
-
65mV
-
+
CVBS
CVBS
OUT
5µA
BIASING &
CONTROL
EN
Ordering Information
PART NUMBER (Note)
PART MARKING
TAPE AND REEL
TEMP. RANGE (°C)
PACKAGE (Pb-Free)
PKG. DWG. #
W3x3.9A
ISL59117IIZ-T7
117Z
7”
-40 to +85
WLCSP
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59117
Absolute Maximum Ratings (T = +25°C)
A
Supply Voltage from V
DD
Input Voltage . . . . . . . . . . . . . . . . . . . . . . .V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C
to GND . . . . . . . . . . . . . . . . . . . . . . . 4.2V
+0.3V to GND -0.3V
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
DD
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
V
= 3.3V, T = +25°C, R = 150Ω to GND, unless otherwise specified.
A L
DD
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Supply Voltage Range
2.5
3.6
6.5
0.5
10
V
DD
I
I
Quiescent Supply Current
Shutdown Supply Current
Y Input Clamp Voltage
V
= 500mV, EN = V , no load
DD
3.9
0.1
-15
5
mA
µA
mV
µA
mA
MΩ
mV
µA
mA
MΩ
mV
kΩ
pA
mV
mV
V/V
%
DD
DD_OFF
IN
EN = 0V
= -100µA
V
I
-30
3
Y_CLAMP
Y_DOWN
Y_UP
Y
I
I
Y Input Clamp Discharge Current
Y Input Clamp Charge Current
Y Input Resistance
V
V
= 0.5V
7
Y
Y
= -0.1V
-3.4
-2.5
R
0.5V < V < 1V
10
-30
3
Y
Y
V
CVBS Input Clamp Voltage
CVBS Input Clamp Discharge current
CVBS Input Clamp Charge current
CVBS Input Resistance
C Input Clamp Voltage
I
= -100µA
Y
-15
5
10
7
CVBS_CLAMP
CVBS_DOWN
CVBS_UP
I
I
V
V
= 0.5V
CVBS
CVBS
= -0.1V
< 1V
-3.4
-2.5
R
0.5V < V
CVBS
10
500
2.0
CVBS
V
V
V
V
= 0.05V, I = 0A
550
2.6
10
700
3.0
C_CLAMP
Y
Y
Y
C
R
C Input Resistance
= 0.05V, 0.25V < V < 0.75V
C
C
I
C Input Bias Current
= 0.3V
C
V
V
Y Input Sync Detect Voltage
Output Level Shift Voltage
Voltage Gain
100
60
150
140
1.99
±0.5
±0.5
60
200
200
2.04
1.75
2.0
Y_SYNC
OLS
V
= 0V, no load
IN
A
R
= 150Ω
1.95
-1.75
-2.0
V
L
∆A
C-Y Channel Gain Mismatch
C/Y-CVBS Channel Gain Mismatch
DC Power Supply Rejection
Output Voltage High Swing
Output Short-Circuit Current
Enable Input Current
V_CY
∆A
%
V_CVBS
PSRR
V
V
V
= 2.5V to 3.6V
dB
V
DD
V
= 2V, R = 150Ω to GND
2.85
100
-0.2
3.2
145
0
OH
IN
IN
L
I
I
= 2V, to GND through 10Ω
mA
µA
V
SC
ENABLE
0V < V
< 3.3V
+0.2
0.8
EN
V
V
Disable Threshold
IL
Enable Threshold
2.0
5
V
IH
R
Shutdown Output Impedance
EN = 0V DC
7
8
kΩ
kΩ
OUT
EN = 0V, f = 4.5MHz
3.4
FN6278.0
September 21, 2006
2
ISL59117
Electrical Specifications
V
= 3.3V, T = +25°C, R = 150Ω to GND, unless otherwise specified. (Continued)
DD
A
L
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
BW
±0.1dB Bandwidth
R
= 150Ω, C = 5pF
5
9
MHz
MHz
dB
%
0.1dB
3dB
L
L
L
-3dB Bandwidth
Normalized Stopband Gain
Differential Gain
Differential Phase
Group Delay Variation
Signal To Noise Ratio
Enable Time
R
= 150Ω, C = 5pF
L
f = 27MHz
-24.2
0.10
0.5
5.4
65
dG
dP
NTSC and PAL
NTSC and PAL
f = 100kHz, 5MHz
100% white signal
°
D/DT
SNR
ns
dB
ns
T
T
V
V
= 500mV, V
= 500mV, V
to 1%
to 1%
200
14
ON
IN
IN
OUT
OUT
Disable Time
ns
OFF
+SR
-SR
Positive Slew Rate
Negative Slew Rate
Fall Time
20% to 80%, V = 1V step
IN
30
40
60
V/µs
V/µs
ns
80% to 20%, V = 1V step
IN
-30
-40
25
-60
t
t
2.5V
2.5V
, 80% - 20%
STEP
F
Rise Time
, 20% - 80%
STEP
22
ns
R
Connection Diagram
3.3V
0.1µF
V
DD
+
S-VIDEO CABLE
-
65mV
Y
Y
IN
OUT
- +
Y (LUMINANCE)
9MHz
9MHz
9MHz
x2
x2
x2
Y
OUT
0.1µF
75
75
5µA
75
500mV
65mV
- +
C
C
IN
OUT
C (CHROMINANCE)
C
OUT
0.1µF
75
+
-
65mV
- +
CVBS
OUT
CVBS
IN
CVBS (COMPOSITE)
µC OR TIE TO 3.3V
CVBS
OUT
0.1µF
75
5µA
75
BIASING &
CONTROL
EN
FN6278.0
September 21, 2006
3
ISL59117
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
A1
A2
A3
B1
B2
B3
C1
C2
C3
C
Chrominance input
Ground
IN
GND
C
Chrominance output
Composite Video input
Enable
OUT
CVBS
EN
IN
CVBS
Composite Video output
Luminance Input
OUT
Y
IN
V
Positive power supply
Luminance output
DD
Y
OUT
Typical Performance Curves
5
5
V
R
= +3.3V
V
R
= +3.3V
= 150Ω
DD
= 150Ω
DD
L
4
3
0
-5
L
2
-10
-15
-20
-25
-30
-3dB BW @ 9MHz
-30dB BW @ 27MHz
1
-0.1dB BW @ 3.8MHz
0
-1
-2
-3
-4
-5
-35
-40
100k
1M
FREQUENCY (Hz)
10M
40M
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY -0.1dB
FIGURE 2. GAIN vs FREQUENCY -3dB POINT
5
4
3
2
1
4.0
V
R
= +3.3V
= 150Ω
V
R
= +3.3V
DD
L
= 100kHz
DD
L
3.5
3.0
2.5
2.0
1.5
1.0
= 150Ω
F
IN
C
= 27pF
L
0
-1
-2
-3
-4
-5
C
= 10pF
L
C
= 470pF
L
C
= 1000pF
L
0.5
0.0
100k
1M
10M
100M
0.0 0.5
1.0
1.5
2.0
(V
2.5
3.0
3.5 4.0
FREQUENCY (Hz)
V
)
IN
P-P
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS C
FIGURE 4. MAXIMUM OUTPUT MAGNITUDE vs INPUT
MAGNITUDE
LOAD
FN6278.0
September 21, 2006
4
ISL59117
Typical Performance Curves (Continued)
270
-20
-30
V
R
= +3.3V
V
= +3.3V
DD
L
DD
= 150Ω
180
90
0
-40
-50
-60
-70
-80
-90
-180
-270
-90
-100
100k
1M
10M
100M
100k
1M
10M
100M
50M
4.0
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. PHASE vs FREQUENCY
FIGURE 6. PSRR vs FREQUENCY
-40
-50
V
= +3.3V
DD
Y
to C
OUT
IN
-60
-70
-80
-90
C
to Y
OUT
IN
-100
-110
100k
1M
FREQUENCY (Hz)
10M
FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 8. ISOLATION vs FREQUENCY
8
7
NO LOAD
NO INPUT
V
IN
= +3.3V
DD
= 1MHz
F
6
5
4
3
2
1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SUPPLY VOLTAGE (V)
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 9. MAXIMUM OUTPUT vs LOAD RESISTANCE
FN6278.0
September 21, 2006
5
ISL59117
Typical Performance Curves (Continued)
2.2
0.5
0.4
V
R
= +3.3V
= 150Ω
DD
L
1.7
1.2
0.7
0.2
-0.3
V
= 1V
OUT
P-P
V
= +3.3V
DD
0.3
0.2
R
= 150Ω
L
T
= 10.46ns
RISE
V
= 200mV
OUT
P-P
T
= 27.85ns
RISE
T
= 26.81ns
FALL
0.1
0
T
= 27.92ns
FALL
-100
0
100 200 300 400 500 600
TIME (ns)
-100
0
100
200
300
400
500 600
TIME (ns)
FIGURE 11. LARGE SIGNAL STEP RESPONSE
FIGURE 12. SMALL SIGNAL STEP RESPONSE
2.5
2.5
V
R
= +3.3V
= 150Ω
DD
L
2.0
2.0
1.5
DISABLE SIGNAL
ENABLE SIGNAL
1.5
1.0
1.0
0.5
0.5
OUTPUT SIGNAL
0.0
0.0
-0.5
-0.5
-1.0
V
R
= +3.3V
= 150Ω
DD
L
OUTPUT SIGNAL
-1.0
-100
-20
-50
0
50
100
150
200
-10
0
10
20
30
TIME (ns)
TIME (ns)
FIGURE 13. ENABLE TIME
FIGURE 14. DISABLE TIME
-10
-20
-30
-40
-50
-60
-70
-80
-10
-20
-30
-40
-50
-60
V
R
= +3.3V
= 150Ω
= 500kHz
DD
L
V
R
= +3.3V
= 150Ω
DD
L
F
IN
V
= 2V
OUT
P-P
THD
THD
2nd THD
3rd THD
3rd THD
2nd THD
-70
-80
0.5
1.0
1.5
V
2.0
(V
2.5
3.0
3.5
1M 2M 3M 4M 5M 6M 7M 8M 9M 10M
)
FREQUENCY (Hz)
OUT P-P
FIGURE 15. HARMONIC DISTORTION vs FREQUENCY
FIGURE 16. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FN6278.0
September 21, 2006
6
ISL59117
Typical Performance Curves (Continued)
16
14
V
R
= +3.3V
V
R
= +3.3V
= 150Ω
DD
L
DD
L
= 150Ω
12
10
8
6
4
2
20
100
180
260
340
420
500
INPUT RESISTANCE (Ω)
FIGURE 17. GROUP DELAY vs FREQUENCY
FIGURE 18. -3dB BANDWIDTH vs INPUT RESISTANCE
50
V
R
= 2V
= 150Ω
OUT
L
P-P
45
40
35
30
POSITIVE SLEW RATE
NEGATIVE SLEW RATE
25
20
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
FIGURE 19. SLEW RATE vs SUPPLY VOLTAGE
100
10
2
4
6
8
1
2
4
6
8
1
2
4
10kHz
100kHz
1MHz
4.2MHz
FREQUENCY (Hz)
FIGURE 20. UNWEIGHTED NOISE FLOOR
FN6278.0
September 21, 2006
7
ISL59117
Typical Performance Curves (Continued)
JEDEC JESD51-3 LOW EFFECTIVE
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
THERMAL CONDUCTIVITY TEST BOARD
1
1.4
1.2
1
0.9
0.8
0.7
952mW
WLCSP (3x3 BUMP)
0.6
0.8
0.6
0.4
0.2
0
462mW
θ
=105°C/W
JA
0.5
WLCSP (3x3 BUMP)
0.4
θ
=216°C/W
JA
0.3
0.2
0.1
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
The Sallen Key Low Pass Filter
Application Information
The Sallen Key is a classic low pass configuration. This
provides a very stable low pass function, and in the case of
the ISL59117, a three-pole roll-off at 9MHz. The three-pole
function is accomplished with an RC low pass network placed
in series with and before the Sallen Key. The first pole is
formed by an RC network, with poles two and three generated
with a Sallen Key, creating a nice three-pole roll-off at 9MHz.
The ISL59117 is a single-supply rail-to-rail triple (one s-video
channel and one composite channel) video amplifier with
internal sync tip clamps, a typical -3dB bandwidth of 9MHz
and slew rate of about 40V/µs. This part is ideally suited for
applications requiring high composite and s-video
performance with very low power consumption. As the
performance characteristics and features illustrate, the
ISL59117 is optimized for portable video applications.
Output Coupling
Internal Sync Clamp
The ISL59117 can be AC or DC coupled to its output. When
AC coupling, a 220µF coupling capacitor is recommended to
ensure that low frequencies are passed, preventing video
“tilt” or “droop” across a line.
Embedded video DACs typically use ground as their most
negative supply. This places the sync tip voltage at a
minimum of 0V. Presenting a 0V input to most single supply
amplifiers will saturate the output stage of the amplifier
resulting in a clipped sync tip and degraded video image.
The ISL59117’s internal sync clamp makes it possible to DC
couple the output to a video load, eliminating the need for
any AC coupling capacitors, saving board space, cost, and
eliminating any “tilt” or offset shift in the output signal. The
trade off is larger supply current draw, since the DC
component of the signal is now dissipated in the load
resistor. Typical load current for AC coupled signals is 5mA
compared to 10mA for DC coupling.
The ISL59117 features an internal sync clamp and offset
function that level shifts the entire video signal to the
optimum level before it reaches the amplifiers’ input stage.
These features also help avoid saturation of the output stage
of the amplifier by setting the signal closer to the best
voltage range.
Output Drive Capability
The simplified block diagram on the front page shows the
basic operation of the ISL59117’s sync clamp. The Y and
CVBS inputs’ AC-coupled video sync signal is pulled
negative by a current source at the input. When the sync tip
goes below the comparator threshold, the comparator output
goes high, pulling up on the input through the diode, forcing
current into the coupling capacitor until the voltage at the
input is again 0V, and the comparator turns off. This forces
the sync tip clamp to always be 0V, setting the offset for the
entire video signal. The C channel is slaved to the Y channel
and clamped to a 500mV level.
The ISL59117 does not have internal short circuit protection
circuitry. If the output is shorted indefinitely, the power
dissipation could easily overheat the die or the current could
eventually compromise metal integrity. Maximum reliability is
maintained if the output current never exceeds ±40mA. This
limit is set by the design of the internal metal interconnect.
Note that for transient short circuits, the part is robust.
Short circuit protection can be provided externally with a
back match resistor in series with the output placed close as
possible to the output pin. In video applications this would be
a 75Ω resistor and will provide adequate short circuit
protection to the device. Care should still be taken not to
stress the device with a short at the output.
FN6278.0
September 21, 2006
8
ISL59117
Power Dissipation
Power Supply Bypassing Printed Circuit Board
Layout
With the high output drive capability of the ISL59117, it is
possible to exceed the +125°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
As with any modern operational amplifier, a good printed
circuit board layout is necessary for optimum performance.
Lead lengths should be as short as possible. The power
supply pin must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, a single
4.7µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor from V + to GND will suffice.
S
The maximum power dissipation allowed in a package is
determined according to:
Printed Circuit Board Layout
T
– T
AMAX
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance.
JMAX
PD
= --------------------------------------------
MAX
Θ
JA
Where:
T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
T
AMAX
Θ
= Thermal resistance of the package
JA
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
for sourcing:
V
OUT
R
L
---------------
PD
= V × I
+ (V – V
) ×
MAX
S
SMAX
S
OUT
for sinking:
PD
= V × I
+ (V
– V ) × I
OUT S LOAD
MAX
S
SMAX
Where:
V = Supply voltage
S
I
= Maximum quiescent supply current
SMAX
V
= Maximum output voltage of the application
OUT
R
= Load resistance tied to ground
LOAD
I
= Load current
LOAD
FN6278.0
September 21, 2006
9
ISL59117
Wafer Level Chip Scale Package (WLCSP)
W3x3.9A
3x3 ARRAY 9 BALL WAFER LEVEL CHIP SCALE PACKAGE
(For ISL59116, ISL59117 Only)
E
SYMBOL
MILLIMETERS
0.62 +0.05 -0.08
0.24 ±0.025
0.38 REF.
NOTES
A
-
PIN A1 ID AREA
A
A
-
1
2
D
-
b
0.32 ±0.03
θ 0.30 REF.
1.45 ±0.05
1.00 BASIC
1.45 ±0.05
1.00 BASIC
0.50 BASIC
0.00 BASIC
9
-
bb
D
-
TOP VIEW
-
D
-
1
bb
E
-
E
-
1
A
2
A
e
-
A
1
SD
N
-
3
b
Rev. 1 6/06
SIDE VIEW
E1
NOTES:
1. Dimensions are in Millimeters.
2. Dimensioning and tolerancing conform to ASME 14.5M-1994.
3. Symbol “N” is the actual number of solder balls.
4. Reference JEDEC MO-211-C, variation DD.
C
B
SD
D
1
A
1
2
3
b
BOTTOM VIEW
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6278.0
September 21, 2006
10
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