ISL59442IBZ [INTERSIL]
1GHz, 4 x 1 Multiplexing Amplifier; 1GHz的4× 1复用放大器
| 型号： | ISL59442IBZ |
| 厂家： | 
Intersil |
| 描述： | 1GHz, 4 x 1 Multiplexing Amplifier |
| 文件： | 总11页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL59442
®
Data Sheet
September 21, 2005
FN7452.2
1GHz, 4 x 1 Multiplexing Amplifier
Features
• 1GHz (-3dB) Bandwidth (V
The ISL59442 is a single-output 4:1 MUX-amp. The
MUX-amp has a fixed gain of 1 and a 1GHz bandwidth. The
device contains logic inputs for channel selection (S0, S1),
and a three-state output control (HIZ) for individual
selection of MUX amps that share a common video output
line. All logic inputs have pull-downs to ground and may be
left floating.
= 200mV
)
P-P
OUT
• 235MHz (-3dB) Bandwidth (V
= 1V )
P-P
OUT
= 5V) . . . . . . . . . . . .1452V/µs
OUT
• Slew Rate (R = 525Ω, V
L
• High Speed Three-state Output (HIZ)
• Pb-Free Plus Anneal Available (RoHS Compliant)
TABLE 1. TRUTH TABLE
Applications
• HDTV/DTV Analog Inputs
HIZ
0
S1
0
S0
0
OUT
IN0
IN1
IN2
IN3
HIZ
• Video Projectors
0
0
1
• Computer Monitors
• Set-top Boxes
0
1
0
0
1
1
1
X
X
• Security Video
• Broadcast Video Equipment
Pinout
ISL59442
(14 LD SO)
TOP VIEW
Functional Diagram
EN0
S0
IN0
NIC
IN1
1
2
3
4
5
6
7
14 V+
13 S0
12 S1
11 HIZ
10 OUT
IN0
EN1
OUT
S1
IN1
IN2
DECODE
EN2
EN3
GND
IN2
IN3
A=1
NIC
IN3
9
8
NIC
V-
HIZ
Ordering Information
TAPE &
PART NUMBER PART MARKING PACKAGE REEL
PKG.
DWG. #
ISL59442IB
59442IB
59442IB
14 Ld SO
14 Ld SO
14 Ld SO
-
7”
13”
-
MDP0027
MDP0027
MDP0027
MDP0027
ISL59442IB-T7
ISL59442IB-T13 59442IB
ISL59442IBZ
(Note)
59442IBZ
14 Ld SO
(Pb-free)
ISL59442IBZ-T7 59442IBZ
(Note)
14 Ld SO
(Pb-free)
7”
MDP0027
MDP0027
ISL59442IBZ-T13 59442IBZ
(Note)
14 Ld SO
(Pb-free)
13”
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL59442
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . .-40°C to 85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
θ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
JA
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, T = 25°C, Input Video = 1V
& R = 500Ω to GND, V
= 0.8V, Unless
HIZ
A
P-P
L
Otherwise Specified
PARAMETER
GENERAL
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
I
Supply Current (V
= 0V)
No load, V
No load, V
= 0.8V
= 2.0V
14.5
12
18
15.5
±3.44
±120
9
20
mA
mA
V
S
OUT
HIZ
HIZ
17.5
V
Positive and Negative Output Swing
Output Current
V
= ±3.5V, R = 500Ω
±3.2
±80
-2
OUT
IN
L
I
R
= 10Ω to GND
±180
20
mA
mV
µA
MΩ
Ω
OUT
L
V
Output Offset Voltage
Input Bias Current
OS
Ib
V
= 0V
-5
-2.5
1.4
-1
IN
R
Output Resistance
HIZ = logic high, (DC)
HIZ = logic low, (DC)
out
0.2
R
Input Resistance
V
V
V
= ±3.5V
10
MΩ
V/V
µA
IN
CL
IN
A
or A
Voltage Gain
= ±1.5V, R = 500Ω
0.999
-35
1.001
6
1.003
35
V
IN
L
I
Output Current in Three-state
= 0V
OUT
TRI
LOGIC
V
V
Input High Voltage (Logic Inputs)
Input Low Voltage (Logic Inputs)
Input High Current (Logic Inputs)
Input Low Current (Logic Inputs)
2
V
V
H
L
0.8
I
I
50
90
2
150
µA
µA
IH
IL
AC GENERAL
-3dB BW
-3dB Bandwidth
0.1dB Bandwidth
V
V
V
V
= 200mV , C = 1.6pF
P-P
1.0
235
100
35
GHz
MHz
MHz
MHz
%
OUT
OUT
OUT
OUT
L
= 2V , C = 23.6pF, R = 25Ω
P-P
L
S
0.1dB BW
= 200mV , C = 1.6pF
P-P
L
= 2V , C = 23.6pF, R = 25Ω
P-P
L
S
dG
Differential Gain Error
Differential Phase Error
Slew Rate
NTC-7, R = 150
0.01
0.02
1452
L
dP
NTC-7, R = 150
°
L
+SR
25% to 75%, V
R = 525Ω, C = 23.6pF
= 5V,
V/µs
OUT
L
L
-SR
Slew Rate
25% to 75%, V
= 5V,
1124
V/µs
OUT
R = 525Ω, C = 23.6pF
L
L
FN7452.2
2
September 21, 2005
ISL59442
Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, T = 25°C, Input Video = 1V
& R = 500Ω to GND, V
= 0.8V, Unless
HIZ
A
P-P
L
Otherwise Specified (Continued)
PARAMETER
PSRR
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
V± = ±4.5V to ±5.5V
-50
-57
dB
ISO
Channel Isolation
f = 10MHz, Ch-Ch X-Talk and Off Isolation,
C = 1.6pF
75
dB
L
SWITCHING CHARACTERISTICS
V
Channel-to-Channel Switching Glitch
HIZ Switching Glitch
V
V
= 0V, C = 23.6pF, R = 25Ω
2
mV
GLITCH
IN
IN
L
S
P-P
P-P
= 0V, C = 23.6pF, R = 25Ω
135
30
mV
L
S
t
t
Channel Switching Time Low to High 1.2V logic threshold to 10% movement of
analog output
ns
SW-L-H
SW-H-L
Channel Switching Time High to Low 1.2V logic threshold to 10% movement of
analog output
28
ns
TRANSIENT RESPONSE
tr, tf Rise & Fall Time, 10% to 90%
V
V
V
V
V
V
V
V
V
= 200mV , C = 1.6pF
P-P
0.69
1.4
ns
ns
ns
ns
ns
ns
ns
%
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
L
= 2V , C = 23.6pF, R = 25Ω
P-P
L
S
t
t
0.1% Settling Time
= 2V , C = 23.6pF, R = 25Ω
P-P
6.6
S
L
S
Propagation Delay - Low to High,
10% to 10%
= 200mV , C = 1.6pF
P-P
0.46
0.92
0.52
0.97
8.3
PLH
L
= 2V , C = 23.6pF, R = 25Ω
P-P
L
S
t
Propagation Delay- High to Low,
10% to 10%
= 200mV , C = 1.6pF
P-P
PHL
L
= 2V , C = 23.6pF, R = 25Ω
P-P
L
S
O
Overshoot
= 200mV , C = 1.6pF
P-P
S
L
= 2V , C = 23.6pF, R = 25Ω
P-P
13.3
%
L
S
Typical Performance Curves V = ±5V, R = 500Ω to GND, T = 25°C, unless otherwise specified.
S
L
A
5
4
3
2
1
0
5
4
3
2
1
0
V
= 200mV
P-P
V
= 200mV
P-P
OUT
= 1.6pF
OUT
C
L
C
= 9.7pF
L
R
= 1kΩ
L
C
= 7.2pF
L
R
= 500Ω
L
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
C
= 5.5pF
L
C
= 1.6pF
L
R
= 150Ω
L
R
= 75Ω
L
C
INCLUDES 1.6pF
L
BOARD CAPACITANCE
0.001
0.01
0.1
1 1.5
0.001
0.01
0.1
1 1.5
FREQUENCY (GHz)
FREQUENCY (MHz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs C
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs R
L
L
FN7452.2
3
September 21, 2005
ISL59442
Typical Performance Curves V = ±5V, R = 500Ω to GND, T = 25°C, unless otherwise specified. (Continued)
S
L
A
5
4
3
2
1
0
5
4
3
2
1
0
V
R
= 2V
P-P
V
= 2V
P-P
= 23.6pF
OUT
= 25Ω
OUT
S
C
L
R
= 25Ω
S
C
= 11.6pF
L
R
= 1kΩ
L
C
= 16.6pF
L
R
= 75Ω
L
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
C
= 23.6pF
R
L
= 500Ω
= 150Ω
L
R
L
C
INCLUDES 1.6pF
L
BOARD CAPACITANCE
C
= 28.6pF
0.1
L
0.001
0.01
1 1.5
0.001
0.01
0.1
1 1.5
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs C
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs R
L
L
0.5
0.2
0.1
C
= 9.7pF
L
V
= 200mV
P-P
OUT
0.4
0.3
0.2
0.1
0
0.0
C
= 7.2pF
L
-0.1
-0.2
-0.3
C
= 5.5pF
L
R
= 1kΩ
L
-0.1
-0.2
-0.3
-0.4
-0.5
-0.4
-0.5
-0.6
-0.7
-0.8
R
= 500Ω
L
C
= 1.6pF
L
R
= 150Ω
L
V
= 200mV
P-P
C
INCLUDES 1.6pF
OUT
= 1.6pF
L
C
BOARD CAPACITANCE
L
R
= 75Ω
L
0.001
0.01
0.1
1 1.5
0.001
0.01
0.1
1 1.5
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 5. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs C
FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs R
L
L
0.5
0.4
0.5
V
= 2V
P-P
= 23.6pF
OUT
R
R
= 1kΩ
0.4
0.3
0.2
0.1
0
L
C
= 11.6pF
L
C
= 500Ω
L
L
0.3
0.2
0.1
0
R
= 25Ω
S
C
= 16.6pF
L
R
= 150Ω
L
R
= 75Ω
L
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
C
= 23.6pF
L
V
R
= 2V
P-P
OUT
= 25Ω
S
C
= 28.6pF
0.1
L
C
INCLUDES 1.6pF
L
BOARD CAPACITANCE
0.001 0.01
1 1.5
0.001
0.01
0.1
1 1.5
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 7. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs C
FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs R
L
L
FN7452.2
4
September 21, 2005
ISL59442
Typical Performance Curves V = ±5V, R = 500Ω to GND, T = 25°C, unless otherwise specified. (Continued)
S
L
A
-10
-20
20
10
0
V
= 1V
P-P
= 23.6pF
IN
V
= 200mV
= 23.6pF
= 25Ω
IN
P-P
C
L
C
L
-30
-40
R
= 25Ω
S
R
S
-10
-20
-30
-40
-50
-60
CROSSTALK
-70
-50
-80
PSRR (V+)
PSRR (V-)
-60
-70
-80
-90
OFF ISOLATION
-100
-110
0.3
1
10
100
1000
0.001
0.01
0.1
1
3
6 10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 10. CROSSTALK AND OFF ISOLATION
FIGURE 9. PSRR CHANNELS
100
V
= 100mV
P-P
OUT
60
50
40
30
20
R
= 500Ω
F
10
1
10
0
0.1
0.1
1
10
FREQUENCY (MHz)
100
1000
1
10
100
0.1
FREQUENCY (kHz)
FIGURE 12. INPUT NOISE vs FREQUENCY
FIGURE 11. R
vs FREQUENCY
OUT
S0, S1
S0, S1
0
0
0
0
V
OUT
V
OUT
20ns/DIV
20ns/DIV
FIGURE 14. CHANNEL TO CHANNEL TRANSIENT RESPONSE
= 1V, R = 25, C = 23.6pF
FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH
= 0V, R = 25, C = 23.6pF
V
V
IN
S
L
IN
S
L
FN7452.2
5
September 21, 2005
ISL59442
Typical Performance Curves V = ±5V, R = 500Ω to GND, T = 25°C, unless otherwise specified. (Continued)
S
L
A
HIZ
HIZ
0
0
0
V
V
OUT
OUT
0
20ns/DIV
20ns/DIV
FIGURE 16. HIZ TRANSIENT RESPONSE V = 1V, R = 25,
IN
FIGURE 15. HIZ SWITCHING GLITCH V = 0V, R = 25,
IN
S
S
C
= 23.6pF
C
= 23.6pF
L
L
160
2.4
2
C
R
= 1.6pF
= 500Ω
L
120
80
L
1.6
1.2
0.8
0.4
0
40
0
-40
-80
C
= 23.6pF
= 25Ω
L
-0.4
-0.8
R
R
-120
-160
S
L
= 500Ω
TIME (4ns/DIV)
TIME (4ns/DIV)
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
CONDUCTIVITY TEST BOARD
1
1.136W
1.2
0.9
0.8
1
0.8
0.6
0.4
0.2
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
833mW
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7452.2
September 21, 2005
6
ISL59442
Pin Descriptions
EQUIVALENT
CIRCUIT
PIN NUMBER
PIN NAME
IN0
DESCRIPTION
1
Circuit 1
Input for channel 0
2, 6, 9
NIC
Not Internally Connected; it is recommended this pin be tied to ground to
minimize crosstalk.
3
4
IN1
GND
IN2
IN3
V-
Circuit 1
Circuit 4
Circuit 1
Circuit 1
Circuit 4
Circuit 3
Circuit 2
Input for channel 1
Ground pin
5
Input for channel 2
Input for channel 3
Negative power supply
Output
7
8
10
11
OUT
HIZ
Output disable (active high); there are internal pull-down resistors, so the
device will be active with no connection; "HI" puts the output in high
impedance state.
12
13
14
S1
S0
V+
Circuit 2
Circuit 2
Circuit 4
Channel selection pin MSB (binary logic code)
Channel selection pin LSB (binary logic code)
Positive power supply
V+
V-
V+
21K
33K
+
-
IN
LOGIC PIN
1.2V
GND.
V-
CIRCUIT 1.
CIRCUIT 2.
V+
V+
OUT
CAPACITIVELY
GND
COUPLED
ESD CLAMP
V-
V-
CIRCUIT 3.
CIRCUIT 4.
FN7452.2
7
September 21, 2005
ISL59442
AC Test Circuits
ISL59442
ISL59442
TEST EQUIPMENT
V
R
IN
S
V
IN
C
2pF
R
50Ω
L
L
475Ω
50Ω
50Ω
or
50Ω
or
C
L
or
500Ω
or
2pF
75Ω
75Ω
75Ω
75Ω
FIGURE 21B. TEST CIRCUIT FOR MEASURING WITH A 50Ω OR 75Ω
FIGURE 21A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
INPUT TERMINATED EQUIPMENT
ISL59442
TEST EQUIPMENT
R
S
V
IN
50Ω or 75Ω
50Ω
or
C
50Ω
or
L
2pF
75Ω
75Ω
FIGURE 21C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω WILL BE
DEGRADED
NOTE: Figure 21A illustrates the optimum output load for testing AC performance. Figure 21B illustrates the optimum output load when connecting
to input terminated equipment. Figure 21C illustrates back loaded test circuit for video cable.
Application Circuits
*C = C + C
OUT
L
T
-
V
OUT
V
IN
+
C
C
OUT
0pF
T
R
= 500Ω
L
50Ω
1.6pF
*C : TOTAL LOAD CAPACITANCE
L
C : TRACE CAPACITANCE
T
OUT
C
: OUTPUT CAPACITANCE
FIGURE 22A. SMALL SIGNAL 200mV
APPLICATION CIRCUIT
P-P
R
S
-
25Ω
V
OUT
V
IN
+
C
OUT
22pF
R
= 500Ω
C
1.6pF
L
T
50Ω
C
= C + C
T
L
OUT
FIGURE 22B. LARGE SIGNAL 1V
APPLICATION CIRCUIT
P-P
FN7452.2
8
September 21, 2005
ISL59442
Power-Up Considerations
Application Information
The ESD protection circuits use internal diodes from all pins the
V+ and V- supplies. In addition, a dV/dT- triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum supply
turn-on slew rate of 1V/µs. Damaging currents can flow for
power supply rates-of-rise in excess of 1V/µs, such as during
hot plugging. Under these conditions, additional methods
should be employed to ensure the rate of rise is not exceeded.
General
The ISL59442 is a 4:1 mux that is ideal as a matrix element in
high performance switchers and routers. The ISL59442 is
optimized to drive a 2pF in parallel with a 500Ω load. The
capacitance can be split between the PCB capacitance an and
external load capacitance. Their low input capacitance and high
input resistance provide excellent 50Ω or 75Ω terminations.
Capacitance at the Output
The output amplifier is optimized for capacitance to ground
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 23) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
(C ) directly on the output pin. Increased capacitance
L
causes higher peaking with an increase in bandwidth. The
optimum range for most applications is ~1.0pF to ~6pF. The
optimum value can be achieved through a combination of
PC board trace capacitance (C ) and an external capacitor
T
(C
OUT)
. A good method to maintain control over the output
pin capacitance is to minimize the trace length (C ) to the
T
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
next component, and include a discrete surface mount
capacitor (C
) directly at the output pin.
OUT
For large signal applications where overshoot is important
the circuit in Figure 22B should be used. The series resistor
(R ) and capacitor (C ) form a low pass network that limits
S
L
system bandwidth and reduces overshoot. The component
values shown result in a typical pulse response shown in
Figure 18.
Ground Connections
HIZ State
For the best isolation and crosstalk rejection, the GND pin
and NIC pins must connect to the GND plane. The NIC pins
are placed on both sides of the input pins. These pins are
not internally connected to the die. It is recommended this
pin be tied to ground to minimize crosstalk.
An internal pull-down resistor connected to the HIZ pin ensures
the device will be active with no connection to the HIZ pin. The
HIZ state is established within approximately 30ns by placing a
logic high (>2V) on the HIZ pin. If the HIZ state is selected, the
output is a high impedance 1.4MΩ. Use this state to control the
logic when more than one mux shares a common output.
Control Signals
In the HIZ state the output is three-stated, and maintains its
high Z even in the presence of high slew rates. The supply
current during this state is basically the same as the active
state.
S0, S1, HIZ - These pins are, TTL/CMOS compatible control
inputs. The S0, S1 pins select which one of the inputs
connect to the output. The HIZ pin is used to three-state the
output amplifiers. For control signal rise and fall times less
than 10nsec the use of termination resistors close to the part
will minimize transients coupled to the output.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than 50mA.
Adequate thermal heat sinking of the parts is also required.
V+ SUPPLY
SCHOTTKY
V+
EXTERNAL
CIRCUITS
V+
PROTECTION
LOGIC
LOGIC
CONTROL
S0
POWER
GND
V- V+
GND
V+
V-
SIGNAL
V+
V-
OUT
IN0
DE-COUPLING
CAPS
IN1
V-
V-
V- SUPPLY
FIGURE 23. SCHOTTKY PROTECTION CIRCUIT
FN7452.2
September 21, 2005
9
ISL59442
PC Board Layout
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip
lines are used.
• Match channel-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices
as possible. Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
FN7452.2
10
September 21, 2005
ISL59442
SO Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
<http://www.intersil.com/design/packages/index.asp>
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7452.2
11
September 21, 2005
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