ISL59532_技术文档

ISL59532

®

Data Sheet

July 24, 2006

FN7432.3

32x32 Video Crosspoint

Features

The ISL59532 is a 300MHz 32x32 Video Crosspoint Switch.

Each input has an integrated DC-restore clamp and an input

buffer. Each output has a fast On-Screen Display (OSD)

switch (for inserting graphics or other video) and an output

buffer. The switch is non-blocking, so any combination of

inputs to outputs can be chosen, including one channel

driving multiple outputs. The Broadcast Mode directs one

input to all 32 outputs. The output buffers can be individually

controlled through the SPI interface, the gain can be

programmed to x1 or x2, and each output can be placed into

a high impedance mode.

• 32x32 non-blocking switch with buffered inputs and

outputs

• 300MHz typical bandwidth

• 0.025%/0.05° dG/dP

• Output gain switchable x1 or x2 for each channel

• Individual outputs can be put in a high impedance state

• -90dB Isolation at 6MHz

• SPI digital interface

• Single +5V supply operation

The ISL59532 offers a typical -3dB signal bandwidth of

300MHz. Differential gain of 0.025% and differential phase of

0.05°, along with 0.1dB flatness out to 50MHz, make the

ISL59532 suitable for many video applications.

• Pb-free plus anneal available (RoHS compliant)

Applications

• Security camera switching

• RGB routing

The switch matrix configuration and output buffer gain are

programmed through an SPI/QSPI™-compatible three-wire

serial interface. The ISL59532 interface is designed to

facilitate both fast updates and initialization. On power-up, all

outputs are high impedance to avoid output conflicts.

• HDTV routing

Ordering Information

The ISL59532 is available in a 356 ball BGA package and

specified over an extended -40°C to +85°C temperature range.

TAPE &

REEL

PACKAGE

(Pb-Free)

PART NUMBER

PKG. DWG. #

The single-supply ISL59532 can accommodate input signals

from 0V to 3.5V and output voltages from 0V to 3.8V. Each

input includes a clamp circuit that restores the input level to

an externally applied reference in AC-coupled applications.

ISL59532IKEZ

-

356 Ld BGA

V356.27x27A

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte

tin plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

The ISL59533 is a fully differential input version of this device.

Block Diagram

VS+

VOVERn OVERn

32

OVERLAY

INPUT

LOGIC

CONTROL

-

+

REF

2uA

Power-on

SWITCH

MATRIX

32 OUTPUTS

32 INPUTS

Clamp

Enable

-

+

2uA

Av

Output

Power-on

x1, x2 Enable

SDI

SCLK

SLATCH

SPI INTERFACE, REGISTER

SDO

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL59532

Pinout

ISL59532

(356 LD BGA)

TOP VIEW

A

B

C

D

E

F

In24

In25

In26

In27

In28

In29

In30

In31

Over31 Over30 Over29 Over28 Out27 Out26 Out25 Out24

Out31 Out30 Out29 Out28 Over27 Over26 Over25 Over24

Vover31 Vover30 Vover29 Vover28 Vover27 Vover26 Vover25 Vover24 Vover23 Out23 Over23

Vover22 Out22 Over22

In23

In22

In21

In20

In19

In18

In17

In16

In15

In14

In13

In12

In11

In10

In9

V

Vs

SDO

Vover21 Out21 Over21

Vover20 Out20 Over20

Vover19 Over19 Out19

Vover18 Over18 Out18

Vover17 Over17 Out17

Vover16 Over16 Out16

Vover15 Out15 Over15

Vover14 Out14 Over14

Vover13 Out13 Over13

Vover12 Out12 Over12

Vover11 Over11 Out11

Vover10 Over10 Out10

Vover9 Over9 Out9

GND GND GND GND GND GND GND GND GND GND

G

H

J

SDO

RESET

SLATCH

SCLK

K

L

SDI

M

N

P

R

T

V

REF

U

V

W

Y

Vs

In8

NC

Vover0 Vover1 Vover2 Vover3 Vover4 Vover5 Vover6 Vover7 Vover8 Over8 Out8

Over0 Over1 Over2 Over3

Out4

Out5

Out6

Out7

In7

In6

In5

In4

In3

In2

In1

In0

Out0

Out1

Out2

Out3 Over4 Over5 Over6 Over7

13 14 15 16 17

1

2

3

4

5

6

7

8

9

10

11

12

18

19

20

= NO BALLS

Balls labelled “NC” should be left unconnected - do not tie them to ground!

Balls with no labels may be tied to ground to slightly reduce thermal impedance.

FN7432.3

July 24, 2006

2

ISL59532

Absolute Maximum Ratings (T = 25°C)

A

Supply Voltage between V and GND. . . . . . . . . . . . . . . . . . . . 6.0V

S

Maximum power supply (V ) slew rate . . . . . . . . . . . . . . . . . . 1V/µs

ESD Classification

S

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

DC Electrical Specifications

V = 5V, R = 150Ω unless otherwise noted.

S L

PARAMETER

DESCRIPTION

Power Supply Voltage

CONDITION

MIN

4.5

1.2

0.98

1.96

-1.5

0

TYP

MAX

5.5

1.02

2.04

+1.5

3.5

3.8

1

UNIT

V

S

V

Power Supply for SDO output pin

Gain

Establishes serial data output high level

V

SDO

A

= 1

= 2

= 1

= 2

= 1

= 2

1

2

V/V

%

V

A

V

GM

Gain Matching (to average of all other

outputs)

A

V

A

%

V

Video Input Voltage Range

Video Output Voltage Range

Input Bias Current

A

V

IN

V

A

0.1

-10

0.5

-20

-100

60

V

OUT

V

I

Clamp function disabled (DC coupled inputs)

Clamp function enabled, V = V + 0.5V

-5

2

µA

mV

mA

dB

mA

B

10

IN

REF

V

Output Offset Voltage

Output Current

A

= 1

= 2

8

35

OS

V

A

-24

108

31

40

V

I

Sourcing, R = 10Ω to GND

L

OUT

Sinking, R = 10Ω to 2.5V

24

L

PSRR

Power Supply Rejection Ratio

Supply Current

A

= 2

50

70

V

I

Enabled, all outputs enabled, no load current

Enabled, all outputs disabled, no load current

Disabled

560

280

1.2

640

320

1.8

720

360

2.4

S

AC Electrical Specifications

V = 5V, R = 150Ω unless otherwise noted.

S L

PARAMETER

BW -3dB

BW 0.1dB

SR

DESCRIPTION

3dB Bandwidth

CONDITION

MIN

TYP

300

50

MAX

UNIT

MHz

V/µs

ns

V

= 200mV , A = 2

V

OUT

P-P

0.1dB Bandwidth

Slew Rate

= 200mV , A = 2

P-P

V

= 2V , A = 2

300

520

12

740

P-P

V

T

Settling Time to 0.1%

Switching Glitch, Peak

Overlay Delay Time

Diff Gain

= 2V , A = 2

S

P-P

V

Glitch

A

= 1

40

mV

V

T

From OVER rising edge to output transition

6

ns

over

dG

dP

Xt

A

= 2, R = 150Ω

0.025

0.05

-85

18

%

V

L

Diff Phase

A

= 2, R = 150Ω

°

V

L

Hostile Crosstalk

Input Referred Noise Voltage

6MHz

dB

V

nV/√Hz

N

FN7432.3

July 24, 2006

3

ISL59532

Pin Descriptions (Continued)

Pin Descriptions

NAME

NUMBER

W16

W17

V20

U20

T20

R20

P19

N19

M19

L19

DESCRIPTION

NAME

NUMBER

DESCRIPTION

Crosspoint Video Input

OUT6

Crosspoint Video Output

IN0

Y8

OUT7

Crosspoint Video Output

IN1

Y7

Crosspoint Video Input

Crosspoint Video Output

OUT8

Crosspoint Video Output

IN2

Y6

OUT9

Crosspoint Video Output

IN3

Y5

OUT10

OUT11

OUT12

OUT13

OUT14

OUT15

OUT16

OUT17

OUT18

OUT19

OUT20

OUT21

OUT22

OUT23

OUT24

OUT25

OUT26

OUT27

OUT28

OUT29

OUT30

OUT31

OVER0

OVER1

OVER2

OVER3

OVER4

OVER5

OVER6

OVER7

OVER8

OVER9

OVER10

OVER11

Crosspoint Video Output

IN4

Y4

Crosspoint Video Output

IN5

Y3

Crosspoint Video Output

IN6

Y2

Crosspoint Video Output

IN7

Y1

Crosspoint Video Output

IN8

V1

Crosspoint Video Output

IN9

U1

K20

J20

Crosspoint Video Output

IN10

IN11

IN12

IN13

IN14

IN15

IN16

IN17

IN18

IN19

IN20

IN21

IN22

IN23

IN24

IN25

IN26

IN27

IN28

IN29

IN30

IN31

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

T1

Crosspoint Video Output

R1

H20

G20

F19

E19

D19

C19

A17

A16

A15

A14

B13

B12

B11

Crosspoint Video Output

P1

Crosspoint Video Output

N1

Crosspoint Video Output

M1

L1

Crosspoint Video Output

K1

Crosspoint Video Output

J1

Crosspoint Video Output

H1

Crosspoint Video Output

G1

F1

Crosspoint Video Output

E1

Crosspoint Video Output

D1

Crosspoint Video Output

C1

Crosspoint Video Output

A1

B10

W10

W11

W12

W13

Y14

Y15

Y16

Y17

V19

U19

T19

R19

Crosspoint Video Output

A2

Overlay Logic Control (with pull-down)

A3

A4

A5

A6

A7

A8

Y10

Y11

Y12

Y13

W14

W15

FN7432.3

July 24, 2006

4

ISL59532

Pin Descriptions (Continued)

NAME

OVER12

OVER13

OVER14

OVER15

OVER16

OVER17

OVER18

OVER19

OVER20

OVER21

OVER22

OVER23

OVER24

OVER25

OVER26

OVER27

OVER28

OVER29

OVER30

OVER31

VOVER0

VOVER1

VOVER2

VOVER3

VOVER4

VOVER5

VOVER6

VOVER7

VOVER8

VOVER9

VOVER10

VOVER11

VOVER12

VOVER13

VOVER14

VOVER15

VOVER16

VOVER17

NUMBER

P20

N20

M20

L20

DESCRIPTION

Overlay Logic Control (with pull-down)

Overlay Video Input

NAME

NUMBER

H18

G18

F18

DESCRIPTION

VOVER18

VOVER19

VOVER20

VOVER21

VOVER22

VOVER23

VOVER24

VOVER25

VOVER26

VOVER27

VOVER28

VOVER29

VOVER30

VOVER31

Overlay Video Input

E18

D18

C18

C17

C16

C15

C14

C13

C12

C11

K19

J19

H19

G19

F20

E20

D20

C20

B17

B16

B15

B14

A13

A12

A11

A10

V10

V11

V12

V13

V14

V15

V16

V17

V18

U18

T18

R18

P18

N18

M18

L18

C10

M3

V

DC-restore clamp reference input.

In an AC-coupled configuration

(DC-Restore clamp enabled), the sync

tip of composite video inputs will be

restored to this level. Set to 0.3 to 0.7V

for optimum performance.

REF

In an DC-coupled configuration

(DC-Restore clamp disabled), this pin

should be tied to ground.

Never let the V

pin float! A floating

REF

VREF pin drifts high (and if the clamp

function is enabled) will cause all of the

outputs to simultaneously try to drive

Overlay Video Input

~4V DC into their 150Ω loads.

Overlay Video Input

SLATCH

J3

Serial Latch. Serial data is latched into

ISL59532 on rising edge of SLATCH.

Overlay Video Input

SCLK

SDI

K3

L3

Serial data clock

Serial data input

Overlay Video Input

SDO

G3

Serial data output. Can be tied to SDI of

another ISL59532 to enable daisy-

chaining of multiple devices.

Overlay Video Input

RESET

H3

D3

Reset input. Pull high then low to reset

device, but not needed in normal opera-

tion. Tie to ground in final application.

Overlay Video Input

V

Power supply for SDO pin. Tie to +5V

for a 0 to 5V SDO output signal swing.

SDO

Overlay Video Input

V

S

+5V power supply

Ground

Overlay Video Input

GND

NC

K18

J18

Overlay Video Input

No Connect - Do not electrically con-

nect to anything, including ground.

Overlay Video Input

FN7432.3

July 24, 2006

5

ISL59532

Typical Performance Curves

33pF

27pF

MUX mode

A

= 2

= 100Ω

V

A

= 1

= 100Ω

V

27pF

22pF

R

L

R

L

INPUT_CH 0

22pF

15pF

OUTPUT_CH 0

15pF

OUTPUT_CH 0

10pF

4.7pF

0pF

FIGURE 1. FREQUENCY RESPONSE - VARIOUS C , A = 1,

FIGURE 2. FREQUENCY RESPONSE - VARIOUS C , A = 2,

L

V

L

V

MUX MODE

100Ω

150Ω

500Ω

1.07kΩ

500Ω

1.07kΩ

MUX mode

A

= 2

= 0

A

= 1

= 0

V

C

L

INPUT_CH 0

OUTPUT_CH 0

FIGURE 4. FREQUENCY RESPONSE - VARIOUS R , A = 2,

FIGURE 3. FREQUENCY RESPONSE - VARIOUS R , A = 1,

L

V

L

V

MUX MODE

Overlay mode

A

= 1

V

A

= 2

V

R

C

= 100Ω

= 0pF

L

R

C

= 100Ω

= 0pF

L

INPUT_CH 31

OUTPUT_CH 31

FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT,

= 1

FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT,

= 2

A

V

FN7432.3

July 24, 2006

6

ISL59532

Typical Performance Curves (Continued)

33pF

27pF

Broadcast mode

33pF

27pF

22pF

Broadcast mode

A

= 1

= 100Ω

V

A

= 2

= 100Ω

V

R

L

R

L

INPUT_CH 0

22pF

15pF

INPUT_CH 0

OUTPUT_CH 0

15pF

10pF

4.7pF

0pF

4.7pF

0pF

FIGURE 7. FREQUENCY RESPONSE - VARIOUS C , A = 1,

FIGURE 8. FREQUENCY RESPONSE - VARIOUS C , A = 2,

L

V

L

V

BROADCAST MODE

100Ω

150Ω

503Ω

1.07kΩ

Broadcast mode

A

= 2

= 0

V

A

= 1

= 0

C

V

L

C

INPUT_CH 0

L

INPUT_CH 0

OUTPUT_CH 0

FIGURE 10. FREQUENCY RESPONSE - VARIOUS R , A = 2,

FIGURE 9A. FREQUENCY RESPONSE - VARIOUS R , A = 1,

L

V

L

V

BROADCAST MODE

A

= 2

= 100Ω

= 0

V

A

= 1

= 100Ω

= 0

ADJACENT

INPUT_CH30

OUTPUT_CH31

V

ADJACENT

INPUT_CH30

OUTPUT_CH31

R

C

L

R

L

C

ALL HOSTILE

INPUT_CH0

OUTPUT_CH31

ALL HOSTILE

INPUT_CH0

OUTPUT_CH31

FIGURE 12. CROSSTALK - A = 2

FIGURE 11. CROSSTALK - A = 1

V

FN7432.3

July 24, 2006

7

ISL59532

Typical Performance Curves (Continued)

A

= 2

= 100Ω

A

= 2

= 100Ω

V

THD

R

L

2nd HD

INPUT_CH 0

THD

OUTPUT_CH 0

FREQUENCY = 1MHz

OUTPUT_CH 0

V

= 2V

OP-P

2nd HD

3rd HD

FIGURE 13. HARMONIC DISTORTION vs FREQUENCY

FIGURE 14. HARMONIC DISTORTION vs V

OUT_P-P

FIGURE 16. ENABLED OUTPUT IMPEDANCE

FIGURE 15. DISABLED OUTPUT IMPEDANCE

MUX MODE

A

= 1

= 100Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

FALL TIME

2.65ns

RISE TIME

2.35ns

MUX MODE

A

= 1

= 100Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

FIGURE 18. FALL TIME - A = 1

FIGURE 17. RISE TIME - A = 1

V

FN7432.3

July 24, 2006

8

ISL59532

Typical Performance Curves (Continued)

MUX MODE

A

= 2

= 100Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

FALL TIME

2.35ns

MUX MODE

RISE TIME

2.19ns

A

= 2

= 100Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

FIGURE 19. RISE TIME - A = 2

FIGURE 20. FALL TIME - A = 2

V

MUX MODE

= 1

A

V

L

R

= 100Ω

INPUT_CH 31

OUTPUT_CH 31

SLEW RATE

-436V/µs

SLEW RATE

448V/µs

MUX MODE

A

= 1

= 100Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

FIGURE 22. FALLING SLEW RATE - A = 1

V

FIGURE 21. RISING SLEW RATE - A = 1

V

MUX MODE

A

= 2

= 100Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

SLEW RATE

-511V/µs

SLEW RATE

531V/µs

MUX MODE

A

= 2

= 100Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

FIGURE 24. FALLING SLEW RATE - A = 2

V

FIGURE 23. RISING SLEW RATE - A = 2

V

FN7432.3

July 24, 2006

9

ISL59532

Typical Performance Curves (Continued)

OUTPUT

OVERLAY

LOGIC

INPUT

OVERLAY

LOGIC

INPUT

FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME

FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME

A

= 2

= 150Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

OSC = 40mV

A

= 2

= 150Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

OSC = 40mV

FIGURE 28. DIFFERENTIAL PHASE, A = 2

V

FIGURE 27. DIFFERENTIAL GAIN, A = 2

V

A

= 2

= 150Ω

V

A

= 2

= 150Ω

V

R

L

R

L

INPUT_CH 31

OUTPUT_CH 31

OSC = 40mV

INPUT_CH 31

OUTPUT_CH 31

OSC = 40mV

FIGURE 30. DIFFERENTIAL PHASE, A = 2

V

FIGURE 29. DIFFERENTIAL GAIN, A = 2

V

FN7432.3

July 24, 2006

10

ISL59532

Typical Performance Curves (Continued)

A

= 1

= 150Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

OSC = 40mV

A

= 1

= 150Ω

V

R

L

INPUT_CH 31

OUTPUT_CH 31

OSC = 40mV

FIGURE 31. DIFFERENTIAL GAIN, A = 1

V

FIGURE 32. DIFFERENTIAL PHASE, A = 1

V

A

= 1

= 150Ω

A

R

= 1

= 150Ω

V

L

R

L

INPUT_CH 31

OUTPUT_CH 31

OSC = 40mV

INPUT_CH 31

OUTPUT_CH 31

OSC = 40mV

FIGURE 33. DIFFERENTIAL GAIN, A = 1

V

FIGURE 34. DIFFERENTIAL GAIN, A = 1

V

A

= 2

= 150Ω

A

= 2

= 150Ω

V

R

L

INPUT_CH 00

OUTPUT_CH 31

OSC = 40mV

INPUT_CH 00

OUTPUT_CH 31

OSC = 40mV

FIGURE 36. DIFFERENTIAL PHASE, A = 2

V

FIGURE 35. DIFFERENTIAL GAIN, A = 2

V

FN7432.3

July 24, 2006

11

ISL59532

Typical Performance Curves (Continued)

A

= 2

= 150Ω

V

R

L

INPUT_CH 00

OUTPUT_CH 31

OSC = 40mV

A

= 2

= 150Ω

V

R

L

INPUT_CH 00

OUTPUT_CH 31

OSC = 40mV

FIGURE 37. DIFFERENTIAL GAIN, A = 2

FIGURE 38. DIFFERENTIAL PHASE, A = 2

V

A

= 1

= 150Ω

V

R

L

INPUT_CH 00

OUTPUT_CH 31

OSC = 40mV

A

= 1

= 150Ω

V

R

L

INPUT_CH 00

OUTPUT_CH 31

OSC = 40mV

FIGURE 39. DIFFERENTIAL GAIN, A = 1

FIGURE 40. DIFFERENTIAL PHASE, A = 1

V

A

= 1

= 150Ω

A

R

= 1

= 150Ω

V

L

R

L

INPUT_CH 00

OUTPUT_CH 31

OSC = 40mV

INPUT_CH 00

OUTPUT_CH 31

OSC = 40mV

FIGURE 41. DIFFERENTIAL GAIN, A = 1

V

FIGURE 42. DIFFERENTIAL PHASE, A = 1

V

FN7432.3

July 24, 2006

12

ISL59532

Typical Performance Curves (Continued)

A

= 2

= 150Ω

V

R

L

INPUT_CH 00

OUTPUT_CH 00

OSC = 40mV

A

R

= 2

= 150Ω

V

L

INPUT_CH 00

OUTPUT_CH 00

OSC = 40mV

FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, A = 2

FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, A = 2

V

A

= 1

= 150Ω

V

R

L

INPUT_CH 00

OUTPUT_CH 00

OSC = 40mV

A

= 1

= 150Ω

V

R

L

INPUT_CH 00

OUTPUT_CH 00

OSC = 40mV

FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, A = 1

V

FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, A = 1

V

FN7432.3

July 24, 2006

13

ISL59532

Block Diagram

VS+

VOVERn OVERn

32

OVERLAY

INPUT

LOGIC

CONTROL

-

+

REF

2uA

Power-on

SWITCH

MATRIX

32 OUTPUTS

32 INPUTS

Clamp

Enable

-

+

2uA

Av

x1, x2

Output

Enable

Power-on

SDI

SCLK

SPI INTERFACE, REGISTER

SDO

SLATCH

daisy-chaining of multiple devices. The serial clock can run

at up to 5MHz (5Mbits/s).

General Description

The ISL59532 is a 32x32 integrated video crosspoint switch

matrix with input and output buffers and On-Screen Display

(OSD) insertion. This device operates from a single +5V

supply. Any output can be generated from any of the 32 input

video signal sources, and each output can have OSD

information inserted through a dedicated, fast 2:1 mux

located before the output buffer. There is also a Broadcast

mode allowing any one input to be broadcast to all 32

outputs. A DC restore clamp function enables the ISL59532

to AC-couple incoming video.

Serial Interface

The ISL59532 is programmed through a simple serial

interface. Data on the SDI (serial data input) pin is shifted

into a 16-bit shift register on the rising edge of the SCLK

(serial clock) signal. (This is continuously done regardless of

the state of the SLATCH signal.) The LSB (bit 0) is loaded

first and the MSB (bit 15) is loaded last (see the Serial

Timing Diagram). After all 16 bits of data have been loaded

into the shift register, the rising edge of SLATCH updates the

internal registers.

The ISL59532 offers a -3dB signal bandwidth of 300MHz.

Differential gain and differential phase of 0.025% and 0.05°

respectively, along with 0.1dB flatness out to 50MHz make

this ideal for multiplexing composite NTSC and PAL signals.

The switch matrix configuration and output buffer gain are

programmed through an SPI/QSPI™-compatible, three-wire

serial interface. The ISL59532 interface is designed to

facilitate both fast initialization and configuration changes.

On power-up, all outputs are initialized to the disabled state

to avoid output conflicts in the user’s system.

While the ISL59532 has an SDO (Serial Data Out) pin, it

does not have a register readback feature. The data on the

SDO pin is an exact replica of the incoming data on the SDI

pin, delayed by 15.5 SCLKs (an input bit is latched on the

rising edge of SLCK, and is output on SDO on the falling

edge of SLCK 15.5 SCLKs later). Multiple ISL59532’s can be

daisy-chained by connecting the SDO of one to the SDI of

the other, with SCLK and SLATCH common to all the daisy-

chained parts. After all the serial data is transmitted (16 bits *

n devices = 16*n SCLKs), the rising edge of SLATCH will

update the configuration registers of all n devices

simultaneously.

Digital Interface

The ISL59532 uses a serial interface to program the

configuration registers. The serial interface uses three

signals (SCLK, SDI, and SLATCH) for programming the

ISL59532, while a fourth signal (SDO) enables optional

The Serial Timing Diagram and Serial Timing Parameters

table show the timing requirements for the serial interface.

FN7432.3

July 24, 2006

18

ISL59532

Serial Timing Diagram

SLATCH

SLATCH falling edge timing/placement is a “don’t care.”

Serial data is latched only on rising edge of SLATCH.

t

SL

T

SCLK

t

HD

t

w

t

SD

B15

(MSB)

B0

(LSB)

SDI

B1

B2

B0

(LSB)

B0

B15

(previous)

B1

B2

SDO

(previous) (previous) (previous)

SDO = SDI delayed by 15.5 SCLKs to allow daisy-chaining of multiple ISL59532s. SDO changes on the falling edge of SCLK.

TABLE 1. SERIAL TIMING PARAMETERS

PARAMETER

RECOMMENDED OPERATING RANGE

DESCRIPTION

T

≥200ns

0.50 * T

≥20ns

SCLK period

t

Clock Pulse Width

Data Setup Time

Data Hold Time

W

t

SD

HD

t

≥20ns

t

≥20ns

Final SLCK rising edge (latching B15) to SLATCH rising edge

SL

Programming Model

The ISL59532 is configured by a series of 16 bit serial control words. The three MSBs (B15-13) of each serial word determine the

basic command:

TABLE 2. COMMAND FORMAT

B15

0

B14

0

B13

0

COMMAND

INPUT/OUTPUT: Maps input channels to output channels

OUTPUT ENABLE: Output enable for individual channels

GAIN SET: Gain (x1 or x2) for each channel

NUMBER OF WRITES

32 (1 channel per write)

4 (8 channels per write)

1

0

1

0

1

0

1

BROADCAST: Enables broadcast mode and selects the input channel to be

broadcast to all output channels

1

CONTROL: Clamp on/off, operational/standby mode, and global output

enable/disable

1

Mapping Inputs to Outputs

Inputs are mapped to their desired outputs using the input/output control word. Its format is:

TABLE 3. INPUT/OUTPUT WORD

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

0

I

-

O

0

4

3

2

1

0

4

3

2

1

I :I form the 5 bit word indicating the input channel (0 to 31), and O :O determine the output channel which that input channel will

4 0

4

0

map to. One input can be mapped to one or multiple outputs. To fully program the ISL59532, 32 INPUT/OUTPUT words must be

transmitted - one for each input channel.

FN7432.3

July 24, 2006

19

ISL59532

Enabling Outputs

The output enable control word is used to enable individual outputs. There are 32 channels to configure, so this is accomplished by

writing 4 serial words, each controlling a bank of eight outputs at a time. The bank is selected by bits B9 and B8. The output enable

control word format is:

TABLE 4. OUTPUT ENABLE FORMAT

B15 B14 B13 B12 B11 B10

B9

0

B8

0

B7

B6

B5

B4

B3

B2

B1

B0

0

1

0

O

7

6

5

4

3

2

1

9

0

8

0

1

O

15

23

31

14

22

30

13

21

29

12

20

28

11

19

27

10

18

26

1

0

O

17

25

16

24

1

O

Setting the O bit = 0 tristates the output. Setting the O bit = 1 enables the output if the Global Output Enable bit is also set (the

N

individual output enable bits are ANDed with the Global Output Enable bit before they are sent to the output stage).

Setting the Gain

The gain of each output may be set to x1 or x2 using the Gain Set word. It is in the same format as the output enable control word:

TABLE 5. GAIN SET FORMAT

B15 B14 B13 B12 B11 B10

B9

0

B8

0

B7

B6

B5

B4

B3

B2

B1

B0

0

1

0

G

7

6

5

4

3

2

1

9

0

1

G

15

23

31

14

22

30

13

21

29

12

20

28

11

19

27

10

18

26

8

1

0

G

17

25

16

24

1

Set G = 0 for a gain of x1 or 1 for a gain of x2.

N

Broadcast Mode

The Broadcast Mode routes one input to all 32 outputs. The broadcast control word is:

TABLE 6. BROADCAST FORMAT

B15 B14 B13 B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Enable Broadcast

0

1

I

0

4

3

2

1

0: Broadcast Mode Disabled

1: Broadcast Mode Enabled

I :I form the 5 bit word indicating the input channel (0 to 31) to be sent to all 32 outputs. Set the Enable Broadcast bit (B0) = 1 to

4 0

enable Broadcast Mode, or to 0 to disable Broadcast Mode. When Broadcast Mode is disabled, the previous channel assignments

are restored.

Control Word

The ISL59532’s power-on reset disables all outputs and places the part in a low-power standby mode. To enable the device, the

following control word should be sent:

TABLE 7. CONTROL WORD FORMAT

B15 B14 B13 B12 B11 B10

B9

B8 B7 B6 B5 B4 B3 B2

B1

B0

1

0

Clamp

0

Power

Global Output Enable

0: Clamp Disabled

1: Clamp Enabled

0: Standby

0: All outputs tristated

1: Operational 1: Individual Output Enable bits control outputs

The Clamp bit enables the input clamp function, forcing the AC-coupled signal’s most negative point to be equal to V

.

REF

Note: The Clamp bit turns the DC-Restore clamp function on or off for all channels - there is no DC-Restore on/off control for

individual channels. The DC-Restore function only works with signals with sync tips (composite video). Signals that do not have

sync tips (the Chroma/C signal in s-video and the Pb, Pr signals in Component video), will be severely distorted if run through a

DC-Restore/clamp function.

FN7432.3

July 24, 2006

20

ISL59532

For this reason, the ISL59532 must be in DC-coupled

mode (Clamp Disabled) to be compatible with s-video

and component video signals.

Linear Operating Region

In addition to bandwidth optimization, to get the best linearity

the ISL59532 should be configured to operate in its most

linear operating region. Figure 48 shows the differential gain

curve. The ISL59532 is a single supply 5V design with its

most linear region between 0.1 and 2V. This range is fine for

most video signals whose nominal signal amplitude is 1V.

The most negative input level (the sync tip for composite

video) should be maintained at 0.3V or above for best

operation.

Bandwidth Considerations

Wide frequency response (high bandwidth) in a video

system means better video resolution. Four sets of

frequency response curves are shown in Figure 47.

Depending on the switch configurations, and the routing (the

path from the input to the output), bandwidth can vary

between 100MHz and 350MHz. A short discussion of the

trade-offs — including matrix configuration, output buffer

gain selection, channel selection, and loading — follows.

2

Mux, Av = 2

0

Mux, Av = 1

Broadcast,

-2

Av = 2

Broadcast,

Av = 1

-4

-6

-8

-10

1

10

100

1000

FIGURE 48. DIFFERENTIAL GAIN RESPONSE

Frequency [MHz]

In a DC-coupled application, it is the system designer’s

responsibility to ensure that the video signal is always in the

optimum range.

FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES

In multiplexer mode, one input typically drives one output

channel, while in broadcast mode, one input drives all 32

outputs. As the number of outputs driven increases, the

parasitic loading on that input increases. Broadcast Mode is

the worst-case, where the capacitance of all 32 channels

loads one input, reducing the overall bandwidth. In addition,

due to internal device compensation, an output buffer gain of

x2 has higher bandwidth than a gain of x1. Therefore, the

highest bandwidth configuration is multiplexer mode (with

each input mapped to only one output) and an output buffer

gain of x2.

When AC coupling, the ISL59532’s DC restore function

automatically adjusts the DC level so that the most negative

portion of the video is always equal to V

.

REF

A discussion of the benefits of the DC-restored system

begins by understanding the block diagram of a typical

DC-restore circuit (Figure 49). It consists of 4 sections: an

AC coupling (DC blocking) capacitor at the input, an opamp,

a FET switch, and a current source. In the absence of an

input signal, R

pulls the input node to ground. The 2µA

TERM

current source slowly drains the input capacitor of charge,

slowly lowering V . However when V goes below

OUT

The relative locations of the input and output channels also

have significant impact on the device bandwidth (due to the

layout of the ISL59530 silicon). When the input and output

channels are further away, there are additional parasitics as

a result of the additional routing, resulting in lower

bandwidth.

V

, Q1 turns on, sourcing current into the capacitor until

REF

is equal to V

, at which point Q1 will turn off. So

OUT

REF

with no V signal, the voltage at the noninverting input of

IN

the opamp will settle to approximately V

, with Q1

REF

sourcing the same 2µA as the current source.

The bandwidth does not change significantly with resistive

loading as shown in the typical performance curves.

However several of the curves demonstrate that frequency

response is sensitive to capacitance loading. This is most

significant when laying out the PCB. If the PCB trace length

between the output of the crosspoint switch and the back-

termination resistor is not minimized, the additional parasitic

capacitance will result in some peaking and eventually a

reduction in overall bandwidth.

FN7432.3

July 24, 2006

21

ISL59532

delivering acceptable droop and C = 0.001µF producing

IN

excessive droop

V_S

When the clamp function is disabled in the CONTROL

register (Clamp = 0) to allow DC-coupled operation, the

-

+

V_REF

Q1

I

current sinks/sources are disabled and the input

CLAMP

passes through the DC Restore block unaffected. In this

application V may be tied to GND.

REF

V_IN

R_TERM

V_OUT

2uA

Overlay Operation

C_IN

The ISL59532 features an overlay feature, that allows an

external video signal or DC level to be inserted in place of

that output channel’s video. When the OVER signal is

N

taken high, the output signal on the OUT pin is replaced

with the signal on the VOVER pin.

N

FIGURE 49. DC RESTORE BLOCK DIAGRAM

When a video signal is applied to V , the most negative

IN

There are several ways the overlay feature can be used.

signal will be the sync tip. If the sync tip goes below V

Q1 will turn on and quickly source enough current into C

,

Toggling the OVER signal at the frame rate or slower will

replace the video frame(s) on the OUT pin with the video

N

REF

N

IN

so that the sync tip is forced to be equal to V

. After the

supplied on the VOVER pin.

REF

N

sync tip, the video jumps up by 300mV or more, so V

OUT

Another option (for OSD displays, for example), is to put a

becomes >> V

, so Q1 will not turn on for the rest of the

REF

DC level on the VOVER line and toggle the OVER signal

N

video line. However the 2µA current source continues to

slowly discharge C , so that by the end of the video line, the

at the pixel rate to create a monocolor image “overlaid” on

channel N’s output signal.

IN

next sync tip will again be slightly below V

, forcing Q1 to

REF

source some current into C1 to make V

the sync tip.

= V

REF

during

Finally, by enabling the OVER signal for some portion of

N

each line over a certain amount of lines, a picture-in-picture

OUT

function can be constructed.

This is how the video is “DC-restored” after being AC

coupled into the ISL59532. The sync tip voltage will be equal

It’s important to note that the overlay inputs do not have the

DC Restore function previously described - the overlay

signal is DC coupled into the output. It is the system

designer’s responsibility to ensure that the video levels are

in the ISL59532’s linear region and matching the output

channel’s offset and amplitude. One easy way to do this is to

run the video to be overlaid through one of the ISL59532’s

to V

, on the right side of C , regardless of the DC level

REF

IN

of the video on the left side of C . Due to various sources of

IN

offset in the actual clamp function, the actual sync tip level is

typically about 75mV higher than V

REF

(for V = 0.5V).

REF

unused channels and then into the VOVER input.

N

The OVER pins all have weak pulldowns, so if they are

N

unused, they can either be left unconnected or tied to GND.

Power Dissipation and Thermal Resistance

With a large number of switches, it is possible to exceed the

150°C absolute maximum junction temperature under

certain load current conditions. Therefore, it is important to

calculate the maximum junction temperature for an

application to determine if load conditions or package types

need to be modified to assure operation of the crosspoint

switch in a safe operating area.

FIGURE 50. DC RESTORE VIDEO WAVEFORMS

The maximum power dissipation allowed in a package is

determined according to:

It is important to choose the correct value for C . Too small

IN

a value will generate too much droop, and the image will be

T

– T

AMAX

visibly darker on the right than on the left. A C value that is

too large may cause the clamp to fail to converge. The droop

JMAX

IN

PD

= --------------------------------------------

MAX

Θ

JA

rate (dV/dt) is i

/C volts/second. In general, the

PULLDOWN IN

droop voltage should be limited to <1 IRE over a period of

one line of video; so for 1 IRE = 7mV, I = 10µA maximum,

B

and an NTSC waveform we will set C > 10µA*60µs/7mV =

IN

0.086µF. Figure 50 shows the result of C = 0.1µF

IN

FN7432.3

July 24, 2006

22

ISL59532

Where:

• T

= Maximum junction temperature = 125°C

= Maximum ambient temperature = 85°C

JMAX

AMAX

• θ = Thermal resistance of the package

JA

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the load, or:

n

V

OUTi

R

Li

-----------------

PD

= V × I

+

(V – V ) ×

OUTi

MAX

S

SMAX

S

∑

i = 1

Where:

• V = Supply voltage = 5V

S

• I

SMAX

= Maximum quiescent supply current = 700mA

= Maximum output voltage of the application = 2V

• V

• R

OUT

= Load resistance tied to ground = 150

LOAD

• n = 1 to 32 channels

n

V

OUTi

R

Li

-----------------

= 4.8W

PD

= V × I

+

(V – V ) ×

OUTi

MAX

S

SMAX

S

∑

i = 1

The required θ to dissipate 4.8W is:

JA

T

– T

AMAX

JMAX

--------------------------------------------

= 8.33(°C/W)

Θ

=

JA

PD

MAX

Table 8 shows θ thermal resistance results with a

JA

Wakefield heatsink and without heatsink and various airflow.

At the thermal resistance equation shows, the required

thermal resistance depends on the maximum ambient

temperature.

TABLE 8. θ THERMAL RESISTANCE [°C/W]

JA

Airflow [LFM]

0

250

14.3

7.0

500

13.0

6.0

750

12.6

4.7

No Heatsink

18

Wakefield

658-25AB

Heatsink

16.0

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7432.3

July 24, 2006

23


型号：	ISL59532
厂家：	Intersil
描述：	32x32 Video Crosspoint 32×32视频交叉点
文件：	总24页 (文件大小：1305K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL59532 [INTERSIL]

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