ISL6115 [INTERSIL]
Power Distribution Controllers; 配电控制器
| 型号： | ISL6115 |
| 厂家： | 
Intersil |
| 描述： | Power Distribution Controllers |
| 文件： | 总12页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6115, ISL6116, ISL6117, ISL6120
®
Data Sheet
March 2004
FN9100.1
Power Distribution Controllers
Features
• HOT SWAP Single Power Distribution Control (ISL6115
for +12V, ISL6116 for +5V, ISL6117 for +3.3V and ISL6120
for +2.5V)
This family of fully featured hot swap power controllers
targets applications in the +2.5V to +12V range. The
ISL6115 is for +12V control, the ISL6116 for +5V, the
ISL6117 for +3.3V and the ISL6120 for +2.5V control
applications. Each has a hard wired undervoltage (UV)
monitoring and reporting threshold level approximately 80%
of the aforementioned voltage.
• Overcurrent Fault Isolation
• Programmable Current Regulation Level
• Programmable Current Regulation Time to Latch-Off
• Rail to Rail Common Mode Input Voltage Range (ISL6115)
The ISL6115 has an integrated charge pump allowing
control of up to +16V rails using an external N-Channel
MOSFET whereas the other devices utilize the +12V bias
voltage to fully enhance the N-channel pass FET. All ICs
feature programmable overcurrent (OC) detection, current
regulation (CR) with time delay to latch off and soft start.
• Internal Charge Pump Allows the use of N-Channel
MOSFET for +12V control (ISL6115)
• Undervoltage and Overcurrent Latch Indicators
• Adjustable Turn-On Ramp
• Protection During Turn On
The current regulation level is set by 2 external resistors;
ISET
R
sets the CR Vth and the other is a low ohmic sense
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
element across which the CR Vth is developed. The CR
duration is set by an external capacitor on the CTIM pin
which is charged with a 20µA current once the CR Vth level
is reached. If the voltage on the CTIM cap reaches 1.9V the
IC then quickly pulls down the GATE output latching off the
pass FET.
• 1µs Response Time to Dead Short
• Pb-Free Packages Available
• Tape & Reel Packing with ‘-T’ Part Number Suffix
Applications
• Power Distribution Control
This family although designed for high side switch control
the ISL6116, ISL6117, ISL6120 can also be used in a low
side configuration for control of much higher voltage
potentials.
• Hot Plug Components and Circuitry
Pinout
Ordering Information
ISL6115, ISL6116, ISL6117, ISL6120 (SOIC)
TEMP.
PKG.
TOP VIEW
PART NUMBER
ISL6115CB
RANGE (°C)
PACKAGE
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
DWG. #
0 to 85
0 to 85
0 to 85
0 to 85
0 to 85
M8.15
M8.15
M8.15
M8.15
M8.15
ISET
ISEN
GATE
VSS
1
2
3
4
8
7
6
5
PWRON
PGOOD
CTIM
ISL6116CB
ISL6117CB
ISL6120CB
VDD
ISL6115CBZA
(Note)
8 Lead SOIC
(Pb-free)
ISL6116CBZA
(Note)
0 to 85
0 to 85
0 to 85
8 Lead SOIC
(Pb-free)
M8.15
M8.15
M8.15
ISL6117CBZA
(Note)
8 Lead SOIC
(Pb-free)
ISL6120CBZA
8 Lead SOIC
(Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6115, ISL6116, ISL6117, ISL6120
Application One - High Side Controller Application Two - Low Side Controller
+VBUS
LOAD
+
-
LOAD
1
2
3
4
8
7
6
5
PWRON
PGOOD
ISL6115
ISL6116
ISL6117
ISL6120
OC
ISL6116/7/20
PWRON
12V REG
+12V
OC
+V supply to be controlled
2
ISL6115, ISL6116, ISL6117, ISL6120
Simplified Block Diagram
V
DD
+
-
POR
+
R
R
S
QN
Q
8V
PWRON
I
SET
SEN
-
UV
-
+
+
-
V
REF
ENABLE
12V
I
PGOOD
CTIM
ISL611X
20µA
UV DISABLE
CLIM
OC
+
-
7.5K
GATE
+
-
FALLING
EDGE
-
+
10µA
+
-
DELAY
1.86V
WOCLIM
18V
ENABLE
20µA
RISING
EDGE
PULSE
V
V
SS
DD
18V
Pin Descriptions
PIN #
SYMBOL
FUNCTION
DESCRIPTION
1
ISET
Current Set
Connect to the low side of the current sense resistor through the current limiting set resistor. This
pin functions as the current limit programming pin.
2
3
ISEN
Current Sense
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor.
GATE
External FET Gate Drive
Pin
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground
sets the turn-on ramp. At turn-on this capacitor will be charged to V
DD
+5V (ISL6115) and to
DD
V
(ISL6116, ISL6117, ISL6120) by a 10µA current source.
4
5
VSS
Chip Return
Chip Supply
V
12V chip supply. This can be either connected directly to the +12V rail supplying the switched
load voltage or to a dedicated V +12V supply.
SS
DD
6
7
8
CTIM
Current Limit Timing
Capacitor
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The duration
of current limit time-out is equal to 93kΩ x C
TIM
.
PGOOD
PWRON
Power Good Indicator
Power ON
Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain
N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV
level for the particular IC.
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven
high or is open. After a current limit time out, the chip is reset by a low level signal applied to
this pin. This input has 20µA pull up capability.
3
ISL6115, ISL6116, ISL6117, ISL6120
Absolute Maximum Ratings T = 25°C
Thermal Information
Thermal Resistance (Typical, Note 1)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
A
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V
θ
(°C/W)
98
DD
JA
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +8V
DD
ISEN, PGOOD, PWRON, CTIM, ISET. . . . . . . -0.3V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5kV
+ 0.3V
DD
Operating Conditions
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . +12V ±15%
DD
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379.1 for
JA
details.)
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER
V
= 12V, T = T = 0°C to 85°C, Unless Otherwise Specified
DD
A
J
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
CURRENT CONTROL
ISET Current Source
I
18.5
19
-6
20
20
0
21.5
21
6
µA
µA
ISET_ft
ISET Current Source
I
T = 15°C to 55°C
J
ISET_pt
Vio_ft
Current Limit Amp Offset Voltage
Current Limit Amp Offset Voltage
GATE DRIVE
V
- V
- V
mV
mV
ISET
ISET
ISEN
Vio_pt
V
T = 15°C to 55°C
-2
0
2
ISEN,
J
GATE Response Time To Severe OC
GATE Response Time to Overcurrent
GATE Turn-On Current
pd_woc_amp
pd_oc_amp
V
V
V
to 10.8V
to 10.8V
to = 6V
-
100
600
10
-
-
ns
ns
µA
mA
A
GATE
GATE
GATE
-
I
8.4
45
0.5
9.2
11.6
GATE
OC_GATE_I_4V
WOC_GATE_I_4V Severe Overcurrent
12V
GATE Pull Down Current
Overcurrent
75
GATE Pull Down Current
0.8
9.6
1.5
10
-
ISL6115 Undervoltage Threshold
ISL6115 GATE High Voltage
ISL6116 Undervoltage Threshold
ISL6117 Undervoltage Threshold
ISL6120 Undervoltage Threshold
ISL6116, 17, 20 GATE High Voltage
BIAS
V
UV_VTH
12VG
GATE Voltage
V
+4.5V
DD
V
+5V
V
DD
5V
4.0
2.4
1.8
4.35
4.5
2.8
1.9
-
V
UV_VTH
UV_VTH
3V
2V
2.6
V
1.85
V
UV_VTH
VG
GATE Voltage
V
-1.5V
DD
V
V
DD
V
V
V
V
Supply Current
I
-
3
5
9
mA
V
DD
DD
DD
DD
VDD
POR Rising Threshold
POR Falling Threshold
POR Threshold Hysteresis
V
V
VDD Low to High
VDD High to Low
7.8
7.5
0.1
2.7
1.4
130
9
8.4
8.1
0.3
3.2
1.7
170
17
DD_POR_L2H
DD_POR_H2L
8.7
0.6
-
V
V
V
V
V
DD_POR_HYS
PWRN_V
DD_POR_L2H - DD_POR_H2L
PWRON Pin Open
PWRON Pull-Up Voltage
PWRON Rising Threshold
PWRON Hysteresis
V
PWR_Vth
PWR_hys
PWRN_I
2.0
250
25
V
mV
µA
PWRON Pull-Up Current
CURRENT REGULATION DURATION
C
C
Charging Current
C
_ichg0
V = 0V
CTIM
16
16
20
20
23
23
µA
mA
V
TIM
TIM
Fault Pull-Up Current
TIM
Current Limit Time-Out Threshold Voltage
C
_Vth
CTIM Voltage
1.3
1.8
2.3
TIM
4
ISL6115, ISL6116, ISL6117, ISL6120
is the case then the N-Channel MOSFET is fully enhanced
and the C capacitor is discharged. Once CTIM charges to
1.87V, signaling that the time out period has expired an
internal latch is set whereby the FET gate is quickly pulled to
0V turning off the N-Channel MOSFET switch, isolating the
faulty load.
Description and Operation
TIM
The members of this family are single power supply
distribution controllers for generic hot swap applications
across the +2.5V to +12V supply range. The ISL6115 is
targeted for +12V switching applications whereas the
ISL6116 is targeted for +5V, the ISL6117 for +3.3V and the
ISL6120 for +2.5V applications. Each IC has a hardwired
undervoltage (UV) threshold level approximately 17% lower
than the stated voltages.
TABLE 1.
R
RESISTOR
10kΩ
NOMINAL OC VTH
200mV
ISET
4.99kΩ
2.5kΩ
750Ω
100mV
50mV
15mV
These ICs feature a highly accurate programmable
overcurrent (OC) detecting comparator, programmable
current regulation (CR) with programmable time delay to
latch off, and programmable soft start turn-on ramp all set
with a minimum of external passive components. The ICs
also include severe OC protection that immediately shuts
down the MOSFET switch should a rapid load current
transient such as a near dead short cause the CR Vth to
exceed the programmed level by 150mV. Additionally, the
ICs have a UV indicator and an OC latch indicator. The
functionality of the PGOOD feature is enabled once the IC is
biased, monitoring and reporting any UV condition on the
ISEN pin.
NOTE: Nominal Vth = R
x 20µA.
ISET
TABLE 2.
C
CAPACITOR
0.022µF
0.047µF
0.1µF
NOMINAL CURRENT LIMITED PERIOD
TIM
2ms
4.4ms
9.3ms
NOTE: Nominal time-out period = C
x 93kΩ.
TIM
This IC responds to a severe overcurrent load (defined as a
voltage across the sense resistor >150mV over the OC Vth set
point) by immediately driving the N-Channel MOSFET gate to
0V in about 10µs. The gate voltage is then slowly ramped up
turning on the N-Channel MOSFET to the programmed current
regulation level; this is the start of the time out period.
Upon initial power up, the IC can either isolate the voltage
supply from the load by holding the external N-Channel
MOSFET switch off or apply the supply rail voltage directly to
the load for true hot swap capability. The PWRON pin must
be pulled low for the device to isolate the power supply from
the load by holding the external N-channel MOSFET off.
With the PWRON pin held high or floating the IC will be in
true hot swap mode. In both cases the IC turns on in a soft
start mode protecting the supply rail from sudden in-rush
current.
Upon a UV condition the PGOOD signal will pull low when
tied high through a resistor to the logic or VDD supply. This
pin is a UV fault indicator. For an OC latch off indication,
monitor CTIM, pin 6. This pin will rise rapidly from 1.9V to
VDD once the time out period expires.
See Figures 12 to 16 for waveforms relevant to text.
At turn-on, the external gate capacitor of the N-Channel
MOSFET is charged with a 10µA current source resulting in
a programmable ramp (soft start turn-on). The internal
ISL6115 charge pump supplies the gate drive for the 12V
The IC is reset after an OC latch-off condition by a low level
on the PWRON pin and is turned on by the PWRON pin
being driven high.
supply switch driving that gate to ~V +5V, for the other
DD
Application Considerations
three ICs the gate drive voltage is limited to the chip bias
voltage, VDD.
During the soft start and the time-out delay duration with the
IC in its current limit mode, the V
of the external N-Channel
GS
Load current passes through the external current sense
resistor. When the voltage across the sense resistor exceeds
the user programmed CR voltage threshold value, (see Table 1
MOSFET is reduced driving the MOSFET switch into a (linear
region) high r state. Strike a balance between the CR
DS(ON)
limit and the timing requirements to avoid periods when the
external N-Channel MOSFETs may be damaged or destroyed
due to excessive internal power dissipation. Refer to the
MOSFET SOA information in the manufacturer’s data sheet.
for R
programming resistor value and resulting nominal
ISET
current regulation threshold voltage, V ) the controller enters
CR
its current regulation mode. At this time, the time-out capacitor,
on C
pin is charged with a 20µA current source and the
TIM
controller enters the current limit time to latch-off period. The
length of the current limit time to latch-off duration is set by the
value of a single external capacitor (see Table 2 for CTIM
capacitor value and resulting nominal current limited time out
to latch-off duration) placed from the CTIM pin (pin 6) to
ground. The programmed current level is held until either the
OC event passes or the time out period expires. If the former
When driving particularly large capacitive loads a longer soft
start time to prevent current regulation upon charging and a
short CR time may offer the best application solution relative
to reliability and FET MTF.
Physical layout of R
SENSE
resistor is critical to avoid the
possibility of false overcurrent occurrences. Ideally, trace
routing between the R resistors and the IC is as direct
SENSE
5
ISL6115, ISL6116, ISL6117, ISL6120
and as short as possible with zero current in the sense lines.
Biasing the ISL6116
(See Figure 1.)
Table 3 gives typical component values for biasing the
ISL6116 in a ±48V application. The formulas and
calculations deriving these values are also shown below.
CORRECT
INCORRECT
TABLE 3. TYPICAL VALUES FOR A -48V HOT SWAP
APPLICATION
SYMBOL
PARAMETER
TO ISEN AND
R
1.58kΩ, 1W
12V Zener Diode, 50mA Reverse Current
CL
R
ISET
DD1
CURRENT
SENSE RESISTOR
When using the ISL6116 to control -48V, a Zener diode may
be used to provide the +12V bias to the chip. If a Zener is
used then a current limit resistor should also be used.
Several items must be taken into account when choosing
values for the current limit resistor (R ) and Zener Diode
FIGURE 1. SENSE RESISTOR PCB LAYOUT
CL
(DD1):
Using the ISL6116 as a -48V Low Side Hot
Swap Power Controller
• The variation of the V
(in this case, -48V nominal)
BUS
• The chip supply current needs for all functional conditions
• The power rating of R
To supply the required V , it is necessary to maintain the
DD
.
CL
chip supply 10 to 16V above the -48V bus. This may be
accomplished with a suitable regulator between the voltage
rail and pin 5 (VDD). By using a regulator, the designer may
ignore the bus voltage variations. However, a low-cost
alternative is to use a Zener diode (See Figure 2 for typical
5A load control); this option is detailed below.
• The current rating of DD1
Formulas
1. Sizing R
:
CL
= (V
R
- 12)/I
CHIP
CL
BUS,MIN
2. Power Rating of R
:
CL
Note that in this configuration the PGOOD feature (pin 7) is
P
= I (V - 12)
RCL
C
BUS,MAX
not operational as the I
threshold.
pin voltage is always < UV
SEN
3. DD1 Current Rating:
I
= (V - 12)/R
DD1
Example
A typical -48V supply may vary from -36 to -72V. Therefore,
BUS,MAX CL
See Figures 17 to 20 for waveforms relevant to -48V and
other high voltage applications.
V
V
= -72V
= -36V
BUS,MAX
BUS,MIN
0.005
1%
LOAD
I
= 15mA (max)
CHIP
0.001µF
1.47kΩ
1%
Sizing R
:
CL
= (V
2kΩ
R
R
R
- 12)/I
C
CL
CL
CL
BUS,MIN
= (36 - 12)/0.015
= 1.6kΩ [Typical Value = 1.58kΩ]
R
CL
1.58kΩ
1W
Power Rating of R
:
CL
0.01µF
P
P
P
= I (V
- 12)
ISL6116
RCL
RCL
RCL
C
BUS,MAX
= (0.015)(72 - 12)
= 0.9W [Typical Value = 1W]
DD1 Current Rating:
NC
I
I
I
= ( - 12)/R
DD1
DD1
DD1
VBUS,MAX CL
= (72 - 12)/1.58kΩ
= 38mA [Typical Value = 12V rating, 50mA reverse
0.047µF
12V
DD1
PWRON
current]
V
-48V
BUS
FIGURE 2.
6
ISL6115, ISL6116, ISL6117, ISL6120
Typical Performance Curves
5.0
20.2
20.0
4.5
19.8
19.6
4.0
3.5
3.0
19.4
19.2
19.0
2.5
2.0
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. VDD BIAS CURRENT
FIGURE 4. ISET SOURCE CURRENT
1.89
1.88
20.5
20.32
C
- 0V
TIM
1.87
1.86
20.16
20.0
1.85
1.84
1.83
19.82
19.66
19.5
0
10
20
30
40
50
60
70
80
90 100
0
10 20 30 40
50 60
70 80
90 100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. C
CURRENT SOURCE
FIGURE 6. C
OC VOLTAGE THRESHOLD
TIM
TIM
9.76
9.75
2.70
2.65
4.37
1.860
ISL6117
ISL6116
ISL6115
4.36
4.35
1.855
1.850
ISL6120
9.74
0
2.60
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
FIGURE 7. ISL6115/6116 UV THRESHOLD
FIGURE 8. ISL6117/6120 UV THRESHOLD
7
ISL6115, ISL6116, ISL6117, ISL6120
Typical Performance Curves (Continued)
12.00
11.99
17.200
17.183
10.2
10.1
17.166
17.150
17.133
17.116
10.0
9.9
11.98
11.97
11.96
11.95
11.94
9.8
9.7
9.6
17.100
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
0
10
20
30
40
50
60
70
80
90 100
TEMPERATURE (°C)
FIGURE 9. GATE CHARGE CURRENT
FIGURE 10. GATE DRIVE VOLTAGE, VDD = 12V
8.5
8.4
8.3
8.2
8.1
8.0
VDD LO TO HI
GATE
VOUT
PGOOD
IOUT
VDD HI TO LO
PWRON
0
10
20
30
40
50
60
70
80
90 100
TEMPERATURE (°C)
5V/DIV. 0.5A/DIV 1ms/DIV
FIGURE 11. POWER ON RESET VOLTAGE THRESHOLD
FIGURE 12. ISL6115 +12V TURN-ON
GATE
PGOOD
IOUT
GATE
PWRON
VOUT
VOUT
IOUT
PGOOD
CTIM
2V/DIV 0.5A/DIV 1ms/DIV
5V/DIV 0.5A/DIV 1ms/DIV
FIGURE 13. ISL6116 +5V TURN-ON
FIGURE 14. ISL6115 ‘LOW’ OVERCURRENT RESPONSE
8
ISL6115, ISL6116, ISL6117, ISL6120
Typical Performance Curves (Continued)
IOUT
IOUT
GATE
VOUT
CTIM
PGOOD
VOUT
GATE
CTIM
PGOOD
5V/DIV 0.5A/DIV 1ms/DIV
2V/DIV 0.5A/DIV 1ms/DIV
FIGURE 15. ISL6115 ‘HIGH’ OVERCURRENT RESPONSE
FIGURE 16. ISL6116 ‘HIGH’ OVERCURRENT RESPONSE
VDRAIN 10V/DIV.
0V
IOUT 1A/DIV.
VDRAIN 10V/DIV.
+50V
IOUT 1A/DIV.
VGATE 5V/DIV.
VGATE 5V/DIV.
PWRON 5V/DIV.
0V
EN 5V/DIV.
-50V
0V
0V
5ms/DIV
5ms/DIV
FIGURE 17. +50V LOW SIDE SWITCHING CGATE = 100pF
FIGURE 18. -50V LOW SIDE SWITCHING CGATE = 1000pF
+350V
+350V
IOUT 1A/DIV
VDRAIN 50V/DIV
IOUT 1A/DIV
VDRAIN 50V/DIV
VGATE 5V/DIV
PWRON 5V/DIV
VGATE 5V/DIV.
PWRON 5V/DIV
0V
0V
2ms/DIV
2ms/DIV
FIGURE 19. +350V LOW SIDE SWITCHING CGATE = 100pF
FIGURE 20. +350V LOW SIDE SWITCHING CGATE = 1000pF
9
ISL6115, ISL6116, ISL6117, ISL6120
Bias and load connection points are provided in addition to
ISL6115EVAL1 Board
test points, TP1-8 for each IC pin. The terminals, J1 and J4
are for the bus voltage and return, respectively, with the
more negative potential being connected to J4. With the load
between terminals J2 and J3 the board is now configured for
evaluation. The device is enabled through LOGIN, TP9 with
a TTL signal. ISL6116EVAL1 includes a level shifting circuit
with an opto-coupling device for the PWRON input so that
standard TTL logic can be translated to the -V reference for
chip control.
The ISL6115EVAL1 is configured as a +12V high side switch
controller with the CR level set at ~1.5A. (See Figure 21 for
ISL6115EVAL1 schematic and Table 4. for BOM.) Bias and
load connection points are provided along with test points for
each IC pin.
With the chip to be biased from the +12V bus being
switched, through B2, GND B5, the load connected between
B3 and B4 and with jumper J1 installed the ISL6115 can be
evaluated. PWRON pin pulls high enabling the ISL6115 if not
driven low.
When controlling a positive voltage, PWRON can be
accessed at TP8.
With R2 = 750Ω the CR Vth is set to 15mV and with the
10mΩ sense resistor the ISL6115EVAL1 has a nominal CR
level of 1.5A. The 0.047µF delay time to latch-off capacitors
results in a nominal 4.4ms before latch-off of outputs after an
OC event.
The ISL6116EVAL1 is provided with a high voltage linear
regulator for convenience to provide chip bias from ±24V to
±350V. This can be removed and replaced with the zener &
resistor bias scheme as discussed earlier. High voltage
regulators and power discrete devices are no longer
available from Intersil but can be purchased from other
semiconductor manufacturers.
Also included with the ISL6115EVAL1 board are one each of
the ISL6116, ISL6117 and ISL6120 for evaluation.
Reconfiguring the ISL6116EVAL1 board for a higher CR
ISL6116EVAL1 Board
level can be done by changing the R
and R
SENSE
ISET
The ISL6116EVAL1 is default configured as a negative
voltage low side switch controller with a ~2.4A CR level.
(See Figure 22 for ISL6116EVAL1 schematic and Table 4 for
BOM and component description.) This basic configuration
is capable of controlling both larger positive or negative
potential voltages with minimal changes.
resistor values as the provided FET is 75A rated. If
evaluation at >60V, an alternate FET must be chosen with
an adequate BV
.
DSS
HI J2
LOAD
C1
J3 LO
Q2
R1
R2
J4
-VBUS
J1
+VBUS
R7
+
-
B3
LOAD
B4
R2
PWRON
TP8
1
2
3
4
8
PWRON
R5
ISL6116
U1
R1
Q1
7
6
5
C3
ISL6115
U1
DD1
3.3V
D1
LOGIN
TP9
R
G
1
C2
D2
R3
C1
R4
C3
R10
R8
R6
R5
B5
DD1
3.3V
R9
R11
OFF
0-5V
JP1
+12V
D2
B1
V
V+ B2
BIAS
ON
OT1
FIGURE 21. ISL6115EVAL1 HIGH SIDE SWITCH APPLICATION
FIGURE 22. ISL6116EVAL1 NEGATIVE VOLTAGE LOW SIDE
CONTROLLER
10
ISL6115, ISL6116, ISL6117, ISL6120
TABLE 4. BILL OF MATERIALS, ISL6115EVAL1, ISL6116EVAL1
COMPONENT
DESIGNATOR
COMPONENT NAME
HUF76132SK8
COMPONENT DESCRIPTION
Q1
Q2
R1
11.5mΩ, 30V, 11.5A Logic Level N-Channel Power MOSFET or equiv.
10mΩ, 80V, 75A N-Channel Power MOSFET or equiv.
Dale, WSL-2512 10mΩ 1W Metal Strip Resistor
750Ω 805 Chip Resistor (Vth = 15mV)
1.21kΩ 805 Chip Resistor (Vth = 24mV)
0.047µF 805 Chip Capacitor (4.5ms)
0.001µF 805 Chip Capacitor (<2ms)
0.1µF 805 Chip Capacitor
HUF7554S3S
Load Current Sense Resistor
High Side R2 Overcurrent Voltage Threshold Set Resistor
Low side R2 Overcurrent Voltage Threshold Set Resistor
C2
C1
C3
R3
R7
JP1
Time Delay Set Capacitor
Gate Timing Capacitor
IC Decoupling Capacitor
Gate Stability Resistor
20Ω 805 Chip Resistor
Gate to Drain Resistor
2kΩ 805 Chip Resistor
Bias Voltage Selection Jumper
Install if switched rail voltage is = +12V ±15%. Remove and provide separate
+12V bias voltage to U1 via TP5 if ISL6116, ISL6117, ISL6120 being
evaluated.
R4, R5
D1, D2
DD1
OT1
LED Series Resistors
2.32kΩ 805 Chip Resistor
Low Current Red SMD LED
3.3V Zener Diode, SOT-23 SMD 350mW
PS2801-1 NEC
Fault Indicating LEDs
Fault Voltage Dropping Diode
PWRON Level Shifting Opto-Coupler
Level Shifting Bias Resistor
Level Shifting Bias Resistor
Level Shifting Bias Resistor
HIP5600IS
R8
2.32kΩ 805 Chip Resistor
1.18kΩ 805 Chip Resistor
200Ω 805 Chip Resistor
R9
R10
RG1
R6
High Voltage Linear Regulator
1.78kΩ 805 Chip Resistor
15kΩ 805 Chip Resistor
Linear Regulator RF1
R11
Linear Regulator RF2
TP1-TP8
Test Points for Device Pin Numbers 1-8
11
ISL6115, ISL6116, ISL6117, ISL6120
Small Outline Plas tic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INDEX
0.25(0.010)
M
L
B M
H
AREA
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
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