ISL6146BFUZ-T7A [INTERSIL]
Low Voltage OR-ing FET Controller; 低电压的OR-ing FET控制器
| 型号： | ISL6146BFUZ-T7A |
| 厂家： | 
Intersil |
| 描述： | Low Voltage OR-ing FET Controller |
| 文件： | 总28页 (文件大小：1113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage OR-ing FET Controller
ISL6146
Features
The ISL6146 represents a family of OR-ing MOSFET controllers
capable of OR-ing voltages from 1V to 18V. Together with suitably
sized N-channel power MOSFETs, the ISL6146 increases power
distribution efficiency when replacing a power OR-ing diode in high
current applications. It provides gate drive voltage for the
MOSFET(s) with a fully integrated charge pump.
• OR-ing Down to 1V and Up to 20V with ISL6146A, ISL6146B,
ISL6146D and ISL6146E
• Programmable Voltage Compliant Operation with ISL6146C
• VIN Hot Swap Transient Protection Rating to +24V
• High Speed Comparator Provides Fast <0.3µs Turn-off in
Response to Shorts on Sourcing Supply
The ISL6146 allows users to adjust with external resistor(s) the
V
- V trip point, which adjusts the control sensitivity to system
OUT IN
• Fastest Reverse Current Fault Isolation with 6A Turn-off
Current
power supply noise. An open drain FAULT pin will indicate if a
conditional or FET fault has occurred.
• Very Smooth Switching Transition
The ISL6146A and ISL6146B are optimized for very low voltage
operation, down to 1V with an additional independent bias of 3V
or greater.
• Internal Charge Pump to Drive N-channel MOSFET
• User Programmable V - V
IN OUT
Vth for Noise Immunity
The ISL6146C provides a voltage compliant mode of operation
down to 3V with programmable Undervoltage Lock Out and
Overvoltage Protection threshold levels
• Open Drain FAULT Output with Delay
- Short between any two of the OR-ing FET Terminals
- GATE Voltage and Excessive FET V
- Power-Good Indicator (ISL6146C)
DS
The ISL6146D and ISL6146E are like the ISL6146A and ISL6146B
respectively but do not have conduction state reporting via the
fault output.
• MSOP and DFN Package Options
TABLE 1. KEY DIFFERENCES BETWEEN PARTS IN FAMILY
Applications
PART NUMBER
ISL6146A
ISL6146B
ISL6146C
ISL6146D
ISL6146E
KEY DIFFERENCES
• N+1 Industrial and Telecom Power Distribution Systems
Separate BIAS and VIN with Active High Enable
Separate BIAS and VIN with Active Low Enable
VIN with OVP/UVLO Inputs
• Uninterruptable Power Supplies
• Low Voltage Processor and Memory
• Storage and Datacom Systems
ISL6146A wo Conduction Monitor & Reporting
ISL6146B wo Conduction Monitor & Reporting
+
C
O
M
M
O
N
Q1
+
VIN GATE VOUT
BIAS
ISL6146B
P
O
W
E
VOLTAGE
DC/DC
(3V - 20V)
GATE FAST OFF, ~200ns FALL TIME
~70ns FROM 20V TO 12.6V ACROSS 57nF
GATE OUTPUT SINKING ~ 6A
ADJ
FLT
EN
R
B
U
S
GND
Q2
-
C
O
M
M
O
N
+
+
VIN GATE VOUT
P
O
W
E
VOLTAGE
DC/DC
(3V - 20V)
BIAS
ADJ
ISL6146B
FLT
EN
R
B
U
S
GND
-
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. ISL6146 GATE HIGH CURRENT PULL-DOWN
April 26, 2013
FN7667.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011-2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL6146
Block Diagram
FAULT DIAGNOSTIC
1. V - V > 570mV
Q-PUMP
BIAS
IN
OUT
2. GATE - V < 220mV (A,B,C only)
FLT
IN
VDS FORWARD
REGULATOR
3. TEMP > +150°C
+
VIN
4. V
< POR (ISL6146A/B/D/E)
BIAS
GATE
5. V OR V
< POR (ISL6146C)
IN
OUT
6. V < V
19mV
57mV
IN
OUT
VOUT
7. Gate to Drain and Gate to Source Shorts
REVERSE DETECTION
COMPARATOR
+
+
UVLO
EN/EN
8mA
ENABLE
EN
ENABLE
+
*
+
OVP
V
REF
-
4A
+
ADJ
HIGH SPEED
COMPARATOR
+
ISL6146A/B/D/E
V
REF
-
* Connected to BIAS on ISL6146A/B/D/E
Connected to VOUT on ISL6146C
ISL6146C
Pin Configuration
ISL6146
(8 LD MSOP/DFN)
TOP VIEW
ISL6146A, ISL6146B, ISL6146D, ISL6146E
ISL6146C
GATE
VIN
8
7
6
GATE
VIN
1
2
VOUT
ADJ
8
7
6
1
2
VOUT
ADJ
BIAS
FAULT
FAULT
GND
3
4
3
4
UVLO
OVP
EN ISL6146A/D
EN ISL6146B/E
5
5
GND
EPAD on DFN only, connect to GND
Pin Descriptions
MSOP/
DFN
SYMBOL
GATE
DESCRIPTION
1
Gate Drive output to the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn-on time is typically
<1ms. Allows active control of external N-Channel FET gate to perform OR-ing function.
The GATE drive is between V + 7V at V = 3.3V and V +12V at V = 18V.
IN IN IN IN
2
VIN
Connected to the sourcing supply side (OR-ing MOSFET Source), this pin serves as the sense pin to determine the OR’d
supply voltage. The OR-ing MOSFET will be turned off when V becomes lower than V
by a value more than the externally
IN
OUT
set threshold or the defaulted internal threshold. Range: 0V to 24V
3
BIAS
Primary bias pin. Connected to an independent voltage supply greater than or equal to 3V and greater than V
.
IN
ISL6146A
ISL6146B
ISL6146D
ISL6146E
Range: 3.0 to 24V
3
UVLO
EN
Programmable UVLO protection to prevent premature turn-on prior to VIN being adequately biased. Range: 0V to 24V
ISL6146C
4
Active high enable input to turn on the FET. Internally pulled low to GND through 2MΩ.
ISL6146A
ISL6146D
Range: 0V to 24V
FN7667.4
April 26, 2013
2
ISL6146
Pin Descriptions (Continued)
MSOP/
DFN
SYMBOL
EN
DESCRIPTION
4
Active low enable input to turn on the FET. Internally pulled high to BIAS through 2MΩ. Range: 0 to 24V
ISL6146B
ISL6146E
4
OVP
Programmable OV protection to prevent continued operation when the monitored voltage is too high. A back-to-back FET
configuration must be employed to implement the OVP capability. Range: 0V to 24V
ISL6146C
5
6
GND
Chip ground reference.
FAULT
Open-Drain pull-down fault indicating output with internal on chip filtering (T ). The ISL6146 fault detection circuitry pulls
FLT
down this pin to GND as it detects a fault or a disabled input (EN = ‘0’ or EN = ‘1’).
Different types of faults and their detection mechanisms are discussed in more detail on page 17. These faults include:
a. GATE is OFF (GATE < V +0.2V) when enabled [this condition is not reported on the ISL6146D and ISL6146E]
IN
b. V -V
IN OUT
> 0.57V when ON.
c. FET G-D or G-S or D-S shorts.
d. V < POR
IN L2H
e. V < V
IN OUT
f. Over-Temperature
Range: 0 to V
OUT
Resistor programmable V - V
7
ADJ
Voltage Threshold (Vth) of the High Speed Comparator. This pin is either directly
IN OUT
connected to VOUT or can be connected through a 5kΩ to 100kΩ resistor to GND. Allows for adjusting the voltage difference
threshold to prevent unintended turn-off of the pass FET due to normal system voltage fluctuations.
Range: 0.4 to V
OUT
8
VOUT
The second sensing node for external FET control and connected to the Load side (OR-ing MOSFET Drain). This is the
common connection point for multiple paralleled supplies. V
to be turned off. Range: 0V to 24V
is compared to V to determine when the OR-ing FET has
OUT
IN
PAD
ThermalPad Connect to GND
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6146AFUZ
6146A
6146A
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
8 Ld MSOP
M8.118
ISL6146AFUZ-T
ISL6146AFUZ-T7A
ISL6146AFUZ-TK
ISL6146AFRZ
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld 3x3 DFN
M8.118
M8.118
M8.118
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
M8.118
M8.118
M8.118
M8.118
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
M8.118
6146A
6146A
46AF
ISL6146AFRZ-T
ISL6146AFRZ-T7A
ISL6146AFRZ-TK
ISL6146BFUZ
46AF
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
8 Ld MSOP
46AF
46AF
6146B
6146B
6146B
6146B
46BF
ISL6146BFUZ-T
ISL6146BFUZ-T7A
ISL6146BFUZ-TK
ISL6146BFRZ
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld 3x3 DFN
ISL6146BFRZ-T
ISL6146BFRZ-T7A
ISL6146BFRZ-TK
ISL6146CFUZ
46BF
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
8 Ld MSOP
46BF
46BF
6146C
FN7667.4
April 26, 2013
3
ISL6146
Ordering Information (Continued)
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6146CFUZ-T
6146C
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld 3x3 DFN
M8.118
ISL6146CFUZ-T7A
ISL6146CFUZ-TK
ISL6146CFRZ
6146C
6146C
46CF
M8.118
M8.118
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
M8.118
M8.118
M8.118
M8.118
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
M8.118
M8.118
M8.118
M8.118
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
ISL6146CFRZ-T
ISL6146CFRZ-T7A
ISL6146CFRZ-TK
ISL6146DFUZ
46CF
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
8 Ld MSOP
46CF
46CF
6146D
6146D
6146D
6146D
46DF
46DF
46DF
46DF
6146E
6146E
6146E
6146E
46EF
ISL6146DFUZ-T
ISL6146DFUZ-T7A
ISL6146DFUZ-TK
ISL6146DFRZ
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld 3x3 DFN
ISL6146DFRZ-T
ISL6146DFRZ-T7A
ISL6146DFRZ-TK
ISL6146EFUZ
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
8 Ld MSOP
ISL6146EFUZ-T
ISL6146EFUZ-T7A
ISL6146EFUZ-TK
ISL6146EFRZ
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld MSOP Tape and Reel
8 Ld 3x3 DFN
ISL6146EFRZ-T
ISL6146EFRZ-T7A
ISL6146EFRZ-TK
ISL6146AEVAL1Z
ISL6146BEVAL1Z
ISL6146CEVAL1Z
ISL6146DEVAL1Z
ISL6146EEVAL1Z
NOTES:
46EF
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
8 Ld 3x3 DFN Tape and Reel
46EF
46EF
ISL6146A Evaluation Board (If desired with ISL6146D, please contact support)
ISL6146B Evaluation Board (If desired with ISL6146E, please contact support)
ISL6146C Evaluation Board
1 pair of ISL6146D Mini Development Boards (If desired with ISL6146A, please contact support)
1 pair of ISL6146E Mini Development Boards (If desired with ISL6146B, please contact support)
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6146. For more information on MSL please see techbrief TB363.
FN7667.4
April 26, 2013
4
ISL6146
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-Up Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Typical Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
ISL6146 Evaluation Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Description and Use of the Evaluation Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
L8.3x3J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
M8.118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
FN7667.4
April 26, 2013
5
ISL6146
Absolute Maximum Ratings
Thermal Information
BIAS, VIN, VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
GATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 40V
EN, EN, UVLO, OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
Thermal Resistance (Typical)
MSOP Package (Notes 4, 7) . . . . . . . . . . . .
DFN Package (Notes 5, 6) . . . . . . . . . . . . . .
θ
JA (°C/W)
140
θ
JC (°C/W)
41
5
46
ADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
OUT
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
OUT
ESD Rating
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 250V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
Bias Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3V to +20V
OR’d Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1V to BIAS
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. For θ , the “case temp” location is taken at the package top center
JC
Electrical Specifications
V
= BIAS = 12V, unless otherwise stated. T = +25°C to +85°C. Boldface limits apply over the operating
CC A
temperature range, -40°C to +125°C.
MIN
MAX
SYMBOL
BIAS
PARAMETERS
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
POR
POR
POR Rising
POR Hysteresis
BIAS Rising, GATE Rising
1.9
2.5
189
3.6
25
2.95
V
L2H
mV
mA
µA
mA
µA
µA
mA
µA
mA
µA
µA
µs
HYS
IBIAS_en_18 ISL6146A/B/D/E BIAS Current
BIAS, V = 18V, ADJ, V
IN
= 16.98V, enabled
= 16.98V, enabled
5
OUT
IVIN_en_18
IVIN_en_18
ISL6146A/B/D/E V Current
IN
BIAS, V = 18V, ADJ, V
IN
40
OUT
ISL6146C V Current
IN
V
= 18V, ADJ, V
OUT
= 16.98V, enabled
= 16.98V, enabled
3
4.5
20
IN
IVOUT_en_18 ISL6146A/B/D/E V
OUT
Current
BIAS, V = 18V, V
IN OUT
14
VOUT_en_18 ISL6146C V
OUT
Current
V
= 18V, V = 16.98V, enabled
400
1.7
27
500
3
IN
OUT
IBIAS_den_18 ISL6146A/B/D/E BIAS Current
BIAS, V = 18V, ADJ, V
IN
= 16.98V, disabled
= 16.98V, disabled
OUT
IVIN_den_18 ISL6146A/B/D/E V Current
BIAS, V = 18V, ADJ, V
37
IN
IN
= 18V, ADJ, V
OUT
OUT
IVIN_den_18 ISL6146C V Current
V
= 16.98V, disabled
= 16.98V, disabled
1.3
14
1.5
20
IN
IN
IVOUT_den_18 ISL6146A/B/D/E V
Current
BIAS, V = 18V, V
IN OUT
OUT
IVOUT_den_18 ISL6146C V
OUT
Current
V
= 18V, V
= 16.98V, disabled
to GATE Rising
385
150
500
210
IN
OUT
L2H
t
BIAS to GATE Delay
BIAS > POR
BIAS2GTE
GATE
V
Charge Pump Voltage
Charge Pump Voltage
Charge Pump Voltage
Low Voltage Level
V
V
V
V
V
V
V
, BIAS = 3V V - V
IN OUT
> V
FWD_VR
V
V
V
+5V
+9V
+9V
V +7V
IN
V
+10.5V
V
V
GH_3
IN
IN
IN
IN
IN
IN
IN
V
, BIAS = 12V V - V
IN OUT
> V
V
+10V
V
+17.5V
GH_12
FWD_VR
FWD_VR
IN
IN
IN
V
, BIAS = 18V V - V
IN OUT
> V
V
+10V
0
V
+18V
V
GH_18
IN
V
- V
< 0V
0.1
13
V
GL
IN OUT
IN
I
Low Pull-Down Current
High Pull-Down Current
Fast Turn-off Time
= 12V, V
= 12.2V ADJ = 11V
5
8.4
mA
A
PDL
OUT
I
falling from 12V to 10V in 2µs
3.5
6.5
65
PDH
IN
t
= V
= 12V, V
GATE
= 18V to 10V,
130
ns
toff
IN
BIAS
= 57nF
C
GATE
FN7667.4
April 26, 2013
6
ISL6146
Electrical Specifications
V
= BIAS = 12V, unless otherwise stated. T = +25°C to +85°C. Boldface limits apply over the operating
A
CC
temperature range, -40°C to +125°C. (Continued)
MIN
MAX
SYMBOL
PARAMETERS
Slow Turn-off Time
TEST CONDITIONS
= 12V, V = 18V to 10V,
(Note 8)
TYP
58
(Note 8)
UNITS
µs
t
V
C
= V
80
toffs
IN
BIAS
= 57nF
GATE
GATE
BIAS = 12V, VG = 0V
BIAS = 12V, VG = 20V
I
Turn-On Current
1
mA
mA
mV
ON
0.15
440
V
V
GATE to V Rising Fault Voltage
IN
GATE > V , enabled, FLT output is high.
IN
(Does not apply to ISL6146D and ISL6146E)
320
140
560
300
VG_FLTr
GATE to V Falling Fault Voltage
IN
GATE > V , enabled, FLT output is low.
IN
220
mV
VG_FLTf
(Does not apply to ISL6146D and ISL6146E)
CONTROL AND REGULATION I/O
Reverse Voltage Detection
V
V
rising
35
10
57
30
10
19
79
51
mV
mV
µs
Rr
OUT
Rising V Threshold
OUT
Reverse Voltage Detection
Falling V Threshold
V
V
falling
Rf
OUT
OUT
t
Reverse Voltage Detection Response
Time
Rs
V
Amplifier Forward Voltage Regulation
ISL6146 controls voltage across FET V to
DS
11
28
mV
FWD_VR
V
during static forward operation at loads
FWD_VR
resulting in Id*r
< V
DS(ON)
FWD_VR
V
HS Comparator Input Offset Voltage
ADJ Adjust Threshold with 5k to GND
ADJ Adjust Threshold with 100k to GND
HS Comparator Response Time
-14
0.57
10
0.7
0.8
40
14
1.1
95
mV
V
OS_HS
V
R
R
= 5kΩ to GND
TH(HS5k)
ADJ
ADJ
OUT
V
= 100kΩ to GND
> V , 1ns transition, 5V differential
mV
ns
TH(HS100k)
t
V
V
V
170
450
44
HSpd
IN
V
V
V
to V
to V
Forward Fault Voltage
Forward Fault Voltage
> V , GATE is fully on, FLT output is low
OUT
330
570
mV
mV
FWD_FLT
IN
OUT
IN
IN
V
> V , GATE is fully on, FLT output is high
OUT
FWD_FLT_HYS
IN
OUT
Hysteresis
FAULT OUTPUT
I
FAULT Sink Current
BIAS = 18V FAULT = 0.5V, V < V , V
IN OUT GATE
= V
GL
5
9
mA
µA
µs
FLT_SINK
I
FAULT Leakage Current
FAULT Low to High Delay
FAULT High to Low Delay
FAULT = “V
”, V > V , V
= V + V
0.04
10
10
23
3
FLT_LEAK
FLT_H IN OUT GATE IN GQP
t
GATE = V
to FAULT output is high
FLT_L2H
GQP
t
GATE = V to FAULT output is low
1.7
µs
FLT_H2L
IN
ENABLE UVLO/OVP/ADJ INPUTS
VthRa
VthR_hysa
VthFb
ISL6146A/D EN Rising Vth
580
580
580
580
606
-90
606
+90
606
+90
606
-90
10
631
631
631
631
mV
mV
mV
mV
mV
mV
mV
mV
µs
ISL6146A/D EN Vth Hysteresis
ISL6146B/E EN Falling Vth
VthF_hysb
VthFc
ISL6146B/E EN Vth Hysteresis
ISL6146C OVP Falling Vth
VthF_hysc
VthRc
ISL6146C OVP Vth Hysteresis
ISL6146C UVLO Rising Vth
VthR_hysc
ISL6146C UVLO Vth Hysteresis
EN/UVLO Rising to GATE Rising Delay
EN/OVP Falling to GATE Rising Delay
t
12
12
EN2GTER
9
µs
FN7667.4
April 26, 2013
7
ISL6146
Electrical Specifications
V
= BIAS = 12V, unless otherwise stated. T = +25°C to +85°C. Boldface limits apply over the operating
A
CC
temperature range, -40°C to +125°C. (Continued)
MIN
MAX
SYMBOL
PARAMETERS
EN/UVLO Falling to GATE Falling Delay
EN/OVP Rising to GATE Falling Delay
ENABLE Pull-Down Resistor
ENABLE Pull-Up Resistor
ADJ Pin Voltage
TEST CONDITIONS
(Note 8)
TYP
2
(Note 8)
UNITS
µs
t
4
4
EN2GTEF
2
µs
Ren_h
Ren_l
Vadj
ISL6146A, ISL6146D
ISL6146B, ISL6146E
5kΩ to 100kΩ
2
MΩ
MΩ
V
2
R
0.4
3.85
140
20
125
ADJ
Radj
OTS
ADJ Pull-Up Resistor
Internal ADJ Pull-up Resistor to V
MΩ
°C
OUT
Over-Temperature Sense
Fault signals in operation
OTS
HYS
Over-Temperature Sense Hysteresis
High Temperature Sense
°C
HTS
Fault signals upon enabling
°C
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7667.4
April 26, 2013
8
ISL6146
Typical Performance Curves
4.0
40
35
30
25
20
15
10
18V ENABLED
12V ENABLED
18V ENABLED
V
CURRENT
IN
3V ENABLED
3.5
3.0
2.5
2.0
1.5
1.0
12V ENABLED
3V ENABLED
18V DISABLED
12V DISABLED
3V DISABLED
18V DISABLED
12V DISABLED
3V DISABLED
V
CURRENT
OUT
-40
25
85
125
-40
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. ISL6146A/B/D/E BIAS AND ISL6146C V CURRENT vs
IN
FIGURE 4. ISL6146A/B/C/D/E V AND V
CURRENT vs
OUT
IN
TEMPERATURE
TEMPERATURE
35
2.60
2.55
2.50
BIAS = 18V
30
POR Vth RISING
BIAS = 12V
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
25
20
15
BIAS = 3V
POR Vth FALLING
10
5
0
-40
25
85
125
-40
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. GATE VOLTAGE vs TEMPERATURE
FIGURE 6. POR Vth RISING AND FALLING VOLTAGE
0.74
0.72
0.70
0.68
0.66
0.64
0.62
0.60
0.58
0.56
0.54
0.70
0.65
0.60
0.55
0.50
0.45
0.40
EN DEASSERT RISING Vth
EN ASSERT RISING Vth
EN DEASSERT FALLING Vth
EN ASSERT FALLING Vth
-40
25
85
125
-40
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. ISL6146A/D EN Vth vs TEMPERATURE
FIGURE 8. ISL6146B/E EN Vth vs TEMPERATURE
FN7667.4
April 26, 2013
9
ISL6146
Typical Performance Curves(Continued)
750
700
650
600
550
500
450
1.3
1.1
0.9
0.7
0.5
0.3
0.1
VG = 0V
OVP RISING
UVLO RISING AND OVP FALLING
UVLO FALLING
-40
25
85
125
-40
25
85
125
125
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. ISL6146C UVLO/OVP Vth vs TEMPERATURE
FIGURE 10. GATE TURN-ON CURRENT V = 12V
IN
10
9
8
7
6
5
4
3
2
1
0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
-40
25
85
125
-40
25
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. GATE HARD TURN-OFF CURRENT
FIGURE 12. GATE SLOW TURN-OFF CURRENT
56.0
55.5
55.0
54.5
54.0
53.5
53.0
52.5
52.0
45
40
35
30
25
20
15
-40
25
85
-40
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 13. INCREASING REVERSE VOLTAGE DETECTION Vth
FIGURE 14. REVERSE VOLTAGE RESPONSE TIME
FN7667.4
April 26, 2013
10
ISL6146
Typical Performance Curves(Continued)
3
300
280
260
240
220
200
180
160
140
120
100
2
1
0
-1
-2
-3
-40
25
85
125
-40
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 15. HIGH SPEED COMPARATOR OFFSET VOLTAGE
FIGURE 16. HIGH SPEED COMPARATOR RESPONSE TIME
900
1.002
800
700
600
500
400
300
200
100
0
1.001
1.000
0.999
0.998
0.997
0.996
0.995
0.994
0.993
R
TO GND = 5kΩ
ADJ
R
TO GND = 100kΩ
ADJ
-40
25
85
125
3
12
18
TEMPERATURE (°C)
BIAS VOLTAGE (V)
FIGURE 17. HS COMPARATOR ADJUSTABLE Vth
FIGURE 18. EN/EN/OVP/UVLO Vth DELTA vs BIAS VOLTAGE
NORMALIZED TO BIAS = 12V
21.0
20.8
20.6
20.4
20.2
20.0
19.8
19.6
19.4
19.2
19.0
465
460
455
450
445
440
435
430
425
420
-40
25
85
125
-40
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 19. FORWARD VOLTAGE REGULATION
FIGURE 20. V TO V FORWARD FAULT VOLTAGE
IN OUT
FN7667.4
April 26, 2013
11
ISL6146
Typical Performance Curves(Continued)
GATE 2
GATE 2
GATE1
GATE1
IIN2
IIN1
IIN1
IIN2
FIGURE 21. ISL6146C SLOW RAMP CONNECT 12V OR-ing
FIGURE 22. ISL6146C SLOW RAMP DISCONNECT 12V OR-ing
GATE1
GATE 2
GATE 2
GATE1
IIN2
IIN1
IIN2
IIN1
FIGURE 23. ISL6146C HOT SWAP CONNECT 12V OR-ing
FIGURE 24. ISL6146C HOT DISCONNECT 12V OR-ing
GATE
GATE
EN/UVLO
EN/UVLO
FIGURE 25. ISL6146A/D EN/ISL6146C UVLO TO GATE ON DELAY
FIGURE 26. ISL6146A/D EN/ISL6146C UVLO TO GATE OFF DELAY
FN7667.4
April 26, 2013
12
ISL6146
Typical Performance Curves(Continued)
GATE
GATE
EN
EN
FIGURE 27. ISL6146B/E EN TO GATE ON DELAY
FIGURE 28. ISL6146B/E EN TO GATE OFF DELAY
GATE
OVP
OVP
GATE
FIGURE 29. ISL6146C OVP TO GATE ON DELAY
FIGURE 30. ISL6146C OVP TO GATE OFF DELAY
V
FALLING THROUGH BOTH THE PROGRAMMED OVP
V
RISING THROUGH BOTH THE PROGRAMMED UVLO
IN
IN
AND UVLO LEVELS. GATE TURNS-ON AS V > 13V THEN
TURNS-OFF AS V > 8.3V
IN
AND OVP LEVELS. GATE TURNS-ON AS V EXCEEDS 10V
THEN TURNS-OFF AS V EXCEEDS 15V
IN
IN
IN
VIN
VIN
GATE
GATE
FIGURE 31. ISL6146C RISING V , UVLO AND OVP FUNCTION
FIGURE 32. ISL6146C FALLING, V OVP AND UVLO FUNCTION
IN
IN
FN7667.4
April 26, 2013
13
ISL6146
Typical Performance Curves(Continued)
VIN RISING TO <2.5V WHEN
GATE BECOMES ACTIVE
GATE
GATE
VIN
VOUT
GATE
VIN
FIGURE 33. BACK-TO-BACK FET TURN_ON DETAIL
FIGURE 34. ISL6146 RISING POR Vth
GATE FAST OFF, ~200ns FALL TIME
~70ns FROM 20V TO 12.6V ACROSS 57nF
GATE OUTPUT SINKING ~ 6A
VOUT
HIGH SPEED COMPARATOR Vth = V
OS(HS)
GATE1
VIN1 SHORTED
TO GND
GATE2
FIGURE 35. FAST GATE TURN-OFF WITH 57nF GATE
FIGURE 36. RESPONSE TO V SHORTED TO GND WITH ADJ
IN
SHORTED TO V
OUT
VOUT
VOUT
HIGH SPEED COMPARATOR Vth = 800mV
HIGH SPEED COMPARATOR Vth = 40mV
GATE1
GATE1
VIN1 SHORTED
TO GND
VIN1 SHORTED
TO GND
GATE2
GATE2
FIGURE 37. RESPONSE TO V SHORTED TO GND WITH
FIGURE 38. RESPONSE TO V SHORTED TO GND WITH
IN
IN
ADJ 5kΩ TO GND
ADJ 100kΩ TO GND
FN7667.4
April 26, 2013
14
ISL6146
Typical Performance Curves(Continued)
VIN
VIN
VOUT
FLT
GATE
VIN - VOUT
FIGURE 39. V HOT SWAPPED TO GATE WITH BIAS = 12V NO LOAD
FIGURE 40. FAULT ASSERTING V TO V
IN OUT
> V
IN
FWD_FLT
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
-1
0
1
2
3
4
5
6
7
17
18
19
20
21
22
HS COMP ADJUST V (mV)
TH
V
(mV)
FWD_VR
FIGURE 41. HIGH SPEED COMPARATOR OFFSET VOLTAGE
DISTRIBUTION
FIGURE 42. FORWARD REGULATION VOLTAGE DISTRIBUTION
40
35
30
25
20
15
10
5
+
V
DS
0V
V
R
t
HSpd
20V
V
GATE
12.6V
0
50
52
54
56
58
60
62
64
66
68
V
= V = 12V
IN
BIAS
t
OFF
VRr (mV)
FIGURE 43. REVERSE DETECTION RISING VOLTAGE DISTRIBUTION
FIGURE 44. FAST RAMP REVERSE PROTECTION TIMING DIAGRAM
FN7667.4
April 26, 2013
15
ISL6146
Typical Performance Curves(Continued)
FLT
VIN
FLT
VIN
GATE
GATE
FIGURE 45. ISL6146A FLT RESPONSE TO NON-CONDUCTION
FIGURE 46. ISL6146D FLT RESPONSE TO NON-CONDUCTION
FN7667.4
April 26, 2013
16
ISL6146
In the event of a V
OUT
> V condition, the ISL6146 responds
IN
Functional Description
Functional Overview
either with a high or low current pull-down on the GATE pin
depending on whether the High Speed comparator (HSCOMP)
has been activated or not. The HSCOMP determines if the VR
occurred within 1μs, by continuously monitoring the FET VDS and
if so, the high pull-down current is used to turn off the OR-ing FET.
In the event of a falling VIN transition in <1μs, (i.e., a catastrophic
failure of the power source) the HSCOMP protects the common
bus from the individual faulted power supply short by turning off
the shorted supply’s OR-ing MOSFET in less than 300ns, ensuring
the integrity of the common bus voltage from reverse current to
the damaged supply.
In a redundant power distribution system, similar potential and
parallel power supplies each contribute to the load current
through various active and passive current sharing schemes.
Typically OR-ing power diodes are used to protect against reverse
current flow in the event that one of the power supplies falls
below the common bus voltage or develops a catastrophic
failure. However, using a discrete OR-ing diode solution has some
significant drawbacks. The primary downside is the increased
power dissipation loss in the OR-ing diodes as system power
requirements increase. At the lowest voltages where the ISL6146
is designed for use, the voltage distribution losses across an
OR-ing diode can be a significant percentage, in some cases
approaching 70%. Another disadvantage when using an OR-ing
diode is failure to detect a shorted or opened current path, which
jeopardizes system power availability and reliability. An open
diode may reduce the system to a single point of failure while a
shorted diode eliminates the system’s power protection.
Once the correct V > V
IN OUT
ISL6146 again turns on the FET.
relationship is established again, the
The FAULT pin is an open drain, active low output indicating that
a fault or specific condition has occurred, these include:
• GATE is OFF (GATE < V +0.2V). Lack of conduction, not a fault,
IN
just not on. ISL6146D and ISL6146E do not respond to this
condition
• Faults resulting in V - V
IN OUT
> 0.57V when ON
Using an active OR-ing FET controller, such as the ISL6146, helps
with these potential issues. The use of a low on-resistance FET as
the OR-ing component allows for a more efficient system design
as the voltage across the FET is much lower than that across a
forward biased diode. Additionally, the ISL6146 has a dedicated
fault (FAULT) output pin that indicates when there is a conditional
or FET fault short providing the diagnostic capability that a diode
is unable to.
• An open FET resulting in body diode conduction
• Excessive current through FET
• FET Faults monitored and reported include
- G-D, gate unable to drive to Q-pump voltage
- G-S, gate unable to drive to Q-pump voltage
- D-S shorts, when GATE is OFF VDS < 2V
The ISL6146 is designed to OR together voltages as low as 1V
when supplied with a separate bias supply of 3V or greater.
Otherwise, the ISL6146 is designed to be biased from and OR
voltages across the 3V to 20V nominal supply range.
- V < POR
IN
- Missing V
IN
- V shorted to GND
IN
On the ISL6146C version, a conditional fault is also signalled if
In a single FET configuration as voltage is first applied to a VIN
pin, the FET body diode conducts providing all the ISL6146s
connected on a common bus circuit, bias via the VOUT pins. As
individual power supply voltages ramp up in excess of the rising
POR threshold, the ISL6146’s internal charge pump activates to
provide a floating gate drive voltage for the external N-channel
the V is not within the programmed UVLO and OVP levels.
IN
The ISL6146 has an on-chip over-temperature fault threshold of
~+140°C with a 20°C hysteresis. Although the ISL6146 itself
produces little heat, it senses the environment in which it is,
likely including a close by FET.
OR-ing MOSFET, thus turning the FETs on once V > V . The
ISL6146 continuously monitors the drain and source of the
OR-ing FET and provides a reverse voltage (N-channel MOSFET
IN OUT
The ISL6146A/D and ISL6146B/E are functional variants with an
enabling input of either polarity. This feature is used when the
need to interrupt the current path via signaling is necessary. This
is accomplished by implementing two FETs in series so that there
is a body diode positioned to block current in either direction.
This functionality is considered an additional enhancement to
the OR-ing diode it replaces.
V
- V ) detection threshold (VR) that, when exceeded,
OUT IN
indicates a reverse current condition. Once this threshold is
exceeded, the ISL6146 turns off the OR-ing FET by pulling down
the GATE pin to GND. The ISL6146 also provides high speed
V
> V transient protection as in the case of a catastrophic
OUT
IN
VIN failure. The ISL6146 additionally provides for adjustment of
the V - V reverse voltage Vth(VR Vth) via the ADJ pin of the
The ISL6146C employs the use of a programmable Undervoltage
Lock Out (UVLO) and a programmable Overvoltage Protection (OVP)
input. This allows the GATE to only turn-on when the monitored
voltage is between the programmed lower and upper levels. This
application would use the back-to-back FET configuration. In the
event that the current path does not need to be interrupted then the
EN, UVLO and OVP inputs can all be overridden.
IN OUT
ISL6146 with an external resistor to GND. This allows adjusting
the V - V voltage threshold level to compensate for normal
IN OUT
system voltage fluctuations, thus eliminating unnecessary
reaction by the ISL6146.
The total V - V
IN OUT
VR Vth is the sum of both the internal offset
and the external programmed VR Vth.
The ISL6146D and ISL6146E are variants of the ISL6146A and
ISL6146B respectively, the difference being the former do not
respond to a nonconduction condition (when enabled and
VIN>VOUT, the GATE is not on) unlike the latter that do signal
a fault.
FN7667.4
April 26, 2013
17
ISL6146
In this configuration, it may be tempting to use the enable inputs
Applications Information
Power-Up Considerations
to force a path by switching between the two as opposed to
having both paths on, and having the higher voltage source
provide current. The problem with that is the timing of the FETs
on and off, so that excessive V
voltage droop is not introduced
BIAS AND V CONSTRAINTS
IN
Upon power-up when the V supply is separate from the BIAS
IN
supply, the BIAS voltage must be greater or equal to the V
voltage at all times.
OUT
if the turn-off happens faster, or before the (or a slower) turn-on
momentarily leaves the load with an inadequate power
connection.
IN
When using a single supply for both the ISL6146 bias and the
Typical Applications Circuits
There are four basic configurations that the ISL6146 can be
used in:
OR-ing supply, the V and BIAS pins can be configured with a low
IN
value resistor between the two pins to provide some isolation and
decoupling to support the chip bias even as the OR’d supply
experiences voltage droops and surges. Although not necessary
to do so, it is a best design practice for particularly noisy
environments.
1. For voltages >3V where the BIAS and V are common
IN
2. For a very low OR-ing voltage, <3V operation, BIAS >3V
3. For a voltage window compliant operation and,
4. For a signaled operation where the current path is controlled
by an input signal or minimum voltage condition.
FET TO IC LAYOUT RECOMMENDATIONS
Connections from the FET(s) to the ISL6146 VIN and VOUT pins
must be Kelvin in nature and as close to the FET drain and source
PCB pads as possible to eliminate any trace resistance errors
that can occur with high currents. This connection placement is
most critical to providing the most accurate voltage sensing
particularly when the back-to-back FET configuration is used.
Likewise, connections from OVP, UVLO and ADJ are also critical to
optimize accuracy.
Each of these configurations can be tailored for the High Speed
Comparator (HS COMP) reverse threshold via the ADJ input being
connected either to VOUT or to GND via a resistor as previously
explained. Additionally, the voltage window is adjustable for both
a minimum and maximum operating voltage via the UVLO and
OVP inputs and a resistor divider also explained earlier. Also,
soft-start and turn-on and turn-off characteristics can be tailored
to suit.
ADJUSTING THE HS COMPARATOR REVERSE VOLTAGE
THRESHOLD
The three evaluation platforms provided demonstrate the four
basic configurations and provide for the additional tailoring of
the various performance characteristics.
The ISL6146 allows adjustment of the HS Comparator reverse
voltage detection threshold (VR Vth), the difference in V
- V .
OUT IN
There are two valid ADJ pin configurations:
BIAS
VOLTAGE
>3V
1. ADJ connected to VOUT: This makes the HS comparator
threshold equal to the intrinsic error in the HS comparator
input. This is the default condition and the most likely used
configuration.
+
Q1
C
O
+
M
M
O
N
2. A single resistor is connected from ADJ pin to ground:
VIN
GATE
VOUT
ADJ
Making the HS comparator threshold = V
- 4k/R .
OUT
ADJ
VERY LOW
VOLTAGE
DC - DC
P
O
W
E
BIAS
So, for a 100kΩ R , HS Comparator threshold = 40mV below
EXT
(1V-3V)
ISL6146A
GND
VOUT and for a 5kΩ R
HS comparator threshold = ~ 800mV
EXT
EN
R
FLT
below VOUT.
B
U
S
The recommended resistor range is 5kΩ to 100kΩ for this
voltage adjustment.
-
+
At power-up, the HS comparator threshold is default set to the
internal device error first, and then released to the user
programmed threshold after the related circuits are ready. It
takes ~20μs for the circuit to switch from the default setting to
the user programmed threshold after a POR startup.
Q2
C
O
M
M
O
N
+
VIN
GATE
VOUT
ADJ
P
O
W
E
The current out of the ADJ pin with a resistor to GND is equal to
VERY LOW
BIAS
0.4V/R
VOLTAGE
DC - DC
(1V-3V)
EXT.
R
ISL6146A
GND
BACK-TO-BACK FET CONFIGURATION
FLT
B
U
S
EN
When using the back-to-back FET configuration, the FET choice
must be such that the voltage across both FETs at full current
loading be less than the minimum forward voltage fault
threshold of 400mV to avoid unintended fault notification.
-
FIGURE 47. LOW VOLTAGE APPLICATION DIAGRAM
FN7667.4
April 26, 2013
18
ISL6146
The Figure 1 circuit shown on page 1 is the basic circuit used for
OR-ing voltages >3V to 20V.
DISTRIBUTED
VOLTAGE
>3V
The ISL6146A application shown in Figure 47 is the configuration
for OR-ing very low voltages of 1V to 3V. Additionally, this
application shows the utilization of the ADJ input with a single
resistor tied to GND. This provides the user a programmable level
Q1
Q2
+
C
O
M
M
O
N
+
of V
> V before the High Speed (HS) Comparator is activated
OUT
IN
VIN
GATE
VOUT
ADJ
VERY LOW
VOLTAGE
DC - DC
and the GATE output is pulled down to allow for normal voltage
fluctuations in the system.
BIAS
P
O
W
E
(1V-BIAS)
ISL6146A/B
FLT
Notice that in both of these circuits, the EN or EN inputs are
defaulted to enabled and have no current path on/off control.
Failure to do so correctly will result in only body diode conduction
and a resulting fault indication.
R
ENABLED
WHEN
SIGNALED
B
U
S
GND EN/EN
-
The V and V
IN OUT
to FET and GND to ADJ connections are drawn
+
Q3
Q4
to emphasize the Kelvin connection necessary to correctly
monitor the voltage across the FET, and for the VR Vth monitor to
eliminate any stray resistance effects.
C
O
M
M
O
N
+
Q1
Q2
+
VIN
GATE
VOUT
ADJ
P
VERY LOW
VOLTAGE
DC - DC
C
O
M
M
O
N
O
W
E
BIAS
+
ISL6146A/B
(1V-BIAS)
R
FLT
B
U
S
VIN
GATE
VOUT
ADJ
ENABLED
WHEN
SIGNALED
GND
EN/EN
UVLO
P
VOLTAGE
DC - DC
3V-20V
O
W
E
-
ISL6146C
GND
FLT
OVP
R
B
U
S
FIGURE 49. CONTROLLED ON/OFF APPLICATION DIAGRAM
-
The application diagram in Figure 49 shows the ISL6146A or
ISL6146B utilizing the EN or EN pin as a signalled input to open
or close the conduction path from power supply to load. This
feature can be implemented on OR-ing 1V to 20V but is shown
for OR-ing <3V.
+
Q3
Q4
C
O
M
M
O
N
+
The enable input signaling can be simultaneous across the N+1
number of ISL6146s used.
VIN
GATE
VOUT
ADJ
P
VOLTAGE
DC - DC
3V-20V
O
W
E
UVLO
Although not needed for thermal relief, connect the DFN EPAD
to GND.
ISL6146C
GND
R
FLT
OVP
B
U
S
SWITCH-OVER CIRCUITS
Switch over applications are different than OR-ing applications in
that, the former are looking for the presence of or a condition of
a preferred supply in order to switch to it. Whereas true OR-ing
consists of a redundant N+1 configuration with no preferred
source.
-
FIGURE 48. TYPICAL ISL6146C APPLICATION DIAGRAM
The ISL6146C application shown in Figure 48 is limited to the 3V
to 20V V range and must implement the back-to-back FET
configuration to utilize the UVLO and OVP inputs and capabilities.
The following 2 circuits are simple single ISL6146 switchover
IN
circuits optimized for situations particular to the V
and V
BATT
EXT
As the V voltage rises above the minimum programmed
voltages relative to each other. Figure 50 shows an ISL6146B
switchover circuit where V , when present, is the preferred
IN
voltage, the related OR-ing FETs will turn on and stay on until
either the minimum voltage requirement is no longer met or the
EXT
source and V
could be lesser or greater than V . This circuit
BATT
EXT
senses the presence of the preferred voltage supply to a
programmable threshold level that when exceeded, V
V
voltage exceeds its programmed maximum. The minimum
IN
and maximum programmed voltage levels are done with the
resistor divider on the UVLO and OVP pins. These levels should be
programmed to take into account conduction path losses to the
load in addition to the IC operational constraints.
is
EXT
is disconnected from the output.
passed to the output as V
BATT
R1 & R2 program the V
EXT
level that must be preset for the
preferred voltage to be passed to the output.
When using the back-to-back FET configuration, the user must
Q3 is necessary if V can ever exceed V
from flowing into V
EXT
to prevent current
EXT
BATT
when present. The body diode of Q3
chose FETs to ensure (2r
+ PCB IR) I
< 0.5V to avoid
DS(ON)
LOAD
tripping the V - V
> 0.5V when ON fault.
IN OUT
FN7667.4
April 26, 2013
19
ISL6146
prevents that when Q1 is on regardless of the V
voltage.
All of the scope shots were taken with a 5A load and 100µF of
BATT
The ISL6146 bias is pulled from the common drain node to
ensure an always adequate bias from either source when the
other is absent
bulk load capacitance.
Figure 52 is a ISL6146A switchover circuit to use where the
preferred V
source is always greater than the V . Because
EXT
BATT
this is so, there is no need for a 3rd FET for blocking as in
Figure 50. Additionally, the preferred V source when present
or at a programmed minimum threshold voltage via R1 and R2
divider will turn on Q2/turn-off Q1 but when absent or not
minimally adequate, will do the opposite. In this circuit, with the
Q1
V
EXT
EXT
SWITCHED
OUTPUT
3.3V - 24V
Use when V
> V
BATT
Q3 disconnects V
EXT
from
Q3
Q2
ISL6146A not connected to the battery, and thus no constant I
BATT
output when GATE is off.
VIN
V
BATT
load on it, which allows for longer battery life.
3.3V-20V
Bias voltage is pulled from the common output to ensure an
always adequate IC bias from either source.
VIN
GATE
VOUT
FLT
Q1
BIAS
V
BATT
SWITCHED
OUTPUT
R1
ADJ
ISL6146B
GND
EN
R3
Use when V
BATT
< V
EXT
Q2
R2
V
EXT
FIGURE 50. ISL6146B EXTERNAL SWITCHOVER SCHEMATIC
Figure 51 shows operational scope shots of the above circuit.
VIN
GATE
VOUT
FLT
BIAS
R1
BATT SUPPLY
EXT SUPPLY
ADJ
ISL6146A
GND
EN
R2
VOUT
FIGURE 53. ISL6146A EXTERNAL SWITCHOVER SCHEMATIC
GATE
BATT SUPPLY
EXT SUPPLY
VOUT
FIGURE 51. EXTERNAL SUPPLY < BATT SUPPLY CONNECTED
BATT SUPPLY
EXT SUPPLY
GATE
VOUT
FIGURE 54. EXTERNAL SUPPLY > BATT SUPPLY CONNECTED
GATE
FIGURE 52. EXTERNAL SUPPLY < BATT SUPPLY DISCONNECTED
FN7667.4
April 26, 2013
20
ISL6146
Figures 56 through 61 illustrate the three ISL6146 evaluation
boards for the three typical applications in photograph and
schematic form.
BATT SUPPLY
VOUT
EXT SUPPLY
There are also 2 mini development boards named
ISL6146DEVAL1 and ISL6146EEVAL1. These boards are
provided as a matching pair of either the ISL6146D or ISL6146E
part type directly from the website or with either the ISL6146A or
ISL6146B installed from the factory (contact support if desired).
The small size (1” x 0.5”) is suitable for adding into an existing
circuit using another OR-ing FET controller. These small and
simple boards have only the necessary components for its
implementation utilizing the already present MOSFET(s) in the
circuit it is being added to.
GATE
The mini evaluation circuit is designed to give the user the
flexibility in either defaulting or signaling the enable ON or to use
a VIN voltage threshold to turn-on the IC function.
FIGURE 55. EXTERNAL SUPPLY > BATT SUPPLY DISCONNECTED
Provided are access to the IC VIN, GATE and VOUT pins for best
practices connections to the MOSFET(s) along with adjustable HS
Vth via the ADJ pin and the FAULT output.
ISL6146 Evaluation Platforms
The mini evaluation circuit is documented in Figures 62 & 63 and
Table 2.
Description and Use of the Evaluation Boards
The three ISL6146 evaluation boards are used to demonstrate
the four application configurations discussed earlier. All the
boards have ADJ shorted to VOUT with the PCB layout having the
component footprints to insert a resistor of choice between ADJ
and GND to adjust the HS COMP Vth. Likewise, the VIN is
connected to BIAS but these can be separated to provide an
adequate BIAS voltage when OR-ing <3V supplies or if providing
a separate from VIN voltage to BIAS.
The ISL6146AEVAL1Z is configured to have a 8.5V minimum
turn-on threshold with a 1.2V hysteresis.
The ISL6146BEVAL1Z is configured as a minimally featured
maximum performance OR-ing FET controller for 3V to 20V.
The ISL6146CEVAL1Z is configured to operate with a 10.8V lower
turn on threshold and 14.9V upper turn-off threshold.
All three boards are equipped with 50A capable FETs for high
current evaluations and with a minimum of V and V
bulk
capacitance likely to be found in any power system design.
IN OUT
After determining the BIAS source along with V voltage criteria
IN
and configuring the evaluation board if necessary, for the
application to be evaluated the board is ready for power.
Apply the BIAS voltage first (via the test points labeled BIAS), if
separate from VIN, then the V voltage. Monitor the provided
IN
test points for device performance with current loads up to 50A.
FN7667.4
April 26, 2013
21
ISL6146
FIGURE 56. ISL6146AEVAL1Z
FIGURE 57. ISL6146AEVAL1Z SCHEMATIC
FIGURE 58. ISL6146BEVAL1Z
FIGURE 59. ISL6146BEVAL1Z SCHEMATIC
FN7667.4
April 26, 2013
22
ISL6146
FIGURE 60. ISL6146CEVAL1Z
FIGURE 61. ISL6146CEVAL1Z SCHEMATIC
Dimensions are
1” x 0.5” (25.4mm x 12.7mm)
FIGURE 62. ISL6146DEVAL1Z
FIGURE 63. ISL6146EDEV1Z SCHEMATIC (Mini-eval)
FN7667.4
April 26, 2013
23
ISL6146
TABLE 2. ISL6146xEVALZ BOM
DESCRIPTION
REFERENCE DESIGNATOR
ISL6146AEVAL1Z
VALUE
MANUFACTURER
PART NUMBER
U1, U2
Q1, Q2, Q11, Q12
R1, 11
ISL6146A OR-ing FET Controller
30V, 50A FET
Intersil
ISL6146AFUZ
Various
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
66.5kꢀ
4.99kꢀ
10ꢀ
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
Alum. Elect SMD Cap
CAP, SMD, 0603, 50V, 10%
CAP, SMD, 0603, 50V, 10%
Test Point
R2, R12, R6, R16
R3, R13
R4, R14
0ꢀ
R5, R15
DNP
R7, R17
10kꢀ
100µF
1µF
C1, C11, C5 C15
C2, C3, C12 C13
C4, C14
DNP
TPx
Jx
Banana Jack
ISL6146BEVAL1Z
U1, U2
Q1, Q11
R4, R14
R1, R10
R2, R12
R3, R13
R5, R15
C1, C11, C5 C15
C2, C3, C12 C13
C4, C14
ISL6146B OR-ing FET Controller
30V, 50A FET
Intersil
ISL6146BFUZ
Various
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
4.99kꢀ
10ꢀ
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
Alum. Elect SMD Cap
CAP, SMD, 0603, 50V, 10%
CAP, SMD, 0603, 50V, 10%
Test Point
0ꢀ
DNP
10kꢀ
100µF
1µF
DNP
TPx
Jx
Banana Jack
ISL6146CEVAL1Z
U1, U2
Q1, Q2, Q11, Q12
R1, 11
ISL6146C OR-ing FET Controller
30V, 50A FET
Intersil
ISL6146CFUZ
Various
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
93.1kꢀ
1.4kꢀ
4.53kꢀ
0ꢀ
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
Alum. Elect SMD Cap
CAP, SMD, 0603, 50V, 10%
Test Point
R2, R12
R3, R13
R4, R14
R5, R15
R6, R16
R7, R17
DNP
4.99kꢀ
10kꢀ
100µF
1µF
C1, C11, C3 C13
C2, C12
TPx
Jx
Banana Jack
FN7667.4
April 26, 2013
24
ISL6146
TABLE 2. ISL6146xEVALZ BOM (Continued)
DESCRIPTION
REFERENCE DESIGNATOR
ISL6146DEVAL1Z
VALUE
MANUFACTURER
PART NUMBER
U1
R1, R2, R3
R4
ISL6146D OR-ing FET Controller
RES, SMD, 0603, 1%
Intersil
ISL6146DFUZ
DNP
4.99kꢀ
10kꢀ
1µF
Generic
Generic
Generic
Generic
RES, SMD, 0603, 1%
R5
RES, SMD, 0603, 1%
C1, C2
CAP, SMD, 0603, 50V, 10%
ISL6146EEVAL1Z
U1
R1, R2, R3
R4
ISL6146E OR-ing FET Controller
RES, SMD, 0603, 1%
Intersil
Generic
Generic
Generic
Generic
ISL6146EFUZ
DNP
4.99kꢀ
10kꢀ
1µF
RES, SMD, 0603, 1%
R5
RES, SMD, 0603, 1%
C1, C2
CAP, SMD, 0603, 50V, 10%
FN7667.4
April 26, 2013
25
ISL6146
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
April 3, 2013
FN7667.4 Added ISL6146DEVAL1Z and ISL6146EEVAL1Z related information. Figurers 62 and 63. Corrected labels in
Figure 61.
September 27, 2012
June 18, 2012
FN7667.3 Added tape and reel parts to Ordering Information table for ISL6146A/B/C/D/E products.
Thermal Information - removed Pb-Free Reflow link
FN7667.2 Added ISL6146D and ISL6146E. References to these products added throughout the datasheet. Added Figures
45 & 46 to illustrate the fault differences between ISL6146A/B and ISL6146D/E. Moved Figure 50 and revised
the related text on page 20 before the evaluation board section. Added Figures 51 - 55 and related text on
page 20 to page 21.
February 27, 2012
December 16, 2011
FN7667.1 Removed note “MSOP packaged parts to be released soon” from “Ordering Information” on page 3. Added
FIgures 42 & 43 on page 15.
FN7667.0 Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7667.4
April 26, 2013
26
ISL6146
Package Outline Drawing
L8.3x3J
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0 9/09
2X 1.950
3.00
A
6X 0.65
B
5
8
(4X)
0.15
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
4
1
4
8X 0.30
0.10 M C A B
8X 0.400 ± 0.10
TOP VIEW
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
0.10
C
C
Max 1.00
0.08
C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
5
0 . 2 REF
C
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7667.4
April 26, 2013
27
ISL6146
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.36
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN7667.4
April 26, 2013
28
相关型号：
ISL6146BFUZ-TK
Low Voltage ORing FET Controller; DFN8, MSOP8; Temp Range: -40° to 125°C
RENESAS
ISL6146CFUZ
Low Voltage ORing FET Controller; DFN8, MSOP8; Temp Range: -40° to 125°C
RENESAS
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