ISL6174 [INTERSIL]
Dual Low Voltage Circuit Breaker; 双路低压断路器
| 型号： | ISL6174 |
| 厂家： | 
Intersil |
| 描述： | Dual Low Voltage Circuit Breaker |
| 文件： | 总16页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6174
®
Data Sheet
December 19, 2008
FN6830.0
Dual Low Voltage Circuit Breaker
Features
This IC targets dual voltage hot swap applications across the
+2.5V to +3.3V (nominal) bias supply voltage range with a
second lower voltage rail down to less than 1V where a circuit
breaker response to an over current event is preferred.
It features a charge pump for driving external N-Channel
MOSFETs, accurate programmable circuit breaker current
thresholds and delay output undervoltage monitoring and
reporting and adjustable soft-start.
• Fast Circuit Breaker Quickly Responds to Overcurrent
Fault Conditions
• Less than 1µs Response Time to Dead Short
• Programmable Circuit Breaker Level and Delay
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• Overcurrent Circuit Breaker and Fault Isolation Functions
• Adjustable Circuit Breaker Threshold as Low as 20mV
The circuit breaker current level (I ) for each rail is set by
CB
• Adjustable Voltage Ramp-up for In-Rush Protection
During Turn-On
two external resistors, and for each rail a delay (t
is set by
CB)
has expired,
an external capacitor on the TCB pin. After t
CB
• Rail Independent Control, Monitoring and Reporting I/O
• Dual Supply Hot Swap Power Distribution Control to <1V
• Charge Pump Allows the Use of N-Channel MOSFETs
• QFN Package:
the IC then quickly pulls down the associated GATE(s)
output turning off its external FET(s).
Ordering Information
TEMP.
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
PART NUMBER
(Note)
PART
MARKING
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
- Near Chip Scale Package Footprint, Which Improves
PCB Efficiency and has a Thinner Profile
ISL6174IRZ*
ISL6174 IRZ -40 to +85 28 Ld 5x5 QFN L28.5x5
ISL617XEVAL1Z Evaluation Platform
• Pb-Free (RoHS Compliant)
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
Applications
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
• Power Supply Sequencing, Distribution and Control
• Hot Swap / Electronic Circuit Breaker Circuits
R
1
V1(IN)
V1(OUT)
SNS
Pinout
ISL6174
(28 LD QFN)
TOP VIEW
VS1 SNS1 GT1 VO1
UV1
EN1 EN2
BIAS
PG1
FLT1
SS1
CPQ+
CPQ-
CPVDD
OCREF
SS2
ISL6174
28 27 26 25 24 23 22
SNS1
VO1
SS1
1
2
3
4
5
6
7
21 SNS2
20 VO2
FLT2
PG2
PGND
GND
TCB1
UV2
SNS2 GT2 VO2
19
SS2
18 GT2
17
TCB2 VS2
GT1
FLT1
PG1
TCB1
FLT2
16 PG2
V2(OUT)
V2(IN)
15 TCB2
R
2
SNS
8
9
10 11 12 13 14
FIGURE 1. TYPICAL APPLICATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL6174
Block Diagram
Io
LOAD
Vin
Vo
Rsns
Q
Iset Rset
10V
24µA
Soft Start
Amplifier
CPVDD
10µA
-
42µA
SS1
+
1k
Css
-
+
WOC
FLT1
Comparator
OC Timer
&
1.178V
+
Logic
Iref
OCREF
Rref
CPVDD
10µA
-
OC
Iref
4
Current
Mirror
Comparator
PG1
BIAS
10K
TCB1
+
-
t
CB1
EN1
1.178V
633mV
Timeout
Rs1
Rs2
Comparator
-
UV1
BIAS
UV
+
Comparator
CPQ+
Cp
10V(out)
X2
Charge
Pump
X2
Charge
Pump
CPQ-
CPVDD
Cv
633mV
POR and
Bandgap
1.178V
ISL6173
FIGURE 2. ISL6174 - INTERNAL BLOCK-DIAGRAM OF THE IC - CHANNEL ONE ONLY
FN6830.0
December 19, 2008
2
ISL6174
Pinout
28 LEAD QFN
TOP VIEW
28
27
26
25
24
23
22
SNS1
VO1
SS1
1
2
3
4
5
6
7
21 SNS2
20 VO2
19
18 GT2
17
SS2
GT1
FLT1
PG1
TCB1
FLT2
16 PG2
15 TCB2
8
9
10
11
12
13
14
Pin Descriptions
PIN
NAME
FUNCTION
DESCRIPTION
1
SNS1
Current Sense Input
This pin is connected to the current sense resistor and control MOSFET Drain node. It provides
current sense signal to the internal comparator in conjunction with VS1 pin.
2
3
VO1
SS1
Output Voltage 1
This pin is connected to the control MOSFET switch source, which connects to a load. Internally, this
voltage is used for SS control.
Soft-Start Duration Set A capacitor from this pin to ground sets the output soft-start ramp slope. This capacitor is charged by
Input
the internal 10µA current source setting the soft-start ramp. The output voltage ramp tracks the SS
ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor continues
to charge to the CPVDD voltage rail. If common capacitor is used (by tying SS1, SS2 together and
the capacitor to GND from the connection) then both the outputs track each other as they ramp up.
4
5
6
7
GT1
FLT1
PG1
Gate Drive Output
Fault Output
Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to
4 X Vbias or 10V(max) from the 24µA source.
This is an open drain output. It asserts (pulls low) once the circuit breaker delay (determined by the
TCB timeout cap) has expired. This output is valid for Vbias>1V.
Power Good Output
This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on
UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V.
TCB1
Circuit Breaker Delay
Timer
A capacitor from this pin to ground sets the delay from the onset of an over current event to channel
shutdown (circuit breaker delay). Once the voltage on TCB cap reaches V
pulled down and the FLT is asserted.
the GATE output is
CT_Vth
The time for circuit breaker delay (t ) = (C
CB
*1.178)/10µA.
TCB
8
9
DNC
GND
Do not connect
Chip Gnd
Do not connect
This pin is also internally shorted to the metal tab at the bottom of the IC.
Charge pump ground. Both GND and PGND must be tied together externally.
10
11
PGND
CPQ-
ChargePumpCapacitor Flying cap lowside.
Low Side
FN6830.0
December 19, 2008
3
ISL6174
Pin Descriptions (Continued)
PIN
NAME
FUNCTION
DESCRIPTION
12
BIAS
Chip Bias Voltage
Provides IC Bias. Should be 2V to 4V for IC to function normally. This pin can be powered from a
supply voltage that is not being controlled. It is preferable to use 3.3V even if the channels being
controlled are 2.5V or lower because more gate drive voltage will be available to the MOSFETs.
13
14
CPQ+
ChargePumpCapacitor Flying cap highside. Use of 0.1µF for 2.5V bias and 0.022µF for 3.3V bias is recommended.
High Side
CPVDD Charge Pump Output
This is the voltage used for some internal pull-ups and bias. Use of 0.47µF (minimum) is
recommended.
15
16
17
18
19
TCB2
PG2
FLT2
GT2
Timer Capacitor
Power Good Output
Fault Output
Same function as pin 7
Same function as pin 6
Same as pin 5
Gate Drive Output
Same as pin 4
SS2
Soft-Start Duration Set Same as pin 3
Input
20
21
22
VO2
SNS2
VS2
Output Voltage 2
Same as pin 2
Same as pin 1
Current Sense Input
Current Sense
Reference
Voltage input for one of the two voltages. Provides a 20µA current source for the ISET series resistor
which sets the voltage to which the sense resistor IR drop is compared.
23
UV2
EN2
Undervoltage Monitor
Input
This pin is one of the two inputs to the undervoltage comparator. The other input is the 633mV
reference. It is meant to sense the output voltage through a resistor divider. If the output voltage
drops so that the voltage on the UV pin goes below 633mV, PG2 is deasserted.
24
25
Enable
This is an active low input. When asserted (pulled low), the SS and gate drive are released and the
output voltage gets enabled. When deasserted (pulled high or left floating), the reverse happens.
OCREF Ref. Current Adj.
Allows adjustment of the reference current through R
thus setting the thresholds for CR, OC and WOC.
and the internal Circuit Breaker set resistor,
SET
26
27
EN1
UV1
Enable Input
Same as pin 24
Same as pin 23
Undervoltage Monitor
Input
28
VS1
Current Sense
Reference
Same as pin 22
FN6830.0
December 19, 2008
4
ISL6174
Absolute Maximum Ratings
Thermal Information
VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +12V
ENx, SNSx, PGx, FLTx, VSx, TCBx, UVx,
SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC
Output Current . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
Thermal Resistance (Typical, Notes 1, 4)
5x5 QFN Package . . . . . . . . . . . . . . . .
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
For recommended soldering conditions, see Tech Brief TB389.
(QFN - Leads Only)
θ
(°C/W)
42
θ
(°C/W)
JA
JC
12.5
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
VBIAS / VIN1 Supply Voltage Range. . . . . . . . . . . +2.25V to +3.63V
Temperature Range (T )
-40°C to +85°C
A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. All voltages are relative to GND, unless otherwise specified.
3. 1V (min) on the BIAS pin required for FLT to be valid.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside..
JC
Electrical Specifications
V
= 2.5V to +3.3V, V = 1V,T = T = -40°C to +85°C, Unless Otherwise Specified. Parameters with MIN
DD S A J
and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested.
PARAMETER
CIRCUIT BREAKER CONTROL
ISET Current
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
R
= 14.7kΩ
19
20
21
µA
mV
mV
SET
OCREF
Over Current Comparator Offset Voltage
Circuit Breaker Threshold Voltage
Vio
V
V
- V
- V
with I
= 0A
-1.25
-0.05
19.7
1.25
VS
SNS
SNS
OUT
at FLT assertion,
= 20µA
V
V
CRVTH
VS
R
= 1.0k, I
ISET
SET
TCB Threshold Voltage
TCB Charging Current
TCB Default Delay
Peak Voltage
TCB = Open
GATE open
1.128
9
1.178
10
1.202
11
V
CT_Vth
I
µA
µs
CT
T
3
CT
GATE DRIVE
GATE Response Time from WOC (Open)
pd_woc_open
pd_woc_load
3
ns
ns
100mV of overdrive on the WOC
comparator
GATE Response Time from WOC
(Loaded)
GATE = 1nF
100mV of overdrive on the WOC
comparator
100
GATE Turn-On Current
GATE Turn-Off Current
GATE Voltage
IGATE_on
IGATE_off
GATE = 2V, V = 2V, V
VS
= 2.1V
21
24
100
8.8
7
27
µA
mA
V
SNS
OC or WOC Turn-off Gate Current
Bias = 2.5V (Figure 5, 6)
V
8.2
9.3
GATE
2.1 < Bias < 2.5 (Figure 5, 6)
V
BIAS
Supply Current
I
V
= 3.3V
6
9.3
2.02
1.98
33
12
mA
V
BIAS
BIAS
POR Rising Threshold
POR Falling Threshold
POR Threshold Hysteresis
VIN_POR_L2H
VIN_POR_H2L
VIN_POR_HYS
1.85
1.80
5
2.12
2.10
V
mV
FN6830.0
December 19, 2008
5
ISL6174
Electrical Specifications
V
= 2.5V to +3.3V, V = 1V,T = T = -40°C to +85°C, Unless Otherwise Specified. Parameters with MIN
DD
S
A
J
and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
I/O
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Undervoltage Comparator Falling
Threshold
V
620
635
650
mV
UV_VTHF
Undervoltage Comparator Hysteresis
EN Rising Threshold
EN Falling Threshold
EN Hysteresis
V
9
17
25
2.25
1.20
1175
0.3
mV
V
UV_HYST
PWR_Vth_R
PWR_Vth_F
PWR_HYST
V
V
V
= 2.5V
= 2.5V
= 2.5V
1.75
0.97
600
0.05
0.05
9
2.04
1.11
905
0.15
0.15
10
BIAS
BIAS
BIAS
V
mV
V
PG Pull-Down Voltage
FLT Pull-Down Voltage (Note 3)
Soft-Start Charging Current
CHARGE PUMP
I
I
= 8mA
PG
VOL_PG
VOL_FLT
= 8mA
0.3
V
FLT
I
VSS = 1V
11
µA
SS
CPVDD
V_CPVDD
V_CPVDD
V
V
= 3.3V
= 3.3V
4.9
5.2
5.0
5.5
V
V
BIAS
CPVDD
BIAS
T = +25°C
External User Load = 6mA
FN6830.0
December 19, 2008
6
ISL6174
Typical Performance Curves (at +25°C unless otherwise specified)
12
10
8
1.04
1.02
1.00
0.98
0.96
0.94
6
4
2
C
= 22nF, C
2.9
= 0.47µF
3.7
PQ
PVDD
-40
0
25
70
85
125
0
1.0
1.4
1.7
2.0
2.3
3.2
TEMPERATURE (°C)
V_BIAS(V)
FIGURE 3. I_BIAS vs V_BIAS
FIGURE 4. NORMALIZED I BIAS (VBIAS = 3.3V) vs
TEMPERATURE
12.0
10.0
8.0
12.0
10.0
8.0
6.0
6.0
C
= 0.1µF, C = 0.47µF
PVDD
PQ
4.0
4.0
2.0
0.0
C
= 22nF, C = 0.47µF
PVDD
PQ
2.0
0.0
2.0 2.2 2.4
2.6 3.8
3.0
3.2 3.4 3.6 3.8 4.0
2.0 2.2 2.4
2.6 3.8
3.0 3.2 3.4 3.6 3.8 4.0
V BIAS(V)
V BIAS (V)
FIGURE 6. V
vs V_BIAS
FIGURE 5. V
vs V_BIAS
GATE
GATE
25.0
24.8
24.6
24.4
24.2
24.0
23.8
23.6
23.4
23.2
23.0
9.2
9.0
8.8
8.6
8.4
8.2
8.0
-40
0
25
70
85
125
-40
0
25
70
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. GATE VOLTAGE vs TEMPERATURE
FIGURE 8. GATE TURN-ON CURRENT vs TEMPERATURE
FN6830.0
December 19, 2008
7
ISL6174
Typical Performance Curves (at +25°C unless otherwise specified) (Continued)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
25
23
21
19
17
15
13
I
= 20µA, R
= 1.0k
SET
SET
-40
0
25
70
85
125
-40
0
25
70
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. CIRCUIT BREAKER GATE TURN-OFF CURRENT
vs TEMPERATURE
FIGURE 10. CIRCUIT BREAKER Vth vs TEMPERATURE
21.00
20.80
20.60
20.40
20.20
20.00
19.80
19.60
19.40
19.20
19.00
660
655
650
RISING VTH
645
640
635
630
FALLING VTH
625
620
-40
0
25
70
85
125
-40
0
25
70
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. UNDERVOLTAGE Vth vs TEMPERATURE
10000
FIGURE 12. I
SET
vs TEMPERATURE
3.0
2.5
2.0
1.5
1.0
0.5
0
1000
100
10
1
100
150
200
OC (% OF LIMIT)
250
300
0
0.1
0.47
1.0
2.0
(nF)
4.0
8.7
14
22
C
G
FIGURE 14. RESPONSE TIME vs I *R
SNS
O
FIGURE 13. WOC RESPONSE vs LOAD CAPACITANCE
FN6830.0
December 19, 2008
8
ISL6174
(SNS) and voltage set (VS) pins. The latter is through a
resistor, R , as shown. Two levels of overcurrent
Detailed Description of Operation
SET
ISL6174 targets dual voltage hot-swap applications with a
bias of 2.1V to 3.6VDC and the voltages being controlled
down to 0.7VDC. The IC’s main functions are to control start-
up inrush current and provide circuit breaker protection of
the sourcing supplies from OC loads. This is achieved by
enhancing an external MOSFET in a controlled manner. In
order to fully enhance the MOSFET, the IC must provide
adequate gate to source voltage, which is typically 5V or
greater. Hence, the final steady-state voltage on Gate (GT)
pin must be a minimum of 5V above the load voltage. Two
internal charge-pumps allow this to happen.
detection are available to protect against all possible fault
scenarios. These levels are:
• Timed Circuit Breaker (CB)
• Way Overcurrent Circuit Breaker (WOC)
Each of these modes is described in detail as follows:
TIMED CIRCUIT BREAKER (CB) MODE
When the load current reaches the Circuit Breaker threshold
(I ) the ISL6174 enters the timed Circuit Breaker Mode.
CB
When the circuit enters this mode, the OC comparator which
directly looks at the voltage drop across R
detects it and
SNS
VIN
VO
starts the CB delay timer. TCB begins to charge whatever
capacitance is on that pin from an internal 10µA current
source. The amount of time it takes for this capacitance to
Q
charge to ~1.18V (V
) sets up the Circuit Breaker delay.
CT_Vth
Upon expiration of the CB delay (t ), the MOSFET gate is
CB
VIN
pulled down quickly.
10V
If during and prior to t
expiring the load current falls below
then in that case, the Circuit Breaker mode is no longer
CB
0
I
CPVDD
24µA
CB
SOFT-
START
AMPLIFIER
active and the IC discharges the C
TCB
The Circuit Breaker threshold (I ) is set by sinking a
CB
cap.
CPVDD
10µA
0
-
reference current, I
, through R
by selecting an
42µA
SET SET
SS1
+
appropriate resistor between OCREF and GND, which sets
+
-
I
. The relationship between I
REF REF
and I
SET
is I
=
REF
4*I = Vocref/Rocref = 1.178/Rocref. I
, where I
SET
would typically be set at 80µA. This I
REF
REF
* R
SET
voltage is
SET
FIGURE 15. SOFT-START OPERATION
then compared to the voltage across a load current series
sense low ohmic resistor.
Controlled Soft-Start
Selecting appropriate values for R
and R
SNS
such that
SET
The output voltages are monitored through the Vo pins and
slew up at a rate determined by the capacitors on the
Soft-start (SS) pin, as illustrated in Figure 15. 24µA of gate
charge current is available. The soft-start amplifier controls
the output voltage by robbing some of the gate charge
current thus slowing down the MOSFET enhancement.
When the load voltage reaches its set level, as sensed by its
respective UV pin through an external resistor divider, the
Power Good (PG) output goes active.
when I = I
,
O
CR
(EQ. 1)
Io*R
SNS
= I
SET SET
*R
WAY OVERCURRENT CIRCUIT BREAKER (WOC) MODE
This mode is designed to handle very fast, very low
impedance shorts on the load side, which can result in very
high di/dt transients on the input current. The WOC circuit
breaker level is typically 200% of the Circuit Breaker limit. In
this mode the comparator, which directly looks at the voltage
Current Monitoring and Circuit Breaker Protection
drop across R
and once the WOC level is exceeded the
SNS
The IC monitors the load current (Io) by sensing the
voltage-drop across the low value current sense resistor
IC pulls the gate very quickly to GND, the SSx capacitor is
discharged, FLT is asserted and a new SS sequence is
allowed to begin after ENx recycle.
(R
), which is connected in series with the MOSFET (as
SNS
shown in the “Block Diagram” on page 2), through Sense
FN6830.0
December 19, 2008
9
ISL6174
7. If the load current on the output exceeds the set current
limit for greater than the circuit breaker delay, FLT gets
asserted and the channel shutdown occurs.
I
o
V
V
-
O
+
IN
Q
+
Rsns
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, the Power Good (PG) output goes
active.
I
R
SET SET
-
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN remains
asserted or there is no other fault condition present that
would attempt to pull down the gate.
OC COMPARATOR
-
GATE
ISL6174
PULLDOWN
CURRENT
Applications Information
+
Selection of External Components
3k
-
The typical application circuit of Figure 2 has been used for
this section, which provides guidelines to select the external
component values.
+
25Ω
WOC
COMPARATOR
MOSFET (Q1)
This component should be selected on the basis of its
r
specification at the expected Vgs (gate to source
DS(ON)
voltage) and the effective input gate capacitance (Ciss). One
needs to ensure that the combined voltage drop across the
FIGURE 16. OC / WOC OPERATION
Rsense and r
at the desired maximum current
DS(ON)
Bias and Charge Pump Voltages:
(including transients) will still keep the output voltage above
the minimum required level.
The BIAS pin feeds the chip bias voltage directly to the first
of the two internal charge pumps, which are cascaded. The
output of the first charge pump, in addition to feeding the
second charge pump, is accessible on the CPVDD pin. The
voltage on the CPVDD pin is approximately 5V. It also
provides power to the POR and band-gap circuitry as shown
in the block diagram. A capacitor connected externally
across CPQ+ and CPQ- pins of the IC is the “flying” cap for
the charge-pump.
Ciss of the MOSFET influences the overcurrent response
time. It is recommended that a MOSFET with Ciss of less
than 10nF be chosen. Ciss will also have an impact on the
SS cap value selection as seen later.
Current Sense Resistor (R
)
SNS
The voltage drop across this resistor, which represents the
load current (Io), is compared against the set threshold of
the Circuit Breaker comparator. The value of this resistor is
determined by how much combined voltage drop is tolerable
between the source and the load. It is recommended that at
least 20mV drop be allowed across this resistor at max load
current. This resistor is expected to carry maximum full load
The second charge-pump is used exclusively to drive the
gates of the MOSFETs during soft start through the 24µA
current sources, one for each channel. The output of this
charge pump is approximately 10V as shown in the “Block
Diagram” on page 2.
current indefinitely. Hence, the power rating of this resistor
2
Typical Hot-plug Power Up Sequence
must be greater than I
*R
.
SNS
O(MAX)
1. When power is applied to the IC on the BIAS pin, the first
charge pump immediately powers up.
This resistor is typically a low value resistor and hence the
voltage signal appearing across it is also small. In order to
maintain high current sense accuracy, current sense trace
routing is critical. It is recommended that either a four wire
resistor or the routing method as shown in Figure 17 be
used.
2. If the BIAS voltage is 2.1V or higher, the IC comes out of
POR. Both SS and TCB caps remain discharged and the
gate (GT) voltage remains low.
3. ENx pin, when pulled below it’s specified threshold,
enables the respective channel.
4. SSx cap begins to charge up through the internal 10µA
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
same rate as the SS cap voltage. This is tightly controlled
by the soft-start amplifier shown in the block diagram.
5. SS cap begins to charge but the corresponding TCBx cap
is held discharged.
6. Fault (FLT) remains deasserted (stays high) and the
output voltage continues to rise.
FN6830.0
December 19, 2008
10
ISL6174
Time-out Capacitor Selection (C )
T
This capacitor determines the current regulation delay
period. As shown in Figure 2, when the voltage across this
capacitor exceeds 1.178V, the time-out comparator detects it
and the gate voltage is pulled to 0V thus shutting down the
channel. An internal 10µA current source charges this
capacitor. Hence, the value of this capacitor is determined by
Equation 2.
LOAD CURRENT CARRYING
TRACES
(EQ. 2)
C = (10μA • T
) ⁄ 1.178
OUT
CURRENT
SENSE
R
T
SNS
TRACES
Where,
FIGURE 17. RECOMMENDED CURRENT SENSE RESISTOR
PCB LAYOUT
T
= Desired time-out period.
OUT
Soft-Start Capacitor Selection (C
)
SS
The rate of change of voltage (dv/dt) on this capacitor, which
is determined by the internal 10µA current source, is the
same as that on the output load capacitance. Hence, the
value of this capacitor directly controls the inrush current
amplitude during hot swap operation.
Current Set Resistor (R
)
SET
This resistor sets the threshold for the Circuit Breaker
comparator in conjunction with R . Once R has been
SNS SNS
selected, use Equation 1 to calculate R . Use 20µA for
SET
I
in a typical application.
SET
(EQ. 3)
C
= C • (10μA ⁄ I
)
INRUSH
SS
O
Reference Current Set Resistor (R
)
REF
This resistor sets up the current in the internal current
source, I /4, shown in Figure 2 for the comparators. The
Where,
REF
voltage at the OCREF pin is the same as the internal
C
= Load Capacitance
O
bandgap reference. The current (I
resistor is simply:
) flowing through this
REF
I
I
= Desired Inrush Current
INRUSH
INRUSH
is the sum of the DC steady-state load current and
I
= 1.178/R
REF
REF
the load capacitance charging current. If the DC steady-state
load remains disabled until after the soft-start period expires
(PGx could be used as a load enable signal, for example),
then only the capacitor charging current should be used as
This current, I
, should be set at 80µA to force 20µA in the
REF
internal current source as shown in Figure 2, because of the
4:1 current mirror. This equates to the resistor value of
14.7k.
I
. The Css value should always be more than (1/2.4)
INRUSH
of that of Ciss of the MOSFET to ensure proper soft-start
operation. This is because the Ciss is charged from 24µA
current source, whereas the Css gets charged from a 10µA
Selection of Rs1 and Rs2
These resistors set the UV detect point. The UV comparator
detects the undervoltage condition when it sees the voltage
at UV pin drop below 0.633V. The resistor divider values
should be selected accordingly.
current source (Figure 15). In order to make sure both V
SS
and V track during the soft-start, this condition is
O
necessary.
Charge Pump Capacitor Selection (C and C )
P
V
ISL6174 Evaluation Platform
C is the “flying cap” and C is the smoothing cap of the
P
V
The ISL617XEVAL1Z is the primary evaluation board for this
IC. For the BOM, schematic and photograph, see the “BOM
for ISL617XEVAL1Z Board and Schematic” on page 15.
charge pump, which operates at 450kHz set internally. The
output resistance of the charge pump, which affects the
regulation, is dependent on the C value and its ESR,
P
charge-pump switch resistance, and the frequency and ESR
The evaluation board has been designed with a typical
application in mind and with accessibility to all the featured
pins to enable a user to understand and verify these features
of the IC. The two circuit breaker levels are programmed to
2.2A for each input rail but they can easily be scaled up or
down by adjusting some component values.
of the smoothing cap, C .
V
It is recommended that C be kept within 0.022µF
P
(minimum) to 0.1µF (maximum) range. Only ceramic
capacitors are recommended. Use 0.1µF cap if CPVDD
output is expected to power an external circuit, in which case
the current draw from CPVDD must be kept below 10mA.
There are two input voltages, one for each channel that are
switched by a dual N-Channel MOSFET (Q1) to the output
connectors.
C should at least be 0.47µF (ceramic only). Higher values
V
may be used if low ripple performance is desired.
FN6830.0
December 19, 2008
11
ISL6174
Pins SS1 and SS2 of the IC are available as jumper test
points so that they can be tied together to achieve
concurrent tracking between Vo1 and Vo2. Both the EN
inputs must be turned on together to check this function,
jumpers are provide to facilitate this.
GATE
Each channel is preloaded with the resistive load that makes
up the UV threshold level. Additional loading can be
externally applied as desired.
TCB
Iin
The internal Circuit Breaker amplifier is fast enough to
respond to very fast di/dt events.
On this board, the timeout capacitor value for side ‘1’ is
0.15µF, which corresponds to a timeout period of 17.67ms.
The scope shots are taken from the ISL6174EVAL1 to
demonstrate the ISL6174s critical operational waveforms.
FIGURE 19. TRANSIENT TO 3.9A OC CIRCUIT BREAKER
OPERATION
Figure 18 illustrates the circuit breaker operation which will
be evident with a slow ramping output current at the
The way to confirm WOC mode, is by looking at the TCB pin
waveform. If no ramping is seen prior to GATE turn off, then
WOC is active. The following waveform in Figure 20 shows
WOC operation:
programmed 2.2A level, I . This mode of operation will be
CB
invoked while the OC event is < ~2X the I . as shown in
CB
Figure 19. Characteristic of this operational mode is the TCB
pin ramping to V
to establish the circuit breaker delay.
CB
:
GATE
GATE
TCB
TCB
Iin
Iin
FIGURE 20. WOC CIRCUIT BREAKER OPERATION
FIGURE 18. SLOW RAMPING TO 2.2A OC CIRCUIT BREAKER
OPERATION
Figure 21 is a 200X zoom of a WOC turn-off event and
clearly illustrates the lack of any TCB ramping during this
WOC event.
FN6830.0
December 19, 2008
12
ISL6174
GATE
GATE
TCB
TCB
Iin
Iin
FIGURE 21. WOC CIRCUIT BREAKER OPERATION ZOOM
FIGURE 23. TRANSIENT TO 3.9A OC CIRCUIT BREAKER
OPERATION with TCB OPEN
Figure 22 illustrates the GATE response time to an output
short. The time from the input current > 2.2A (I ) to the
CB
FET gate being pulled down is ~0.6µs.
Dual Voltage Tracking During Turn-on
The ISL6174 Dual Circuit Breaker is also designed to
provide either concurrent or ratiometric tracking of the two
output voltages during turn-on. This capability is critical in
providing power to many high value loads.
GATE
The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor, C . In addition, their EN pins also must be tied
Iin
SS
together. Typical Start-up waveforms in this mode are shown
in Figure 24, where the common C value is 0.066µF.
SS
V
O1
FIGURE 22. SHORTED OUTPUT GATE RESPONSE
The previous scope shots illustrate the performance with a
V
O2
~18ms circuit breaker delay, t
as determined by the
CB
10.5µF cap on TCB pin. Figure 23 shows the performance
with an open TCB pin for the same amplitude of OC event as
shown in Figure 19. Once again, see the TCB pin ramp
duration and t
response.
of ~3µs, the intrinsic delay of the IC OC
CB
FIGURE 24. CONCURRENT TRACKING MODE
If one channel experiences a CB event and turns off, the
other one will too.
To achieve ratiometric tracking, the ratio of the two C must
SS
match the ratio of the two voltages being handled. In the
illustrated case in Figure 25, the 1.5V to 3.3V ratio of 1:2.2 is
FN6830.0
December 19, 2008
13
ISL6174
reflected in the choices of C cap values of 0.033µF and
SS
0.072µF. These cap values result in the performance
demonstrated, the variance from a perfect match being the
effect of variance in capacitor values, V and I
SS
SS.
V
O1
V
O2
FIGURE 25. RATIOMETRIC TRACKING MODE
ISL617XEVAL1Z Photograph
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6830.0
December 19, 2008
14
ISL6174
BOM for ISL617XEVAL1Z Board and Schematic
REFERENCE
PART
PKG
MFG P/N
ISL6174DRZ
MANUFACTURER
U1
Circuit Breaker IC
28 Ld 5X5
QFN
Intersil
Q1
FDS6912A
0.033µF
0.15µF
0.47µF
2.2µF
0.1µF
0.022µF
0.22µF
0.01
SO8
0402
0402
FDS6912A or equivalent
Various
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
C1
C2
C7
C3
C5, C9
C6, C11
0402
0402
C10
R7, R13
2512
R1
3.57k
2.55k
14.7k
0
0402
R16
0402
R10
0402
R3
0402
R4, R5, R14, R15
R8, R12
10k
0402
1.1k
0402
R2, R6, R17, R18
1k
0402
J_EN1, EN1-2, J_EN2, JRTR_LTCH, SS1_SS2 Jumper
2 PIN, 0.1”
ISL6174
FN6830.0
December 19, 2008
15
ISL6174
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/07
4X
3.0
5.00
0.50
24X
A
6
B
PIN #1 INDEX AREA
28
22
6
PIN 1
INDEX AREA
1
21
3 .10 ± 0 . 15
15
7
(4X)
0.15
8
14
0.10 M C A B
- 0.07
TOP VIEW
28X 0.55 ± 0.10
BOTTOM VIEW
4
28X 0.25
+ 0.05
SEE DETAIL "X"
C
0.10
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08
C
( 4. 65 TYP )
(
( 24X 0 . 50)
SIDE VIEW
3. 10)
(28X 0 . 25 )
( 28X 0 . 75)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6830.0
December 19, 2008
16
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