ISL61853EIRZ [INTERSIL]

Dual USB Port Power Supply Controller; 双USB端口电源控制器
ISL61853EIRZ
型号: ISL61853EIRZ
厂家: Intersil    Intersil
描述:

Dual USB Port Power Supply Controller
双USB端口电源控制器

光电二极管 控制器
文件: 总20页 (文件大小:394K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Dual USB Port Power Supply Controller  
ISL6185  
Features  
• 2.5V to 5V Operating Range  
The ISL6185 USB power controller family provides  
fully independent overcurrent (OC) fault protection  
for two or more USB ports.  
• 71mΩ Integrated Power P-channel MOSFET Switches  
• Continuous Current Options for 0.6A, 1.1A, 1.5A and  
1.8A  
This product family consists of sixteen individual  
functional product variants and three package options  
and is operation rated for a nominal +2.5V to +5V  
range and specified over the full commercial and  
industrial temperature ranges.  
• Thermally insensitive 12ms of Current Limiting Prior  
to Turn-Off  
• Output Discharges with Reverse Current Blocking  
when Disabled  
Each ISL6185 type incorporates in a single package  
two 71mΩ P-channel MOSFET power switches for  
power control and features internal current  
monitoring, accurate current limiting and current  
limited delay to turn-off for system supply protection  
along with control and communication I/O.  
• Latch-off or Auto Restart Options  
• 1µA Off-State Supply Current.  
• Enable Polarity Options  
• Industry Std Pin for Pin SOIC and Smaller DFN Pkgs  
Available  
The ISL6185 family offers product variants with specified  
continuous output current levels of 0.6A, 1.1A, 1.5A or  
1.8A, enable active high or low inputs and latch off or  
automatic retry after over current turn-off making these  
devices well suited for many low power applications.  
Applications  
• USB 1, 2, 3 Port Power Management  
• Low Power (18W) Electronic Circuit Limiting and  
Breaker  
This family of ICs is offered in an industry std. SOIC  
pinout and also in the 70% smaller 3x3 DFN packages  
providing similar or enhanced performance in the  
smallest possible package.  
Typical Application  
Normalized r  
DS(ON)  
Temperature Characteristic  
D+  
Curve  
D-  
USB  
PORT 1  
1.3  
U
S
B
VBUS  
OUT_1  
ENABLE_1  
FAULT_1  
VIN  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
C
O
N
T
R
O
L
L
E
R
+5V  
GND  
ISL6185  
FAULT_2  
ENABLE_2  
OUT_2  
VBUS  
USB  
PORT_2  
D+  
D-  
-40  
-25  
0
25  
45  
75  
85  
115  
TEMPERATURE (°C)  
USB PORT POWER  
October 22, 2010  
FN6937.0  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2010. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
ISL6185  
Simplified Block Diagram  
CHANNEL 1 LIKE CHANNEL 2  
GND  
VIN  
FAULT_1  
OUT_1  
-
-V  
comp  
+
POR  
EN_1  
EN_2  
CURRENT AND TEMP.  
MONITORING, GATE,  
DELAY & OUTPUT CONTROL  
LOGIC  
OUT_2  
FAULT_2  
Ordering Information  
V
= 5V  
IN  
PART  
MAXIMUM  
NUMBER  
(Notes 1, 2, 3)  
PART  
MARKING  
EN/EN  
INPUT  
CONTINUOUS LATCH/AUTO  
TEMP.  
RANGE (°C)  
PACKAGE  
(Pb-free)  
PKG.  
DWG. #  
IOUT (A)  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
ISL61851ACBZ  
ISL61851BCBZ  
ISL61851CCBZ  
ISL61851DCBZ  
ISL61851ECBZ  
ISL61851FCBZ  
ISL61851GCBZ  
ISL61851HCBZ  
ISL61851ICBZ  
ISL61851JCBZ  
ISL61851KCBZ  
ISL61851LCBZ  
ISL61852ACRZ  
ISL61852BCRZ  
ISL61852CCRZ  
ISL61852DCRZ  
ISL61852ECRZ  
ISL61852FCRZ  
61851A CBZ  
61851B CBZ  
61851C CBZ  
61851D CBZ  
61851E CBZ  
61851F CBZ  
61851G CBZ  
61851H CBZ  
61851I CBZ  
61851J CBZ  
61851K CBZ  
61851L CBZ  
52AC  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
0.6  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
0.6  
1.1  
1.1  
0.6  
0.6  
1.1  
1.1  
1.5  
1.5  
1.5  
1.5  
0.6  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
52BC  
0.6  
52CC  
1.1  
52DC  
1.1  
52EC  
0.6  
52FC  
0.6  
FN6937.0  
October 22, 2010  
2
ISL6185  
Ordering Information(Continued)  
V
= 5V  
IN  
PART  
MAXIMUM  
NUMBER  
(Notes 1, 2, 3)  
PART  
MARKING  
EN/EN  
INPUT  
CONTINUOUS LATCH/AUTO  
TEMP.  
RANGE (°C)  
PACKAGE  
(Pb-free)  
PKG.  
DWG. #  
IOUT (A)  
1.1  
1.1  
1.5  
1.5  
1.5  
1.5  
0.6  
0.6  
1.1  
1.1  
0.6  
0.6  
1.1  
1.1  
1.5  
1.5  
1.5  
1.5  
1.8  
1.8  
1.8  
1.8  
0.6  
0.6  
1.1  
1.1  
0.6  
0.6  
1.1  
1.1  
1.5  
1.5  
1.5  
1.5  
0.6  
0.6  
1.1  
1.1  
0.6  
0.6  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
ISL61852GCRZ  
ISL61852HCRZ  
ISL61852ICRZ  
ISL61852JCRZ  
ISL61852KCRZ  
ISL61852LCRZ  
ISL61853ACRZ  
ISL61853BCRZ  
ISL61853CCRZ  
ISL61853DCRZ  
ISL61853ECRZ  
ISL61853FCRZ  
ISL61853GCRZ  
ISL61853HCRZ  
ISL61853ICRZ  
ISL61853JCRZ  
ISL61853KCRZ  
ISL61853LCRZ  
ISL61853MCRZ  
ISL61853NCRZ  
ISL61853OCRZ  
ISL61853PCRZ  
ISL61851AIBZ  
ISL61851BIBZ  
ISL61851CIBZ  
ISL61851DIBZ  
ISL61851EIBZ  
ISL61851FIBZ  
ISL61851GIBZ  
ISL61851HIBZ  
ISL61851IIBZ  
ISL61851JIBZ  
ISL61851KIBZ  
ISL61851LIBZ  
ISL61852AIRZ  
ISL61852BIRZ  
ISL61852CIRZ  
ISL61852DIRZ  
ISL61852EIRZ  
ISL61852FIRZ  
52GC  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
0 to +70  
0 to +70  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
52HC  
52IC  
0 to +70  
52JC  
0 to +70  
52KC  
0 to +70  
52LC  
0 to +70  
53AC  
0 to +70  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
8 Lead SOIC M8.15  
53BC  
0 to +70  
53CC  
0 to +70  
53DC  
0 to +70  
53EC  
0 to +70  
53FC  
0 to +70  
53GC  
0 to +70  
53HC  
0 to +70  
53IC  
0 to +70  
53JC  
0 to +70  
53KC  
0 to +70  
53LC  
0 to +70  
53MC  
0 to +70  
53NC  
0 to +70  
53OC  
0 to +70  
53PC  
0 to +70  
61851A IBZ  
61851B IBZ  
61851C IBZ  
61851D IBZ  
61851E IBZ  
61851F IBZ  
61851G IBZ  
61851H IBZ  
61851I IBZ  
61851J IBZ  
61851K IBZ  
61851L IBZ  
52AI  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
52BI  
52CI  
52DI  
52EI  
52FI  
FN6937.0  
October 22, 2010  
3
ISL6185  
Ordering Information(Continued)  
V
= 5V  
IN  
PART  
MAXIMUM  
NUMBER  
(Notes 1, 2, 3)  
PART  
MARKING  
EN/EN  
INPUT  
CONTINUOUS LATCH/AUTO  
TEMP.  
RANGE (°C)  
PACKAGE  
(Pb-free)  
PKG.  
DWG. #  
IOUT (A)  
1.1  
1.1  
1.5  
1.5  
1.5  
1.5  
0.6  
0.6  
1.1  
1.1  
0.6  
0.6  
1.1  
1.1  
1.5  
1.5  
1.5  
1.5  
1.8  
1.8  
1.8  
1.8  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
LATCH  
RETRY  
ISL61852GIRZ  
ISL61852HIRZ  
ISL61852IIRZ  
ISL61852JIRZ  
ISL61852KIRZ  
ISL61852LIRZ  
ISL61853AIRZ  
ISL61853BIRZ  
ISL61853CIRZ  
ISL61853DIRZ  
ISL61853EIRZ  
ISL61853FIRZ  
ISL61853GIRZ  
ISL61853HIRZ  
ISL61853IIRZ  
ISL61853JIRZ  
ISL61853KIRZ  
ISL61853LIRZ  
ISL61853MIRZ  
ISL61853NIRZ  
ISL61853OIRZ  
ISL61853PIRZ  
ISL61851EVAL1Z  
ISL61852EVAL1Z  
ISL61853EVAL1Z  
NOTES:  
52GI  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
EN  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
-40 to +85  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
8 Lead DFN  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
L8.3x3J  
52HI  
52II  
52JI  
52KI  
52LI  
53AI  
53BI  
53CI  
53DI  
53EI  
53FI  
53GI  
53HI  
53II  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
10 Lead DFN L10.3x3  
53JI  
53KI  
53LI  
53MI  
53NI  
53OI  
53PI  
8 Lead SOIC Evaluation Platform  
8 Lead DFN Evaluation Platform  
10 Lead DFN Evaluation Platform  
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.  
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach  
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both  
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that  
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6185. For more information on MSL please see  
techbrief TB363.  
FN6937.0  
October 22, 2010  
4
ISL6185  
Pin Configurations  
ISL6185  
(8 LD SOIC/DFN)  
TOP VIEW  
ISL6185  
(10 LD DFN)  
TOP VIEW  
GND  
VIN  
FLT1  
OUT1  
NC  
1
2
3
4
5
10  
9
GND  
VIN  
FLT1  
OUT1  
OUT2  
1
2
3
4
8
7
6
5
(GND)  
EPAD  
DFN Only  
(GND)  
EPAD  
VIN  
8
7
EN1/EN1  
EN2/EN2  
OUT2  
FLT2  
EN1/EN1  
6
EN2/EN2  
FLT2  
Pin Descriptions  
PIN NUMBER  
8 Ld  
SOIC/DFN  
10 Ld  
DFN  
SYMBOL  
GND  
DESCRIPTION  
1
2
1
IC ground reference  
2, 3  
VIN  
Chip bias, Controlled Voltage Input, Undervoltage Lock Out (UVLO). VIN provides chip  
bias voltage. At VIN < 1.7V chip functionality is disabled, FLT is active and floating and  
OUT is held low. Range 0V to 5.5V  
3,  
4
4,  
5
EN1, EN1/  
EN2, EN2  
Enable/Disable inputs, Active high (EN) and active low (EN) options enable the power  
switch. These inputs have internal 1MΩ pull off resistors. Range 0V to VIN  
5,  
8
6,  
10  
FLT2  
FLT1  
Overcurrent Fault Indicator. Overcurrent fault indicator. FLT floats and is disabled until  
VIN >V  
. This output is pulled low after the current limit time-out period has  
expired. Fault is not signaled due to over-temperature shut down. Range 0V to VIN  
UVLO  
6,  
7
7,  
9
OUT2,  
OUT1  
Controlled Supply Output. Upon an OC condition I is current limited. Current limit  
OUT  
response time is within 200µs. This output will remain in current limit for a nominal  
12ms before being turned off either for the latch or auto retry versions. Range 0V to VIN  
-
8
NC  
This pin is not electrically connected internally  
PD  
PD  
EPAD  
Thermal Dissipation Exposed PAD Range: Connect to GND  
(DFN only)  
FN6937.0  
October 22, 2010  
5
ISL6185  
Absolute Maximum Ratings  
Thermal Information  
Supply Voltage (VIN to GND, Note 7) . . . . . . . . . . . . . .6.5V  
EN, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN  
OUT . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VIN 0.3V  
Output Current . . . . . . . . . . . . . . . . Short Circuit Protected  
ESD Rating  
Human Body Model (Per MIL-STD-883 Method 3015.7) 3kV  
Machine Model (Per MIL-STD-883 Method 3015.7). . . 300V  
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . 100mA  
Thermal Resistance (Typical, Note 4) θJA (°C/W) θJC (°C/W)  
8 Lead SOIC Package (Note 4) . . .  
8 Lead 3x3 DFN Package (Notes 5, 6)  
120  
48  
N/A  
6
10 Lead 3x3 DFN Package (Notes 5, 6) 53  
6
Maximum Junction Temperature . . . . . . . . . . . . . . +150°C  
Maximum Storage Temperature Range . . . . -65°C to +150°C  
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below  
http://www.intersil.com/pbfree/Pb-FreeReflow.asp  
Operating Conditions  
Commercial Temperature Range. . . . . . . . . . . 0°C to +70°C  
Industrial Temperature Range . . . . . . . . . . .-40°C to +85°C  
Supply Voltage Range (Typical) . . . . . . . . . . . . 2.3V to 5.5V  
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact  
product reliability and result in failures not covered by warranty.  
NOTES:  
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief  
JA  
TB379 for details.  
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”  
JA  
features. See Tech Brief TB379.  
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.  
JC  
7. All voltages are relative to GND, unless otherwise specified.  
Electrical Specifications  
V
= 5V, T = T , Unless Otherwise Specified. Boldface limits apply over the operating  
A J  
IN  
temperature range, 0°C to +75°C or -40°C to +85°C.  
MIN  
MAX  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
(Note 8) TYP (Note 8) UNITS  
POWER SWITCH  
r
r
r
ON-Resistance at 5.0V  
(Pulse Tested)  
V
= 5V, I  
OUT  
= 0.1A, T = T = +25°C  
-
-
-
-
-
-
-
8
-
-
-
71  
90  
87  
110  
105  
130  
127  
150  
70  
12  
-
mΩ  
mΩ  
mΩ  
mΩ  
mΩ  
mΩ  
mV  
kΩ  
DS(ON)_50  
DS(ON)_33  
DS(ON)_25  
IN  
A
J
T = T = +85°C  
A
J
ON-Resistance at 3.3V  
(Pulse Tested)  
V
= 3.3V, I  
= 0.1A, T = T = +25°C  
IN  
OUT A J  
T = T = +85°C  
A
J
On Resistance at 2.5V  
(Pulse Tested)  
V
= 2.5V, I  
= 0.1A, T = T = +25°C  
114  
IN  
OUT  
A
J
T = T = +85°C  
A
J
V
Disabled Output Voltage  
Output Pull-Down Resistor  
V
= 5V, Switch Disabled, 50µA Load  
= 5V, Switch Disabled  
50  
9.6  
100  
200  
23  
OUT_DIS  
IN  
IN  
R
V
OUT_PU  
t
V
Rise Time  
R = 10Ω, C =10µF, 10% to 90%  
µs  
R
OUT  
L
L
t
Slow V  
Turn-off Fall Time  
Turn-off Fall Time  
R = 10Ω, C =10µF, 90% to 10%  
-
µs  
F
OUT  
OUT  
L
L
t
Fast V  
R = 1Ω, C =10µF, 80% to 20%  
-
µs  
F_fast  
L
L
CURRENT CONTROL  
I
I
I
I
I
I
I
I
Maximum Continuous Current, ISL6185xA,B,E,F  
-
-
-
-
-
-
-
-
0.6  
1.1  
1.5  
1.8  
0.6  
0.9  
1.3  
1.5  
A
A
A
A
A
A
A
A
OUT_CONT_5  
OUT_CONT_5  
OUT_CONT_5  
OUT_CONT_5  
OUT_CONT_3  
OUT_CONT_3  
OUT_CONT_3  
OUT_CONT_3  
V
= 5V.  
IN  
ISL6185xC,D,G,H  
Guaranteed by Itrip minimum  
specification.  
ISL6185xI,J,K,L  
ISL61853M,N,O,P (10 Ld DFN)  
Maximum Continuous Current, ISL6185xA,B,E,F  
V
= 3.3V.  
IN  
ISL6185xC,D,G,H  
Guaranteed by Itrip minimum  
specification.  
ISL61851I,J,K,L (SOIC)  
ISL61852, ISL61853 (DFN)  
FN6937.0  
October 22, 2010  
6
ISL6185  
Electrical Specifications  
V
= 5V, T = T , Unless Otherwise Specified. Boldface limits apply over the operating  
IN  
A
J
temperature range, 0°C to +75°C or -40°C to +85°C. (Continued)  
MIN  
MAX  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
(Note 8) TYP (Note 8) UNITS  
I
I
I
I
I
Maximum Continuous Current, ISL6185xA,B,E,F  
-
0.6  
0.9  
-
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
OUT_CONT_2  
OUT_CONT_2  
OUT_CONT_2  
OUT_CONT_2  
OUT_CONT_2  
V
= 2.5V  
IN  
ISL61851C,D,G,H (SOIC)  
-
-
ISL61852, ISL61853 C,D,G,H (DFN)  
ISL61853I,J,K,L (10 Ld DFN)  
ISL61853M,N,O,P (10 Ld DFN)  
ISL6185xA,B,E,F  
-
1
-
-
1
-
-
1
-
I
I
I
I
I
I
I
I
I
I
I
I
Trip Current, V = 5V  
IN  
0.70  
1.15  
1.55  
1.85  
0.65  
0.95  
1.35  
1.55  
-
1.02  
1.45  
1.82  
1.99  
0.86  
1.25  
1.60  
1.89  
0.65  
1
1.52  
1.95  
2.25  
2.15  
1.20  
1.60  
1.85  
2.25  
-
TRIP_5  
TRIP_5  
TRIP_5  
TRIP_5  
TRIP_3  
TRIP_3  
TRIP_3  
TRIP_3  
TRIP_2  
TRIP_2  
TRIP_2  
TRIP_2  
ISL6185xC,D,G,H  
ISL61853I,J,K,L  
ISL61853M.N,O,P  
Trip Current, V = 3.3V  
IN  
ISL6185xA,B,E,F  
ISL6185xC,D,G,H  
ISL61853I,J,K,L  
ISL61853M.N,O,P  
Trip Current, V = 2.5V  
IN  
ISL6185xA,B,E,F  
ISL6185xC,D,G,H  
-
-
ISL61853I,J,K,L  
-
1.2  
-
ISL61853M.N,O,P  
-
1.6  
-
I
Current Limit, V = 5V  
IN  
ISL6185xA,B,E,F, V - V  
IN OUT  
= 1V  
= 1V  
0.50  
0.98  
1.30  
1.52  
0.45  
0.90  
1.25  
1.48  
0.47  
0.90  
1.15  
1.3  
0.60  
1.00  
1.15  
1.20  
0.35  
0.65  
0.70  
0.90  
-
0.65  
1.14  
1.55  
1.83  
0.63  
1.10  
1.50  
1.78  
0.61  
1.05  
1.37  
1.63  
0.80  
1.27  
1.61  
1.70  
0.48  
0.80  
1.06  
1.24  
0.61  
1.06  
1.30  
1.39  
0.78  
1.28  
1.72  
2.20  
0.75  
1.26  
1.68  
2.05  
0.74  
1.17  
1.58  
1.90  
1.00  
1.55  
1.85  
2.5  
LIM_5  
I
ISL6185xC,D,G,H, V - V  
IN  
LIM_5  
OUT  
I
ISL61853I,J,K,L, V - V  
IN  
= 1V  
LIM_5  
OUT  
I
ISL61853M,N,O,P, V - V  
IN  
= 1V  
= 1V  
= 1V  
LIM_5  
OUT  
I
Current Limit, V = 3.3V  
IN  
ISL6185xA,B,E,F, V - V  
IN OUT  
LIM_3  
I
ISL6185xC,D,G,H, V - V  
IN  
LIM_3  
OUT  
I
ISL61853I,J,K,L, V - V  
IN  
= 1V  
LIM_3  
OUT  
I
ISL61853M,N,O,P, V - V  
IN  
= 1V  
= 1V  
= 1V  
LIM_3  
OUT  
I
Current Limit, V = 2.5V  
IN  
ISL6185xA,B,E,F, V - V  
IN OUT  
LIM_2  
I
ISL6185xC,D,G,H, V - V  
IN  
LIM_2  
OUT  
I
ISL61853I,J,K,L, V - V  
IN  
= 1V  
LIM_2  
OUT  
I
ISL61853M,N,O,P, V - V  
IN  
= 1V  
LIM_2  
OUT  
I
I
I
I
I
I
I
I
I
I
I
I
Short Circuit Current, V = 5V ISL6185xA,B,E,F, V  
IN OUT  
= 0V  
= 0V  
sc_5  
sc_5  
sc_5  
sc_5  
sc_3  
sc_3  
sc_3  
sc_3  
sc_2  
sc_2  
sc_2  
sc_2  
ISL6185xC,D,G,H, V  
OUT  
ISL61853I,J,K,L, V  
= 0V  
OUT  
ISL61853M,N,O,P, V  
ISL6185XA,B,E,F, V  
= 0V  
= 0V  
OUT  
Short Circuit Current,  
= 3.3V  
0.60  
0.95  
1.25  
1.50  
OUT  
V
IN  
ISL6185XC,D,G,H, V  
= 0V  
OUT  
ISL61853I,J,K,L, V  
= 0V  
OUT  
ISL61853M,N,O,P, V  
ISL6185xA,B,E,F, V  
= 0V  
= 0V  
OUT  
Short Circuit Current,  
= 2.5V  
OUT  
V
IN  
ISL6185xC,D,G,H, V  
= 0V  
-
-
-
-
OUT  
ISL61853I,J,K,L, V  
= 0V  
-
OUT  
ISL61853M,N,O,P, V  
= 0V  
-
OUT  
FN6937.0  
October 22, 2010  
7
ISL6185  
Electrical Specifications  
V
= 5V, T = T , Unless Otherwise Specified. Boldface limits apply over the operating  
IN  
A
J
temperature range, 0°C to +75°C or -40°C to +85°C. (Continued)  
MIN  
MAX  
SYMBOL  
tsett  
PARAMETER  
TEST CONDITIONS  
(Note 8) TYP (Note 8) UNITS  
OC to Limit Settling Time  
V
/R = 2I  
, C = 10µF to within 10% of  
-
200  
-
-
µs  
Ilim  
IN  
L
LIM  
L
I
LIM  
tsett  
Ilim_sev  
Severe OC to Limit Settling  
Time  
V
/R = 4I  
, C = 10µF to within 10% of  
L
-
30  
µs  
IN  
L
LIM  
I
LIM  
t
Current Limit Duration  
Automatic Retry Period  
I
= I  
LIM  
9.2  
12  
1
15  
ms  
s
CL  
OUT  
t
0.80  
1.35  
RTY  
I/O PARAMETERS  
Vfault_lo  
Ifault  
Fault Output Voltage  
Fault I  
OUT  
= 10mA  
-
-
-
0.4  
-
V
µA  
V
Fault Leakage  
5
Venr_5  
ENABLE Rising Threshold  
V
= 5V  
1.5  
80  
1.8  
140  
2
IN  
Hys_Venr_5 ENABLE Rising Threshold  
Hysteresis  
V
= 5V  
175  
mV  
IN  
Venr_3  
ENABLE Rising Threshold  
V
= 3.3V  
= 3.3V  
1.0  
58  
1.3  
80  
1.6  
V
IN  
Hys_Venr_3 ENABLE Rising Threshold  
Hysteresis  
V
120  
mV  
IN  
Venr_2  
ENABLE Rising Threshold  
V
= 2.5V  
= 2.5V  
0.95  
30  
1.1  
70  
1.3  
V
IN  
Hys_Venr_2 ENABLE Rising Threshold  
Hysteresis  
V
110  
mV  
IN  
Ren_h  
Ren_l  
ENABLE Pull-Down Resistor  
ENABLE Pull-Up Resistor  
Enable asserted high options  
Enable asserted low options  
0.6  
0.6  
-
1
1
1.55  
1.55  
-
MΩ  
MΩ  
ms  
t
Enable to Output Turn-on Time R = 10Ω, C = 10µF, Enable 50% to Output  
0.1  
ON  
L
L
90%  
t
Enable to Output Turn-off Time R = 10Ω, C = 10µF, Enable 50% to Output  
-
0.25  
-
ms  
OFF  
L
L
10%  
BIAS PARAMETERS  
I
I
Enabled V Current  
IN  
Switches Closed, OUTPUT = OPEN  
Switches Open, OUTPUT = OPEN  
50  
2
75  
5
µA  
µA  
V
VDD  
VDD  
UVLO  
Disabled V Current  
IN  
-
1.7  
200  
-
V
Rising POR Threshold  
POR Hysteresis  
V
Rising to functional operation  
2.1  
360  
2.3  
580  
2
IN  
UV  
HYS  
mV  
µA  
I
Reverse Blocking Leakage  
Current  
V
= 0V, V = 5V  
OUT  
VR  
IN  
Temp_dis  
Temp_hys  
Over-Temperature Disable  
-
-
150  
20  
-
-
°C  
°C  
Over-Temperature Hysteresis  
NOTE:  
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established  
by characterization and are not production tested.  
FN6937.0  
October 22, 2010  
8
ISL6185  
Introduction  
Functional Description  
The ISL6185 is a dual channel fully independent  
overcurrent (OC) fault protection IC for the +2.5V to +5V  
environment. Each ISL6185 incorporates in a single  
package two 85mΩ P-channel MOSFET power switches  
for power control. Independent enabling inputs and fault  
reporting outputs compatible with 2.5V to 5V logic allows  
for external control and reporting. This device features  
integrated power switches with current monitoring,  
accurate current limiting, reverse bias protection and  
current limited timed delay to turn-off for system  
reliability. See Figures 11 through 26 for typical  
operational waveforms including both under and  
overcurrent situations.  
Power On Preset (POR)  
The ISL6185 POR feature inhibits device functionality  
when VIN <V  
.
UVLO  
Reverse Polarity Protection  
In any event where the power switch is disabled and  
V
> V there will be no output to input current flow  
OUT  
IN  
nor will the output voltage appear on the input.  
Soft-Start  
Upon enable, the switch passes a constant current to  
the load. The voltage on the VOUT pin will ramp up  
according the equation: I  
active load will slow the V  
of its curve.  
/C  
(V/s). Resistive or  
ramp up toward the top  
LIM OUT  
The ISL6185 offers current sense and limiting with  
OUT  
V
= 5V guaranteed continuous current product  
IN  
variants of 0.6A, 1.1A, 1.5A and 1.8A making these  
devices well suited for a myriad of USB and other low  
power (9W max) port power management applications  
and configurations.  
Fault Blanking On Start-Up  
During initial turn-on, the ISL6185 prevents nuisance  
faults being reported to the system controller by blanking  
the fault signal until the internal FET is fully enhanced.  
The ISL6185 also provides a thermally insensitive timed  
OC turn-off and fault notification, isolating and protecting  
the voltage bus in the event of a peripheral OC event or  
short circuit event independent of the adjoining switch’s  
electrical or the ambient thermal condition.  
Current Trip and Limiting Levels  
The ISL6185 provides integrated current sensing in the  
MOSFET that allows for rapid control of OC events. Once  
an OC condition is detected the ISL6185 goes into its  
current limiting (CL) control mode. The ISL6185 is  
variant specified to allow a continuous current (I  
operation of 0.6A, 1.1A, 1.5A or 1.8A. As the current  
increases past its continuous current rating it will reach a  
level that causes the device to enter its current limit  
mode, that is the current trip level. The current trip level  
is in all cases adequately above the I  
not cause unintended false faults. The current limit is  
The ISL6185 undervoltage lockout feature prevents  
turn-on of the outputs unless the correct ENABLE  
)
CONT  
state and V > V  
turn-on the ISL6185 prevents fault reporting by  
are present. During initial  
IN  
UVLO  
blanking the fault signal.  
During operation, once an OC condition is detected  
rating as to  
CONT  
the output is current limited for t to allow transient  
CL  
OC conditions to pass. If still in current limit after the  
current limit period has elapsed, the output is then  
turned off and the fault is reported by pulling the  
corresponding FAULT output low. On the latch off  
options, after turn-off both the output and the FAULT  
signal are latched low until reset by the enable signal  
being de-asserted or a POR occurs at which time the  
FAULT signal will clear and the switch is ready to be  
turned back on. On the auto restart options the  
ISL6185 will attempt to periodically turn-on the  
output as long as the enable is asserted.  
specified at V = V - 1V to test a known  
OUT IN  
representative condition and is featured at a nominal  
value slightly higher than the continuous current rating.  
The speed of this current limiting control is inversely  
related to the magnitude of the OC fault. Thus a hard  
overcurrent is more quickly pulled to its limiting value  
than a marginal OC condition.  
Over-Temperature Shutdown  
Although the ISL6185 has an over-temperature  
shutdown and lockout feature, because of the 12ms  
timed shutdown the thermal shutdown is likely only to be  
invoked in extremely high ambient temperatures.  
When disabled the ISL6185 has a low quiescent supply  
current and output to input reverse current flow blocking  
capability.  
The over- temperature protection invokes and disables  
the switch turn-on operation once the die temperature is  
~+140°C, it will turn off an already on switch at  
~+150°C and releases the part to operation once the die  
temperature falls to ~+120°C.  
The ISL6185 family is provided with enable polarity  
options and an industry standard 8 lead SOIC pinout  
along with two versions in the 70% smaller 3x3 DFN. The  
8 Ld DFN package offers the same performance as the  
8 Ld SOIC whereas the 10 Ld DFN offers higher current  
capability in the smallest possible package because of  
lower package electrical and thermal resistance.  
FN6937.0  
October 22, 2010  
9
ISL6185  
reset by the enable signal being de-asserted at which  
Turn-off Time Delay  
time the FAULT signal will clear and the IC is ready for  
enable to assert. On the auto restart options the  
ISL6185 will attempt to periodically turn-on the  
output at approximately 1s intervals as long as the  
enable is asserted. If the OC condition remains  
indefinitely so will the fault indication and the restart  
attempts until such time that the thermal protection  
feature is invoked increasing the restart period.  
During operation, once an OC condition is detected  
the output is current limited for ~12ms to allow  
transient OC conditions to pass. If still in current limit  
and after the current limit period has elapsed, the  
output is then turned off and the fault is reported by  
pulling the corresponding FAULT low. The internal  
12ms timer starts upon current limiting and is  
independent of ambient or IC thermal conditions  
providing more consistent operation over the entire  
temp range.  
Active Output Pull-down  
Another ISL6185 feature is the 10kΩ active pull-down on  
the outputs to <60mV above GND when the device is  
disabled ensuring discharge of the load.  
Latchoff Restart/Auto-Restart Start  
After turn-off, with the latch off options both the  
output and the FAULT signal are latched low until  
Typical Performance Curves  
150  
140  
130  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
V
= 2.5V  
= 3.3V  
IN  
120  
110  
100  
90  
V
IN  
80  
70  
V
= 5V  
115  
IN  
60  
50  
-40 -25  
0
25  
45  
75  
85  
-40  
-25  
0
25  
45  
75  
85  
115  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 1. SWITCH ON-RESISTANCE AT 0.5A  
FIGURE 2. NORMALIZED SWITCH RESISTANCE  
1.6  
1.5  
1.2  
5V I  
TRIP  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
5V I  
TRIP  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
5V I  
SC  
3.3V I  
TRIP  
3.3V I  
TRIP  
5V I  
LIM  
5V I  
5V I  
SC  
3.3V I  
LIM  
LIM  
3.3V I  
LIM  
3.3V I  
85  
SC  
3.3V I  
75 85  
SC  
115  
-40 -25  
0
25  
45  
-40 -25  
0
25  
45  
75  
115  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 4. 1.1A CONTINUOUS CURRENT  
CHARACTERISTICS  
FIGURE 3. 0.6A CONTINUOUS CURRENT  
CHARACTERISTICS  
FN6937.0  
October 22, 2010  
10  
ISL6185  
Typical Performance Curves (Continued)  
2.0  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
5V I  
TRIP  
1.8 5V I  
TRIP  
3.3V I  
TRIP  
3.3V I  
5V I  
TRIP  
SC  
1.6  
1.4  
1.2  
1.0  
0.8  
5V I  
SC  
5V I  
3.3V I  
LIM  
LIM  
5V I  
LIM  
3.3V I  
LIM  
3.3V I  
3.3V I  
SC  
SC  
-40 -25  
0
25  
45  
75  
85  
115  
-40  
-25  
0
25  
45  
75  
85  
115  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 5. 1.5A CONTINUOUS CURRENT  
CHARACTERISTICS  
FIGURE 6. 1.8A CONTINUOUS CURRENT  
CHARACTERISTICS  
0.75  
1.25  
0.6A CONTINUOUS I  
OUT  
VERSION  
1.1A CONTINUOUS I  
VERSION  
OUT  
+3 SIGMA  
0.70  
0.65  
0.60  
0.55  
0.50  
1.20  
1.15  
1.10  
1.05  
1.00  
+3 SIGMA  
TYPICAL  
-3 SIGMA  
TYPICAL  
-3 SIGMA  
-40 -25  
0
25  
45  
75  
85  
115  
-40  
-25  
0
25  
45  
75  
85  
115  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 7. LIMITING CURRENT ±3 SIGMA, V  
IN  
= 5V  
FIGURE 8. LIMITING CURRENT ±3 SIGMA, V = 5V  
IN  
1.65  
2.00  
1.8A CONTINUOUS I  
VERSION  
1.5A CONTINUOUS I  
VERSION  
OUT  
OUT  
1.95  
1.90  
1.85  
1.80  
1.75  
1.70  
1.65  
1.60  
+3 SIGMA  
1.60  
1.55  
1.50  
1.45  
1.40  
1.35  
+3 SIGMA  
TYPICAL  
TYPICAL  
-3 SIGMA  
-3 SIGMA  
-40  
-25  
0
25  
45  
75  
85  
115  
-40 -25  
0
25  
45  
75  
85  
115  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 10. LIMITING CURRENT ±3 SIGMA, V =5V  
IN  
FIGURE 9. LIMITING CURRENT ±3 SIGMA, V  
= 5V  
IN  
FN6937.0  
October 22, 2010  
11  
ISL6185  
Typical Performance Curves (Continued)  
ENABLE  
ENABLE  
C =1µF  
L
C =10µF  
L
C =10µF  
L
V
OUT  
1V/DIV  
C =100µF  
L
C =100µF  
L
VOUT  
1V/DIV  
C =1µF  
L
FIGURE 11. V  
TURN-ON/RISE TIME vs C  
.
FIGURE 12. V  
TURN-OFF/FALL TIME  
OUT  
OUT  
LOAD  
V
= 5V, R = 10Ω  
vs C  
. V  
= 5V, R = 10Ω  
IN  
L
LOAD  
IN L  
0.6A I  
VARIANT  
CONT  
FLT  
C =10µF  
L
V
V
OUT  
OUT  
1V/DIV  
C =100µF  
L
I
IN  
C =1µF  
L
FIGURE 13. LATCH-OFF vs C  
FIGURE 14. I  
VARIANT  
WAVEFORM  
LIM  
LOAD  
0.6A I  
VARIANT  
0.6A I  
CONT  
CONT  
2A OC 27µs  
6A/ms  
0.6A/ms  
1A OC 57µs  
0.08A/ms  
0.5A OC 200µs  
0.72A CURRENT LIMIT  
0.53A LOAD CURRENT  
0.66A CURRENT LIMIT  
0.56A LOAD CURRENT  
I
2A/DIV  
IN  
FIGURE 16. PEAK CURRENT SETTLING TIMES  
FIGURE 15. OC RAMP RATE I  
WAVEFORMS  
LIM  
FN6937.0  
October 22, 2010  
12  
ISL6185  
Typical Performance Curves (Continued)  
ENABLE  
ENABLE  
0.6A I  
VARIANT  
V
CONT  
OUT  
0.6A I  
CONT  
VARIANT  
FAULT  
FAULT  
I
IN  
LIMITED TO 0.64A  
I
IN  
V
OUT  
FIGURE 18. TURN-ON INTO MOMENTARY OC  
FIGURE 17. TURN-ON INTO A SHORT  
1.1A I  
VARIANT  
FLT  
CONT  
V
OUT  
FLT  
V
OUT  
I
IN  
I
IN  
FIGURE 19. ISL6185 RETRY FUNCTION  
FIGURE 20. I  
WAVEFORM  
LIM  
ENABLE  
FAULT  
ENABLE  
FAULT  
V
OUT  
V
OUT  
Iin  
I
1.8A I  
VARIANT  
IN  
CONT  
1.8A I  
VARIANT  
CONT  
FIGURE 21. V  
= 2.5V TURN-ON INTO 2.2Ω  
FIGURE 22. V  
= 5V TURN-ON INTO 2.7Ω  
IN  
IN  
FN6937.0  
October 22, 2010  
13  
ISL6185  
Typical Performance Curves (Continued)  
CH1 and CH2 ON  
(3.6A TOTAL I  
I
IN  
)
IN  
ENABLE  
FAULT  
V
OUT  
CH1 ON  
(1.8A)  
I
IN  
LIMITED TO 1.7A  
ENABLE  
FAULT  
1.8A I  
1.8A ICONT VARIANT  
VARIANT  
V
CONT  
OUT  
FIGURE 24. TURN-ON 2ND OUTPUT TO FULL LOAD  
FIGURE 23. TURN-ON INTO A SHORT  
1.1A I  
VARIANT  
FLT  
CONT  
V
OUT  
FLT  
V
OUT  
I
IN  
I
IN  
FIGURE 25. ISL6185 RETRY FUNCTION  
FIGURE 26. PROPAGATION DELAY AND OUTPUT TRANSITION TIMES  
FIGURE 26. I  
WAVEFORM  
LIM  
Test Circuits  
-
+
V
10k  
10k  
FLT  
OUTPUT  
sized  
for desired  
OC level  
FLT  
5V  
VIN  
EN  
OUT  
ISL6185  
R
L
5V  
OUTPUT  
VIN  
OUT  
10µF  
10  
10µF  
ISL6185  
EN  
10  
R
L
r
= V/(VOUT/10Ω)  
DS(ON)  
FIGURE 27B. CURRENT LIMITING  
FIGURE 27. DC TEST CIRCUIT  
FIGURE 27A. r  
DS(ON)  
FN6937.0  
October 22, 2010  
14  
ISL6185  
Test Circuits(Continued)  
VIN  
0V  
EN  
0.5VIN  
0.5VIN  
OFF  
10k  
t
t
ON  
FLT  
OUT  
ISL6185  
VIN  
90%  
5V  
OUTPUT  
VIN  
EN  
OUTPUT  
10µF  
10%  
0-V  
IN  
GND  
10  
VIN  
90%  
90%  
OUTPUT  
10%  
10%  
t
-GND  
t
R
F
FIGURE 28A. TRANSIENT TEST CIRCUIT  
FIGURE 29. TRANSIENT WAVEFORM MEASUREMENT  
POINTS  
ISL6185xEVAL1Z Schematic and Photo  
R1  
FLT1  
OUT1  
10k  
R3  
10  
AGND  
C2  
FLT1  
AGND  
U1  
V+  
EN1  
OUT1  
OUT2  
A
10µF  
V+  
A
ISL6185  
R4  
FLT2  
OUT2  
EN2  
A
10  
C3  
A
A
10µF  
R2  
FLT2  
10k  
NOTE: EXPOSED PAD only on DFN packages  
FIGURE 30A. ISL6185xEVAL SCHEMATIC  
FIGURE 30B. ISL61851EVAL1Z BOARD PHOTO  
FIGURE 30. ISL6185xEVAL1Z SCHEMATIC and ISL61851EVAL1Z PHOTOGRAPH  
FN6937.0  
October 22, 2010  
15  
ISL6185  
Application Information  
Using the ISL6185xEVAL1Z Platform  
General and Biasing Information  
Application Considerations  
The application considerations for the ISL6185 family are  
widely accepted best industry practices. Good decoupling  
practices on the VIN pin must be followed with placement  
close to the IC with at least 2.2µF being recommended.  
Work to reduce the input and output inductance to the  
ISL6185 with good PCB layout practices.  
There are three (3) evaluation platforms for the ISL6185  
family. There is one (1) for each package style, each with  
a different continuous output current level and a mix of  
enable polarity and output retry or latch options. See the  
bottom of Table 1 for standard available evaluation board  
options. Figure 30A, illustrates the common schematic  
for all of the evaluation boards, consult the individual  
package pinouts for those differences.  
When designing with the 1.5A and 1.8A versions in an  
implementation where the output may be unloaded  
(open) while the ISL6185 is turned on, a minimum of  
4.7µF of capacitive output load is recommended to  
prevent high dv/dt from unnecessarily activating the  
surge/ESD control circuit.  
The evaluation platform is biased and monitored through  
numerous labeled test points. See Table 1 for test point  
assignments and descriptions.  
The ISL6185 provides several continuous current rated  
TABLE 1. ISL61851EVAL1Z TEST POINT ASSIGNMENTS  
devices specified at V = 5V, these are 0.6A, 1.1A, 1.5A  
and 1.8A options capable over the entire temperature  
IN  
TP NAME  
GND  
DESCRIPTION  
Eval Board and IC Gnd  
extreme. At V = 3.3V the current capability is  
IN  
degraded and the ISL6185 is specified at 0.6A, 1.1A,  
V+  
Eval Board and IC Bias  
Enable Switch 1  
Enable Switch 2  
Switch 2 Fault  
1.3A and 1.5A respectively. At V = 2.5V there are no  
IN  
min specifications but a typical value is provided for  
+25°C operation in the specification table. This degraded  
EN1  
EN2  
capability is due to the higher r  
at the lower bias voltage.  
of the FET switch  
DS(ON)  
FLT2  
The enhanced thermal characteristics and increased  
number of bond wires allows the 10 Ld DFN to have a  
higher current capability than either the 8 Ld SOIC or  
DFN.  
OUT2  
OUT1  
FLT1  
Switch Out 2  
Switch Out 1  
Switch 1 Fault  
TABLE 2. ISL6185XEVAL1Z BOARD COMPONENT  
LISTING  
Upon proper bias and of the evaluation platform and  
correct enabling of the IC the ISL6185 will have a  
COMPONENT  
DESIGNATOR  
COMPONENT  
FUNCTION  
COMPONENT  
DESCRIPTION  
nominal V /10Ω load current passing through each  
IN  
enabled switch which is below the continuous current  
rating. See Figures 11 and 12 for typical ISL6185 turn-on  
and off waveforms.  
U1  
ISL6185  
Intersil, ISL6185  
R3 - R4  
Output Load  
Resistors  
10Ω, 5%, 3W  
External current loading in excess of the trip current level  
for the particular part being evaluated will result in the  
ISL6185 entering the current limiting mode. Figure 14  
illustrates the current limiting mode for the ISL6185  
product variants with 0.6A of continuous load current  
rating. The scope shot shows current limiting for ~12ms  
before it is turned off and the fault signal is asserted.  
R1 - R2  
C1  
FLT Output pull 10kΩ, 0805  
up resistor  
Decoupling  
Capacitor  
2.2µF, 0805  
C2 - C3  
Load Capacitor  
10µF 16V Electrolytic,  
Radial Lead  
FN6937.0  
October 22, 2010  
16  
ISL6185  
Revision History  
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to  
web to make sure you have the latest Rev.  
DATE  
REVISION  
CHANGE  
10/22/10  
FN6937.0  
Initial release.  
Products  
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The  
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,  
handheld products, and notebooks. Intersil's product families address power management and analog signal  
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.  
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device  
information page on intersil.com: ISL6185  
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff  
FITs are available from our website at http://rel.intersil.com/reports/search.php  
FN6937.0  
October 22, 2010  
17  
ISL6185  
Package Outline Drawing  
L8.3x3J  
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE  
Rev 0 9/09  
2X 1.950  
3.00  
A
6X 0.65  
B
5
8
(4X)  
0.15  
1.64 +0.10/ - 0.15  
6
PIN 1  
INDEX AREA  
6
PIN #1 INDEX AREA  
4
1
4
8X 0.30  
0.10 M C A B  
8X 0.400 ± 0.10  
TOP VIEW  
2.38  
+0.10/ - 0.15  
BOTTOM VIEW  
SEE DETAIL "X"  
( 2.38 )  
( 1.95)  
C
0.10  
C
Max 1.00  
0.08  
C
SIDE VIEW  
( 8X 0.60)  
(1.64)  
( 2.80 )  
PIN 1  
5
C
0 . 2 REF  
(6x 0.65)  
0 . 00 MIN.  
0 . 05 MAX.  
( 8 X 0.30)  
DETAIL "X"  
TYPICAL RECOMMENDED LAND PATTERN  
NOTES:  
1. Dimensions are in millimeters.  
Dimensions in ( ) for Reference Only.  
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.  
3.  
Unless otherwise specified, tolerance : Decimal ± 0.05  
4. Dimension applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
Tiebar shown (if present) is a non-functional feature.  
5.  
6.  
The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
FN6937.0  
October 22, 2010  
18  
ISL6185  
Package Outline Drawing  
L10.3x3  
10 LEAD DUAL FLAT PACKAGE (DFN)  
Rev 6, 09/09  
6
3.00  
A
B
PIN #1 INDEX AREA  
1
2
6
PIN 1  
INDEX AREA  
10 x 0.23  
4
(4X)  
0.10  
1.60  
10x 0.35  
4
TOP VIEW  
BOTTOM VIEW  
C A B  
M
0.10  
(4X)  
0.415  
0.23  
PACKAGE  
OUTLINE  
0.35  
SEE DETAIL "X"  
0.10  
(10 x 0.55)  
(10x 0.23)  
C
C
BASE PLANE  
0.20  
SEATING PLANE  
0.08 C  
SIDE VIEW  
(8x 0.50)  
5
0.20 REF  
0.05  
C
1.60  
TYPICAL RECOMMENDED LAND PATTERN  
DETAIL "X"  
NOTES:  
1. Dimensions are in millimeters.  
Dimensions in ( ) for Reference Only.  
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.  
3. Unless otherwise specified, tolerance : Decimal ± 0.05  
4. Lead width applies to the metallized terminal and is measured  
between 0.18mm and 0.30mm from the terminal tip.  
Tiebar shown (if present) is a non-functional feature.  
5.  
6.  
The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 indentifier may be  
either a mold or mark feature.  
FN6937.0  
October 22, 2010  
19  
ISL6185  
Small Outline Plastic Packages (SOIC)  
M8.15 (JEDEC MS-012-AA ISSUE C)  
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE  
N
INDEX  
AREA  
0.25(0.010)  
M
B M  
H
INCHES MILLIMETERS  
E
SYMBOL  
MIN  
MAX  
MIN  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
MAX  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
NOTES  
-B-  
A
A1  
B
C
D
E
e
0.0532  
0.0040  
0.013  
0.0688  
0.0098  
0.020  
-
-
1
2
3
L
9
SEATING PLANE  
A
0.0075  
0.1890  
0.1497  
0.0098  
0.1968  
0.1574  
-
-A-  
3
h x 45°  
D
4
-C-  
0.050 BSC  
1.27 BSC  
-
α
H
h
0.2284  
0.0099  
0.016  
0.2440  
0.0196  
0.050  
5.80  
0.25  
0.40  
6.20  
0.50  
1.27  
-
e
A1  
C
5
B
0.10(0.004)  
L
6
0.25(0.010) M  
C
A M B S  
N
α
8
8
7
NOTES:  
0°  
8°  
0°  
8°  
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  
Publication Number 95.  
Rev. 1 6/05  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate burrs.  
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006  
inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions. Inter-  
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per  
side.  
5. The chamfer on the body is optional. If it is not present, a visual index  
feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater  
above the seating plane, shall not exceed a maximum value of  
0.61mm (0.024 inch).  
10. Controlling dimension: MILLIMETER. Converted inch dimensions  
are not necessarily exact.  
For additional products, see www.intersil.com/product_tree  
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted  
in the quality certifications found at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications  
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by  
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any  
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any  
patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN6937.0  
October 22, 2010  
20  

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