ISL6208CRZ-T [INTERSIL]
High Voltage Synchronous Rectified Buck MOSFET Driver; 高电压同步整流降压MOSFET驱动器
| 型号： | ISL6208CRZ-T |
| 厂家： | 
Intersil |
| 描述： | High Voltage Synchronous Rectified Buck MOSFET Driver |
| 文件： | 总10页 (文件大小：325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6208
®
Data Sheet
March 2004
FN9115
High Voltage Synchronous Rectified Buck
MOSFET Driver
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Adaptive Shoot-Through Protection
• 0.5Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency up to 2MHz
- Fast Output Rise and Fall Time
- Low Propagation Delay
• Three-State PWM Input for Power Stage Shutdown
• Internal Bootstrap Schottky Diode
The ISL6208 is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology. It is
especially suited for mobile computing applications that
require high efficiency and excellent thermal performance.
This driver, combined with an Intersil multiphase Buck PWM
controller, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.
• Low Bias Supply Current (5V, 80µA)
The ISL6208 features 4A typical sinking current for the lower
gate driver. This current is capable of holding the lower
MOSFET gate off during the rising edge of the Phase node.
This prevents shoot-through power loss caused by the high
dv/dt of phase voltages. The operating voltage matches the
30V breakdown voltage of the MOSFETs commonly used in
mobile computer power supplies.
• Diode Emulation for Enhanced Light Load Efficiency and
Pre-Biased Startup Applications
• VCC POR (Power-On-Reset) Feature Integrated
• Low Three-State Shutdown Holdoff Time (Typical 160ns)
• Pin-to-pin Compatible with ISL6207
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
The ISL6208 also features a three-state PWM input that,
working together with Intersil’s multiphase PWM controllers,
will prevent negative voltage output during CPU shutdown.
This feature eliminates a protective Schottky diode usually
seen in a microprocessor power systems.
• Lead-Free Available as an Option
Applications
• Core Voltage Supplies for Intel® and AMD® Mobile
Microprocessors
• High Frequency Low Profile DC-DC Converters
• High Current Low Output Voltage DC-DC Converters
• High Input Voltage DC-DC Converters
MOSFET gates can be efficiently switched up to 2MHz using
the ISL6208. Each driver is capable of driving a 3000pF load
with propagation delays of 8ns and transition times under
10ns. Bootstrapping is implemented with an internal
Schottky diode. This reduces system cost and complexity,
while allowing the use of higher performance MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.
Ordering Information
TEMP. RANGE
(°C)
PKG.
A diode emulation feature is integrated in the ISL6208 to
enhance converter efficiency at light load conditions. This
feature also allows for monotonic start-up into pre-biased
outputs. When diode emulation is enabled, the driver will
allow discontinuous conduction mode by detecting when the
inductor current reaches zero and subsequently turning off
the low side MOSFET gate.
PART NUMBER
ISL6208CB
PACKAGE
DWG. #
-10 to 100
-10 to 100
8 Ld SOIC
M8.15
M8.15
ISL6208CBZ (Note)
8 Ld SOIC
(Lead-Free)
ISL6208CB-T
8 Ld SOIC Tape and Reel
ISL6208CBZ-T (Note) 8 Ld SOIC Tape and Reel (Lead-Free)
ISL6208CR
-10 to 100
-10 to 100
8 Ld 3x3 QFN L8.3x3
Related Literature
ISL6208CRZ (Note)
8 Ld 3x3 QFN L8.3x3
(Lead-Free)
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
ISL6208CR-T
8 Ld 3x3 QFN Tape and Reel
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for MLFP Packages”
ISL6208CRZ-T (Note) 8 Ld 3x3 QFN Tape and Reel (Lead-Free)
NOTE: Intersil Lead-Free products employ special lead-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which is compatible with both SnPb
and lead-free soldering operations. Intersil Lead-Free products are
MSL classified at lead-free peak reflow temperatures that meet or
exceed the lead-free requirements of IPC/JEDEC J Std-020B.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6208
Pinouts
ISL6208CB
(8 LD SOIC)
TOP VIEW
ISL6208CR
(8 LD 3x3 QFN)
TOP VIEW
UGATE
BOOT
PWM
1
2
3
4
8
7
6
5
PHASE
FCCM
VCC
7
4
8
3
BOOT
PWM
1
2
6 FCCM
GND
LGATE
5 VCC
2
ISL6208
ti
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Thermal Information
Thermal Resistance (Typical Notes 2, 3, 4) θ (°C/W)
SOIC Package (Note 2) . . . . . . . . . . . .
QFN Package (Notes 3, 4). . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
θ
(°C/W)
n/a
15
JA
JC
BOOT Voltage (V
Phase Voltage (V
FCCM PWM
UGATE. . . . . . . . . . . . . . . . . . . . . . V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to 125°C
). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V
BOOT
110
80
) (Note 1). . . V
- 7V to V
+ 0.3V
PHASE
BOOT BOOT
Input Voltage (V
, V
) . . . . . . . . . . . . -0.3V to VCC + 0.3V
- 0.3V to V
BOOT
+ 0.3V
PHASE
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-10°C to 100°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
2. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
POR
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
PWM pin floating, V
FCCM
= 5V
-
80
-
-
µA
VCC
-
-
Vcc Rising
-
2.40
-
3.40
2.90
500
3.90
V
V
Vcc Falling
-
-
Hysteresis
mV
BOOTSTRAP DIODE
Forward Voltage
V
V
= 5V, forward bias current = 2mA
0.40
0.52
0.60
V
F
VCC
PWM INPUT
Input Current
I
V
V
V
V
V
= 5V
-
250
-250
1.00
3.8
-
µA
µA
V
PWM
PWM
PWM
VCC
VCC
VCC
= 0V
-
-
PWM Three-State Rising Threshold
PWM Three-State Falling Threshold
Three-State Shutdown Holdoff Time
FCCM INPUT
= 5V
0.70
3.5
100
1.30
4.1
250
= 5V
V
t
= 5V, temperature = 25°C
175
ns
TSSHD
FCCM LOW Threshold
FCCM HIGH Threshold
SWITCHING TIME
0.50
-
-
-
-
V
V
2.0
UGATE Rise Time
t
t
V
V
V
V
= 5V, 3nF Load
= 5V, 3nF Load
= 5V, 3nF Load
= 5V, 3nF Load
-
-
-
-
8.0
8.0
8.0
4.0
-
-
-
-
ns
ns
ns
ns
RU
VCC
VCC
VCC
VCC
LGATE Rise Time
t
RL
UGATE Fall Time
FU
LGATE Fall Time
t
FL
3
ISL6208
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
= 5V, Outputs Unloaded
= 5V, Outputs Unloaded
= 5V, Outputs Unloaded
= 5V, Outputs Unloaded
= 5V, Outputs Unloaded
MIN
TYP
35
MAX
UNITS
ns
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
UG/LG Three-state Propagation Delay
Minimum LG On TIME in DCM (Note 5)
OUTPUT
t
V
V
V
V
V
-
-
-
-
-
-
-
-
-
-
-
-
PDLU
VCC
VCC
VCC
VCC
VCC
t
35
ns
PDLL
t
20
ns
PDHU
t
20
ns
PDHL
t
35
ns
PTS
t
400
ns
LGMIN
Upper Drive Source Resistance
Upper Driver Source Current (Note 5)
Upper Drive Sink Resistance
R
500mA Source Current
= 2.5V
-
-
-
-
-
-
-
-
1
2.5
-
Ω
A
Ω
A
Ω
A
Ω
A
U
U
I
V
2.00
1
U
UGATE-PHASE
500mA Sink Current
= 2.5V
R
2.5
-
Upper Driver Sink Current (Note 5)
Lower Drive Source Resistance
Lower Driver Source Current (Note 5)
Lower Drive Sink Resistance
I
V
2.00
1
U
UGATE-PHASE
500mA Source Current
= 2.5V
R
2.5
-
L
I
V
2.00
0.5
4.00
L
LGATE
500mA Sink Current
V = 2.5V
LGATE
R
1.0
-
L
Lower Driver Sink Current (Note 5)
I
L
NOTE:
5. Guaranteed by design, not tested.
4
ISL6208
continuous conduction mode is forced. See the Diode
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
Emulation section under DESCRIPTION for more detail.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
Description
Theory of Operation
Designed for speed, the ISL6208 dual MOSFET driver
controls both high-side and low-side N-Channel FETs from
one externally provided PWM signal.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation (see
the three-state PWM Input section under DESCRIPTION for
further details). Connect this pin to the PWM output of the
controller.
delay [t
], the lower gate begins to fall. Typical fall times
PDLL
[t ] are provided in the Electrical Specifications section.
FL
Adaptive shoot-through circuitry monitors the LGATE
voltage. When LGATE has fallen below 1V, UGATE is
allowed to turn ON. This prevents both the lower and upper
MOSFETs from conducting simultaneously, or shoot-
through.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin for the IC.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
] is encountered before the upper
PDLU
gate begins to fall [t ]. The upper MOSFET gate-to-source
FU
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
voltage is monitored, and the lower gate is allowed to rise
after the upper MOSFET gate-to-source voltage drops below
1V. The lower gate then rises [t ], turning on the lower
MOSFET.
RL
FCCM (Pin 7 for SOIC-8, Pin 6 for QFN)
The FCCM pin enables or disables Diode Emulation. When
FCCM is LOW, diode emulation is allowed. Otherwise,
VCC
BOOT
FCCM
UGATE
PHASE
SHOOT-
THROUGH
PROTECTION
CONTROL
LOGIC
VCC
PWM
LGATE
GND
10K
THERMAL PAD (FOR QFN PACKAGE ONLY)
FIGURE 1. BLOCK DIAGRAM
5
ISL6208
Typical Application - Two Phase Converter Using ISL6208 Gate Drivers
V
BAT
+5V
+5V
VCC
+V
CORE
BOOT
+5V
FB
COMP
UGATE
FCCM
PWM
VCC
VSEN
PHASE
DRIVE
PWM1
PWM2
ISL6208
PGOOD
LGATE
THERMAL
PAD
FCCM
MAIN
CONTROL
ISEN1
VID
V
BAT
ISEN2
+5V
VCC
BOOT
FS
DACOUT
GND
FCCM
PWM
UGATE
PHASE
DRIVE
ISL6208
LGATE
THERMAL
PAD
Timing Diagram
2.5V
t
PWM
PDHU
t
t
PDLU
TSSHD
t
t
RU
RU
t
t
FU
FU
t
PTS
1V
UGATE
LGATE
t
PTS
1V
t
RL
t
FL
t
TSSHD
t
PDHL
t
PDLL
t
FL
This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement.
The 0.5Ω on-resistance and 4A sink current capability
enable the lower gate driver to absorb the current injected to
the lower gate through the drain-to-gate capacitor of the
lower MOSFET and prevent a shoot through caused by the
high dv/dt of the phase node.
6
ISL6208
Typical Performance Waveforms
FIGURE 2. LOAD TRANSIENT (0 - 30A, 3-PHASE)
FIGURE 3. LOAD TRANSIENT (30 - 0A, 3-PHASE)
FIGURE 5. CCM TO DCM TRANSITION AT NO LOAD
FIGURE 7. PRE-BIASED STARTUP IN DCM MODE
FIGURE 4. DCM TO CCM TRANSITION AT NO LOAD
FIGURE 6. PRE-BIASED STARTUP IN CCM MODE
7
ISL6208
Diode Emulation
2.0
1.8
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6208 will detect the zero current crossing of the output
inductor and turn off LGATE. This ensures that
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
discontinuous conduction mode (DCM) is achieved. Diode
emulation is asynchronous to the PWM signal. Therefore,
the ISL6208 will respond to the FCCM input immediately
after it changes state. Refer to the waveforms on page 7.
Q
= 100nC
GATE
NOTE: Intersil does not recommend Diode Emulation use with
r
current sensing topologies. The turn-OFF of the low side
DS(ON)
MOSFET can cause gross current measurement inaccuracies.
20nC
Three-State PWM Input
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
A unique feature of the ISL6208 and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
∆V (V)
BOOT_CAP
FIGURE 8. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate-to-source voltage during
UGATE turn-off. Once the upper MOSFET gate-to-source
voltage has dropped below a threshold of 1V, the LGATE is
allowed to rise.
P = f (1.5V Q + V Q ) + I V
VCC
CC
(EQ. 2)
sw
U
L
U
L
where f is the switching frequency of the PWM signal. V
sw
U
and V represent the upper and lower gate rail voltage. Q
L
L
U
and Q is the upper and lower gate charge determined by
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage rating
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be chosen from the following equation:
MOSFET selection and any external capacitance added to
the gate pins. The lV
V
product is the quiescent power
CC CC
of the driver and is typically negligible.
1000
Q
L
=50nC
Q
=100nC
U
U
L
Q
=50nC
U
L
Q =100nC
Q =200nC
900
800
700
600
500
400
300
200
100
0
Q =50nC
Q
∆V
GATE
-----------------------
C
≥
(EQ. 1)
BOOT
BOOT
Q
=20nC
U
L
Q =50nC
where Q
is the amount of gate charge required to fully
GATE
charge the gate of the upper MOSFET. The ∆V
term is
BOOT
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q
GATE
, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125µF is required.
The next larger standard value capacitance is 0.15µF. A
good quality ceramic capacitor is recommended.
0
200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 9. POWER DISSIPATION vs FREQUENCY
8
ISL6208
Quad Flat No-Lead Plas tic Package (QFN)
L8.3x3
8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VEEC ISSUE C)
MILLIMETERS
SYMBOL
MIN
0.80
NOMINAL
0.90
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
-
-
-
-
-
-
9
0.20 REF
0.28
9
0.23
0.25
0.25
0.38
1.25
1.25
5, 8
D
3.00 BSC
2.75 BSC
1.10
-
D1
D2
E
9
7, 8
3.00 BSC
2.75 BSC
1.10
-
E1
E2
e
9
7, 8
0.65 BSC
-
k
0.25
0.35
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
8
2
2
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
9
ISL6208
Small Outline Plas tic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
0.25(0.010)
M
B M
H
AREA
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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