ISL6210_技术文档

ISL6210

®

Data Sheet

November 28, 2006

FN6392.0

PRELIMINARY

Dual Synchronous Rectified MOSFET

Drivers

Features

• 5V Quad N-Channel MOSFET Drives for Two

Synchronous Rectified Bridges

The ISL6210 integrates two ISL6208A drivers and is

optimized to drive two independent power channels in a

synchronous-rectified buck converter topology. These

drivers combined with an Intersil ISL62xx multiphase PWM

controller forms a complete single-stage core-voltage

regulator solution with high efficiency performance at high

switching frequency for advanced microprocessors.

• Adaptive Shoot-Through Protection

- Active Gate Threshold Monitoring

- Programmable Dead-Time

• 0.4Ω On-Resistance and 4A Sink Current Capability

• Supports High Switching Frequency

- Fast Output Rise and Fall

The IC is biased by a single low voltage supply (5V),

minimizing driver switching losses in high MOSFET gate

capacitance and high switching frequency applications.

Each driver is capable of driving a 3nF load with less than

10ns rise/fall time. Bootstrapping of the upper gate driver is

implemented via an internal low forward drop diode,

reducing implementation cost, complexity, and allowing the

use of higher performance, cost effective N-Channel

MOSFETs. Adaptive shoot-through protection is integrated

to prevent both MOSFETs from conducting simultaneously.

- Ultra Low Three-State Hold-Off Time (20ns)

• Low V Internal Bootstrap Diode

F

• Low Bias Supply Current

• Power-On Reset

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat

No Leads-Product Outline

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile

The ISL6210 features 4A typical sink current for the lower

gate driver, enhancing the lower MOSFET gate hold-down

capability during PHASE node rising edge, preventing power

loss caused by the self turn-on of the lower MOSFET due to

the high dV/dt of the switching node.

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Core Voltage Supplies for Intel® and AMD®

Microprocessors

The ISL6210 also features an input that recognizes a high-

impedance state, working together with Intersil multiphase

PWM controllers to prevent negative transients on the

controlled output voltage when operation is suspended. This

feature eliminates the need for the schottky diode that may

be utilized in a power system to protect the load from

negative output voltage damage.

• High Frequency Low Profile High Efficiency DC/DC

Converters

• High Current Low Voltage DC/DC Converters

• Synchronous Rectification for Isolated Power Supplies

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

Ordering Information

PART

NUMBER

(Note)

TEMP.

RANGE

(°C)

PART

MARKING

PACKAGE

(Pb-Free)

PKG.

DWG. #

• Technical Brief 400 and Technical Brief 417 for Power

Train Design, Layout Guidelines, and Feedback

Compensation Design

ISL6210CRZ

62 10CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4

ISL6210CRZ-T 62 10CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4

• Technical Brief 447 “Guidelines for Preventing Boot-to-

Phase Stress on Half-Bridge MOSFET Driver ICs”

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.

ISL6210

Pinout

ISL6210

(16 LD 4X4 QFN)

TOP VIEW

16 15 14 13

GND

LGATE1

PVCC

1

2

3

4

12 UGATE1

11 BOOT1

10 BOOT2

GND

FCCM

9

UGATE2

5

6

7

8

Block Diagram

ISL6210

EN

PVCC

BOOT1

FCCM

VCC

UGATE1

PHASE1

CHANNEL 1

SHOOT-

THROUGH

4.25K

4K

PROTECTION

PVCC

PWM1

LGATE1

PGND

CONTROL

LOGIC

VCC

PVCC

BOOT2

4.25K

4K

UGATE2

PWM2

GND

PHASE2

SHOOT-

THROUGH

PROTECTION

CHANNEL 2

PVCC

LGATE2

PGND

PAD

THE PAD ON THE BOTTOM SIDE OF THE QFN PACKAGE

MUST BE SOLDERED TO THE CIRCUIT’S GROUND.

FN6392.0

November 28, 2006

2

ISL6210

Typical Application - Multiphase Converter Using ISL6210 Gate Drivers

BOOT1

+5V

+12V

UGATE1

PHASE1

VCC

FCCM

LGATE1

PVCC

EN

DUAL

DRIVER

ISL6210

+5V

BOOT2

+12V

COMP

V

FB

CC

VSEN

UGATE2

PHASE2

ISEN1

PWM1

PWM2

PGOOD

EN

PWM2

ISEN2

LGATE2

MAIN

PAD

CONTROL

ISL62xx

PGND

GND

VID

+V

CORE

ISEN3

PWM3

PWM4

FCCM

+5V

BOOT1

+12V

GND

ISEN4

UGATE1

PHASE1

VCC

LGATE1

PVCC

FCCM

DUAL

DRIVER

ISL6210

+5V

EN

BOOT2

+12V

UGATE2

PHASE2

PWM1

PWM2

LGATE2

PAD

GND

PGND

FN6392.0

November 28, 2006

3

ISL6210

Absolute Maximum Ratings

Thermal Information

Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

Input Voltage (V , V ) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V

Thermal Resistance (Notes 1 and 2)

QFN Package. . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

θ

(°C/W)

46

θ

(°C/W)

8.5

JA

JC

EN PWM

BOOT Voltage (V

). . . -0.3V to 33V (DC) or 36V (<200ns)

BOOT-GND

BOOT To PHASE Voltage (V

). . . . . . -0.3V to 7V (DC)

-0.3V to 9V (<10ns)

BOOT-PHASE

PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V (DC)

GND -8V (<20ns Pulse Width, 10μJ)

UGATE Voltage . . . . . . . . . . . . . . . . V

- 0.3V (DC) to V

PHASE

BOOT

- 5V (<20ns Pulse Width, 10μJ) to V

BOOT

V

PHASE

LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V

GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V

Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C

HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV

Recommended Operating Conditions

Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +100°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

JA

2. θ , “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.

JC

Electrical Specifications These specifications apply for T = -10°C to +100°C, Unless Otherwise Noted

A

PARAMETER

SUPPLY CURRENT

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Bias Supply Current

POWER-ON RESET

POR Rising

I

PWM pin floating, V

= 5V

VCC

-

170

-

μA

VCC

-

2.6

-

3.4

3.0

400

4.2

V

POR Falling

-

Hysteresis

mV

BOOTSTRAP DIODE

Forward Voltage Drop

PWM INPUT

V

= 5V, forward bias current = 2mA

0.3

0.60

0.7

V

F

VCC

Sinking Impedance

Source Impedance

Three-State Rising Threshold

Three-State Falling Threshold

Three-State Shutdown Holdoff Time

R

8.0

8.3

1.08

3.4

-

10.4

10.6

1.3

15

25

1.5

3.98

-

kΩ

V

PWM_SNK

PWM_SRC

V

= 5V

VCC

3.65

80

V

t

or t

PDLL

+ Gate Falling Time

ns

TSSHD

PDLU

Three-state to UG/LG Rising Propagation

Delay

t

-

20

-

PTS

SWITCHING TIME (See Figure 1)

UGATE Rise Time (Note 3)

t

V

= 5V, 3nF Load

-

8.0

4.0

20

-

ns

RU

VCC

LGATE Rise Time (Note 3)

t

= 5V, 3nF Load

RL

UGATE Fall Time (Note 3)

= 5V, 3nF Load

FU

LGATE Fall Time (Note 3)

t

= 5V, 3nF Load

FL

UGATE Turn-Off Propagation Delay

LGATE Turn-Off Propagation Delay

UGATE Turn-On Propagation Delay

LGATE Turn-On Propagation Delay

t

= 5V, Outputs Unloaded

= 5V, Outputs Unloaded; R

PDLU

t

27

PDLL

t

= 0Ω

26

PDHU

SET

t

26

PDHL

FN6392.0

November 28, 2006

4

ISL6210

Electrical Specifications These specifications apply for T = -10°C to +100°C, Unless Otherwise Noted (Continued)

A

PARAMETER

UGATE Turn-On Propagation Delay

LGATE Turn-On Propagation Delay

Minimum LGATE On Time in DCM (Note 3)

OUTPUT

SYMBOL

TEST CONDITIONS

= 5V, Outputs Unloaded; R

MIN

TYP

41

MAX

UNITS

ns

t

V

= 80kΩ

-

PDHU

VCC

SET

t

33

ns

PDHL

t

400

ns

LGMIN

Upper Drive Source Resistance (Note 3)

Upper Drive Source Current (Note 3)

Upper Drive Sink Resistance (Note 3)

Upper Drive Sink Current (Note 3)

Lower Drive Source Resistance (Note 3)

Lower Drive Source Current (Note 3)

Lower Drive Sink Resistance (Note 3)

Lower Drive Sink Current (Note 3)

NOTE:

R

250mA Source Current

V = 2.5V

-

1.0

2.00

1.0

2.5

-

Ω

A

Ω

A

Ω

A

Ω

A

UG_SRC

I

UG_SCR

UGATE-PHASE

250mA Sink Current

= 2.5V

R

2.5

-

UG_SNK

I

V

2.00

1.0

UG_SNK

UGATE-PHASE

250mA Source Current

= 2.5V

R

-

2.5

-

LG_SRC

I

V

2.00

0.4

LG_SCR

LGATE

250mA Sink Current

= 2.5V

R

1.0

-

LG_SNK

I

V

4.00

LG_SNK

LGATE

3. Guaranteed by Characterization. Not 100% tested in production.

Functional Pin Description

NUMBER

NAME

FUNCTION

1

2

3

GND

Bias and reference ground. All signals are referenced to this node.

LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.

PVCC This pin supplies power to both the lower and higher gate drives in ISL6614. Its operating range is +5V to 12V. Place a high

quality low ESR ceramic capacitor from this pin to GND.

4

FCCM Logic control input that will force continuous conduction mode (HIGH state) or allow discontinuous conduction mode

(LOW state). Placing a series resistor in this input will allow the switching dead-time to be programmed.

5

6

7

8

PGND It is the power ground return of both low gate drivers.

LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.

EN

Logic control input that will enable (HIGH state) or disable (LOW state) the IC. Shutdown current is <1μA.

PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin

provides a return path for the upper gate drive.

9

UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.

10

BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin and

the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap

Device section under DESCRIPTION for guidance in choosing the capacitor value.

11

BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin and

the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap

Device section under DESCRIPTION for guidance in choosing the capacitor value.

12

13

UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.

PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin

provides a return path for the upper gate drive.

14

15

VCC

Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic

capacitor from this pin to GND.

PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation, see

the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller.

16

PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation, see

the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller.

N/A

PAD

Connect this pad to the power ground plane (GND) via thermally enhanced connection.

FN6392.0

November 28, 2006

5

ISL6210

Timing Diagram

2.5V

t

PWM

PDHU

t

PDLU

TSSHD

t

RU

t

FU

t

PTS

1V

UGATE

LGATE

t

PTS

1V

t

RL

t

TSSHD

t

PDHL

t

PDLL

FL

FIGURE 1. TIMING DIAGRAM

the lower gate through the drain-to-gate capacitor of the

lower MOSFET and prevent a shoot through caused by the

high dv/dt of the phase node.

Description

Theory of Operation

Designed for speed, the ISL6210 dual MOSFET driver

controls both high-side and low-side N-Channel FETs for two

separate channels of a Multiphase PWM system from two

independent PWM signals.

Diode Emulation

Diode emulation allows for higher converter efficiency under

light-load situations. With diode emulation active, the

ISL6210 will detect the zero current crossing of the output

inductor and turn off LGATE. This ensures that

discontinuous conduction mode (DCM) is achieved. Diode

emulation is asynchronous to the PWM signal. Therefore,

the ISL6210 will respond to the FCCM input immediately

after it changes state.

A rising edge on PWM initiates the turn-off of the lower

MOSFET (see Timing Diagram). After a short propagation

delay [t

], the lower gate begins to fall. Typical fall times

PDLL

[t ] are provided in the Electrical Specifications section.

FL

Adaptive shoot-through circuitry monitors the LGATE

voltage. When LGATE has fallen below 1V, UGATE is

allowed to turn ON. This prevents both the lower and upper

MOSFETs from conducting simultaneously, or shoot-

through.

NOTE: Intersil does not recommend Diode Emulation use with

r

current sensing topologies. The turn-OFF of the low side

DS(ON)

MOSFET can cause gross current measurement inaccuracies.

Three-State PWM Input

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

A unique feature of the ISL6210 and other Intersil drivers is

the addition of a shutdown window to the PWM input. If the

PWM signal enters and remains within the shutdown window

for a set holdoff time, the output drivers are disabled and

both MOSFET gates are pulled and held low. The shutdown

state is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the ELECTRICAL SPECIFICATIONS

determine when the lower and upper gates are enabled.

propagation delay [t

] is encountered before the upper

PDLU

gate begins to fall [t ]. The upper MOSFET gate-to-source

FU

voltage is monitored, and the lower gate is allowed to rise

after the upper MOSFET gate-to-source voltage drops below

1V. The lower gate then rises [t ], turning on the lower

RL

MOSFET.

This driver is optimized for converters with large step down

compared to the upper MOSFET because the lower

MOSFET conducts for a much longer time in a switching

period. The lower gate driver is therefore sized much larger

to meet this application requirement.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection

to prevent upper and lower MOSFETs from conducting

simultaneously and shorting the input supply. This is

accomplished by ensuring the falling gate has turned off one

MOSFET before the other is allowed to turn on.

The 0.5Ω on-resistance and 4A sink current capability

enable the lower gate driver to absorb the current injected to

FN6392.0

November 28, 2006

6

ISL6210

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a 1V threshold, at which time the

UGATE is released to rise. Adaptive shoot-through circuitry

monitors the upper MOSFET gate-to-source voltage during

UGATE turn-off. Once the upper MOSFET gate-to-source

voltage has dropped below a threshold of 1V, the LGATE is

allowed to rise.

50

45

40

35

30

25

20

15

10

5

t

DELAY

In addition to gate threshold monitoring, a programmable

delay between MOSFET switching can be accomplished by

placing a resistor in series with the FCCM input. This delay

allows for maximum design flexibility over MOSFET

selection. The delay can be programmed from 5ns to 50ns

and is obtained from the absolute value of the current

flowing into the FCCM pin. If no resistor is used, the

0

minimum 5ns delay is selected. Gate threshold monitoring is

not affected by the addition or removal of the additional

dead-time. Refer to Figure 2 and Figure 3 for more detail.

0

167

333

500

667

833

1000

R

(kΩ)

DELAY

FIGURE 3. ISL6210 PROGRAMMABLE DEAD-TIME vs

DELAY RESISTOR

FCCM = VCC or GND

The equation governing the dead-time seen in Figure 3 is

expressed as:

GATE B

GATE A

(EQ. 1)

T

= [0.045 × R

] + 5ns

DELAY(kΩ)

DELAY(ns)

The equation can be rewritten to solve for R

follows:

as

DELAY

ADAPTIVE SHOOT-THROUGH

PROTECTION

(T

– 5ns)

DELAY(ns)

------------------------------------------------------

(kΩ) =

R

(EQ. 2)

DELAY

0.045

1V

Internal Bootstrap Diode

This driver features an internal bootstrap diode. Simply

adding an external capacitor across the BOOT and PHASE

pins completes the bootstrap circuit.

FCCM = RESISTOR to VCC or GND

GATE B

GATE A

The following equation helps select a proper bootstrap

capacitor size:

ADAPTIVE PROTECTION

WITH DELAY

Q

GATE

-------------------------------------

C

≥

BOOT_CAP

ΔV

BOOT_CAP

(EQ. 3)

T

= 5n - 50ns

DELAY

Q

• PVCC

G1

-----------------------------------

Q

=

• N

Q1

1V

GATE

V

GS1

where Q is the amount of gate charge per upper MOSFET

G1

at V

gate-source voltage and N is the number of

GS1

Q1

control MOSFETs. The ΔV

BOOT_CAP

term is defined as the

FIGURE 2. PROGRAMMABLE DEAD-TIME

allowable droop in the rail of the upper gate drive.

As an example, suppose two IRLR7821 FETs are chosen as

the upper MOSFETs. The gate charge, Q , from the data

G

sheet is 10nC at 4.5V (V ) gate-source voltage. Then the

GS

Q

is calculated to be 22nC at PVCC level. We will

GATE

assume a 200mV droop in drive voltage over the PWM

cycle. We find that a bootstrap capacitance of at least

0.110μF is required. The next larger standard value

FN6392.0

November 28, 2006

7

ISL6210

capacitance is 0.22µF. A good quality ceramic capacitor is

recommended.

where the gate charge (Q and Q ) is defined at a

G2

G1

particular gate to source voltage (V

and V

) in the

GS1

GS2

corresponding MOSFET data sheet; I is the driver’s total

2.0

1.8

Q

quiescent current with no load at both drive outputs; N

Q1

and N are number of upper and lower MOSFETs,

Q2

1.6

1.4

1.2

1.0

0.8

respectively. The I

V

product is the quiescent power of

Q

CC

the driver without capacitive load and is typically negligible.

The total gate drive power losses are dissipated among the

resistive components along the transition path. The drive

resistance dissipates a portion of the total gate drive power

losses, the rest will be dissipated by the external gate

Q

= 100nC

0.6

0.4

0.2

0.0

GATE

resistors (R and R , should be a short to avoid

G1 G2

interfering with the operation shoot-through protection

circuitry) and the internal gate resistors (R and R ) of

20nC

GI1

GI2

MOSFETs. Figures 5 and 6 show the typical upper and lower

gate drives turn-on transition path. The power dissipation on

the driver can be roughly estimated as:

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

ΔV (V)

BOOT_CAP

FIGURE 4. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

P

= P

+ P

+ I • VCC

(EQ. 6)

DR

DR_UP

DR_LOW

Q

R

P

Qg_Q1

Power Dissipation

⎛

⎞

HI1

LO1

-------------------------------------- --------------------------------------- ---------------------

P

=

+

•

⎜

⎝

⎟

DR_UP

R

+ R

R

+ R

EXT1

2

⎠

Package power dissipation is mainly a function of the

HI1

EXT1

LO1

switching frequency (F ), the output drive impedance, the

SW

R

P

Qg_Q2

⎛

⎜

⎝

⎞

HI2

LO2

external gate resistance, and the selected MOSFET’s

internal gate resistance and total gate charge. Calculating

the power dissipation in the driver for a desired application is

critical to ensure safe operation. Exceeding the maximum

allowable power dissipation level will push the IC beyond the

maximum recommended operating junction temperature of

125°C. The maximum allowable IC power dissipation for the

SO14 package is approximately 1W at room temperature,

while the power dissipation capacity in the QFN packages,

with an exposed heat escape pad, is around 2W. See Layout

Considerations paragraph for thermal transfer improvement

suggestions. When designing the driver into an application, it

is recommended that the following calculation is used to

ensure safe operation at the desired frequency for the

selected MOSFETs. The total gate drive power losses due to

the gate charge of MOSFETs and the driver’s internal

circuitry and their corresponding average driver current can

be estimated with Equations 4 and 5, respectively,

-------------------------------------- --------------------------------------- ---------------------

P

R

=

+

•

⎟

DR_LOW

R

+ R

R

+ R

⎠

EXT2

2

HI2

EXT2

LO2

R

GI1

GI2

-------------

= R

+

R

= R +

G2

EXT2

G1

EXT2

N

Q1

Q2

PVCC

BOOT

D

C

GD

R

HI1

G

C

DS

R

LO1

R

GI1

C

G1

UGATE

PHASE

GS

Q1

S

FIGURE 5. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

PVCC

(EQ. 4)

P

= P

+ P

+ I • VCC

Q

Qg_TOT

Qg_Q1

Qg_Q2

2

D

Q

• PVCC

G1

C

GD

--------------------------------------

P

=

• F

• N

Qg_Q1

SW

Q1

V

LGATE

GS1

R

HI2

G

C

DS

2

Q

• PVCC

G2

R

LO2

R

GI2

C

G2

--------------------------------------

P

=

• F

• N

Qg_Q2

Q2

V

GS2

GS

Q2

S

GND

Q

• N

Q

• N

G2 Q2

V

GS2

⎛

⎜

⎝

⎞

⎟

⎠

G1

V

Q1

(EQ. 5)

----------------------------- -----------------------------

I

=

+

• F

+ I

Q

DR

SW

GS1

FIGURE 6. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

FN6392.0

November 28, 2006

8

ISL6210

A good layout would help reduce the ringing on the phase

and gate nodes significantly:

Layout Considerations

Reducing Phase Ring

• Avoid uses via for decoupling components across BOOT

and PHASE pins and in between VCC and GND pins. The

decoupling loop should be short.

The parasitic inductances of the PCB and the power devices

(both upper and lower FETs) could cause serious ringing,

exceeding absolute maximum rating of the devices. The

negative ringing at the edges of the PHASE node could add

charges to the bootstrap capacitor through the internal

bootstrap diode, in some cases, it could cause over stress

across BOOT and PHASE pins. Therefore, user should do a

careful layout and select proper MOSFETs and drivers. The

• All power traces (UGATE, PHASE, LGATE, GND, VCC)

should be short and wide, and avoid using via; otherwise,

use two vias for interconnection when possible.

• Keep SOURCE of upper FET and DRAIN of lower FET as

close as thermally possible.

2

D PAK and DPAK package MOSFETs have high parasitic

• Keep connection in between SOURCE of lower FET and

power ground wide and short.

lead inductance, which can exacerbate this issue. FET

selection plays an important role in reducing PHASE ring. If

higher inductance FETs must be used, a Schottky diode is

recommended across the lower MOSFET to clamp negative

PHASE ring.

• Input capacitors should be placed as close to the DRAIN

of upper FET and SOURCE of lower FETs as thermally

possible.

NOTE: Refer to Intersil Tech Brief TB447 for more information.

Thermal Management

For maximum thermal performance in high current, high

switching frequency applications, connecting the thermal

pad of the QFN part to the power ground with multiple vias is

recommended. This heat spreading allows the part to

achieve its full thermal potential.

FN6392.0

November 28, 2006

9

ISL6210

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.23

1.95

0.28

0.35

2.25

5, 8

D

4.00 BSC

-

D1

D2

E

3.75 BSC

9

2.10

7, 8

4.00 BSC

-

E1

E2

e

3.75 BSC

9

2.10

7, 8

0.65 BSC

-

k

0.25

0.50

-

L

0.60

0.75

0.15

8

L1

N

-

16

4

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 5 5/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6392.0

November 28, 2006

10


型号：	ISL6210
厂家：	Intersil
描述：	Dual Synchronous Rectified MOSFET Drivers 双同步整流MOSFET驱动器驱动器
文件：	总10页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6210 [INTERSIL]

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