ISL6236IRZA [INTERSIL]
High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook Computers; 高效率，四路输出，主电源控制器，用于笔记本电脑
| 型号： | ISL6236IRZA |
| 厂家： | 
Intersil |
| 描述： | High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook Computers |
| 文件： | 总36页 (文件大小：3155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6236
®
Data Sheet
February 1, 2007
FN6373.2
High-Efficiency, Quad-Output, Main Power
Supply Controllers for Notebook
Computers
Features
• Wide Input Voltage Range 5.5V to 25V
• Dual Fixed 1.05V/3.3V and 1.5V/5.0V Outputs or
Adjustable 0.7V to 5.5V (SMPS1) and 0V to 2.5V
(SMPS2), ±1.5% Accuracy
The ISL6236 dual step-down, switch-mode power-supply
(SMPS) controller generates logic-supply voltages in
battery-powered systems. The ISL6236 include two
• Secondary Feedback Input (Maintains Charge Pump
Voltage)
pulse-width modulation (PWM) controllers, 5V/3.3V and
1.5V/1.05V. The output of SMPS1 can also be adjusted from
0.7V to 5.5V. The SMPS2 output can be adjusted from 0V to
2.5V by setting REFIN2 voltage. An optional external charge
pump can be monitored through SECFB. This device feature
a linear regulator providing 3.3V/5V, or adjustable from 0.7V to
4.5V output via LDOREFIN. The linear regulator provides up
to 100mA output current with automatic linear-regulator
bootstrapping to the BYP input. When in switchover, the LDO
output can source up to 200mA. The ISL6236 includes
on-board power-up sequencing, the power-good (POK )
outputs, digital soft-start, and internal soft-stop output
discharge that prevents negative voltages on shutdown.
• 1.7ms Digital Soft-Start and Independent Shutdown
• Fixed 3.3V/5.0V, or Adjustable Output 0.7V to 4.5V,
±1.5% (LDO): 200mA
• 3.3V Reference Voltage ±2.0%: 5mA
• 2.0V Reference Voltage ±1.0%: 50µA
• Constant ON-TIME Control with 100ns Load-Step
Response
• Frequency Selectable
• r
Current Sensing
DS(ON)
A constant on-time PWM control scheme operates without
sense resistors and provides 100ns response to load
transients while maintaining a relatively constant switching
frequency. The unique ultrasonic pulse-skipping mode
maintains the switching frequency above 25kHz, which
eliminates noise in audio applications. Other features include
pulse skipping, which maximizes efficiency in light-load
applications, and fixed-frequency PWM mode, which reduces
RF interference in sensitive applications.
• Programmable Current Limit with Foldback Capability
• Selectable PWM, Skip or Ultrasonic Mode
• BOOT Voltage Monitor with Automatic Refresh
• Independent POK1 and POK2 Comparators
• Soft-Start with Pre-Biased Output and Soft-Stop
• Independent ENABLE
• High Efficiency - up to 97%
Ordering Information
• Very High Light Load Efficiency (Skip Mode)
• 5mW Quiescent Power Dissipation
TEMP.
PART
NUMBER
PART
MARKING
RANGE
(°C)
PKG.
DWG. #
PACKAGE
• Thermal Shutdown
ISL6236IRZA
(Note)
ISL6236 IRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B
(Pb-free)
• Extremely Low Component Count
• Pb-Free Plus Anneal Available (RoHS Compliant)
ISL6236IRZA-T ISL6236 IRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B
(Note)
(Pb-free)
(Tape and Reel)
Applications
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• Notebook and Sub-Notebook Computers
• PDAs and Mobile Communication Devices
• 3-Cell and 4-Cell Li+ Battery-Powered Devices
• DDR1, DDR2, and DDR3 Power Supplies
• Graphic Cards
• Game Consoles
• Telecommunications
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL6236
Pinout
ISL6236
(32 LD 5x5 QFN)
TOP VIEW
32 31 30 29 28 27 26 25
REF
TON
BOOT2
LGATE2
PGND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
EN LDO
VREF3
VIN
GND
SECFB
PVCC
LDO
LGATE1
BOOT1
LDOREFIN
9
10 11 12 13 14 15 16
FN6373.2
February 1, 2007
2
ISL6236
Absolute Voltage Ratings
Thermal Information
VIN, EN LDO to GND. . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +27V
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
VCC, EN, SKIP#, TON,
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°CW)
3.0
JA
JC
32 Ld QFN (Notes 1, 2) . . . . . . . . . . . . 32
Operating Temperature Range . . . . . . . . . . . . . . . .-40°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
PVCC, POK to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
LDO, FB1, REFIN2, LDOREFIN to GND . . . -0.3V to (VCC + 0.3V)
OUT, SECFB, VREF3, REF to GND . . . . . . . . -0.3V to (VCC + 0.3V
UGATE to PHASE . . . . . . . . . . . . . . . . . . . . -0.3V to (PVCC + 0.3V)
ILIM to GND. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V)
LGATE, BYP to GND . . . . . . . . . . . . . . . . . . -0.3V to (PVCC + 0.3V)
PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
LDO, REF, VREF3 Short Circuit to GND . . . . . . . . . . . .Continuous
VCC Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1s
LDO Current (Internal Regulator) Continuous . . . . . . . . . . . . 100mA
LDO Current (Switched Over to OUT1) Continuous . . . . . . +200mA
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications No load on LDO, OUT1, OUT2, V
, and REF, V = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
REF3 IN
VEN_LDO = 5V, T = -40°C to +100°C, unless otherwise noted. Typical values are at T = +25°C.
A
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MAIN SMPS CONTROLLERS
V
Input Voltage Range
LDO in regulation
5.5
4.5
25
V
V
V
V
IN
V
V
V
= LDO, VOUT1 <4.43V
5.5
IN
IN
IN
3.3V Output Voltage in Fixed Mode
1.05V Output Voltage in Fixed Mode
= 5.5V to 25V, REFIN2 > (VCC - 1V), SKIP# = 5V
3.285
1.038
3.330
1.05
3.375
1.062
= 5.5V to 25V, 3.0 < REFIN2 < (VCC - 1.1V),
SKIP# = 5V
1.5V Output Voltage in Fixed Mode
5V Output Voltage in Fixed Mode
FB1 in Output Adjustable Mode
REFIN2 in Output Adjustable Mode
SECFB Voltage
V
V
V
V
V
= 5.5V to 25V, FB1 = VCC, SKIP# = 5V
= 5.5V to 25V, FB1 = GND, SKIP# = 5V
= 5.5V to 25V
1.482
4.975
0.693
0.7
1.500
5.050
0.700
1.518
5.125
0.707
2.50
V
V
V
V
V
V
V
%
IN
IN
IN
IN
IN
= 5.5V to 25V
= 5.5V to 25V
1.920
0.70
0.50
-1.0
2.00
2.080
5.50
SMPS1 Output Voltage Adjust Range
SMPS2 Output Voltage Adjust Range
SMPS1
SMPS2
2.50
SMPS2 Output Voltage Accuracy
(Referred for REFIN2)
REFIN2 = 0.7V to 2.5V, SKIP# = VCC
1.0
DC Load Regulation
Either SMPS, SKIP# = VCC, 0 to 5A
Either SMPS, SKIP# = REF, 0 to 5A
Either SMPS, SKIP# = GND, 0 to 5A
Either SMPS, 6V < VIN < 24V
Temperature = +25°C
-0.1
-1.7
-1.5
0.005
5
%
%
%
Line Regulation
%/V
µA
V
Current-Limit Current Source
ILIM Adjustment Range
4.75
0.2
93
5.25
2
Current-Limit Threshold (Positive, Default) ILIM = VCC, GND - PHASE
(No temperature compensation)
100
107
mV
FN6373.2
February 1, 2007
3
ISL6236
Electrical Specifications No load on LDO, OUT1, OUT2, V
, and REF, V = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
REF3 IN
VEN_LDO = 5V, T = -40°C to +100°C, unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
A
PARAMETER
Current-Limit Threshold
CONDITIONS
MIN
40
TYP
50
MAX
60
UNITS
mV
mV
mV
mV
mV
ms
kHz
kHz
kHz
kHz
kHz
kHz
µs
GND - PHASE
V
= 0.5V
= 1V
ILIM
ILIM
ILIM
(Positive, Adjustable)
V
V
93
100
200
3
107
215
= 2V
185
Zero-Current Threshold
SKIP# = GND, REF, or OPEN, GND - PHASE
Current-Limit Threshold (Negative, Default) SKIP# = VCC, GND - PHASE
-120
1.7
Soft-Start Ramp Time
Operating Frequency
Zero to full limit
(V
= GND), SKIP# = VCC
SMPS 1
SMPS 2
SMPS 1
SMPS 2
SMPS 1
SMPS 2
400
500
400
300
200
300
tON
(V
= REF or OPEN),
tON
SKIP# = VCC
(V
= VCC), SKIP# = VCC
tON
On-Time Pulse Width
V
= GND (400kHz/500kHz)
V
V
V
V
V
V
= 5.00V
= 3.33V
= 5.05V
= 3.33V
= 5.05V
= 3.33V
0.895
0.475
0.895
0.833
1.895
0.833
200
1.052
0.555
1.052
0.925
2.105
0.925
300
88
1.209
0.635
1.209
1.017
2.315
1.017
400
tON
OUT1
OUT2
OUT1
OUT2
OUT1
OUT2
µs
V
= REF or OPEN
µs
tON
(400kHz/300kHz)
µs
V
= VCC (200kHz/300kHz)
µs
tON
µs
Minimum Off-Time
ns
Maximum Duty Cycle
V
= GND
V
V
V
V
V
V
= 5.05V
= 3.33V
= 5.05V
= 3.33V
= 5.05V
= 3.33V
%
tON
tON
tON
OUT1
OUT2
OUT1
OUT2
OUT1
OUT2
85
%
V
= REF or OPEN
= VCC
88
%
91
%
V
94
%
91
%
Ultrasonic SKIP Operating Frequency
SKIP# = REF or OPEN
25
37
kHz
INTERNAL REGULATOR AND REFERENCE
LDO Output Voltage
BYP = GND, 5.5V < V < 25V, LDOREFIN < 0.3V,
IN
0 < ILDO < 100mA
4.925
3.250
0.7
5.000
3.300
5.075
3.350
V
V
LDO Output Voltage
BYP = GND, 5.5V < V < 25V, LDOREFIN > (VCC -1V),
IN
0 < ILDO < 100mA
LDO Output in Adjustable Mode
V
= 5.5V to 25V, V
= 5.5V to 25V, V
= 5.5V to 25V, V
= 2 x V
LDOREFIN
4.5
±2.5
±1.5
2.25
100
200
100
V
%
IN
LDO
LDO Output Accuracy in Adjustable Mode
V
V
V
= 0.35V to 0.5V
= 0.5V to 2.25V
IN
LDOREFIN
LDOREFIN
%
IN
LDOREFIN Input Range
= 2 x V
LDOREFIN
0.35
V
LDO
LDO Output Current
BYP = GND, V = 5.5V to 25V, Guaranteed by design
IN
mA
mA
mA
LDO Output Current During Switchover
BYP = 5V, V = 5.5V to 25V, LDOREFIN < 0.3V
IN
LDO Output Current During Switchover
to 3.3V
BYP = 3.3V, V = 5.5V to 25V, LDOREFIN > (VCC - 1V)
IN
FN6373.2
February 1, 2007
4
ISL6236
Electrical Specifications No load on LDO, OUT1, OUT2, V
, and REF, V = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
REF3 IN
VEN_LDO = 5V, T = -40°C to +100°C, unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
A
PARAMETER
LDO Short-Circuit Current
CONDITIONS
MIN
TYP
200
MAX
400
4.5
UNITS
mA
LDO = GND, BYP = GND
Rising edge of PVCC
Falling edge of PVCC
Undervoltage-Lockout Fault Threshold
4.35
4.05
4.68
V
3.9
LDO 5V Bootstrap Switch Threshold to BYP Rising edge at BYP regulation point
LDOREFIN = GND
4.53
4.83
3.2
V
V
Ω
Ω
LDO 3.3V Bootstrap Switch Threshold to
BYP
Rising edge at BYP regulation point
LDOREFIN = VCC
3.0
3.1
0.7
1.5
LDO 5V Bootstrap Switch Equivalent
Resistance
LDO to BYP, BYP = 5V, LDOREFIN > (VCC -1V),
Guaranteed by design
1.5
3.0
LDO 3.3V Bootstrap Switch Equivalent
Resistance
LDO to BYP, BYP = 3.3V, LDOREFIN < 0.3V, Guaranteed
by design
VREF3 Output Voltage
No external load, VCC > 4.5V
No external load, VCC < 4.0V
3.235
3.220
3.300
3.300
10
3.365
3.380
V
V
VREF3 Load Regulation
VREF3 Current Limit
REF Output Voltage
0 < I
< 5mA
mV
mA
V
LOAD
VREF3 = GND
10
17
No external load
1.980
10
2.000
10
2.020
REF Load Regulation
REF Sink Current
0 < I
< 50µA
mV
µA
µA
LOAD
REF in regulation
VIN Operating Supply Current
Both SMPSs on, FB1 = SKIP# = GND, REFIN2 = VCC
25
50
V
= BYP = 5.3V, V
= 3.5V
OUT2
OUT1
VIN Standby Supply Current
VIN Shutdown Supply Current
Quiescent Power Consumption
V
= 5.5V to 25V, both SMPSs off, EN LDO = VCC
= 4.5V to 25V, EN1 = EN2 = EN LDO = 0V
180
20
5
250
30
7
µA
µA
IN
IN
V
Both SMPSs on, FB1 = SKIP# = GND, REFIN2 = VCC,
= BYP = 5.3V, V = 3.5V
mW
V
OUT1
OUT2
FAULT DETECTION
Overvoltage Trip Threshold
FB1 with respect to nominal regulation point
REFIN2 with respect to nominal regulation point
FB1 or REFIN2 delay with 50mV overdrive
+8
+11
+16
10
+14
+20
%
%
µs
%
+12
Overvoltage Fault Propagation Delay
POK Threshold
FB1 or REFIN2 with respect to nominal output, falling
edge, typical hysteresis = 1%
-12
-9
-6
POK Propagation Delay
POK Output Low Voltage
POK Leakage Current
Falling edge, 50mV overdrive
10
µs
V
I
= 4mA
0.2
1
SINK
High state, forced to 5.5V
µA
°C
%
Thermal-Shutdown Threshold
Out-Of-Bound Threshold
+150
5
FB1 or REFIN2 with respect to nominal output voltage
Output Undervoltage Shutdown Threshold FB1 or REFIN2 with respect to nominal output voltage
65
10
70
75
30
%
Output Undervoltage Shutdown Blanking
Time
From EN signal
20
ms
INPUTS AND OUTPUTS
FB1 Input Voltage
Low level
High level
0.3
V
V
VCC - 1.0
FN6373.2
February 1, 2007
5
ISL6236
Electrical Specifications No load on LDO, OUT1, OUT2, V
, and REF, V = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
REF3 IN
VEN_LDO = 5V, T = -40°C to +100°C, unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
A
PARAMETER
REFIN2 Input Voltage
CONDITIONS
= V
MIN
0.5
TYP
MAX
2.50
UNITS
V
OUT2 Dynamic Range, V
Fixed OUT2 = 1.05V
Fixed OUT2 = 3.3V
Fixed LDO = 5V
OUT2
REFIN2
3.0
VCC - 1.1
V
VCC - 1.0
V
LDOREFIN Input Voltage
SKIP# Input Voltage
TON Input Voltage
0.30
2.25
V
OUT2 Dynamic Range, V
Fixed LDO = 3.3V
= 2 x V
0.35
V
LDO
LDOREFIN
VCC - 1.0
V
Low level (SKIP)
0.8
2.3
V
Float level (ULTRASONIC SKIP)
High level (PWM)
Low level
1.7
2.4
V
V
0.8
2.3
V
Float level
1.7
2.4
V
High level
V
EN1, EN2 Input Voltage
Clear fault level/SMPS off level
Delay start level
SMPS on level
0.8
2.3
V
1.7
2.4
1.2
0.94
-1
V
V
EN LDO Input Voltage
Input Leakage Current
Rising edge
1.6
2.0
1.06
+1
V
Falling edge
1.00
V
V
V
V
V
V
V
= 0V or 5V
µA
µA
µA
µA
µA
µA
tON
= V
LDO = 0V or 5V
-0.1
-1
+0.1
+1
EN
EN
= 0V or 5V
SKIP#
= VSECFB = 0V or 5V
-0.2
-0.2
-0.2
+0.2
+0.2
+0.2
FB1
= 0V or 2.5V
REFIN
= 0V or 2.75V
LDOREFIN
INTERNAL BOOT DIODE
V
Forward Voltage
PVCC - V
, I = 10mA
BOOT
0.65
0.8
V
D
F
I
Leakage Current
V
= 30V, PHASE = 25V, PVCC = 5V
BOOT
500
nA
BOOT LEAKAGE
MOSFET DRIVERS
UGATE Gate-Driver Sink/Source Current
LGATE Gate-Driver Source Current
LGATE Gate-Driver Sink Current
UGATE Gate-Driver On-Resistance
LGATE Gate-Driver On-Resistance
UGATE1, UGATE2 forced to 2V
2
A
A
LGATE1 (source), LGATE2 (source), forced to 2V
LGATE1 (sink), LGATE2 (sink), forced to 2V
BST - PHASE forced to 5V, Guaranteed by design
LGATE, high state (pull-up), Guaranteed by design
LGATE, low state (pull-down), Guaranteed by design
LGATE Rising
1.7
3.3
1.5
2.2
0.6
20
A
4.0
5.0
1.5
35
Ω
Ω
Ω
ns
ns
Ω
Dead Time
15
20
UGATE Rising
30
50
OUT1, OUT2 Discharge On Resistance
25
40
FN6373.2
February 1, 2007
6
ISL6236
Pin Descriptions
PIN
NAME
FUNCTION
REF
2V Reference Output. Bypass to GND with a 0.1µF (min) capacitor. REF can source up to 50A for external loads.
Loading REF degrades FB and output accuracy according to the REF load-regulation error.
1
TON
Frequency Select Input. Connect to GND for 400kHz/500kHz operation. Connect to REF (or leave OPEN) for
400kHz/300kHz operation. Connect to VCC for 200kHz/300kHz operation (5V/3.3V SMPS switching frequencies,
respectively.)
2
VCC
Analog Supply Voltage Input for PWM Core. Bypass to GND with a 1µF ceramic capacitor.
3
4
EN LDO LDO Enable Input. The LDO is enabled if EN LDO is within logic high level and disabled if EN LDO is less than the logic
low level.
VREF3
3.3V Reference Output. VREF3 can source up to 5mA for external loads. Bypass to GND with a 0.01µF capacitor if
loaded. Leave open if there is no load.
5
6
VIN
Power-Supply Input. VIN is used for the constant-on-time PWM on-time one-shot circuits. VIN is also used to power the
linear regulators. The linear regulators are powered by SMPS1 if OUT1 is set greater than 4.78V and BYP is tied to
OUT1. Connect VIN to the battery input and bypass with a 1µF capacitor.
LDO
Linear-Regulator Output. LDO can provide a total of 100mA external loads. The LDO regulate at 5V If LDOREFIN is
connected to GND. When the LDO is set at 5V and BYP is within 5V switchover threshold, the internal regulator shuts
down and the LDO output pin connects to BYP through a 0.7Ω switch. The LDO regulate at 3.3V if LDOREFIN is
connected to VCC. When the LDO is set at 3.3V and BYP is within 3.3V switchover threshold, the internal regulator
shuts down and the LDO output pin connects to BYP through a 1.5Ω switch. Bypass LDO output with a minimum of
4.7µF ceramic.
7
LDOREFIN LDO Reference Input. Connect LDOREFIN to GND for fixed 5V operation. Connect LDOREFIN to VCC for fixed 3.3V
operation. LDOREFIN can be used to program LDO output voltage from 0.7V to 4.5V. LDO output is two times the
voltage of LDOREFIN. There is no switchover in adjustable mode.
8
BYP
OUT1
FB1
BYP is the switchover source voltage for the LDO when LDOREFIN connected to GND or VCC. Connect BYP to 5V if
LDOREFIN is tied GND. Connect BYP to 3.3V if LDOREFIN is tied to VCC.
9
SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. OUT1 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode.
10
11
12
SMPS1 Feedback Input. Connect FB1 to GND for fixed 5V operation. Connect FB1 to VCC for fixed 1.5V operation
Connect FB1 to a resistive voltage-divider from OUT1 to GND to adjust the output from 0.7V to 5.5V.
ILIM1
SMPS1 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over a
0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM1. Connect ILIM1 to REF for a fixed 200mV
threshold. The logic current limit threshold is default to 100mV value if ILIM1 is higher than VCC - 1V.
POK1
EN1
SMPS1 Power-Good Open-Drain Output. POK1 is low when the SMPS1 output voltage is more than 10% below the
normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK1 is low in shutdown.
13
14
SMPS1 Enable Input. The SMPS1 is enabled if EN1 is greater than the logic high level and disabled if EN1 is less than
the logic low level. If EN1 is connected to REF, the SMPS1 starts after the SMPS2 reaches regulation (delay start). Drive
EN1 below 0.8V to clear fault level and reset the fault latches.
UGATE1 High-Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1.
15
16
PHASE1 Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high-side gate driver.
PHASE1 is the current-sense input for the SMPS1.
BOOT1
Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the typical application
circuits (Figure 66, Figure 67, and Figure 68). See “MOSFET Gate Drivers (UGATE, LGATE )” on page 28.
17
LGATE1 SMPS1 Synchronous-Rectifier Gate-Drive Output. LGATE1 swings between GND and PVCC.
18
19
PVCC
SECFB
GND
PVCC is the supply voltage for the low-side MOSFET driver LGATE. Connect a 5V power source to the PVCC pin
(bypass with 1µF MLCC capacitor to PGND if necessary). There is internal 10Ω connecting PVCC to VCC. Make sure
that both VCC and PVCC are bypassed with 1µF MLCC capacitors.
The SECFB is used to monitor the optional external 14V charge pump. Connect a resistive voltage-divider from 14V
charge pump output to GND to detect the output. If SECFB drops below the threshold voltage, LGATE1 turns on for
300ns. This will refresh the external charge pump driven by LGATE1 without over-discharging the output voltage.
20
21
Analog Ground for both SMPS and LDO. Connect externally to the underside of the exposed pad.
FN6373.2
February 1, 2007
7
ISL6236
Pin Descriptions (Continued)
PIN
NAME
FUNCTION
PGND
Power Ground for SMPS controller. Connect PGND externally to the underside of the exposed pad.
22
LGATE2 SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between GND and PVCC.
23
BOOT2
Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the typical application
circuits (Figure 66, Figure 67, and Figure 68). See “MOSFET Gate Drivers (UGATE, LGATE )” on page 28.
24
PHASE2 Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high-side gate driver.
PHASE2 is the current-sense input for the SMPS2.
25
UGATE2 High-Side MOSFET Floating Gate-Driver Output for SMPS2. UGATE1 swings between PHASE2 and BOOT2.
26
27
EN2
SMPS2 Enable Input. The SMPS2 is enabled if EN2 is greater than the logic high level and disabled if EN2 is less than
the logic low level. If EN2 is connected to REF, the SMPS2 starts after the SMPS1 reaches regulation (delay start). Drive
EN2 below 0.8V to clear fault level and reset the fault latches.
POK2
SMP2 Power-Good Open-Drain Output. POK2 is low when the SMPS2 output voltage is more than 10% below the
normal regulation point or during soft-start. POK2 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK2 is low in shutdown.
28
SKIP#
OUT2
ILIM2
Low-Noise Mode Control. Connect SKIP# to GND for normal Idle-Mode (pulse-skipping) operation or to VCC for PWM
mode (fixed frequency). Connect to REF or leave floating for ultrasonic skip mode operation.
29
30
31
SMPS2 Output Voltage-Sense Input. Connect to the SMPS2 output. OUT2 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode.
SMPS2 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM2 over a
0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM2. Connect ILIM2 to REF for a fixed 200mV.
The logic current limit threshold is default to 100mV value if ILIM2 is higher than VCC - 1V.
REFIN2
Output voltage control for SMPS2. Connect REFIN2 to VCC for fixed 3.3V. Connect REFIN2 to VREF3 for fixed 1.05V.
REFIN2 can be used to program SMPS2 output voltage from 0.5V to 2.50V. SMPS2 output voltage is 0V if
REFIN2 <0.5V.
32
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
REF3
= 5V, T = -40°C to +100°C,
V
= 12V, EN2 = EN1 = VCC, V = 5V, PVCC = 5V, V
BYP EN LDO
IN
unless otherwise noted. Typical values are at T = +25°C.
A
A
7 V SKIP MODE
12 V ULTRA SKIP MODE
IN
IN
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
7 V PWM MODE
25 V SKIP MODE
IN
IN
7 V PWM MODE
25 V SKIP MODE
IN
IN
7 V ULTRA SKIP MODE
IN
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
7 V ULTRA SKIP MODE
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
IN
12 V SKIP MODE
IN
12 V SKIP MODE
IN
12 V PWM MODE
IN
12 V PWM MODE
IN
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
10
0
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
FIGURE 1. V
= 1.05V EFFICIENCY vs LOAD (300kHz)
FIGURE 2. V
= 1.5V EFFICIENCY vs LOAD (200kHz)
OUT1
OUT2
FN6373.2
February 1, 2007
8
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
IN
7 V PWM MODE
IN
25 V SKIP MODE
7 V PWM MODE
IN
25 V SKIP MODE
IN
IN
7 V ULTRA SKIP MODE
IN
25 V PWM MODE
IN
7 V ULTRA SKIP MODE
IN
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
12 V SKIP MODE
IN
25 V ULTRA SKIP MODE
IN
12 V SKIP MODE
IN
12 V PWM MODE
IN
12 V PWM MODE
IN
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
FIGURE 3. V
= 3.3V EFFICIENCY vs LOAD (500kHz)
FIGURE 4. V
= 5V EFFICIENCY vs LOAD (400kHz)
OUT1
OUT2
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
7 V PWM MODE
IN
25 V SKIP MODE
IN
7 V PWM MODE
IN
25 V SKIP MODE
IN
7 V ULTRA SKIP MODE
IN
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
7 V ULTRA SKIP MODE
IN
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
12 V SKIP MODE
IN
12 V SKIP MODE
IN
12 V PWM MODE
IN
12 V PWM MODE
IN
1.070
1.068
1.066
1.064
1.062
1.060
1.058
1.056
1.054
1.052
1.050
1.540
1.535
1.530
1.525
1.520
1.515
1.510
1.505
1.500
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
FIGURE 5. V
= 1.05V REGULATION vs LOAD (300kHz)
FIGURE 6. V
= 1.5V REGULATION vs LOAD (200kHz)
OUT1
OUT2
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
7 V PWM MODE
IN
25 V SKIP MODE
IN
7 V PWM MODE
IN
25 V SKIP MODE
IN
7 V ULTRA SKIP MODE
IN
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
7 V ULTRA SKIP MODE
IN
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
12 V SKIP MODE
IN
12 V SKIP MODE
IN
12 V PWM MODE
IN
12 V PWM MODE
IN
3.380
3.370
3.360
3.350
3.340
3.330
3.320
3.310
5.160
5.140
5.120
5.100
5.080
5.060
5.040
5.020
5.000
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
FIGURE 7. V
= 3.3V REGULATION vs LOAD (500kHz)
FIGURE 8. V
= 5V REGULATION vs LOAD (400kHz)
OUT1
OUT2
FN6373.2
February 1, 2007
9
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
7 V PWM MODE
25 V SKIP MODE
7 V PWM MODE
25 V SKIP MODE
IN
IN
IN
IN
7 V ULTRA SKIP MODE
25 V PWM MODE
7 V ULTRA SKIP MODE
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
IN
IN
IN
12 V SKIP MODE
25 V ULTRA SKIP MODE
IN
12 V SKIP MODE
IN
IN
12 V PWM MODE
12 V PWM MODE
IN
IN
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
FIGURE 9. V
= 1.05V POWER DISSIPATION vs LOAD
FIGURE 10. V
= 1.5V POWER DISSIPATION vs LOAD
OUT2
OUT1
(300kHz)
(200kHz)
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
7 V SKIP MODE
IN
12 V ULTRA SKIP MODE
IN
7 V PWM MODE
IN
25 V SKIP MODE
IN
7 V PWM MODE
IN
25 V SKIP MODE
IN
7 V ULTRA SKIP MODE
IN
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
7 V ULTRA SKIP MODE
IN
25 V PWM MODE
IN
25 V ULTRA SKIP MODE
IN
12 V SKIP MODE
IN
12 V SKIP MODE
IN
12 V PWM MODE
IN
12 V PWM MODE
IN
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
FIGURE 11. V
= 3.3V POWER DISSIPATION vs LOAD
FIGURE 12. V
= 5V POWER DISSIPATION vs LOAD
OUT2
OUT1
(500kHz)
(400kHz)
1.064
1.062
1.060
1.058
1.056
1.054
1.052
1.050
1.048
1.068
1.066
1.064
1.062
1.060
1.058
1.056
1.054
1.052
1.050
1.048
NO LOAD PWM
NO LOAD PWM
MID LOAD PWM
MID LOAD PWM
MAX LOAD PWM
MAX LOAD PWM
5
7
9
11
13
15
17
19
21
23
25
5
7
9
11
13
15
17
19
21
23
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 13. V
= 1.05V OUTPUT VOLTAGE REGULATION
FIGURE 14. V
= 1.05V OUTPUT VOLTAGE REGULATION
OUT2
OUT2
vs V (PWM MODE)
vs V (SKIP MODE)
IN
IN
FN6373.2
February 1, 2007
10
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
1.518
1.516
1.514
1.512
1.510
1.508
1.506
1.504
1.530
1.525
NO LOAD PWM
MAX LOAD PWM
NO LOAD PWM
1.520
MID LOAD PWM
MID LOAD PWM
1.515
1.510
1.505
1.500
MAX LOAD PWM
5
7
9
11
13
15
17
19
21
23
25
5
7
9
11 13
15
17
19
21 23
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 15. V
= 1.5V OUTPUT VOLTAGE REGULATION
FIGURE 16. V
= 1.5V OUTPUT VOLTAGE REGULATION
OUT1
OUT1
vs V (PWM MODE)
vs V (SKIP MODE)
IN
IN
3.340
3.335
3.330
3.325
3.320
3.315
3.310
3.380
3.370
3.360
3.350
3.340
3.330
3.320
3.310
3.300
NO LOAD PWM
NO LOAD PWM
MAX LOAD PWM
MID LOAD PWM
MID LOAD PWM
MAX LOAD PWM
7
9
11
13
15
17
19
21
23
25
7
9
11
13
15
17
19
21
23
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 17. V
= 3.3V OUTPUT VOLTAGE REGULATION
FIGURE 18. V
= 3.3V OUTPUT VOLTAGE REGULATION
OUT2
OUT2
vs V (PWM MODE)
vs V (SKIP MODE)
IN
IN
5.065
5.060
5.055
5.050
5.045
5.040
5.140
5.120
5.100
5.080
5.060
5.040
5.020
NO LOAD PWM
MAX LOAD PWM
NO LOAD PWM
MID LOAD PWM
MID LOAD PWM
MAX LOAD PWM
7
9
11
13
15
17
19
21
23
25
7
9
11
13
15
17
19
21
23
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 19. V
V
= 5V OUTPUT VOLTAGE REGULATION vs
(PWM MODE)
FIGURE 20. V
= 5V OUTPUT VOLTAGE REGULATION vs
OUT1
OUT1
V
(SKIP MODE)
IN
IN
FN6373.2
February 1, 2007
11
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
50
45
40
35
30
300
250
200
150
100
50
PWM
PWM
25
ULTRA-SKIP
20
15
10
ULTRA-SKIP
0.010
SKIP
1.000
5
SKIP
0
0
0.001
0.010
0.100
10.000
0.001
0.100
OUTPUT LOAD (A)
1.000
10.000
OUTPUT LOAD (A)
FIGURE 21. V
= 1.05V FREQUENCY vs LOAD
FIGURE 22. V
OUT2
= 1.05V RIPPLE vs LOAD
OUT2
250
50
45
40
35
30
25
20
15
10
5
PWM
200
150
100
50
PWM
SKIP
ULTRA-SKIP
ULTRA-SKIP
SKIP
0.010
0
0
0.001
0.100
1.000
10.000
0.001
0.010
0.100
1.000
10.000
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 23. V
= 1.5V FREQUENCY vs LOAD
FIGURE 24. V
= 1.5V RIPPLE vs LOAD
OUT1
OUT1
14
12
10
8
600
PWM
PWM
500
400
300
200
100
0
ULTRA-SKIP
SKIP
6
4
ULTRA-SKIP
2
SKIP
0
0.001
0.010
0.100
1.000
10.000
0.001
0.010
0.100
1.000
10.000
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 25. V
= 3.3V FREQUENCY vs LOAD
FIGURE 26. V
= 3.3V RIPPLE vs LOAD
OUT2
OUT2
FN6373.2
February 1, 2007
12
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
450
400
350
300
250
200
150
100
50
40
PWM
35
30
PWM
ULTRA-SKIP
25
20
SKIP
15
10
5
ULTRA-SKIP
SKIP
1.000
0
0
0.001
0.010
0.100
1.000
10.000
0.001
10.000
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 27. V
= 5V FREQUENCY vs LOAD
FIGURE 28. V = 5V RIPPLE vs LOAD
OUT1
OUT1
5.04
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
5.02
5.00
4.98
4.96
4.94
4.92
4.90
4.88
4.86
4.84
BYP = 0V
BYP = 0V
BYP = 3.3V
BYP = 5V
0
50
100
OUTPUT LOAD (mA)
150
200
0
50
100
OUTPUT LOAD (mA)
150
200
FIGURE 29. LDO OUTPUT 5V vs LOAD
FIGURE 30. LDO OUTPUT 3.3V vs LOAD
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
0
2
4
6
8
10
0
2
4
5
8
10
OUTPUT LOAD (mA)
OUTPUT LOAD (mA)
FIGURE 31. V
vs LOAD
FIGURE 32. CHARGE PUMP vs LOAD (PWM)
REF3
FN6373.2
February 1, 2007
13
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
50
45
40
35
30
25
20
1400
1200
1000
800
600
400
200
0.0
7
9
11
13
15
17
19
21
23
IN
25
7
9
11
13
15
17
19
21
23
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 33. PWM NO LOAD INPUT CURRENT vs V
(EN = EN2 = EN LDO = VCC)
FIGURE 34. SKIP NO LOAD INPUT CURRENT vs V
(EN1 = EN2 = EN LDO = VCC)
IN
177.5
177.0
176.5
176.0
175.5
175.0
174.5
174.0
173.5
173.0
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
22.5
22.0
7
9
11
13
15
17
19
21
23
25
7
9
11
13
15
17
19
21
IN
23
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 35. STANDBY INPUT CURRENT vs V
(EN = EN2 = 0, EN LDO = VCC)
FIGURE 36. SHUTDOWN INPUT CURRENT vs V
(EN = EN2 = EN LDO = 0)
IN
V
500mV/DIV
REF3
EN1 5V/DIV
V
2V/DIV
OUT1
LDO 1V/DIV
CP 5V/DIV
IL1 2A/DIV
REF 1V/DIV
POK1 2V/DIV
FIGURE 37. REF, VREF3, LDO = 5V, CP, NO LOAD
FIGURE 38. START-UP V
= 5V (NO LOAD, SKIP MODE)
OUT1
FN6373.2
February 1, 2007
14
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
EN1 5V/DIV
EN1 5V/DIV
V
2V/DIV
V
2V/DIV
OUT1
OUT1
IL1 5A/DIV
IL1 2A/DIV
POK1 2V/DIV
POK1 2V/DIV
FIGURE 39. START-UP V
= 5V (NO LOAD, PWM MODE)
FIGURE 40. START-UP V
= 5V (FULL LOAD, PWM MODE)
OUT1
OUT1
EN2 5V/DIV
EN2 5V/DIV
V
2V/DIV
V
2V/DIV
OUT2
OUT2
IL2 2A/DIV
IL2 2A/DIV
POK2 2V/DIV
POK2 2V/DIV
FIGURE 41. START-UP V
OUT2
= 3.3V (NO LOAD, SKIP MODE)
FIGURE 42. START-UP V
= 3.3V (NO LOAD, PWM MODE)
OUT1
EN2 5V/DIV
EN2 5V/DIV
V
2V/DIV
2V/DIV
OUT2
V
2V/DIV
V
OUT2
OUT1
IL2 5A/DIV
POK2 5V/DIV
POK1 5V/DIV
POK2 2V/DIV
FIGURE 43. START-UP V
OUT1
= 3.3V (FULL LOAD,
FIGURE 44. DELAYED START-UP (V
EN1 = REF)
= 5V, V
OUT2
= 3.3V,
OUT1
PWM MODE)
FN6373.2
February 1, 2007
15
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
EN1 5V/DIV
EN1 5V/DIV
V
2V/DIV
OUT2
VOUT1 2V/DIV
V
2V/DIV
OUT2
V
2V/DIV
OUT1
POK1 5V/DIV
POK2 5V/DIV
POK1 OR POK2 5V/DIV
FIGURE 45. DELAYED START-UP(V
EN2 = REF)
= 5V, V
= 3.3V,
FIGURE 46. SHUTDOWN (V
EN2 = REF)
= 5V, V
= 3.3V,
OUT2
OUT1
OUT2
OUT1
LGATE1 5V/DIV
LGATE1 5V/DIV
V
RIPPLE 50mV/DIV
OUT1
V
RIPPLE 100mV/DIV
OUT1
IL1 5A/DIV
IL1 5A/DIV
V
RIPPLE 50mV/DIV
V
RIPPLE 50mV/DIV
OUT2
OUT2
FIGURE 47. LOAD TRANSIENT V
= 5V
FIGURE 48. LOAD TRANSIENT V
= 5V (SKIP)
OUT1
OUT1
LGATE1 5V/DIV
LGATE2 5V/DIV
V
RIPPLE 20mV/DIV
OUT1
IL2 5A/DIV
V
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 50mV/DIV
OUT2
IL2 5A/DIV
V
RIPPLE 50mV/DIV
OUT2
FIGURE 49. LOAD TRANSIENT V
= 3.3V (PWM)
FIGURE 50. LOAD TRANSIENT V
= 3.3V (SKIP)
OUT1
OUT1
FN6373.2
February 1, 2007
16
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
V
RIPPLE 20mV/DIV
OUT
V
RIPPLE 20mV/DIV
OUT
LDO 1V/DIV
V
0.5V/DIV
OUT2
REFIN2 0.5V/DIV
LDOREFIN 0.5V/DIV
LDO RIPPLE 50mV/DIV
V
RIPPLE 50mV/DIV
OUT2
FIGURE 51. V
TRACKING TO REFIN2
FIGURE 52. LDO TRACKING TO LDOREFIN
OUT2
EN1 5V/DIV
EN1 5V/DIV
V
0.5V/DIV
V
0.5V/DIV
OUT1
OUT1
IL1 2A/DIV
IL1 2A/DIV
POK1 2V/DIV
POK1 2V/DIV
FIGURE 53. START-UP V
OUT1
= 1.5V (NO LOAD, SKIP MODE)
FIGURE 54. START-UP V
= 1.5V (NO LOAD, PWM MODE)
OUT1
EN1 5V/DIV
EN2 5V/DIV
V
0.5V/DIV
OUT1
V
0.5V/DIV
OUT2
IL1 5A/DIV
IL2 2A/DIV
POK2 2V/DIV
POK1 2V/DIV
FIGURE 55. START-UP V
OUT1
= 1.5V (FULL LOAD,
FIGURE 56. START-UP V
= 1.05V (NO LOAD,
OUT2
SKIP MODE)
PWM MODE)
FN6373.2
February 1, 2007
17
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
EN2 5V/DIV
V
0.5V/DIV
OUT2
EN2 5V/DIV
IL2 2A/DIV
V
0.5V/DIV
OUT2
IL2 2A/DIV
POK2 2V/DIV
POK2 2V/DIV
FIGURE 57. START-UP V
OUT1
= 1.05V (NO LOAD,
FIGURE 58. START-UP V
= 1.05V (FULL LOAD,
OUT1
PWM MODE)
PWM MODE)
EN2 5V/DIV
V
2V/DIV
OUT1
EN1 500mV/DIV
V
0.5V/DIV
OUT2
V
500mV/DIV
V
2V/DIV
OUT2
OUT1
POK2 5V/DIV
POK1 5V/DIV
POK1 5V/DIV
POK2 5V/DIV
FIGURE 59. DELAYED START-UP (V
= 1.5V,
FIGURE 60. DELAYED START-UP (V
= 1.5V,
OUT1
VOUT2 = 1.05V, EN1 = REF)
OUT1
= 1.05V, EN2 = REF)
V
OUT2
LGATE1 5V/DIV
EN1 5V/DIV
V
RIPPLE 50mV/DIV
IL1 5A/DIV
OUT1
V
2V/DIV
OUT2
V
2V/DIV
OUT1
POK1 OR POK2 5V/DIV
V
RIPPLE 20mV/DIV
OUT2
FIGURE 61. SHUTDOWN (V
EN2 = REF)
= 1.5V, V
OUT2
= 1.05V,
FIGURE 62. LOAD TRANSIENT V
= 1.5V (PWM)
OUT1
OUT1
FN6373.2
February 1, 2007
18
ISL6236
Typical Performance Curves Circuit of Figure 66, Figure 67, and Figure 68, no load on LDO, OUT1, OUT2, V
, and REF,
= 5V, T = -40°C to +100°C,
REF3
V
= 12V, EN2 = EN1 = VCC, V
= 5V, PVCC = 5V, V
IN
BYP
EN LDO A
unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
LGATE1 5V/DIV
LGATE2 5V/DIV
V
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 50mV/DIV
IL1 5A/DIV
OUT1
IL1 5A/DIV
V
RIPPLE 20mV/DIV
= 1.5V (SKIP)
OUT2
V
RIPPLE 20mV/DIV
OUT2
FIGURE 63. LOAD TRANSIENT V
FIGURE 64. LOAD TRANSIENT V
= 1.05V (PWM)
OUT1
OUT1
LGATE2 5V/DIV
V
RIPPLE 20mV/DIV
OUT1
IL2 5A/DIV
V
RIPPLE 20mV/DIV
OUT2
FIGURE 65. LOAD TRANSIENT V
= 1.05V (SKIP)
OUT1
pin-selectable switching frequency, allowing operation for
200kHz/300kHz, 400kHz/300kHz, or 400kHz/500kHz on the
SMPSs.
Typical Application Circuits
The typical application circuits (Figures 66, 67 and 68) generate
the 5V/7A, 3.3V/11A, 1.25V/5A, dynamic voltage/10A, 1.5V/5A,
1.05V/5A and external 14V charge pump main supplies in a
notebook computer. The ISL6236 is also equipped with a
secondary feedback, SECFB, used to monitor the output of the
14V charge pump. In an event when the 14V drops below its
threshold voltage, SECFB comparator will turn on LGATE1 for
300ns. This will refresh an external 14V charge pump without
overcharging the output voltage. The input supply range is
5.5V to 25V.
Light-load efficiency is enhanced by automatic Idle-Mode
operation, a variable-frequency pulse-skipping mode that
reduces transition and gate-charge losses. Each step-down,
power-switching circuit consists of two n-channel MOSFETs,
a rectifier, and an LC output filter. The output voltage is the
average AC voltage at the switching node, which is
regulated by changing the duty cycle of the MOSFET
switches. The gate-drive signal to the n-channel high-side
MOSFET must exceed the battery voltage, and is provided
by a flying-capacitor boost circuit that uses a 100nF
capacitor connected to BOOT.
Detailed Description
The ISL6236 dual-buck, BiCMOS, switch-mode power-
supply controller generates logic supply voltages for
Both SMPS1 and SMPS2 PWM controllers consist of a
triple-mode feedback network and multiplexer, a multi-input
PWM comparator, high-side and low-side gate drivers and
notebook computers. The ISL6236 is designed primarily for
battery-powered applications where high efficiency and low-
quiescent supply current are critical. The ISL6236 provides a
FN6373.2
February 1, 2007
19
ISL6236
logic. In addition, SMPS2 can also use REFIN2 to track its
output from 0.5V to 2.50V. The ISL6236 contains fault-
protection circuits that monitor the main PWM outputs for
undervoltage and overvoltage conditions. A power-on
sequence block controls the power-up timing of the main
PWMs and monitors the outputs for undervoltage faults. The
ISL6236 includes an adjustable low drop-out linear regulator.
The bias generator blocks include the linear regulator, 3.3V
precision reference, 2V precision reference and automatic
bootstrap switchover circuit.
switch on-time is inversely proportional to the battery voltage
as measured by the VIN input and proportional to the output
voltage. This algorithm results in a nearly constant switching
frequency despite the lack of a fixed-frequency clock
generator. The benefit of a constant switching frequency is
that the frequency can be selected to avoid noise-sensitive
frequency regions:
K(V
+ I
⋅ r
)
OUT
LOAD DSON(LOWERQ)
-----------------------------------------------------------------------------------------------------
(EQ. 1)
t
=
ON
V
IN
See Table 2 for approximate K- factors. Switching frequency
increases as a function of load current due to the increasing
drop across the synchronous rectifier, which causes a faster
inductor-current discharge ramp. On-times translate only
roughly to switching frequencies. The on-times guaranteed
in the Electrical Characteristics are influenced by switching
delays in the external high-side power MOSFET. Also, the
dead-time effect increases the effective on-time, reducing
the switching frequency. It occurs only in PWM mode
(SKIP# = VCC) and during dynamic output voltage
transitions when the inductor current reverses at light or
negative load currents. With reversed inductor current, the
inductor's EMF causes PHASE to go high earlier than
normal, extending the on-time by a period equal to the
UGATE-rising dead time.
The synchronous-switch gate drivers are directly powered
from PVCC, while the high-side switch gate drivers are
indirectly powered from PVCC through an external capacitor
and an internal Schottky diode boost circuit.
An automatic bootstrap circuit turns off the LDO linear
regulator and powers the device from BYP if LDOREFIN is
set to GND or VCC. See Table 1.
TABLE 1. LDO OUTPUT VOLTAGE TABLE
LDO VOLTAGE
CONDITIONS
COMMENT
VOLTAGE at BYP LDOREFIN < 0.3V,
BYP > 4.63V
Internal LDO is
disabled.
VOLTAGE at BYP LDOREFIN > VCC - 1V,
BYP > 3V
Internal LDO is
disabled.
5V
LDOREFIN < 0.3V,
BYP < 4.63V
Internal LDO is
active.
TABLE 2. APPROXIMATE K-FACTOR ERRORS
SWITCHING
FREQUENCY K-FACTOR
APPROXIMATE
K-FACTOR
3.3V
LDOREFIN > VCC - 1V,
BYP < 3V
Internal LDO is
active.
SMPS
(kHz)
(µs)
ERROR (%)
2 x LDOREFIN
0.35V < LDOREFIN < 2.25V Internal LDO is
active.
(t
= GND, REF,
400
2.5
±10
±10
±10
±10
ON
or OPEN), VOUT1
(t = GND),
500
200
300
2.0
5.0
3.3
ON
VOUT2
FREE-RUNNING, CONSTANT ON-TIME PWM
CONTROLLER WITH INPUT FEED-FORWARD
(t = VCC),
ON
VOUT1
The constant on-time PWM control architecture is a
pseudo-fixed-frequency, constant on-time, current-mode
type with voltage feed forward. The constant on-time PWM
control architecture relies on the output ripple voltage to
provide the PWM ramp signal; thus the output filter
capacitor's ESR acts as a current-feedback resistor. The
high-side switch on-time is determined by a one-shot whose
period is inversely proportional to input voltage and directly
proportional to output voltage. Another one-shot sets a
minimum off-time (300ns typ). The on-time one-shot triggers
when the following conditions are met: the error comparator's
output is high, the synchronous rectifier current is below the
current-limit threshold, and the minimum off time one-shot
has timed out. The controller utilize the valley point of the
output ripple to regulate and determine the off time.
(t = VCC, REF,
ON
or OPEN), VOUT2
For loads above the critical conduction point, the actual
switching frequency is:
V
+ V
DROP1
OUT
-------------------------------------------------------
(EQ. 2)
f =
t
(V + V
)
DROP2
ON IN
where:
• V
is the sum of the parasitic voltage drops in the
DROP1
inductor discharge path, including synchronous rectifier,
inductor, and PC board resistances
• V
DROP2
is the sum of the parasitic voltage drops in the
charging path, including high-side switch, inductor, and PC
board resistances
ON-TIME ONE-SHOT (t
)
ON
Each PWM core includes a one-shot that sets the high-side
switch on-time for each controller. Each fast, low-jitter,
adjustable one-shot includes circuitry that varies the on-time
in response to battery and output voltage. The high-side
• t
is the on-time calculated by the ISL6236
ON
FN6373.2
February 1, 2007
20
ISL6236
VIN: 5.5V to 25V
5V
C5
1µF
C8
1µF
PVCC
VIN
VCC
NC
LDO
GND
LDOREFIN
BOOT2
C1
10µF
C10
10µF
BOOT1
Q3a
Q3b
Q1
IRF7821
SI4816BDY
UGATE2
UGATE1
OUT2-GFX
TRACK REFIN2/10A
C4
0.22µF
OUT1 – PCI-e
1.25V/5A
C9
L1: 3.3µH
L2: 2.2µH
0.1µF
PHASE2
LGATE2
PHASE1
LGATE1
OUT1
Q2
IRF7832
C11
330µF
9mΩ
6.3V
C2
2 x 330µF
4mΩ
6.3V
PGND
OUT2
VCC
5V
R1
7.87kΩ
EN1
BYP
VCC
2 BITS
DAC
EN2
ISL6236
REFIN2: DYNAMIC 0 TO 2.5V
FB1
REFIN2 TIED TO VREF3 = 1.05V
FB1 TIED TO GND = 5V
FB1 TIED TO VCC = 1.5V
-
DROOP
+
REFIN2 TIED TO VCC = 3.3V
+
AGND
REFIN2
ILIM2
+
R5
R3
200kΩ
R2
10kΩ
200kΩ
ILIM1
VCC
VCC
C3
OPEN
VREF3
REF
SKIP#
C7
0.1µF
R4
R6
200kΩ
GND
EN LDO
200kΩ
VCC
VCC
SECFB
TON
POK1
POK2
PAD
FREQUENCY-DEPENDENT COMPONENTS
1.25V/1.05V SMPS
SWITCHING
t
= VCC
ON
FREQUENCY
200kHz/300kHz
3.3µH
L1
L2
2.7µH
C2
C11
2 x 330µF
330µF
FIGURE 66. ISL6236 TYPICAL DYNAMIC GFX APPLICATION CIRCUIT
FN6373.2
February 1, 2007
21
ISL6236
VIN: 5.5V to 25V
5V
C5
1µF
LDOREFIN TIED TO GND = 5V
LDOREFIN TIED TO VCC = 3.3V
C8
1µF
LDO
PVCC
VIN
VCC
LDO
C6
VCC
LDOREFIN
BOOT2
4.7µF
C1
10µF
C10
10µF
SI4816BDY
C9
BOOT1
Q3a
Q3b
Q1a
UGATE2
UGATE1
OUT2
1.05V/5A
OUT1
1.5V/5A
C4
0.22µF
L1: 3.3µH
L2: 2.2µF
SI4816BDY
0.1µF
PHASE2
LGATE2
PHASE1
LGATE1
Q1b
C11
C2
330µF
4mΩ
6.3V
33µF
9mΩ
6.3V
PGND
OUT2
OUT1
VCC
3.3V
EN1
BYP
ISL6236
VCC
EN2
VCC
FB1 TIED TO GND = 5V
FB1 TIED TO VCC = 1.5V
REFIN2: DYNAMIC 0 TO 2.5V
REFIN2 TIED TO VREF3 = 1.05V
REFIN2 TIED TO VCC = 3.3V
FB1
VREF3
REFIN2
AGND
R3
200kΩ
R5
200kΩ
ILIM2
VREF3
REF
ILIM1
VCC
VCC
C3
0.01µF
SKIP#
C7
0.1µF
ON
R4
R6
200kΩ
EN LDO
200kΩ
OFF
VCC
VCC
SECFB
TON
POK1
POK2
PAD
FREQUENCY-DEPENDENT COMPONENTS
1.5V/1.05V SMPS
SWITCHING
t
= VCC
ON
FREQUENCY
200kHz/300kHz
3.3µH
L1
L2
2.7µH
330µF
330µF
C2
C11
FIGURE 67. ISL6236 TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITHOUT CHARGE PUMP
FN6373.2
February 1, 2007
22
ISL6236
VIN: 5.5V to 25V
C5
1µF
LDOREFIN TIED TO GND = 5V
LDOREFIN TIED TO VCC = 3.3V
LDO
VCC
PVCC
VIN
LDO
C6
LDOREFIN
4.7µF
C1
C10
10µF
10µF
BOOT1
BOOT2
Q3
IRF7807V
Q1
UGATE2
UGATE1
IRF7821
OUT2
C9
0.1µF
C4
0.1µF
OUT1
5V/7A
L1: 4.7µH
L2: 4.7µH
3.3V/11A
PHASE2
LGATE2
PGND
PHASE1
LGATE1
Q4
IRF7811AV
Q2
IRF7832
C11
330µF
9mΩ
6.3V
C2
330µF
9mΩ
4V
OUT1
EN1
VCC
ISL6236
OUT2
EN2
D3
BYP
FB1
VCC
D1
REFIN2: DYNAMIC 0 TO 2V
REFIN2 TIED TO VREF3 = 1.05V
REFIN2 TIED TO VCC = 3.3V
C8
0.1µF
FB1 TIED TO GND = 5V
FB1 TIED TO VCC = 1.5V
C12
0.1µF
D1a
REFIN2
VCC
AGND
ILIM1
D1b
R3
200kΩ
R5
150kΩ
ILIM2
VREF3
REF
VCC
VCC
C3
OPEN
C14
0.1µF
SKIP#
D2a
D2b
CP
C7
0.1µF
ON
14V/10mA
R4
200kΩ
R6
200kΩ
EN LDO
OFF
D2
C15
0.1µF
SECFB
TON
POK1
POK2
GND
R1
200kΩ
R2
39.2kΩ
PAD
FREQUENCY-DEPENDENT COMPONENTS
= REF
t
ON
5V/3.3V SMPS
SWITCHING
FREQUENCY
t
= VCC
(OR OPEN)
t
= GND
ON
200kHz/300kHz
6.8µH
ON
400kHz/500kHz
4.7µH
400kHz/300kHz
L1
L2
C2
6.8µH
7.6µH
4.7µH
4.7µH
2x470µF
330µF
2x330µF
330µF
2x330µF
330µF
C11
FIGURE 68. ISL6236 TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITH 14V CHARGE PUMP
FN6373.2
February 1, 2007
23
ISL6236
TON
SKIP#
BOOT2
BOOT1
UGATE1
PHASE1
UGATE2
PHASE2
PVCC
PVCC
SMPS1
SMPS2
SYNCH.
PWM BUCK
CONTROLLER
LGATE1
GND
LGATE2
SYNCH.
PWM BUCK
CONTROLLER
PGND
ILIM2
ILIM1
EN1
EN2
FB1
OUT1
BYP
REFIN2
OUT2
POK1
POK2
OUT1
OUT2
POK2
SW THRES.
POK1
VCC
LDO
LDO
INTERNAL
LOGIC
LDOREFIN
VIN
10Ω
PVCC
EN LDO
EN1
POWER-ON
VREF3
VREF3
REF
SEQUENCE
CLEAR FAULT
LATCH
THERMAL
SHUTDOWN
REF
EN2
FIGURE 69. DETAIL FUNCTIONAL DIAGRAM ISL6236
FN6373.2
February 1, 2007
24
ISL6236
t
ON
MIN. t
OFF
TRIG
ONE SHOT
Q
VIN
TO UGATE DRIVER
+
Q
R
S
OUT
Q
+
+
REFIN2 (SMPS2)
VREF
SLOPE COMP
+
ILIM
+
+
COMP
BOOT
BOOT
UV
DETECT
5µA
VCC
+
TO LGATE DRIVER
S
+
PHASE
OUT
+
S Q
R
Q
ONE-SHOT
+
SKIP#
SECFB
2V
SMSP1 ONLY
+
FB
DECODER
PGOOD
0.9V
1.1V
REF
FB
+
+
OV LATCH
UV LATCH
FAULT
REF
LATCH
LOGIC
20ms
BLANKING
0.7V
REF
FIGURE 70. PWM CONTROLLER (ONE SIDE ONLY)
FN6373.2
February 1, 2007
25
ISL6236
DC output accuracy specifications refer to the trip level of the
Automatic Pulse-Skipping Switchover
(Idle Mode)
error comparator. When the inductor is in continuous
conduction, the output voltage has a DC regulation higher
than the trip level by 50% of the ripple. In discontinuous
conduction (SKIP# = GND, light load), the output voltage has
a DC regulation higher than the trip level by approximately
1.0% due to slope compensation.
In Idle Mode (SKIP# = GND), an inherent automatic
switchover to PFM takes place at light loads. This switchover
is affected by a comparator that truncates the low-side
switch on-time at the inductor current's zero crossing. This
mechanism causes the threshold between pulse-skipping
PFM and nonskipping PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation (also known as the critical
conduction point):
Forced-PWM Mode
The low-noise, forced-PWM (SKIP# = VCC) mode disables
the zero-crossing comparator, which controls the low-side
switch on-time. Disabling the zero-crossing detector causes
the low-side, gate-drive waveform to become the
complement of the high-side, gate-drive waveform. The
inductor current reverses at light loads as the PWM loop
K ⋅ V
V
– V
OUT IN OUT
------------------------ -------------------------------
=
(EQ. 3)
I
LOAD(SKIP)
2 ⋅ L
V
IN
where K is the on-time scale factor (see “ON-TIME ONE-
strives to maintain a duty ratio of V
/V . The benefit of
OUT IN
SHOT (t )” on page 20). The load-current level at which
ON
PFM/PWM crossover occurs, I
forced-PWM mode is to keep the switching frequency fairly
constant, but it comes at a cost: the no-load battery current
can be 10mA to 50mA, depending on switching frequency
and the external MOSFETs.
, is equal to half
LOAD(SKIP)
the peak-to-peak ripple current, which is a function of the
inductor value (Figure 71). For example, in the ISL6236
typical application circuit with V
= 5V, V = 12V,
OUT1
IN
Forced-PWM mode is most useful for reducing
audio-frequency noise, improving load-transient response,
providing sink-current capability for dynamic output voltage
adjustment, and improving the cross-regulation of
multiple-output applications that use a flyback transformer or
coupled inductor.
L = 7.6µH, and K = 5µs, switchover to pulse-skipping
operation occurs at I = 0.96A or about on-fifth full load.
LOAD
The crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used.
Δ I
V
-V
IN OUT
=
t
L
I
PEAK
Enhanced Ultrasonic Mode
(25kHz (min) Pulse Skipping)
Leaving SKIP# unconnected or connecting SKIP# to REF
activates a unique pulse-skipping mode with a minimum
switching frequency of 25kHz. This ultrasonic pulse-skipping
mode eliminates audio-frequency modulation that would
otherwise be present when a lightly loaded controller
automatically skips pulses. In ultrasonic mode, the controller
automatically transitions to fixed-frequency PWM operation
when the load reaches the same critical conduction point
(ILOAD(SKIP)).
I
= I
LOAD PEAK/2
0
ON-TIME
TIME
An ultrasonic pulse occurs when the controller detects that
no switching has occurred within the last 20µs. Once
triggered, the ultrasonic controller pulls LGATE high, turning
on the low-side MOSFET to induce a negative inductor
current. After FB drops below the regulation point, the
controller turns off the low-side MOSFET (LGATE pulled low)
and triggers a constant on-time (UGATE driven high). When
the on-time has expired, the controller re-enables the
low-side MOSFET until the controller detects that the
inductor current dropped below the zero-crossing threshold.
Starting with a LGATE pulse greatly reduces the peak output
voltage when compared to starting with a UGATE pulse, as
long as VFB < VREF, LGATE is off and UGATE is on, similar
to pure SKIP mode.
FIGURE 71. ULTRASONIC CURRENT WAVEFORMS
The switching waveforms may appear noisy and
asynchronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM noise
vs light-load efficiency are made by varying the inductor
value. Generally, low inductor values produce a broader
efficiency vs load curve, while higher values result in higher
full-load efficiency (assuming that the coil resistance remains
fixed) and less output voltage ripple. Penalties for using
higher inductor values include larger physical size and
degraded load-transient response (especially at low
input-voltage levels).
FN6373.2
February 1, 2007
26
ISL6236
D2a. Finally, C14 charges C15 thru D2b when LAGET1
switched to high. CP output voltage is:
40μs (MAX)
CP = V
+ 2 ⋅ V
– 4 ⋅ V
LGATE1 D
(EQ. 4)
OUT1
INDUCTOR
CURRENT
where:
• V
LGATE1
is the peak voltage of the LGATE1 driver
• V is the forward diode dropped across the Schottkys
D
ZERO-CROSSING
DETECTION
SECFB is used to monitor the charge pump through resistive
divider. In an event when SECFB dropped below 2V, the
detection circuit force the highside MOSFET (SMPS1) off
and the lowside MOSFET (SMPS1) on for 300ns to allow CP
to recharge and SECFB rise above 2V. In the event of an
overload on CP where SECFB can not reach more than 2V,
the monitor will be deactivated. Special care should be taken
to ensure enough normal voltage ripple on each cycle as to
prevent CP shut-down. The SECFB pin has ~17mV of
hysteresis, so the ripple should be enough to bring the
SECFB voltage above the threshold by ~3x the hystersis, or
(2V + 3 * 17mV) = 2.051V. Reducing the CP decoupling
capacitor and placing a small ceramic capacitor (10pF to
47pF) in parallel with the upper leg of the SECFB resistor
feedback network (R1 of Figure 68), will also increase the
robustness of the charge pump.
0A
FB<REG.POINT
ON-TIME (t )
ON
FIGURE 72. ULTRASONIC CURRENT WAVEFORMS
Reference and Linear Regulators (VREF3,
REF, LDO and 14V Charge Pump)
The 3.3V reference (VREF3) is accurate to ±1.5% over
temperature, making VREF3 useful as a precision system
reference. VREF3 can supply up to 5mA for external loads.
Bypass VREF3 to GND with a 0.01µF capacitor. Leave it
open if there is no load.
The 2V reference (REF) is accurate to ±1% over
Current-Limit Circuit (ILIM ) with r
Temperature Compensation
DS(ON)
temperature, also making REF useful as a precision system
reference. Bypass REF to GND with a 0.1µF (min) capacitor.
REF can supply up to 50µA for external loads.
The current-limit circuit employs a "valley" current-sensing
algorithm. The ISL6236 uses the on-resistance of the
synchronous rectifier as a current-sensing element. If the
magnitude of the current-sense signal at PHASE is above
the current-limit threshold, the PWM is not allowed to initiate
a new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit
An internal regulator produces a fixed 5V
(LDOREFIN < 0.2V) or 3.3V (LDOREFIN > VCC - 1V). In an
adjustable mode, the LDO output can be set from 0.7V to
4.5V. The LDO output voltage is equal to two times the
LDOREFIN voltage. The LDO regulator can supply up to
100mA for external loads. Bypass LDO with a minimum
4.7µF ceramic capacitor. When the LDOREFIN < 0.2V and
BYP voltage is 5V, the LDO bootstrap-switchover to an
internal 0.7Ω P-Channel MOSFET switch connects BYP to
LDO pin while simultaneously shutting down the internal
linear regulator. These actions bootstrap the device,
powering the loads from the BYP input voltages, rather than
through internal linear regulators from the battery. Similarly,
when the BYP = 3.3V and LDOREFIN = VCC, the LDO
bootstrap-switchover to an internal 1.5Ω P-Channel
MOSFET switch connects BYP to LDO pin while
characteristic and maximum load capability are a function of
the current-limit threshold, inductor value and input and
output voltage.
I
PEAK
I
LOAD
Δ I
simultaneously shutting down the internal linear regulator.
No switchover action in adjustable mode.
I
LIMIT
I
LOAD(MAX)
In Figure 68, the external 14V charge pump is driven by
LGATE1. When LGATE1 is low, D1a charged C8 sourced
from OUT1. C8 voltage is equal to OUT1 minus a diode
drop. When LGATE1 transitions to high, the charges from C8
will transfer to C12 through D1b and charge it to VLGATE1
plus VC8. As LGATE1 transitions low on the next cycle, C12
will charge C14 to its voltage minus a diode drop through
ΔI
I
= I
-
LOAD
2
LIM (VAL)
TIME
FIGURE 73. “VALLEY” CURRENT LIMIT THRESHOLD POINT
FN6373.2
February 1, 2007
27
ISL6236
For lower power dissipation, the ISL6236 uses the
on-resistance of the synchronous rectifier as the
current-sense element. Use the worst-case maximum value
5V
BOOT
for r
from the MOSFET data sheet. Add some margin
10
Ω
DS(ON)
for the rise in r
VIN
Q1
with temperature. A good general rule
DS(ON)
is to allow 0.5% additional resistance for each °C of
temperature rise. The ISL6236 controller has a built-in 5µA
current source as shown in Figure 74. Place the hottest
power MOSEFTs as close to the IC as possible for best
thermal coupling. The current limit varies with the on-
resistance of the synchronous rectifier. When combined with
the undervoltage-protection circuit, this current-limit method
is effective in almost every circumstance.
UGATE
C
BOOT
OUT
PHASE
SL6236
FIGURE 75. REDUCING THE SWITCHING-NODE RISE TIME
The internal pull-down transistors that drive LGATE low have
a 0.6Ω typical on-resistance. These low on-resistance
pulldown transistors prevent LGATE from being pulled up
during the fast rise time of the inductor nodes due to
capacitive coupling from the drain to the gate of the low-side
synchronous-rectifier MOSFETs. However, for high-current
applications, some combinations of high- and low-side
MOSFETs may cause excessive gate-drain coupling, which
leads to poor efficiency and EMI-producing shoot-through
currents. Adding a 1Ω resistor in series with BOOT
increases the turn-on time of the high-side MOSFETs at the
expense of efficiency, without degrading the turn-off time
(Figure 75).
ILIM
+
5mA
+
TO CURRENT
LIMIT LOGIC
9R
R
R
ILIM
V
ILIM
VCC
Adaptive dead-time circuits monitor the LGATE and UGATE
drivers and prevent either FET from turning on until the other
is fully off. This algorithm allows operation without shoot-
through with a wide range of MOSFETs, minimizing delays
and maintaining efficiency. There must be low-resistance,
low-inductance paths from the gate drivers to the MOSFET
gates for the adaptive dead-time circuit to work properly.
Otherwise, the sense circuitry interprets the MOSFET gate
as "off" when there is actually charge left on the gate. Use
very short, wide traces measuring 10 to 20 squares (50 mils
to 100 mils wide if the MOSFET is 1” from the device).
FIGURE 74. CURRENT LIMIT BLOCK DIAGRAM
A negative current limit prevents excessive reverse inductor
currents when VOUT sinks current. The negative
current-limit threshold is set to approximately 120% of the
positive current limit and therefore tracks the positive current
limit when ILIM is adjusted. The current-limit threshold is
adjusted with an external resistor for ISL6236 at ILIM. The
current-limit threshold adjustment range is from 20mV to
200mV. In the adjustable mode, the current-limit threshold
voltage is 1/10th the voltage at ILIM. The voltage at ILIM pin
is the product of 5µA * R
. The threshold defaults to
ILIM
Boost-Supply Capacitor Selection (Buck)
100mV when ILIM is connected to VCC. The logic threshold
for switch-over to the 100mV default value is approximately
VCC -1V.
The boost capacitor should be 0.1µF to 4.7µF, depending on
the input and output voltages, external components, and PC
board layout. The boost capacitance should be as large as
possible to prevent it from charging to excessive voltage, but
small enough to adequately charge during the minimum
low-side MOSFET conduction time, which happens at
maximum operating duty cycle (this occurs at minimum input
The PC board layout guidelines should be carefully
observed to ensure that noise and DC errors do not corrupt
the current-sense signals at PHASE.
MOSFET Gate Drivers (UGATE, LGATE )
voltage). The minimum gate to source voltage (V
determined by:
) is
GS(MIN)
The UGATE and LGATE gate drivers sink 2.0A and 3.3A
respectively of gate drive, ensuring robust gate drive for
high-current applications. The UGATE floating high-side
MOSFET drivers are powered by diode-capacitor charge
pumps at BOOT. The LGATE synchronous-rectifier drivers
are powered by PVCC.
C
BOOT
---------------------------------------
(EQ. 5)
V
= PVCC ⋅
GS(MIN)
C
+ C
GS
BOOT
FN6373.2
February 1, 2007
28
ISL6236
where:
OVERVOLTAGE PROTECTION
When the output voltage of VOUT1 is 11% (16% for
VOUT2) above the set voltage, the overvoltage fault
protection activates. This latches on the synchronous
rectifier MOSFET with 100% duty cycle, rapidly
discharging the output capacitor until the negative current
limit is achieved. Once negative current limit is met,
UGATE is turned on for a minimum on-time, followed by
another LGATE pulse until negative current limit. This
effectively regulates the discharge current at the negative
current limit in an effort to prevent excessively large
negative currents that cause potentially damaging
negative voltages on the load. Once an overvoltage fault
condition is set, it can only be reset by toggling SHDN#,
EN, or cycling VIN (POR).
• PVCC is 5V
• C
GS
is the gate capacitance of the high-side MOSFET
Boost-Supply Refresh Monitor
In pure skip mode, the converter frequency can be very low
with little to no output loading. This produces very long off
times, where leakage can bleed down the BOOT capacitor
voltage. If the voltage falls too low, the converter may not be
able to turn on UGATE when the output voltage falls to the
reference. To prevent this, the ISL6236 monitors the BOOT
capacitor voltage, and if it falls below 3V, it initiates an
LGATE pulse, which will refresh the BOOT voltage.
POR, UVLO, and Internal Digital Soft-Start
UNDERVOLTAGE PROTECTION
Power-on reset (POR) occurs when VIN rises above
approximately 3V, resetting the undervoltage, overvoltage,
and thermal-shutdown fault latches. PVCC
When the output voltage drops below 70% of its regulation
voltage for at least 100µs, the controller sets the fault latch
and begins the discharge mode (see the Shutdown and
Output Discharge section below). UVP is ignored for at
least 20ms (typical), after start-up or after a rising edge on
EN. Toggle EN or cycle VIN (POR) to clear the
undervoltage-lockout (UVLO) circuitry inhibits switching
when PVCC is below 4V. LGATE is low during UVLO. The
output voltages begin to ramp up once PVCC exceeds its 4V
UVLO and REF is in regulation. The internal digital soft-start
timer begins to ramp up the maximum-allowed current limit
during start-up. The 1.7ms ramp occurs in five steps. The
step size are 20%, 40%, 60%, 80% and 100% of the positive
current limit value.
undervoltage fault latch and restart the controller. UVP
only applies to the buck outputs.
THERMAL PROTECTION
The ISL6236 has thermal shutdown to protect the devices
from overheating. Thermal shutdown occurs when the die
temperature exceeds +150°C. All internal circuitry shuts
down during thermal shutdown. The ISL6236 may trigger
thermal shutdown if LDO is not bootstrapped from OUT
while applying a high input voltage on VIN and drawing the
maximum current (including short circuit) from LDO. Even
if LDO is bootstrapped from OUT, overloading the LDO
causes large power dissipation on the bootstrap switches,
which may result in thermal shutdown. Cycling EN,
Power-Good Output (POK )
The POK comparator continuously monitors both output
voltages for undervoltage conditions. POK is actively held
low in shutdown, standby, and soft-start. POK1 releases and
digital soft-start terminates when VOUT1 outputs reach the
error-comparator threshold. POK1 goes low if VOUT1 output
turns off or is 10% below its nominal regulation point. POK1
is a true open-drain output. Likewise, POK2 is used to
monitor VOUT2.
EN LDO, or VIN (POR) ends the thermal-shutdown state.
Fault Protection
Discharge Mode (Soft-Stop)
The ISL6236 provides overvoltage/undervoltage fault
protection in the buck controllers. Once activated, the
controller continuously monitors the output for undervoltage
and overvoltage fault conditions.
When a transition to standby or shutdown mode occurs, or
the output undervoltage fault latch is set, the outputs
discharge to GND through an internal 25Ω switch. The
reference remains active to provide an accurate threshold
and to provide overvoltage protection.
OUT-OF-BOUND CONDITION
When the output voltage is 5% above the set voltage, the
out-of-bound condition activates. LGATE turns on until
output reaches within regulation. Once the output is within
regulation, the controller will operate as normal. It is the
"first line of defense" before OVP. The output voltage
ripple must be sized low enough as to not nuisance trip
the OOB threshold. The equations in the Output Capacitor
Selection section on page 32 should be used to size the
output voltage ripple below 3% of the nominal output
voltage set point.
Shutdown Mode
The ISL6236 SMPS1, SMPS2 and LDO have independent
enabling control. Drive EN1, EN2 and EN LDO below the
precise input falling-edge trip level to place the ISL6236 in its
low-power shutdown state. The ISL6236 consumes only
20µA of quiescent current while in shutdown. When
shutdown mode activates, the 3.3V VREF3 remain on. Both
SMPS outputs are discharged to 0V through a 25Ω switch.
FN6373.2
February 1, 2007
29
ISL6236
second SMPS remains on until the first SMPS turns off, the
Power-Up Sequencing and On/Off Controls (EN )
device shuts down, a fault occurs or PVCC goes into
undervoltage lockout. Both supplies begin their power-down
sequence immediately when the first supply turns off. Driving
EN below 0.8V clears the overvoltage, undervoltage and
thermal fault latches.
EN1 and EN2 control SMPS power-up sequencing. EN1 or
EN2 rising above 2.4V enables the respective outputs. EN1
or EN2 falling below 1.6V disables the respective outputs.
Connecting EN1 or EN2 to REF will force its outputs off while
the other output is below regulation. The sequenced SMPS
will start once the other SMPS reaches regulation. The
TABLE 3. OPERATING-MODE TRUTH TABLE
MODE
Power-Up
CONDITION
COMMENT
PVCC < UVLO threshold.
Transitions to discharge mode after a VIN POR and after REF becomes valid. LDO,
VREF3, and REF remain active.
Run
EN LDO = high, EN1 or EN2
enabled.
Normal operation
Overvoltage
Protection
Either output > 111% (VOUT1) or
116% (VOUT2) of nominal level.
LGATE is forced high. LDO, VREF3 and REF active. Exited by a VIN POR, or by
toggling EN1 or EN2.
Undervoltage
Protection
Either output < 70% of nominal after The internal 25Ω switch turns on. LDO, VREF3 and REF are active. Exited by a VIN
20ms time-out expires and output is POR or by toggling EN1 or EN2.
enabled.
Discharge
Standby
Either SMPS output is still high in
either standby mode or shutdown
mode
Discharge switch (25Ω) connects OUT to GND. One output may still run while the
other is in discharge mode. Activates when PVCC is in UVLO, or transition to UVLO,
standby, or shutdown has begun. LDO, VREF3 and REF active.
EN1, EN2 < startup threshold, EN
LDO= High
LDO, VREF3 and REF active.
Shutdown
EN1, EN2, EN LDO = low
TJ >+150°C
Discharge switch (25Ω) connects OUT to PGND. All circuitry off except VREF3.
Thermal Shutdown
All circuitry off. Exited by VIN POR or cycling EN. VREF3 remain active.
TABLE 4. SHUTDOWN AND STANDBY CONTROL LOGIS
VEN2 (V) LDO SMPS1
Low Off Off
VEN LDO
Low
VEN1 (V)
Low
SMPS2
Off
“>2.5” → High
“>2.5” → High
“>2.5” → High
“>2.5” → High
“>2.5” → High
“>2.5” → High
Low
Low
High
Low
High
REF
High
On
On
On
On
On
On
Off
Off
High
High
Low
On
On
On
Off
Off
On
On
On (after SMPS1 is up)
On
High
REF
On (after SMPS2 is up)
FN6373.2
February 1, 2007
30
ISL6236
condition. The minimum practical inductor value is one
that causes the circuit to operate at critical conduction
(where the inductor current just touches zero with every
cycle at maximum load). Inductor values lower than this
grant no further size-reduction benefit.
Adjustable-Output Feedback (Dual-Mode FB)
Connect FB1 to GND to enable the fixed 5V or tie FB1 to
VCC to set the fixed 1.5V output. Connect a resistive
voltage-divider at FB1 between OUT1 and GND to adjust the
respective output voltage between 0.7V and 5.5V
(Figure 76). Choose R2 to be approximately 10k and solve
for R1 using Equation 6.
The ISL6236 pulse-skipping algorithm (SKIP# = GND)
initiates skip mode at the critical conduction point, so the
inductor's operating point also determines the load
current at which PWM/PFM switchover occurs. The
optimum LIR point is usually found between 25% and
50% ripple current.
V
⎛
⎜
⎝
⎞
OUT1
------------------
R1 = R2 ⋅
– 1
⎟
V
⎠
FB1
(EQ. 6)
where V
FB1
= 0.7V nominal.
V
IN
Likewise, connect REFIN2 to VCC to enable the fixed 3.3V
or tie REFIN2 to VREF3 to set the fixed 1.05V output. Set
REFIN2 from 0 to 2.50V for SMPS2 tracking mode
Q3
Q4
UGATE1
(Figure 77).
VR
OUT1
⎛
⎝
⎞
– 1
------------------
R3 = R4 ⋅
⎠
V
OUT2
ISL6236
(EQ. 7)
LGATE1
where:
• VR = 2V nominal (if tied to REF)
R1
R2
OUT1
FB1
or
• VR = 3.3V nominal (if tied to VREF3)
Design Procedure
Establish the input voltage range and maximum load current
before choosing an inductor and its associated ripple current
ratio (LIR). The following four factors dictate the rest of the
design:
FIGURE 76. SETTING V
WITH A RESISTOR DIVIDER
OUT1
1. Input Voltage Range. The maximum value (V
)
V
IN(MAX)
must accommodate the maximum AC adapter voltage.
The minimum value (V ) must account for the
IN
IN(MIN)
Q1
lowest input voltage after drops due to connectors, fuses
and battery selector switches. Lower input voltages result
in better efficiency.
UGATE2
ISL6236
OUT2
2. Maximum Load Current. The peak load current
(I
) determines the instantaneous component
LOAD(MAX)
LGATE2
stress and filtering requirements and thus drives output
capacitor selection, inductor saturation rating and the
design of the current-limit circuit. The continuous load
Q2
current (I
) determines the thermal stress and drives
OUT2
LOAD
the selection of input capacitors, MOSFETs and other
critical heat-contributing components.
VR
REFIN2
3. Switching Frequency. This choice determines the basic
trade-off between size and efficiency. The optimal
frequency is largely a function of maximum input voltage
and MOSFET switching losses.
R3
R4
4. Inductor Ripple Current Ratio (LIR). LIR is the ratio of the
peak-peak ripple current to the average inductor current.
Size and efficiency trade-offs must be considered when
setting the inductor ripple current ratio. Low inductor
values cause large ripple currents, resulting in the
smallest size, but poor efficiency and high output noise.
Also, total output ripple above 3.5% of the output
FIGURE 77. SETTING V
TRACKING
WITH A VOLTAGE DIVIDER FOR
OUT2
regulation will cause controller to trigger out-of-bound
FN6373.2
February 1, 2007
31
ISL6236
Inductor Selection
I
= (25mV) ⁄ ((5mΩ × 1.2) > 5A – (0.35 ⁄ 2)5A)
LIMIT(LOW)
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as follows:
(EQ. 13)
V
(V + V
)
OUT_
OUT_ IN
--------------------------------------------------------------------
(EQ. 8)
L =
(EQ. 14)
4.17A > 4.12A
V
⋅ f ⋅ LIR ⋅ I
LOAD(MAX)
IN
4.17A is greater than the valley current of 4.12A, so the
circuit can easily deliver the full-rated 5A using the 30mV
nominal current-limit threshold voltage.
Example: I
LOAD(MAX)
f = 200kHz, 35% ripple current or LIR = 0.35:
= 5A, V = 12V, V = 5V,
IN OUT2
5V(12V – 5V)
12V ⋅ 200kHz ⋅ 0.35 ⋅ 5A
Output Capacitor Selection
-----------------------------------------------------------------
(EQ. 9)
L =
= 8.3μH
The output filter capacitor must have low enough equivalent
series resistance (ESR) to meet output ripple and
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice. The core must be large enough
not to saturate at the peak inductor current (IPEAK):
load-transient requirements, yet have high enough ESR to
satisfy stability requirements. The output capacitance must
also be high enough to absorb the inductor energy while
transitioning from full-load to no-load conditions without
tripping the overvoltage fault latch. In applications where the
output is subject to large load transients, the output
capacitor's size depends on how much ESR is needed to
prevent the output from dipping too low under a load
transient. Ignoring the sag due to finite capacitance:
(EQ. 10)
IPEAK = I
+ [(LIR ⁄ 2) ⋅ I
]
LOAD(MAX)
LOAD(MAX)
The inductor ripple current also impacts transient response
performance, especially at low V - V differences. Low
IN OUT
inductor values allow the inductor current to slew faster,
replenishing charge removed from the output filter capacitors
by a sudden load step. The peak amplitude of the output
transient (VSAG) is also a function of the maximum duty
factor, which can be calculated from the on-time and
minimum off-time:
V
DIP
---------------------------------
(EQ. 15)
R
≤
SER
I
LOAD(MAX)
where V
is the maximum-tolerable transient voltage drop.
DIP
In non-CPU applications, the output capacitor's size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple:
V
⎛
⎛
⎜
⎝
⎞⎞
⎟⎟
⎠⎠
2
OUT_
------------------
(ΔI
)
⋅ L K
+ t
⎜
LOAD(MAX)
OFF(MIN)
V
⎝
IN
---------------------------------------------------------------------------------------------------------------------------
VSAG =
V
– V
V
⎛
⎜
⎝
⎞
⎟
⎠
IN
OUT
P – P
-------------------------------
(EQ. 16)
-----------------------------------------------
2 ⋅ C
⋅ V
K
-
R ≤
ESR
OUT
OUT
t
V
L
⋅ I
OFF(MIN)
IN
IR LOAD(MAX)
(EQ. 11)
where V
P-P
is the peak-to-peak output voltage ripple. The
actual capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry of
the capacitor technology. Thus, the capacitor is usually
selected by ESR and voltage rating rather than by
capacitance value (this is true of tantalum, OS-CON, and
other electrolytic-type capacitors).
where minimum off-time = 0.35µs (max) and K is from
Table 2.
Determining the Current Limit
The minimum current-limit threshold must be great enough
to support the maximum load current when the current limit
is at the minimum tolerance value. The valley of the inductor
When using low-capacity filter capacitors such as polymer
types, capacitor size is usually determined by the capacity
current occurs at I
current; therefore:
minus half of the ripple
LOAD(MAX)
required to prevent V
and V from tripping the
SAG
SOAR
(EQ. 12)
I
> I
– [(LIR ⁄ 2) ⋅ I
]
LOAD(MAX)
undervoltage and overvoltage fault latches during load
LIMIT(LOW)
LOAD(MAX)
transients in ultrasonic mode.
where: I
voltage divided by the r
= minimum current-limit threshold
LIMIT(LOW)
For low input-to-output voltage differentials (V / V
IN OUT
additional output capacitance is required to maintain stability
< 2),
of Q2/Q4.
DS(ON)
and good efficiency in ultrasonic mode. The amount of
overshoot due to stored inductor energy can be calculated
as:
Use the worst-case maximum value for r
from the
DS(ON)
MOSFET Q2/Q4 data sheet and add some margin for the
rise in r with temperature. A good general rule is to
DS(ON)
2
allow 0.2% additional resistance for each °C of temperature
rise.
I
⋅ L
PEAK
-----------------------------------------------
(EQ. 17)
V
=
SOAR
2 ⋅ C
⋅ V
OUT_
OUT
Examining the 5A circuit example with a maximum
where I
is the peak inductor current.
r
= 5mΩ at room temperature. At +125°C reveals the
PEAK
DS(ON)
following:
FN6373.2
February 1, 2007
32
ISL6236
Input Capacitor Selection
V
⎛
⎜
⎝
⎞
⎟
⎠
2
OUT_
------------------------
The input capacitors must meet the input-ripple-current
PD(Q Resistance) =
(I
) ⋅ r
LOAD DS(ON)
H
V
IN(MIN)
(I
) requirement imposed by the switching current. The
(EQ. 19)
RMS
ISL6236 dual switching regulator operates at different
frequencies. This interleaves the current pulses drawn by
the two switches and reduces the overlap time where they
add together. The input RMS current is much smaller in
comparison than with both SMPSs operating in phase. The
input RMS current varies with load and the input voltage.
Generally, a small high-side MOSFET reduces switching
losses at high input voltage. However, the r required
to stay within package power-dissipation limits often limits
how small the MOSFET can be. The optimum situation
occurs when the switching (AC) losses equal the conduction
DS(ON)
(r
) losses.
DS(ON)
The maximum input capacitor RMS current for a single
SMPS is given by:
Switching losses in the high-side MOSFET can become an
insidious heat problem when maximum battery voltage is
applied, due to the squared term in the CV f switching-loss
2
V
(V – V
)
OUT_
⎛
⎜
⎝
⎞
⎟
⎠
OUT IN
------------------------------------------------------------
(EQ. 18)
I
≈ I
equation. Reconsider the high-side MOSFET chosen for
RMS
LOAD
V
IN
adequate r
at low battery voltages if it becomes
DS(ON)
extraordinarily hot when subjected to V
.
IN(MAX)
When V = 2 ⋅ V
(D = 50%) , IRMS has maximum
OUT_
IN
current of I
⁄ 2 .
Calculating the power dissipation in NH (Q1/Q3) due to
switching losses is difficult since it must allow for quantifying
factors that influence the turn-on and turn-off times. These
factors include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board layout
characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substitute for
bench evaluation, preferably including verification using a
thermocouple mounted on NH (Q1/Q3):
LOAD
The ESR of the input-capacitor is important for determining
2
capacitor power dissipation. All the power (I
x ESR)
RMS
heats up the capacitor and reduces efficiency. Nontantalum
chemistries (ceramic or OS-CON) are preferred due to their
low ESR and resilience to power-up surge currents. Choose
input capacitors that exhibit less than +10°C temperature
rise at the RMS input current for optimal circuit longevity.
Place the drains of the high-side switches close to each
other to share common input bypass capacitors.
C
⋅ f
⋅ I
⎛
⎜
⎝
⎞
⎟
⎠
2
RSS SW LOAD
----------------------------------------------------
PD(Q Switching) = (V
)
IN(MAX)
H
I
GATE
Power MOSFET Selection
(EQ. 20)
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability (>5A)
when using high-voltage (>20V) AC adapters. Low-current
applications usually require less attention.
where C
RSS
(Q1/Q3) and I
current.
is the reverse transfer capacitance of Q
H
is the peak gate-drive source/sink
GATE
Choose a high-side MOSFET (Q1/Q3) that has conduction
losses equal to the switching losses at the typical battery
voltage for maximum efficiency. Ensure that the conduction
losses at the minimum input voltage do not exceed the
package thermal limits or violate the overall thermal budget.
Ensure that conduction losses plus switching losses at the
maximum input voltage do not exceed the package ratings
or violate the overall thermal budget.
For the synchronous rectifier, the worst-case power
dissipation always occurs at maximum battery voltage:
V
⎛
⎞
⎟
⎠
2
OUT
--------------------------
(EQ. 21)
PD(Q ) = 1 –
I
⋅ r
LOAD DS(ON)
⎜
L
V
⎝
IN(MAX)
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
but are not quite high enough to exceed the
LOAD(MAX)
current limit and cause the fault latch to trip. To protect
against this possibility, "overdesign" the circuit to tolerate:
Choose a synchronous rectifier (Q2/Q4) with the lowest
possible r
. Ensure the gate is not pulled up by the
DS(ON)
high-side switch turning on due to parasitic drain-to-gate
capacitance, causing cross-conduction problems. Switching
losses are not an issue for the synchronous rectifier in the
buck topology since it is a zero-voltage switched device
when using the buck topology.
(EQ. 22)
I
= I
+ ((LIR) ⁄ 2) ⋅ I
LIMIT(HIGH) LOAD(MAX)
LOAD
where I
is the maximum valley current allowed
by the current-limit circuit, including threshold tolerance and
LIMIT(HIGH)
resistance variation.
MOSFET Power Dissipation
Rectifier Selection
Worst-case conduction losses occur at the duty-factor
Current circulates from ground to the junction of both
MOSFETs and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is
negative with respect to ground. This voltage is
extremes. For the high-side MOSFET, the worst-case power
dissipation (PD) due to the MOSFET's r
minimum battery voltage:
occurs at the
DS(ON)
approximately -0.7V (a diode drop) at both transition edges
FN6373.2
February 1, 2007
33
ISL6236
while both switches are off (dead time). The drop is
when the low-side switch conducts.
where V
DROP1
and V
are the parasitic voltage drops
DROP2
I
⋅ r
in the discharge and charge paths (see “ON-TIME ONE-
SHOT (t )” on page 20), t is from the Electrical
L
DS(ON)
ON OFF(MIN)
The rectifier is a clamp across the synchronous rectifier that
catches the negative inductor swing during the dead time
between turning the high-side MOSFET off and the
synchronous rectifier on. The MOSFETs incorporate a
high-speed silicon body diode as an adequate clamp diode if
efficiency is not of primary importance. Place a Schottky
diode in parallel with the body diode to reduce the forward
voltage drop and prevent the Q2/Q4 MOSFET body diodes
from turning on during the dead time. Typically, the external
diode improves the efficiency by 1% to 2%. Use a Schottky
diode with a DC current rating equal to one-third of the load
current. For example, use an MBR0530 (500mA-rated) type
for loads up to 1.5A, a 1N5817 type for loads up to 3A, or a
1N5821 type for loads up to 10A. The rectifier's rated
reverse breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating
factor.
Specifications table on page 3 and K is taken from Table 2.
The absolute minimum input voltage is calculated with h = 1.
Operating frequency must be reduced or h must be
increased and output capacitance added to obtain an
acceptable V
SAG
if calculated V
is greater than the
IN(MIN)
required minimum input voltage. Calculate V
to be sure
SAG
of adequate transient response if operation near dropout is
anticipated.
Dropout Design Example:
ISL6236: With V
= 5V, fsw = 400kHz, K = 2.25µs,
OUT2
= 350ns, V
t
= V = 100mV, and
DROP2
OFF(MIN)
DROP1
h = 1.5, the minimum V is:
IN
(5V + 0.1V)
----------------------------------------------
+ 0.1V – 0.1V= 6.65V
(EQ. 24)
(EQ. 25)
V
=
IN(MIN)
0.35μs ⋅ 1.5
2.25μs
⎛
⎞
-------------------------------
1 –
⎝
⎠
Applications Information
Calculating with h = 1 yields:
Dropout Performance
(5V + 0.1V)
-----------------------------------------
+ 0.1V – 0.1V= 6.04V
V
=
IN(MIN)
The output voltage-adjust range for continuous-conduction
operation is restricted by the nonadjustable 350ns (max)
minimum off-time one-shot. Use the slower 5V SMPS for the
higher of the two output voltages for best dropout
performance in adjustable feedback mode. The duty-factor
limit must be calculated using worst-case values for on- and
off-times, when working with low input voltages.
Manufacturing tolerances and internal propagation delays
introduce an error to the TON K-factor. Also, keep in mind
that transient-response performance of buck regulators
operated close to dropout is poor, and bulk output
capacitance must often be added (see Equation 11 on
page 32).
0.35μs ⋅ 1
2.25μs
⎛
⎞
--------------------------
1 –
⎝
⎠
Therefore, V must be greater than 6.65V. A practical input
IN
voltage with reasonable output capacitance would be 7.5V.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve minimal switching
losses and clean, stable operation. This is especially true when
multiple converters are on the same PC board where one
circuit can affect the other. Refer to the ISL6236 Evaluation Kit
data sheet for a specific layout example.
Mount all of the power components on the top side of the board
with their ground terminals flush against one another, if
possible. Follow these guidelines for good PC board layout:
The absolute point of dropout occurs when the inductor
current ramps down during the minimum off-time (ΔI
)
DOWN
as much as it ramps up during the on-time ( ΔI ). The ratio
• Isolate the power components on the top side from the
sensitive analog components on the bottom side with a
ground shield. Use a separate PGND plane under the
OUT1 and OUT2 sides (called PGND1 and PGND2). Avoid
the introduction of AC currents into the PGND1 and PGND2
ground planes. Run the power plane ground currents on the
top side only, if possible.
UP
h = ΔI /ΔI
UP DOWN
indicates the ability to slew the inductor
current higher in response to increased load, and must
always be greater than 1. As h approaches 1, the absolute
minimum dropout point, the inductor current is less able to
increase during each switching cycle and V
greatly
SAG
increases unless additional output capacitance is used.
• Use a star ground connection on the power plane to
minimize the crosstalk between OUT1 and OUT2.
A reasonable minimum value for h is 1.5, but this can be
adjusted up or down to allow trade-offs between V
SAG,
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
output capacitance and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
• Keep the power traces and load connections short. This
practice is essential for high efficiency. Using thick copper
PC boards (2oz vs 1oz) can enhance full-load efficiency
by 1% or more. Correctly routing PC board traces must be
approached in terms of fractions of centimeters, where a
(V
+ V
)
DROP
OUT_
--------------------------------------------------
(EQ. 23)
V
=
+ V
– V
DROP2 DROP1
IN(MIN)
t
⋅ h
OFF(MIN)
⎛
⎝
⎞
⎠
-----------------------------------
1 –
K
FN6373.2
February 1, 2007
34
ISL6236
single mΩ of excess trace resistance causes a
Group the gate-drive components (BOOT capacitor, VIN
measurable efficiency penalty.
bypass capacitor) together near the controller device.
Make the DC/DC controller ground connections as follows:
1. Near the device, create a small analog ground plane.
• PHASE (ISL6236) and GND connections to the
synchronous rectifiers for current limiting must be made
using Kelvin-sense connections to guarantee the
current-limit accuracy with 8-pin SO MOSFETs. This is
best done by routing power to the MOSFETs from outside
using the top copper layer, while connecting PHASE
traces inside (underneath) the MOSFETs.
2. Connect the small analog ground plane to GND and use
the plane for the ground connection for the REF and VCC
bypass capacitors, FB dividers and ILIM resistors (if any).
3. Create another small ground island for PGND and use
the plane for the VIN bypass capacitor, placed very close
to the device.
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be made
longer than the discharge path. For example, it is better to
allow some extra distance between the input capacitors
and the high-side MOSFET than to allow distance
between the inductor and the synchronous rectifier or
between the inductor and the output filter capacitor.
4. Connect the GND and PGND planes together at the
metal tab under device.
On the board's top side (power planes), make a star ground
to minimize crosstalk between the two sides. The top-side
star ground is a star connection of the input capacitors and
synchronous rectifiers. Keep the resistance low between the
star ground and the source of the synchronous rectifiers for
accurate current limit. Connect the top-side star ground
(used for MOSFET, input, and output capacitors) to the small
island with a single short, wide connection (preferably just a
via). Create PGND islands on the layer just below the
top-side layer (refer to the ISL6236 EV kit for an example) to
act as an EMI shield if multiple layers are available (highly
recommended). Connect each of these individually to the
star ground via, which connects the top side to the PGND
plane. Add one more solid ground plane under the device to
act as an additional shield, and also connect the solid
ground plane to the star ground via.
• Ensure that the OUT connection to COUT is short and
direct. However, in some cases it may be desirable to
deliberately introduce some trace length between the OUT
connector node and the output filter capacitor.
• Route high-speed switching nodes (BOOT, UGATE,
PHASE, and LGATE ) away from sensitive analog areas
(REF, ILIM, and FB ). Use PGND1 and PGND2 as an EMI
shield to keep radiated switching noise away from the IC's
feedback divider and analog bypass capacitors.
• Make all pin-strap control input connections (SKIP#, ILIM,
etc.) to GND or VCC of the device.
Layout Procedure
Place the power components first with ground terminals
adjacent (Q2/Q4 source, CIN, COUT ). If possible, make all
these connections on the top layer with wide, copper-filled
areas.
Connect the output power planes (VCORE and system
ground planes) directly to the output filter capacitor positive
and negative terminals with multiple vias.
Mount the controller IC adjacent to the synchronous rectifier
MOSFETs close to the hottest spot, preferably on the back
side in order to keep UGATE, GND, and the LGATE gate
drive lines short and wide. The LGATE gate trace must be
short and wide, measuring 50 mils to 100 mils wide if the
MOSFET is 1” from the controller device.
FN6373.2
February 1, 2007
35
ISL6236
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.18
3.15
3.15
0.23
0.30
3.45
3.45
5,8
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
3.30
7,8
5.00 BSC
-
E1
E2
e
4.75 BSC
9
3.30
7,8
0.50 BSC
-
k
0.25
0.30
-
-
-
-
L
0.40
0.50
0.15
8
L1
N
-
32
8
8
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6373.2
February 1, 2007
36
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