ISL6251_06 [INTERSIL]
Low Cost Multi-Chemistry Battery Charger Controller; 低成本多化学电池充电器控制器
| 型号： | ISL6251_06 |
| 厂家： | 
Intersil |
| 描述： | Low Cost Multi-Chemistry Battery Charger Controller |
| 文件： | 总20页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6251, ISL6251A
®
Data Sheet
May 10, 2006
FN9202.2
Low Cost Multi-Chemistry Battery
Charger Controller
Features
• ±0.5% Charge Voltage Accuracy (-10°C to 100°C)
• ±3% Accurate Input Current Limit
The ISL6251, ISL6251A is a highly integrated battery
charger controller for Li-Ion/Li-Ion polymer batteries and
NiMH batteries. High Efficiency is achieved by a
synchronous buck topology and the use of a MOSFET,
instead of a diode, for selecting power from the adapter or
battery. The low side MOSFET emulates a diode at light
loads to improve the light load efficiency and prevent system
bus boosting.
• ±3% Accurate Battery Charge Current Limit
• ±25% Accurate Battery Trickle Charge Current Limit
(ISL6251A)
• Programmable Charge Current Limit, Adapter Current
Limit and Charge Voltage
• Fixed 300kHz PWM Synchronous Buck Controller with
Diode Emulation at Light Load
The constant output voltage can be selected for 2, 3 and 4
series Li-Ion cells with 0.5% accuracy over temperature. It
can be also programmed between 4.2V+5%/cell and
4.2V-5%/cell to optimize battery capacity. When supplying
the load and battery charger simultaneously, the input
current limit for the AC adapter is programmable to within
3% accuracy to avoid overloading the AC adapter, and to
allow the system to make efficient use of available adapter
power for charging. It also has a wide range of
programmable charging current. The ISL6251, ISL6251A
provides outputs that are used to monitor the current drawn
from the AC adapter, and monitor for the presence of an AC
adapter. The ISL6251, ISL6251A automatically transitions
from regulating current mode to regulating voltage mode.
• Output for Current Drawn from AC Adapter
• AC Adapter Present Indicator
• Fast Input Current Limit Response
• Input Voltage Range 7V to 25V
• Support 2, 3 and 4 Cells Battery Pack
• Up to 17.64V Battery-Voltage Set Point
• Thermal Shutdown
• Support Pulse Charging
• Less than 10µA Battery Leakage Current
• Charge Any Battery Chemistry: Li-Ion, NiCd, NiMH, etc.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART
NUMBER
(Notes 1, 2)
TEMP
RANGE
(°C)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
Applications
• Notebook, Desknote and Sub-notebook Computers
• Personal Digital Assistant
ISL6251HRZ ISL6251HRZ -10 to 100 28 Ld 5x5 QFN L28.5×5
ISL6251HAZ ISL6251HAZ -10 to 100 24 Ld QSOP M24.15
ISL6251AHRZ ISL6251AHRZ -10 to 100 28 Ld 5x5 QFN L28.5×5
ISL6251AHAZ ISL6251AHAZ -10 to 100 24 Ld QSOP
NOTES:
M24.15
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. Add “-T” for Tape and Reel.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL6251, ISL6251A
Pinouts
ISL6251, ISL6251A
(28 LD QFN)
ISL6251, ISL6251A
(24 LD QSOP)
TOP VIEW
TOP VIEW
VDD
ACSET
EN
DCIN
1
2
3
4
5
24
23
22
21
20
ACPRN
CSON
CSOP
CSIN
28 27 26 25 24 23 22
1
2
3
4
5
6
7
21
CSOP
EN
CELLS
ICOMP
VCOMP
ICM
20 CSIN
19 CSIP
CELLS
CSIP
6
19
18
17
16
15
14
13
ICOMP
VCOMP
ICM
PHASE
UGATE
BOOT
VDDP
LGATE
PGND
7
NA
17 NA
18
VREF
CHLIM
ACLIM
VADJ
GND
8
9
10
11
12
PHASE
16
VREF
15 UGATE
CHLIM
8
9
10 11 12 13 14
FN9202.2
May 10, 2006
2
ISL6251, ISL6251A
Absolute Maximum Ratings
Thermal Information
DCIN, CSIP, CSON to PGND . . . . . . . . . . . . . . . . . . .-0.3V to +28V
CSIP-CSIN, CSOP-CSON. . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
PHASE to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 30V
BOOT to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +35V
ACLIM, ACPRN, CHLIM, VDD to GND . . . . . . . . . . . . . . -0.3V to 7V
BOOT-PHASE, VDDP-PGND . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
ICM, ICOMP, VCOMP to GND. . . . . . . . . . . . . . -0.3V to VDD+0.3V
VREF, CELLS to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V
UGATE. . . . . . . . . . . . . . . . . . . . . . . . . PHASE-0.3V to BOOT+0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . PGND-0.3V to VDDP+0.3V
Thermal Resistance
θ
(°C/W)
θ
(°C/W)
9.5
N/A
JA
JC
QFN Package (Notes 4, 6). . . . . . . . . .
QSOP Package (Note 5) . . . . . . . . . . .
Junction Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
39
88
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. When the voltage across ACSET is below 0V, the current through ACSET should be limited to less than 1mA.
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating,
EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C
= 1µF, I
= 0mA, T = -10°C to +100°C,
VDD A
VDD
T
≤ 125°C, unless otherwise noted.
J
PARAMETER
SUPPLY AND BIAS REGULATOR
DCIN Input Voltage Range
TEST CONDITIONS
MIN
TYP
MAX
UNITS
7
25
3
V
mA
µA
V
DCIN Quiescent Current
EN = VDD or GND, 7V ≤ DCIN ≤ 25V
1.4
3
Battery Leakage Current (Note 7)
VDD Output Voltage/Regulation
DCIN = 0, no load
10
7V ≤ DCIN ≤ 25V, 0 ≤ I
VDD Rising
≤ 30mA
4.925
4.0
5.075
4.4
5.225
4.6
400
2.415
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
VDD
VDD Undervoltage Lockout Trip Point
V
Hysteresis
200
2.365
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
250
2.39
mV
V
Reference Output Voltage VREF
Battery Charge Voltage Accuracy
0 ≤ I
≤ 300µA
VREF
CSON = 16.8V, CELLS = VDD, VADJ = Float
CSON = 12.6V, CELLS = GND, VADJ = Float
CSON = 8.4V, CELLS = Float, VADJ = Float
CSON = 17.64V, CELLS = VDD, VADJ = VREF
CSON = 13.23V, CELLS = GND, VADJ = VREF
CSON = 8.82V, CELLS = Float, VADJ = VREF
CSON = 15.96V, CELLS = VDD, VADJ = GND
CSON = 11.97V, CELLS = GND, VADJ = GND
CSON = 7.98V, CELLS = Float, VADJ = GND
%
%
%
%
%
%
%
%
%
TRIP POINTS
ACSET Threshold
1.24
2.2
2.2
-1
1.26
3.4
3.4
0
1.28
4.4
4.4
1
V
ACSET Input Bias Current Hysteresis
ACSET Input Bias Current
ACSET Input Bias Current
µA
µA
µA
ACSET ≥ 1.26V
ACSET < 1.26V
FN9202.2
May 10, 2006
3
ISL6251, ISL6251A
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating,
EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C
= 1µF, I
= 0mA, T = -10°C to +100°C,
VDD A
VDD
T
≤ 125°C, unless otherwise noted. (Continued)
J
PARAMETER
OSCILLATOR
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Frequency
245
97
300
1.6
1
355
kHz
V
PWM Ramp Voltage (peak-peak)
CSIP = 18V
CSIP = 11V
V
SYNCHRONOUS BUCK REGULATOR
Maximum Duty Cycle
99
1.8
1.0
1.0
1.8
1.8
1.0
1.0
1.8
99.6
3.0
%
Ω
A
UGATE Pull-Up Resistance
UGATE Source Current
BOOT-PHASE = 5V, 500mA source current
BOOT-PHASE = 5V, BOOT-UGATE = 2.5V
BOOT-PHASE = 5V, 500mA sink current
BOOT-PHASE = 5V, UGATE-PHASE = 2.5V
VDDP-PGND = 5V, 500mA source current
VDDP-PGND = 5V, VDDP-LGATE = 2.5V
VDDP-PGND = 5V, 500mA sink current
VDDP-PGND = 5V, LGATE = 2.5V
UGATE Pull-DOWN Resistance
UGATE Sink Current
1.8
3.0
1.8
Ω
A
LGATE Pull-UP Resistance
LGATE Source Current
Ω
A
LGATE Pull-DOWN Resistance
LGATE Sink Current
Ω
A
CHARGING CURRENT SENSING AMPLIFIER
Input Common-Mode Range
0
18
2.5
2
V
Input Offset Voltage
Guaranteed by design
-2.5
0
mV
µA
µA
V
Input Bias Current at CSOP
Input Bias Current at CSON
CHLIM Input Voltage Range
0 < CSOP < 18V
0 < CSON < 18V
0.25
75
100
3.6
173
170
105
103
15.0
12.5
1
0
CSOP to CSON Full-Scale Current
Sense Voltage
ISL6251: CHLIM = 3.3V
ISL6251A, CHLIM = 3.3V
ISL6251: CHLIM = 2.0V
ISL6251A: CHLIM = 2.0V
ISL6251: CHLIM = 0.2V
ISL6251A: CHLIM = 0.2V
CHLIM = GND or 3.3V, DCIN = 0V
CHLIM rising
157
160
95
165
165
100
100
10
mV
mV
mV
mV
mV
mV
µA
mV
97
5.0
7.5
-1
10
CHLIM Input Bias Current
CHLIM Power-Down Mode Threshold
Voltage
80
88
25
95
CHLIM Power-Down Mode Hysteresis
Voltage
15
40
mV
ADAPTER CURRENT SENSING AMPLIFIER
Input Common-Mode Range
7
25
2
V
Input Offset Voltage
Guaranteed by design
-2
mV
µA
Input Bias Current at CSIP and CSIN
Combined
CSIP = CSIN = 25V
100
130
Input Bias Current at CSIN
0 < CSIN < DCIN, Guaranteed by design
0.10
1
µA
FN9202.2
May 10, 2006
4
ISL6251, ISL6251A
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating,
EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C
= 1µF, I
= 0mA, T = -10°C to +100°C,
VDD A
VDD
T
≤ 125°C, unless otherwise noted. (Continued)
J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ADAPTER CURRENT LIMIT THRESHOLD
CSIP to CSIN Full-Scale Current Sense ACLIM = VREF
97
72
47
10
-20
100
75
103
78
mV
mV
mV
µA
Voltage
ACLIM = Float
ACLIM = GND
50
53
ACLIM Input Bias Current
ACLIM = VREF
ACLIM = GND
16
20
-16
-10
µA
VOLTAGE REGULATION ERROR AMPLIFIER
Error Amplifier Transconductance from CELLS = VDD
CSON to VCOMP
30
µA/V
CURRENT REGULATION ERROR AMPLIFIER
Charging Current Error Amplifier
Transconductance
50
50
µA/V
µA/V
Adapter Current Error Amplifier
Transconductance
BATTERY CELL SELECTOR
CELLS Input Voltage for 4 Cell Select
CELLS Input Voltage for 3 Cell Select
CELLS Input Voltage for 2 Cell Select
LOGIC INTERFACE
4.3
2.1
V
V
V
2
4.2
EN Input Voltage Range
0
1.030
0.985
30
VDD
1.100
1.025
90
V
V
EN Threshold Voltage
Rising
1.06
1.000
60
Falling
V
Hysteresis
mV
µA
mA
µA
%
EN Input Bias Current
ACPRN Sink Current
ACPRN Leakage Current
EN = 2.5V
1.8
3
2.0
2.2
ACPRN = 0.4V
ACPRN = 5V
CSIP - CSIN = 100mV
CSIP - CSIN = 75mV
CSIP - CSIN = 50mV
8
11
-0.5
-3
0.5
ICM Output Accuracy
(Vicm = 19.9 x (Vcsip-Vcsin))
0
0
+3
-4
+4
%
-5
0
+5
%
Thermal Shutdown Temperature
150
25
°C
°C
Thermal Shutdown Temperature
Hysteresis
NOTE:
7. This is the sum of currents in these pins (CSIP, CSIN, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V. No current in pins EN, ACSET,
VADJ, CELLS, ACLIM, CHLIM.
FN9202.2
May 10, 2006
5
ISL6251, ISL6251A
Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, T = 25°C, unless otherwise noted.
A
0.1
0.6
VDD=5.075V
EN=0
VREF=2.390V
0.08
0.3
0
0.06
0.04
-0.3
-0.6
0.02
0
0
100
200
300
400
0
8
16
24
32
40
LOAD CURRENT (µA)
LOAD CURRENT (mA)
FIGURE 2. VREF LOAD REGULATION
FIGURE 1. VDD LOAD REGULATION
1
10
9
8
7
6
5
4
3
2
1
0
0.96
VCSON=8.4V
2 CELLS
VCSON=12.6V
(3 CELLS)
0.92
0.88
0.84
0.8
VCSON=16.8V
4 CELLS
0.76
10 20 30 40 50 60 70 80 90 100
CSIP-CSIN (mV)
0
0.5
1
1.5
2
2.5
3
3.5
4
CHARGE CURRENT (A)
FIGURE 3. ICM ACCURACY vs AC ADAPTER CURRENT
FIGURE 4. SYSTEM EFFICIENCY vs CHARGE CURRENT
LOAD
CURRENT
5A/div
CSON
5V/div
ADAPTER
CURRENT
5A/div
EN
5V/div
CHARGE
CURRENT
2A/div
INDUCTOR
CURRENT
2A/div
LOAD STEP: 0-4A
CHARGE CURRENT: 3A
AC ADAPTER CURRENT LIMIT: 5.15A
BATTERY
VOLTAGE
2V/div
CHARGE
CURRENT
2A/div
FIGURE 5. LOAD TRANSIENT RESPONSE
FIGURE 6. CHARGE ENABLE AND SHUTDOWN
FN9202.2
May 10, 2006
6
ISL6251, ISL6251A
Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, T = 25°C, unless otherwise noted. (Continued)
A
CHLIM=0.2V
CSON=8V
INDUCTOR
CURRENT
2A/div
PHASE
10V/div
BATTERY
REMOVAL
BATTERY
INSERTION
CSON
INDUCTOR
CURRENT
1A/div
10V/div
VCOMP
2V/div
VCOMP
ICOMP
UGATE
5V/div
ICOMP
2V/div
FIGURE 7. BATTERY INSERTION AND REMOVAL
FIGURE 8. SWITCHING WAVEFORMS AT DIODE EMULATION
PHASE
10V/div
CHARGE
CURRENT
1A/div
UGATE
2V/div
CHLIM
1V/div
LGATE
2V/div
FIGURE 9. SWITCHING WAVEFORMS IN CC MODE
FIGURE 10. TRICKLE TO FULL-SCALE CHARGING
FN9202.2
May 10, 2006
7
ISL6251, ISL6251A
PGND
Functional Pin Descriptions
PGND is the power ground. Connect PGND to the source of
the low side MOSFET for the low side MOSFET gate driver.
BOOT
Connect BOOT to a 0.1µF ceramic capacitor to PHASE pin
and connect to the cathode of the bootstrap schottky diode.
VDD
VDD is an internal LDO output to supply IC analog circuit.
Connect a 1μF ceramic capacitor to ground.
UGATE
UGATE is the high side MOSFET gate drive output.
VDDP
LGATE
VDDP is the supply voltage for the low-side MOSFET gate
driver. Connect a 4.7Ω resistor to VDD and a 1μF ceramic
capacitor to power ground.
LGATE is the low side MOSFET gate drive output; swing
between 0V and VDDP.
PHASE
ICOMP
The Phase connection pin connects to the high side
MOSFET source, output inductor, and low side MOSFET
drain.
ICOMP is a current loop error amplifier output.
VCOMP
VCOMP is a voltage loop amplifier output.
CSOP/CSON
CELLS
CSOP/CSON is the battery charging current sensing
positive/negative input. The differential voltage across CSOP
and CSON is used to sense the battery charging current,
and is compared with the charging current limit threshold to
regulate the charging current. The CSON pin is also used as
the battery feedback voltage to perform voltage regulation.
This pin is used to select the battery voltage. CELLS = VDD
for a 4S battery pack, CELLS = GND for a 3S battery pack,
CELLS = Float for a 2S battery pack.
VADJ
VADJ adjusts battery regulation voltage. VADJ = VREF for
4.2V+5%/cell; VADJ = Floating for 4.2V/cell; VADJ = GND
for 4.2V-5%/cell. Connect to a resistor divider to program the
desired battery cell voltage between 4.2V-5% and 4.2V+5%.
CSIP/CSIN
CSIP/CSIN is the AC adapter current sensing
positive/negative input. The differential voltage across CSIP
and CSIN is used to sense the AC adapter current, and is
compared with the AC adapter current limit to regulate the
AC adapter current.
CHLIM
CHLIM is the battery charge current limit set pin. CHLIM
input voltage range is 0.1V to 3.6V. When CHLIM = 3.3V, the
set point for CSOP-CSON is 165mV. The charger shuts
down if CHLIM is forced below 88mV.
GND
GND is an analog ground.
DCIN
ACLIM
The DCIN pin is the input of the internal 5V LDO. Connect it
to the AC adapter output. Connect a 0.1μF ceramic
capacitor from DCIN to PGND.
ACLIM is the adapter current limit set pin. ACLIM = VREF for
100mV, ACLIM = Floating for 75mV, and ACLIM = GND for
50mV. Connect a resistor divider to program the adapter
current limit threshold between 50mV and 100mV.
ACSET
VREF
ACSET is an AC adapter detection input. Connect to a
resistor divider from the AC adapter output.
VREF is a 2.39V reference output pin. It is internally
compensated. Do not connect a decoupling capacitor.
ACPRN
Open-drain output signals AC adapter is present. ACPRN
pulls low when ACSET is higher than 1.26V; and pulled high
when ACSET is lower than 1.26V.
EN
EN is the Charge Enable input. Connecting EN to high
enables the charge control function, connecting EN to low
disables charging functions. Use with a thermistor to detect
a hot battery and suspend charging.
ICM
ICM is the adapter current output. The output of this pin
produces a voltage proportional to the adapter current.
FN9202.2
May 10, 2006
8
ISL6251, ISL6251A
ICM
CSIP
CSIN
ACSET
ACPRN
-
+
CA1
×19.9
DCIN
VDD
+
-
LDO
Regulator
1.26V
VREF
152K
-
gm3
Adapter
Current
+
ACLIM
Limit Set
BOOT
152K
Min
Current
Buffer
ICOMP
UGATE
PHASE
Min
Voltage
Buffer
VCOMP
+
-
-
VREF
0.25VCA2
PWM
+
gm1
+
514K
514K
VDDP
-
VADJ
LGATE
gm2
-
Voltage
Selector
VCA2
PGND
EN
CELLS
1.06V
VDD
-
×20
CA2
-
+
VREF
Reference
CSON
GND
CSOP
CHLIM
FIGURE 11. FUNCTIONAL BLOCK DIAGRAM
FN9202.2
May 10, 2006
9
ISL6251, ISL6251A
D4
AC ADAPTER
R8
130k
1%
D3
C8
0.1µF
R9
10.2k
1%
DCIN
ACSET
CSIP
CSIN
C2
0.1µF
R2
20mΩ
ISL6251
ISL6251A
C7
1µF
VDDP
SYSTEM LOAD
R3
18Ω
R10
4.7Ω
3.3V
C1
10µF
VDDP
D2
C4
VDD
C9
1µF
BOOT
UGATE
PHASE
LGATE
PGND
R5
100k
Q1
To Host
ACPRN
ICOMP
VCOMP
VADJ
Controller
C6:6.8nF
0.1µF
Q2
R6:10k
C5:10nF
D1
Optional
L
10µH
FLOATING
4.2V/CELL
CHARGE
ENABLE
CSOP
EN
R1
40mΩ
C3
1µF
R4
2.2Ω
R12
2.6A CHARGE LIMIT
253mA Trickle Charge
BAT+
Battery
CSON
CELLS
VREF 20k 1%
C10
10µF
CHLIM
ACLIM
VREF
VDD
4 CELLS
Pack
R13
1.87k
1%
R11
130k
1%
BAT-
ICM
C11
3300pF
Trickle Charge
R7: 100Ω
GND
Q3
FIGURE 12. ISL6251, ISL6251A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS
FN9202.2
May 10, 2006
10
ISL6251, ISL6251A
D4
AC ADAPTER
C8
0.1µF
D3
R8
130k
1%
R9
DCIN
10.2k,1%
CSIP
CSIN
ACSET
C2
0.1µF
R2
20mΩ
SYSTEM LOAD
VDDP
C7
1µF
R10
4.7Ω
ISL6251
ISL6251A
R3: 18Ω
C1
10µF
VCC
VDDP
VDD
BOOT
R5
100k
C9
1µF
D2
DIGITAL
INPUT
ACPRN
CHLIM
Q1
UGATE
PHASE
C4
0.1µF
D/A OUTPUT
OUTPUT
LGATE
D1
Optional
EN
L
10µH
R7: 100Ω
Q2
PGND
A/D INPUT
ICM
C11
3300pF
5.15A INPUT
ACLIM
CSOP
CURRENT LIMIT
R1
40mΩ
R4
2.2Ω
C3
1µF
VREF
C6
HOST
6.8nF
CSON
BAT+
ICOMP
CELLS
3 CELLS
C10
10µF
VCOMP
Battery
Pack
R6
C5
GND
10k
10nF
AVDD/VREF
VADJ
R11, R12, R13
10k
FLOATING
4.2V/CELL
SCL
SDL
SCL
SDL
A/D INPUT
GND
TEMP
BAT-
FIGURE 13. ISL6251, ISL6251A TYPICAL APPLICATION CIRCUIT WITH MICRO-CONTROLLER
FN9202.2
May 10, 2006
11
ISL6251, ISL6251A
voltage approaches the input voltage, the DC/DC converter
Theory of Operation
operates in dropout mode, where there is a timer to prevent
the frequency from dropping into the audible frequency
range. It can achieve duty cycle of up to 99.6%.
Introduction
The ISL6251, ISL6251A includes all of the functions
necessary to charge 2 to 4 cell Li-Ion and Li-polymer
batteries. A high efficiency synchronous buck converter is
used to control the charging voltage and charging current up
to 10A. The ISL6251, ISL6251A has input current limiting
and analog inputs for setting the charge current and charge
voltage; CHLIM inputs are used to control charge current
and VADJ inputs are used to control charge voltage.
To prevent boosting of the system bus voltage, the battery
charger operates in standard-buck mode when CSOP-
CSON drops below 4.25mV. Once in standard-buck mode,
hysteresis does not allow synchronous operation of the
DC/DC converter until CSOP-CSON rises above 12.5mV.
An adaptive gate drive scheme is used to control the dead
time between two switches. The dead time control circuit
monitors the LGATE output and prevents the upper side
MOSFET from turning on until LGATE is fully off, preventing
cross-conduction and shoot-through. In order for the dead
time circuit to work properly, there must be a low resistance,
low inductance path from the LGATE driver to MOSFET
gate, and from the source of MOSFET to PGND. The
external Schottky diode is between the VDDP pin and BOOT
pin to keep the bootstrap capacitor charged.
The ISL6251, ISL6251A charges the battery with constant
charge current, set by CHLIM input, until the battery voltage
rises up to a programmed charge voltage set by VADJ input;
then the charger begins to operate at a constant voltage
charge mode.
The EN input allows shutdown of the charger through a
command from a micro-controller. It also uses EN to safely
shutdown the charger when the battery is in extremely hot
conditions. The amount of adapter current is reported on the
ICM output. Figure 11 shows the IC functional block
diagram.
Setting the Battery Regulation Voltage
The ISL6251, ISL6251A uses a high-accuracy trimmed
band-gap voltage reference to regulate the battery charging
voltage. The VADJ input adjusts the charger output voltage,
and the VADJ control voltage can vary from 0 to VREF,
providing a 10% adjustment range (from 4.2V-5% to
4.2V+5%) on CSON regulation voltage. An overall voltage
accuracy of better than 0.5% is achieved.
The synchronous buck converter uses external N-channel
MOSFETs to convert the input voltage to the required
charging current and charging voltage. Figure 12 shows the
ISL6251, ISL6251A typical application circuit with charging
current and charging voltage fixed at specific values. The
typical application circuit shown in Figure 13 shows the
ISL6251, ISL6251A typical application circuit which uses a
micro-controller to adjust the charging current set by CHLIM
input. The voltage at CHLIM and the value of R1 sets the
charging current. The DC/DC converter generates the
control signals to drive two external N-channel MOSFETs to
regulate the voltage and current set by the ACLIM, CHLIM,
VADJ and CELLS inputs.
The per-cell battery termination voltage is a function of the
battery chemistry. Consult the battery manufacturers to
determine this voltage.
• Float VADJ to set the battery voltage V
number of the cells,
= 4.2V ×
CSON
• Connect VADJ to VREF to set 4.41V × number of cells,
• Connect VADJ to ground to set 3.99V × number of the
cells.
The ISL6251, ISL6251A features a voltage regulation loop
(VCOMP) and two current regulation loops (ICOMP). The
VCOMP voltage regulation loop monitors CSON to ensure
that its voltage never exceeds the voltage and regulates the
battery charge voltage set by VADJ. The ICOMP current
regulation loops regulate the battery charging current
delivered to the battery to ensure that it never exceeds the
charging current limit set by CHLIM; and the ICOMP current
regulation loops also regulate the input current drawn from
the AC adapter to ensure that it never exceeds the input
current limit set by ACLIM, and to prevent a system crash
and AC adapter overload.
So, the maximum battery voltage of 17.6V can be achieved.
Note that other battery charge voltages can be set by
connecting a resistor divider from VREF to ground. The
resistor divider should be sized to draw no more than 100µA
from VREF; or connect a low impedance voltage source like
the D/A converter in the micro-controller. The programmed
battery voltage per cell can be determined by the following
equation:
VCELL = 0.175 VVADJ + 3.99V
An external resistor divider from VREF sets the voltage at
VADJ according to:
PWM Control
The ISL6251, ISL6251A employs a fixed frequency PWM
current mode control architecture with a feed forward
function. The feed-forward function maintains a constant
modulator gain of 11 to achieve fast line regulation as the
buck input voltage changes. When the battery charge
||
R
514k
bot_VADJ
------------------------------------------------------------------------------------------------
= VREF ×
V
VADJ
R
||
top_VADJ 514k + R
||
514k
bot_VADJ
FN9202.2
May 10, 2006
12
ISL6251, ISL6251A
where R
and R
are external resistors at
top_VADJ
bias current and less influence on current-sense accuracy
and voltage regulation accuracy.
bot_VADJ
VADJ. To minimize accuracy loss due to interaction with
VADJ’s internal resistor divider, ensure the AC resistance
looking back into the external resistor divider is less than 25k.
Setting the Input Current Limit
The total input current from an AC adapter, or other DC
source, is a function of the system supply current and the
battery-charging current. The input current regulator limits
the input current by reducing the charging current, when the
input current exceeds the input current limit set point.
System current normally fluctuates as portions of the system
are powered up or down. Without input current regulation,
the source must be able to supply the maximum system
current and the maximum charger input current
Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+
cells. When charging other cell chemistries, use CELLS to
select an output voltage range for the charger. The internal
error amplifier gm1 maintains voltage regulation. The voltage
error amplifier is compensated at VCOMP. The component
values shown in Figure 12 provide suitable performance for
most applications. Individual compensation of the voltage
regulation and current-regulation loops allows for optimal
compensation.
simultaneously. By using the input current limiter, the current
capability of the AC adapter can be lowered, reducing
system cost.
TABLE 1. CELL NUMBER PROGRAMMING
CELLS
VDD
CELL NUMBER
The ISL6251, ISL6251A limits the battery charge current
when the input current-limit threshold is exceeded, ensuring
the battery charger does not load down the AC adapter
voltage. This constant input current regulation allows the
adapter to fully power the system and prevent the AC
adapter from overloading and crashing the system bus.
4
3
2
GND
Float
Setting the Battery Charge Current Limit
The CHLIM input sets the maximum charging current. The
current set by the current sense-resistor connects between
CSOP and CSON. The full-scale differential voltage between
CSOP and CSON is 165mV for CHLIM = 3.3V, so the
maximum charging current is 4.125A for a 40mΩ sensing
resistor. Other battery charge current-sense threshold
values can be set by connecting a resistor divider from
VREF or 3.3V to ground, or by connecting a low impedance
voltage source like a D/A converter in the micro-controller.
Unlike VADJ and ACLIM, CHLIM does not have an internal
resistor divider network. The charge current limit threshold is
given by:
An internal amplifier gm3 compares the voltage between
CSIP and CSIN to the input current limit threshold voltage
set by ACLIM. Connect ACLIM to REF, Float and GND for
the full-scale input current limit threshold voltage of 100mV,
75mV and 50mV, respectively, or use a resistor divider from
VREF to ground to set the input current limit as the following
equation:
1
0.05
⎛
⎞
⎟
IINPUT
=
VACLIM + 0.050
⎜
R2 VREF
⎝
⎠
An external resistor divider from VREF sets the voltage at
ACLIM according to:
V
165mV
CHLIM
3.3V
------------------- ---------------------
I
=
||
R
152k
CHG
bot_ACLIM
------------------------------------------------------------------------------------------------------
R
1
V
= VREF ×
ACLIM
R
||
top_ACLIM 152k + R
||
152k
bot_ACLIM
To set the trickle charge current for the dumb charger, a
resistor in series with a switch Q3 (Figure 12) controlled by
the micro-controller is connected from CHLIM pin to ground.
The trickle charge current is determined by:
where R
and R are external resistors at
top_ACLIM
bot_ACLIM
ACLIM. To minimize accuracy loss due to interaction with
ACLIM’s internal resistor divider, ensure the AC resistance
looking back into the external resistor divider is less than 25k.
V
165mV
CHLIM,trickle
------------------- ---------------------------------------
I
=
CHG
R
3.3V
1
When choosing the current sense resistor, note that the
voltage drop across this resistor causes further power
dissipation, reducing efficiency. The AC adapter current
sense accuracy is very important. Use a 1% tolerance
current-sense resistor. The highest accuracy of ±3% is
achieved with 100mV current-sense threshold voltage for
ACLIM = VREF, but it has the highest power dissipation. For
example, it has 400mW power dissipation for rated 4A AC
adapter and 1W sensing resistor may have to be used. ±4%
and ±6% accuracy can be achieved with 75mV and 50mV
current-sense threshold voltage for ACLIM = Floating and
ACLIM = GND, respectively.
When the CHLIM voltage is below 88mV (typical), it will
disable the battery charger. When choosing the current
sensing resistor, note that the voltage drop across the
sensing resistor causes further power dissipation, reducing
efficiency. However, adjusting CHLIM voltage to reduce the
voltage across the current sense resistor R1 will degrade
accuracy due to the smaller signal to the input of the current
sense amplifier. There is a trade-off between accuracy and
power dissipation. A low pass filter is recommended to
eliminate switching noise. Connect the resistor to the CSOP
pin instead of the CSON pin, as the CSOP pin has lower
FN9202.2
May 10, 2006
13
ISL6251, ISL6251A
A low pass filter is suggested to eliminate the switching
temperature characteristic that abruptly decreases above a
critical temperature. This arrangement automatically shuts
down the charger when the battery pack is above a critical
temperature.
noise. Connect the resistor to CSIN pin instead of CSIP pin
because CSIN pin has lower bias current and less influence
on the current-sense accuracy.
Another method for inhibiting charging is to force CHLIM
below 88mV (typ).
AC Adapter Detection
Connect the AC adapter voltage through a resistor divider to
ACSET to detect when AC power is available, as shown in
Figure 12. ACPRN is an open-drain output and is high when
Short Circuit Protection and 0V Battery Charging
Since the battery charger will regulate the charge current to
the limit set by CHLIM, it automatically has short circuit
protection and is able to provide the charge current to wake
up an extremely discharged battery.
ACSET is less than V
, and active low when ACSET is
are given by:
th,rise
above V
. V
and V
th,fall
th,fall th,rise
⎛
⎜
⎜
⎝
⎞
⎟
⎠
R
8
⎟
V
=
=
+1 •V
th,rise
ACSET
R
9
Over Temperature Protection
If the die temp exceeds 150°C, it stops charging. Once the
die temp drops below 125°C, charging will start up again.
⎛
⎜
⎜
⎝
⎞
R
R
8
9
⎟
V
+1 •V
− I
R
hys 8
th,fall
ACSET
⎟
⎠
Application Information
Where I
is the ACSET input bias current hysteresis and
hys
= 1.24V (min), 1.26V (typ) and 1.28V (max). The
V
The following battery charger design refers to the typical
application circuit in Figure 12, where typical battery
configuration of 4S2P is used. This section describes how to
select the external components including the inductor, input
and output capacitors, switching MOSFETs, and current
sensing resistors.
ACSET
hysteresis is I R , where I = 2.2µA (min), 3.4µA (typ)
and 4.4µA (max).
hys
8
hys
Current Measurement
Use ICM to monitor the input current being sensed across
CSIP and CSIN. The output voltage range is 0 to 2.5V. The
voltage of ICM is proportional to the voltage drop across
CSIP and CSIN, and is given by the following equation:
Inductor Selection
The inductor selection has trade-offs between cost, size and
efficiency. For example, the lower the inductance, the
smaller the size, but ripple current is higher. This also results
in higher AC losses in the magnetic core and the windings,
which decrease the system efficiency. On the other hand,
the higher inductance results in lower ripple current and
smaller output filter capacitors, but it has higher DCR (DC
resistance of the inductor) loss, and has slower transient
response. So, the practical inductor design is based on the
inductor ripple current being ±(15-20)% of the maximum
operating DC current at maximum input voltage. The
required inductance can be calculated from:
ICM = 19.9 • I
• R
2
INPUT
where I
INPUT
ICM has ±3% accuracy.
is the DC current drawn from the AC adapter.
A low pass filter connected to ICM output is used to filter the
switching noise.
LDO Regulator
VDD provides a 5.075V supply voltage from the internal LDO
regulator from DCIN and can deliver up to 30mA of current.
The MOSFET drivers are powered by VDDP, which must be
connected to VDDP as shown in Figure 12. VDDP connects
to VDD through an external resistor. Bypass VDDP and VDD
with a 1µF capacitor.
V
− VBAT
VBAT
IN,MAX
L =
Δ IL
V
fs
IN,MAX
Where V
, V
, and f are the maximum input
s
IN,MAX BAT
Shutdown
voltage, battery voltage and switching frequency,
respectively. The inductor ripple current ΔI is found from:
The ISL6251, ISL6251A features a low-power shutdown
mode. Driving EN low shuts down the charger. In shutdown,
the DC/DC converter is disabled, and VCOMP and ICOMP
are pulled to ground. The ICM, ACPRN outputs continue to
function.
Δ IL = 30% ⋅ IBAT,MAX
where the maximum peak-to-peak ripple current is 30% of
the maximum charge current is used.
EN can be driven by a thermistor to allow automatic
shutdown when the battery pack is hot. Often a NTC
thermistor is included inside the battery pack to measure its
temperature. When connected to the charger, the thermistor
forms a voltage divider with a resistive pull-up to the VREF.
The threshold voltage of EN is 1.06V with 60mV hysteresis.
The thermistor can be selected to have a resistance vs
For V
IN,MAX
= 19V, V
BAT
= 16.8V, I = 2.6A, and
BAT,MAX
f = 300kHz, the calculated inductance is 8.3µH. Choosing
s
the closest standard value gives L = 10µH. Ferrite cores are
often the best choice since they are optimized at 300kHz to
FN9202.2
May 10, 2006
14
ISL6251, ISL6251A
600kHz operation with low core loss. The core must be large
MOSFET turning on; otherwise, cross-conduction problems
enough not to saturate at the peak inductor current I
:
may occur. Reasonably slowing turn-on speed of the
high-side MOSFET by connecting a resistor between the
BOOT pin and gate drive supply source, and the high sink
current capability of the low-side MOSFET gate driver help
reduce the possibility of cross-conduction.
Peak
1
IPeak = IBAT ,MAX
+
Δ IL
2
Output Capacitor Selection
The output capacitor in parallel with the battery is used to
absorb the high frequency switching ripple current and
smooth the output voltage. The RMS value of the output
For the high-side MOSFET, the worst-case conduction
losses occur at the minimum input voltage:
VOUT
PQ1,Conduction
=
IB2AT RDSON
ripple current I
is given by:
rms
VIN
V
IN,MAX
IRMS
=
D
(1 − D
)
The optimum efficiency occurs when the switching losses
equal the conduction losses. However, it is difficult to
calculate the switching losses in the high-side MOSFET
since it must allow for difficult-to-quantify factors that
influence the turn-on and turn-off times. These factors
include the MOSFET internal gate resistance, gate charge,
threshold voltage, stray inductance, pull-up and pull-down
resistance of the gate driver. The following switching loss
calculation provides a rough estimate.
12 L fs
where the duty cycle D is the ratio of the output voltage
(battery voltage) over the input voltage for continuous
conduction mode which is typical operation for the battery
charger. During the battery charge period, the output voltage
varies from its initial battery voltage to the rated battery
voltage. So, the duty cycle change can be in the range of
between 0.53 and 0.88 for the minimum battery voltage of
10V (2.5V/Cell) and the maximum battery voltage of 16.8V.
Qgd
Qgd
1
2
1
2
PQ1,Switching
=
V I fs
+
V I fs
+ QrrVIN fs
IN LV
IN LP
For V
IN,MAX
= 19V, VBAT = 16.8V, L = 10µH, and
Ig,source
Ig,sin k
f = 300kHz, the maximum RMS current is 0.19A. A typical
s
Where Q : drain-to-gate charge, Q : total reverse recovery
gd rr
10F ceramic capacitor is a good choice to absorb this
current and also has very small size. The tantalum capacitor
has a known failure mechanism when subjected to high
surge current.
charge of the body-diode in low side MOSFET, I : inductor
LV
valley current, I
Inductor peak current, I
and
g,sink
LP:
are the peak gate-drive source/sink current of Q1,
I ,
g source
respectively.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads. Beads may be added in
series with the battery pack to increase the battery
To achieve low switching losses, it requires low drain-to-gate
charge Q . Generally, the lower the drain-to-gate charge,
gd
the higher the on-resistance. Therefore, there is a trade-off
between the on-resistance and drain-to-gate charge. Good
MOSFET selection is based on the Figure of Merit (FOM),
which is a product of the total gate charge and
on-resistance. Usually, the smaller the value of FOM, the
higher the efficiency for the same application.
impedance at 300kHz switching frequency. Switching ripple
current splits between the battery and the output capacitor
depending on the ESR of the output capacitor and battery
impedance. If the ESR of the output capacitor is 10mΩ and
battery impedance is raised to 2Ω with a bead, then only
0.5% of the ripple current will flow in the battery.
For the low-side MOSFET, the worst-case power dissipation
occurs at minimum battery voltage and maximum input
voltage:
MOSFET Selection
The Notebook battery charger synchronous buck converter
has the input voltage from the AC adapter output. The
maximum AC adapter output voltage does not exceed 25V.
Therefore, 30V logic MOSFET should be used.
⎛
⎞
⎟
⎟
⎠
VOUT
VIN
2
⎜
PQ2 = 1 −
IBAT RDSON
⎜
⎝
The high side MOSFET must be able to dissipate the
conduction losses plus the switching losses. For the battery
charger application, the input voltage of the synchronous
buck converter is equal to the AC adapter output voltage,
which is relatively constant. The maximum efficiency is
achieved by selecting a high side MOSFET that has the
conduction losses equal to the switching losses. Ensure that
ISL6251, ISL6251A LGATE gate driver can supply sufficient
gate current to prevent it from conduction, which is due to
the injected current into the drain-to-source parasitic
Choose a low-side MOSFET that has the lowest possible
on-resistance with a moderate-sized package like the SO-8
and is reasonably priced. The switching losses are not an
issue for the low side MOSFET because it operates at
zero-voltage-switching.
Choose a Schottky diode in parallel with low-side MOSFET
Q2 with a forward voltage drop low enough to prevent the
low-side MOSFET Q2 body-diode from turning on during the
dead time. This also reduces the power loss in the high-side
MOSFET associated with the reverse recovery of the
low-side MOSFET Q2 body diode.
capacitor (Miller capacitor C ), and caused by the voltage
gd
rising rate at phase node at the time instant of the high-side
FN9202.2
May 10, 2006
15
ISL6251, ISL6251A
TABLE 2. COMPONENT LIST (Continued)
PART NUMBERS AND MANUFACTURER
Signal N-channel MOSFET, 2N7002
40mΩ, ±1%, LRC-LR2512-01-R040-F, IRC
20mΩ, ±1%, LRC-LR2010-01-R020-F, IRC
18Ω, ±5%, (0805)
As a general rule, select a diode with DC current rating equal
to one-third of the load current. One option is to choose a
combined MOSFET with the Schottky diode in a single
package. The integrated packages may work better in
practice because there is less stray inductance due to a
short connection. This Schottky diode is optional and may be
removed if efficiency loss can be tolerated. In addition,
ensure that the required total gate drive current for the
selected MOSFETs should be less than 24mA. So, the total
gate charge for the high-side and low-side MOSFETs is
limited by the following equation:
PARTS
Q3
R1
R2
R3
R4
2.2Ω, ±5%, (0805)
R5
100kΩ, ±5%, (0805)
R6
10k, ±5%, (0805)
IGATE
R7
100Ω, ±5%, (0805)
QGATE
≤
fs
R8, R11
R9
130k, ±1%, (0805)
10.2kΩ, ±1%, (0805)
Where I
is the total gate drive current and should be
GATE
less than 24mA. Substituting I
= 24mA and f = 300kHz
s
GATE
R10
R12
R13
4.7Ω, ±5%, (0805)
into the above equation yields that the total gate charge
should be less than 80nC. Therefore, the ISL6251,
ISL6251A easily drives the battery charge current up to 10A.
20kΩ, ±1%, (0805)
1.87kΩ, ±1%, (0805)
Input Capacitor Selection
Loop Compensation Design
The input capacitor absorbs the ripple current from the
synchronous buck converter, which is given by:
ISL6251, ISL6251A uses constant frequency current mode
control architecture to achieve fast loop transient response.
An accurate current sensing resistor in series with the output
inductor is used to regulate the charge current, and the
sensed current signal is injected into the voltage loop to
achieve current mode control to simplify the loop
compensation design. The inductor is not considered as a
state variable for current mode control and the system
becomes single order system. It is much easier to design a
compensator to stabilize the voltage loop than voltage mode
control. Figure 14 shows the small signal model of the
synchronous buck regulator.
V
(
V
−V
OUT
)
OUT IN
I
= I
BAT
rms
V
IN
This RMS ripple current must be smaller than the rated RMS
current in the capacitor datasheet. Non-tantalum chemistries
(ceramic, aluminum, or OSCON) are preferred due to their
resistance to power-up surge currents when the AC adapter
is plugged into the battery charger. For Notebook battery
charger applications, it is recommend that ceramic
capacitors or polymer capacitors from Sanyo be used due to
their small size and reasonable cost.
PWM Comparator Gain F :
m
Table 2 shows the component lists for the typical application
circuit in Figure 12.
The PWM comparator gain F for peak current mode control
m
is given by:
TABLE 2. COMPONENT LIST
11
---------
M =
.
V
PARTS
PART NUMBERS AND MANUFACTURER
IN
C1, C10
10μF/25V ceramic capacitor, Taiyo Yuden
TMK325 MJ106MY X5R (3.2x2.5x1.9mm)
Power Stage Transfer Functions
Transfer function F (S) from control to output voltage is:
1
C2, C4, C8 0.1μF/50V ceramic capacitor
S
C3, C7, C9 1μF/10V ceramic capacitor, Taiyo Yuden
1 +
ˆ
LMK212BJ105MG
v
ω
o
ˆ
esr
S
F
(
S
)
=
= V
1
in
2
d
S
ω
1
C5
C6
10nF ceramic capacitor
+
+1
2
o
ω Q
o
p
6.8nF ceramic capacitor
1
C
ω
=
o
o
C11
D1
3300pF ceramic capacitor
ω
=
,
Where
Q
≈ R
,
esr
p
o
LC
R C
o
L
c
o
30V/3A Schottky diode, EC31QS03L (optional)
100mA/30V Schottky Diode, Central Semiconductor
8A/30V Schottky rectifier, STPS8L30B (optional)
10μH/3.8A/26mΩ, Sumida, CDRH104R-100
30V/35mΩ, FDS6912A, Fairchild.
Transfer function F (S) from control to inductor current is:
2
D2, D3
D4
S
1 +
ˆ
i
V
ω
z
1
L
ˆ
in
F
(
S
)
=
=
ω
≈
2
, where
.
z
2
R
+ R
L
R C
o
d
o
S
S
o
L
+
+1
2
o
ω Q
p
ω
o
Q1, Q2
FN9202.2
May 10, 2006
16
ISL6251, ISL6251A
Current loop gain T(S) is expressed as the following
i
Vo
equation:
T (S) = 0.25 R F (S)M
i
T 2
VFB
VREF
-
VCOMP
where R is the trans-resistance in current loop. R is
T
T
gm
usually equal to the product of the charging current sensing
resistance and the gain of the current sense amplifier, CA2.
+
R1
C1
For ISL6251, ISL6251A, R = 20R .
T
1
The voltage gain with open current loop is:
T (S) = KM F (S)A (S)
v
1
V
V
FB
FIGURE 15. VOLTAGE LOOP COMPENSATOR
K =
Where
, V is the feedback voltage of the voltage
FB
V
o
error amplifier. The Voltage loop gain with current loop
Compensator design goal:
closed is given by:
• High DC gain
T
(S)
v
1
5
1
⎛
⎜
⎞
⎟
L (S) =
v
−
f
s
• Loop bandwidth f :
c
1 +T
S
( )
i
20
⎝
⎠
• Gain margin: >10dB
If T(S)>>1, then it can be simplified as follows:
i
• Phase margin: 40°
S
1 + -----------
4V (R + R )
ω
esr
The compensator design procedure is as follows:
1
FB
O
L
-------------------------------------------------------------------
-----------------
A (S), ω ≈
V P
L (S) =
V
V
R
S
R C
O
T
O O
1 + -------
1. Put compensator zero at:
ω
P
1
ω
=
(1− 3
)
cz
From the above equation, it is shown that the system is a
R C
o
o
ω
single order system, which has a single pole located at
p
2. Put one compensator pole at zero frequency to achieve
high DC gain, and put another compensator pole at either
ESR zero frequency or half switching frequency,
whichever is lower.
before the half switching frequency. Therefore, simple type II
compensator can be easily used to stabilize the system.
ˆ
ˆ
iin
L
i
ˆ
vo
L
The loop gain T (S) at cross over frequency of f has unity
v
c
ˆ
d
V
in
gain. Therefore, the compensator resistance R is
ˆ
1
1:D
I d
ˆ
v
L
in
determined by:
Rc
Ro
+
RT
8πf V
C R
O T
V
FB
C
O
R
= --------------------------------------
1
g
Co
m
VCA2
where g is the trans-conductance of the voltage loop error
m
amplifier. Compensator capacitor C1 is then given by:
Ti(S)
ˆ
d
K
11/Vin
1
C
=
1
R ω
1
cz
+
Tv(S)
0.25VCA2
-
Example: V = 19V, V = 16.8V, I = 2.6A, f = 300kHz,
in
C = 10μF/10mΩ, L = 10μH, g = 250μs, R = 0.8Ω,
o
o
s
ˆ
vcomp
o
m
T
-Av(S)
V
= 2.1V, f = 20kHz, then compensator resistance
FB
c
R = 10kΩ. Choose R = 10kΩ. Put the compensator zero at
1
1
FIGURE 14. SMALL SIGNAL MODEL OF SYNCHRONOUS
BUCK REGULATOR
1.5kHz. The compensator capacitor is C = 6.5nF.
1
Therefore, choose voltage loop compensator: R = 10k,
1
Figure 15 shows the voltage loop compensator, and its
transfer function is expressed as follows:
C = 6.5nF.
1
S
1 +
ˆ
v
ω
comp
cz
A
(
S
)
=
= g
v
m
ˆ
v
SC
1
FB
1
ω
=
where
cz
R C
1
1
FN9202.2
May 10, 2006
17
ISL6251, ISL6251A
PHASE Pin
PCB Layout Considerations
This trace should be short, and positioned away from other
weak signal traces. This node has a very high dv/dt with a
voltage swing from the input voltage to ground. No trace
should be in parallel with it. This trace is also the return path
for UGATE. Connect this pin to the high-side MOSFET
source.
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
UGATE Pin
This pin has a square shape waveform with high dv/dt. It
provides the gate drive current to charge and discharge the
top MOSFET with high di/dt. This trace should be wide,
short, and away from other traces similar to the LGATE.
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
BOOT Pin
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
This pin’s di/dt is as high as the UGATE; therefore, this trace
should be as short as possible.
CSOP, CSON Pins
Component Placement
The current sense resistor connects to the CSON and the
CSOP pins through a low pass filter. The CSON pin is also
used as the battery voltage feedback. The traces should be
away from the high dv/dt and di/di pins like PHASE, BOOT
pins. In general, the current sense resistor should be close
to the IC. Other layout arrangements should be adjusted
accordingly.
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under the
IC has less noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
EN Pin
Signal Ground and Power Ground Connection.
This pin stays high at enable mode and low at idle mode and
is relatively robust. Enable signals should refer to the signal
ground.
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
DCIN Pin
This pin connects to AC adapter output voltage, and should
be less noise sensitive.
GND and VDD Pin
Copper Size for the Phase Node
At least one high quality ceramic decoupling cap should be
used to cross these two pins. The decoupling cap can be put
close to the IC.
The capacitance of PHASE should be kept very low to
minimize ringing. It would be best to limit the size of the
PHASE node copper in strict accordance with the current
and thermal management of the application.
LGATE Pin
Identify the Power and Signal Ground
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
The input and output capacitors of the converters, the source
terminal of the bottom switching MOSFET PGND should
connect to the power ground. The other components should
connect to signal ground. Signal and power ground are tied
together at one point.
PGND Pin
Clamping Capacitor for Switching MOSFET
PGND pin should be laid out to the negative side of the
relevant output cap with separate traces. The negative side
of the output capacitor must be close to the source node of
the bottom MOSFET. This trace is the return path of LGATE.
It is recommended that ceramic caps be used closely
connected to the drain of the high-side MOSFET, and the
source of the low-side MOSFET. This capacitor reduces the
noise and the power loss of the MOSFET.
FN9202.2
May 10, 2006
18
ISL6251, ISL6251A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)
2X
0.15
E1/2
A2
C A
MILLIMETERS
D
A
9
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
D/2
A
A1
A2
A3
b
0.80
0.90
-
D1
-
-
0.02
-
D1/2
2X
0.65
9
N
0.15 C
B
6
0.20 REF
9
INDEX
AREA
1
2
3
E/2
9
0.18
2.95
2.95
0.25
0.30
3.25
3.25
5,8
E1
D
5.00 BSC
-
E
B
D1
D2
E
4.75 BSC
9
2X
3.10
7,8
0.15 C
B
5.00 BSC
-
2X
TOP VIEW
SIDE VIEW
0.15 C A
E1
E2
e
4.75 BSC
9
0
3.10
7,8
4X
A
/ /
0.10 C
0.08 C
0.50 BSC
-
C
k
0.20
0.50
-
0.60
28
7
-
-
L
0.75
8
SEATING PLANE
A3 A1
9
N
2
5
NX b
Nd
Ne
P
3
0.10 M C A B
4X P
7
3
D2
D2
8
7
-
-
-
0.60
12
9
NX k
(DATUM B)
θ
-
9
2
N
4X P
Rev. 1 11/04
1
NOTES:
(DATUM A)
2
3
(Ne-1)Xe
REF.
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
E2
6
INDEX
AREA
7
8
E2/2
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
NX L
8
N
e
9
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
(Nd-1)Xe
REF.
CORNER
OPTION 4X
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
BOTTOM VIEW
A1
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
C
L
C
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
L
L
L
10
10
L1
L1
e
e
C
C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
FN9202.2
May 10, 2006
19
ISL6251, ISL6251A
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M24.15
N
24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
INDEX
AREA
0.25(0.010)
M
B M
H
E
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
-B-
SYMBOL
MAX
0.069
0.010
0.061
0.012
0.010
0.344
0.157
MIN
1.35
0.10
-
MAX
1.75
0.25
1.54
0.30
0.25
8.74
3.98
NOTES
A
A1
A2
B
0.053
0.004
-
-
1
2
3
-
L
0.25
0.010
SEATING PLANE
A
-
-A-
0.008
0.007
0.337
0.150
0.20
0.18
8.55
3.81
9
D
h x 45°
C
D
E
-
-C-
3
α
4
A2
e
A1
C
e
0.025 BSC
0.635 BSC
-
B
0.10(0.004)
H
h
0.228
0.0099
0.016
0.244
0.0196
0.050
5.80
0.26
0.41
6.19
0.49
1.27
-
0.17(0.007) M
C
A M B S
5
L
6
NOTES:
N
α
24
24
7
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
0°
8°
0°
8°
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 2 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual in-
dex feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9202.2
May 10, 2006
20
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