ISL6256HAZ [INTERSIL]
Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers; 高度集成的电池充电器具有自动电源选择器，用于笔记本电脑
| 型号： | ISL6256HAZ |
| 厂家： | 
Intersil |
| 描述： | Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers |
| 文件： | 总27页 (文件大小：653K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6256, ISL6256A
®
Data Sheet
July 19, 2007
FN6499.1
Highly Integrated Battery Charger with
Automatic Power Source Selector for
Notebook Computers
Features
• ±0.5% Charge Voltage Accuracy (-10°C to +100°C)
• ±3% Accurate Input Current Limit
The ISL6256, ISL6256A is a highly integrated battery charger
controller for Li-Ion/Li-Ion polymer batteries. High Efficiency is
achieved by a synchronous buck topology and the use of a
MOSFET, instead of a diode, for selecting power from the
adapter or battery. The low side MOSFET emulates a diode at
light loads to improve the light load efficiency and prevent
system bus boosting.
• ±3% Accurate Battery Charge Current Limit
• ±25% Accurate Battery Trickle Charge Current Limit
• Programmable Charge Current Limit, Adapter Current
Limit and Charge Voltage
• Fixed 300kHz PWM Synchronous Buck Controller with
Diode Emulation at Light Load
The constant output voltage can be selected for 2, 3 and 4
series Li-Ion cells with 0.5% accuracy over-temperature. It
can also be programmed between 4.2V+5%/cell and 4.2V-
5%/cell to optimize battery capacity. When supplying the load
and battery charger simultaneously, the input current limit for
the AC adapter is programmable to within 3% accuracy to
avoid overloading the AC adapter, and to allow the system to
make efficient use of available adapter power for charging. It
also has a wide range of programmable charging current. The
ISL6256, ISL6256A provides outputs that are used to monitor
the current drawn from the AC adapter, and monitor for the
presence of an AC adapter. The ISL6256, ISL6256A
automatically transitions from regulating current mode to
regulating voltage mode.
• Overvoltage Protection
• Output for Current Drawn from AC Adapter
• AC Adapter Present Indicator
• Fast Input Current Limit Response
• Input Voltage Range 7V to 25V
• Support 2-, 3- and 4-Cells Battery Pack
• Up to 17.64V Battery-Voltage Set Point
• Control Adapter Power Source Select MOSFET
• Thermal Shutdown
• Aircraft Power Capable
ISL6256, ISL6256A has a feature for automatic power source
selection by switching to the battery when the AC adapter is
removed or switching to the AC adapter when the AC adapter
is available. It also provides a DC adapter monitor to support
aircraft power applications with the option of no battery
charging.
• DC Adapter Present Indicator
• Battery Discharge MOSFET Control
• Less than 10µA Battery Leakage Current
• Supports Pulse Charging
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART
NUMBER
(Notes 1, 2)
TEMP
RANGE
(°C)
Applications
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
• Notebook, Desknote and Sub-notebook Computers
• Personal Digital Assistant
ISL6256HRZ* ISL 6256HRZ
ISL6256HAZ* ISL 6256HAZ
-10 to +100 28 Ld 5x5 QFN L28.5×5
-10 to +100 28 Ld QSOP M28.15
ISL6256AHRZ* ISL6256 AHRZ -10 to +100 28 Ld 5x5 QFN L28.5×5
ISL6256AHAZ* ISL6256 AHAZ -10 to +100 28 Ld QSOP M28.15
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. *Add “-T” for Tape and Reel. Please refer to TB347 for details on reel
specifications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL6256, ISL6256A
Pinouts
ISL6256, ISL6256A
(28 LD QFN)
ISL6256, ISL6256A
(28 LD QSOP)
TOP VIEW
TOP VIEW
1
2
3
4
5
28
27
26
25
24
DCPRN
ACPRN
CSON
CSOP
CSIN
DCIN
VDD
28 27 26 25 24 23 22
ACSET
DCSET
EN
1
2
3
4
5
6
7
21
EN
CSOP
CELLS
20 CSIN
6
23
22
21
20
19
18
17
16
15
CSIP
CELLS
ICOMP
VCOMP
ICM
CSIP
19
18
17
ICOMP
7
SGATE
BGATE
PHASE
UGATE
BOOT
VDDP
VCOMP
SGATE
BGATE
8
9
ICM
VREF
10
11
12
13
14
VREF
CHLIM
ACLIM
VADJ
16 PHASE
UGATE
15
CHLIM
8
9
10
11 12 13 14
LGATE
PGND
GND
FN6499.1
July 19, 2007
2
ISL6256, ISL6256A
SGATE
ICM
CSIP CSIN
DCSET
DCPRN
-
ACSET
ACPRN
+
X19.9
CA1
+
+
1.26V
-
1.26V
-
VREF
152kΩ
-
CSON
-
BGATE
gm3
ADAPTER
CURRENT
LIMIT SET
+
ACLIM
ICOMP
+
152kΩ
DCIN
VDD
LDO
REGULATOR
MIN
CURRENT
BUFFER
BOOT
300kHz
RAMP
UGATE
PHASE
-
PWM
MIN
VOLTAGE
BUFFER
Σ
+
VCOMP
VADJ
VDDP
VREF
-0.25
LGATE
PGND
514kΩ
514kΩ
gm1
2.1V
288kΩ
32kΩ
-
gm2
-
1.065V
-
+
16kΩ
48kΩ
VOLTAGE
SELECTOR
EN
CELLS
VREF
CA2
X19.9
VDD
-
+
REFERENCE
GND
FB
CSON CSOP
CHLIM
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
FN6499.1
July 19, 2007
3
ISL6256, ISL6256A
Q3
AC ADAPTER
VDD
C8
R8
130k
1%
0.1µF
CSON
Q5
R9
10.2k
1%
DCIN
SGATE
CSIP
R21
2.2Ω
22Ω
ACSET
R2
C2
0.1µF
ISL6256
20mΩ
C7
1µF
ISL6256A
SYSTEM LOAD
CSIN
BGATE
BOOT
VDDP
R22
R10
4.7Ω
3.3V
VDDP
D2
VDD
Q4
C1:10µF
C9
1µF
R5
100k
TO HOST
CONTROLLER
UGATE
PHASE
LGATE
PGND
ACPRN
ICOMP
VCOMP
VADJ
Q1
C4
0.1µF
C6
R6
6.8nF
C5
10nF
D1
OPTIONAL
L
Q2
R11
4.7µH
4.7k
FLOATING
4.2V/CELL
22Ω
22Ω
CHARGE
ENABLE
CSOP
EN
R1
20mΩ
C3
0.047uF
ACLIM
VREF
BAT+
CSON
R12
VDD
4 CELLS
BATTERY
PACK
C10
22uF
CELLS
R12
20k 1%
2.6A CHARGE LIMIT
253mA TRICKLE CHARGE
VREF
BAT-
ICM
CHLIM
C11
3300pF
R7: 100Ω
R13
1.87k
1%
R11
130k
1%
GND
TRICKLE
CHARGE
Q6
FIGURE 2. ISL6256, ISL6256A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS
FN6499.1
July 19, 2007
4
ISL6256, ISL6256A
ADAPTER
Q3
C8
0.1µF
VDD
R8
130k
1%
CSON
Q5
R14
100k
1%
R9
10.2k
1%
DCIN
SGATE
CSIP
R21
2.2Ω
22Ω
ACSET
C2
0.1µF
R2
20mΩ
DCSET
R15
11.5k
1%
SYSTEM LOAD
CSIN
ISL6256
C7
1µF
ISL6256A
R22
Q4
BGATE
BOOT
VDDP
R10
4.7Ω
VDDP
C1:10µF
Q1
C9
1µF
VCC
D2
VDD
R16
R5
UGATE
PHASE
LGATE
PGND
100k
100k
C4
0.1µF
DIGITAL
INPUT
ACPRN
DCPRN
DIGITAL
INPUT
D1
OPTIONAL
L
Q2
4.7µH
D/A OUTPUT
OUTPUT
CHLIM
R11
22Ω
EN
CSOP
R7: 100Ω
R1
20mΩ
C3
A/D INPUT
ICM
0.047uF
C11
3300pF
VREF
5.15A INPUT
CSON
CELLS
VADJ
BAT+
R12
ACLIM
VREF
22Ω
HOST
C10
GND
CURRENT LIMIT
22µF
3 CELLS
C6
6.8nF
FLOATING
4.2V/CELL
R11, R12
R13: 10k
BATTERY
PACK
ICOMP
AVDD/VREF
GND
VCOMP
R6
4.7k
C5
10nF
SCL
SDL
SCL
SDL
A/D INPUT
GND
TEMP
BAT-
FIGURE 3. ISL6256, ISL6256A TYPICAL APPLICATION CIRCUIT WITH µP CONTROL AND AIRCRAFT POWER SUPPORT
FN6499.1
July 19, 2007
5
ISL6256, ISL6256A
Absolute Maximum Ratings
Thermal Information
DCIN, CSIP, CSON to GND. . . . . . . . . . . . . . . . . . . . .-0.3V to +28V
CSIP-CSIN, CSOP-CSON. . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
CSIP-SGATE, CSIP-BGATE . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 30V
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +35V
BOOT to VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 28V
ACLIM, ACPRN, CHLIM, DCPRN, VDD to GND. . . . . . . -0.3V to 7V
BOOT-PHASE, VDDP-PGND . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
ACSET and DCSET to GND (Note 3) . . . . . . . -0.3V to VDD +0.3V
ICM, ICOMP, VCOMP to GND. . . . . . . . . . . . . . -0.3V to VDD +0.3V
VREF, CELLS to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
UGATE. . . . . . . . . . . . . . . . . . . . . . . . PHASE -0.3V to BOOT +0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . PGND -0.3V to VDDP +0.3V
Thermal Resistance
θ
(°C/W)
θ
(°C/W)
JA
JC
QFN Package (Notes 4, 5). . . . . . . . . .
QSOP Package (Note 4) . . . . . . . . . . .
39
80
9.5
NA
Junction Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. ACSET may be operated 1V below GND if the current through ACSET is limited to less than 1mA.
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C
= 1µF, I = 0mA,
VDD
VDD
T
= -10°C to +100°C, T ≤ +125°C, Unless Otherwise Noted.
J
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY AND BIAS REGULATOR
DCIN Input Voltage Range
7
25
V
mA
µA
V
DCIN Quiescent Current
EN = VDD or GND, 7V ≤ DCIN ≤ 25V
1.4
3
3
10
Battery Leakage Current (Note 6)
VDD Output Voltage/Regulation
DCIN = 0, no load
7V ≤ DCIN ≤ 25V, 0 ≤ I
VDD Rising
≤ 30mA
4.925
4.0
5.075
4.4
5.225
4.6
VDD
VDD Undervoltage Lockout Trip Point
V
Hysteresis
200
250
400
2.415
0.5
mV
V
Reference Output Voltage VREF
Battery Charge Voltage Accuracy
0 ≤ I
≤ 300µA
2.365
-0.5
-0.5
-0.5
-0.5
2.39
VREF
CSON = 16.8V, CELLS = VDD, VADJ = Float
CSON = 12.6V, CELLS = GND, VADJ = Float
CSON = 8.4V, CELLS = Float, VADJ = Float
%
0.5
%
0.5
%
CSON = 17.64V, CELLS = VDD,
VADJ = VREF
0.5
%
CSON = 13.23V, CELLS = GND,
VADJ = VREF
-0.5
0.5
%
CSON = 8.82V, CELLS = Float, VADJ = VREF
CSON = 15.96V, CELLS = VDD, VADJ = GND
CSON = 11.97V, CELLS = GND, VADJ = GND
CSON = 7.98V, CELLS = Float, VADJ = GND
-0.5
-0.5
-0.5
-0.5
0.5
0.5
0.5
0.5
%
%
%
%
TRIP POINTS
ACSET Threshold
1.24
2.4
1.26
3.4
1.28
4.4
V
ACSET Input Bias Current Hysteresis
ACSET Input Bias Current
µA
µA
ACSET ≥ 1.26V
2.4
3.4
4.4
FN6499.1
July 19, 2007
6
ISL6256, ISL6256A
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C
= 1µF, I = 0mA,
VDD
VDD
T
= -10°C to +100°C, T ≤ +125°C, Unless Otherwise Noted. (Continued)
J
A
PARAMETER
ACSET Input Bias Current
DCSET Threshold
TEST CONDITIONS
ACSET < 1.26V
MIN
-1
TYP
0
MAX
UNITS
1
µA
V
1.24
2.4
2.4
-1
1.26
3.4
3.4
0
1.28
4.4
4.4
1
DCSET Input Bias Current Hysteresis
DCSET Input Bias Current
DCSET Input Bias Current
OSCILLATOR
µA
µA
µA
DCSET ≥ 1.26V
DCSET < 1.26V
Frequency
245
300
1.6
1
355
kHz
V
PWM Ramp Voltage (peak-peak)
CSIP = 18V
CSIP = 11V
V
SYNCHRONOUS BUCK REGULATOR
Maximum Duty Cycle
97
99
1.8
1.0
1.0
1.8
1.8
1.0
1.0
1.8
99.6
3.0
%
Ω
A
UGATE Pull-Up Resistance
UGATE Source Current
UGATE Pull-down Resistance
UGATE Sink Current
BOOT-PHASE = 5V, 500mA source current
BOOT-PHASE = 5V, BOOT-UGATE = 2.5V
BOOT-PHASE = 5V, 500mA sink current
BOOT-PHASE = 5V, UGATE-PHASE = 2.5V
VDDP-PGND = 5V, 500mA source current
VDDP-PGND = 5V, VDDP-LGATE = 2.5V
VDDP-PGND = 5V, 500mA sink current
VDDP-PGND = 5V, LGATE = 2.5V
1.8
3.0
1.8
30
Ω
A
LGATE Pull-Up Resistance
LGATE Source Current
LGATE Pull-Down Resistance
LGATE Sink Current
Ω
A
Ω
A
Dead Time
Falling UGATE to rising LGATE or
falling LGATE to rising UGATE
10
0
ns
CHARGING CURRENT SENSING AMPLIFIER
Input Common-Mode Range
18
2
V
Input Bias Current at CSOP
Input Bias Current at CSON
CHLIM Input Voltage Range
5 < CSOP < 18V
0.25
75
µA
µA
V
5 < CSON < 18V
100
3.6
0
160
95
ISL6256
ISL6256: CHLIM = 3.3V
ISL6256: CHLIM = 2.0V
ISL6256: CHLIM = 0.2V
ISL6256A: CHLIM = 3.3V
ISL6256A: CHLIM = 2.0V
ISL6256A: CHLIM = 0.2V
165
100
10
170
105
15.0
168.3
103
12.5
mV
mV
mV
mV
mV
mV
mV
CSOP to CSON Full-Scale Current Sense
Voltage
5.0
161.7
97
ISL6256A
165
100
10
CSOP to CSON Full-Scale Current Sense
Voltage
7.5
ISL6256 CSOP to CSON Full-Scale
Current Sense Voltage formula
Charge current limit mode
0.2V < CHLIM < 3.3V
CHLIM*50
-5
CHLIM*50
+5
ISL6256A CSOP to CSON Full-Scale
Current Sense Voltage formula
Charge current limit mode
0.2V < CHLIM < 3.3V
CHLIM*49.72
-2.4
CHLIM*50.28
+2.4
mV
CHLIM Input Bias Current
CHLIM = GND or 3.3V, DCIN = 0V
CHLIM rising
-1
1
µA
CHLIM Power-Down Mode Threshold
Voltage
80
88
25
95
mV
CHLIM Power-Down Mode Hysteresis
Voltage
15
40
mV
FN6499.1
July 19, 2007
7
ISL6256, ISL6256A
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C
= 1µF, I = 0mA,
VDD
VDD
T
= -10°C to +100°C, T ≤ +125°C, Unless Otherwise Noted. (Continued)
J
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ADAPTER CURRENT SENSING AMPLIFIER
Input Common-Mode Range
7
25
V
Input Bias Current at CSIP and CSIN
Combined
CSIP = CSIN = 25V
100
130
µA
Input Bias Current at CSIN
0 < CSIN < DCIN
0.10
µA
ADAPTER CURRENT LIMIT THRESHOLD
CSIP to CSIN Full-Scale Current Sense
Voltage
ACLIM = VREF
ACLIM = Float
ACLIM = GND
ACLIM = VREF
ACLIM = GND
97
72
47
10
-20
100
75
103
78
mV
mV
mV
µA
50
53
ACLIM Input Bias Current
16
20
-16
-10
µA
VOLTAGE REGULATION ERROR AMPLIFIER
Error Amplifier Transconductance from
CSON to VCOMP
CELLS = VDD
30
µA/V
CURRENT REGULATION ERROR AMPLIFIER
Charging Current Error Amplifier
Transconductance
50
50
µA/V
µA/V
Adapter Current Error Amplifier
Transconductance
BATTERY CELL SELECTOR
CELLS Input Voltage for 4 Cell Select
CELLS Input Voltage for 3 Cell Select
CELLS Input Voltage for 2 Cell Select
MOSFET DRIVER
4.3
2.1
V
V
V
2
4.2
BGATE Pull-Up Current
BGATE Pull-Down Current
CSIP-BGATE Voltage High
CSIP-BGATE Voltage Low
CSIP-BGATE = 3V
CSIP-BGATE = 5V
10
2.7
8
30
4.0
9.6
0
45
5.0
11
mA
mA
V
-50
-100
50
mV
mV
DCIN-CSON Threshold for CSIP-BGATE DCIN = 12V, CSON Rising
Going High
0
100
DCIN-CSON Threshold Hysteresis
250
7
300
12
160
9
400
15
mV
mA
µA
V
SGATE Pull-Up Current
SGATE Pull-Down Current
CSIP-SGATE Voltage High
CSIP-SGATE Voltage Low
CSIP-SGATE = 3V
CSIP-SGATE = 5V
50
8
370
11
-50
2.5
0
50
mV
mV
CSIP-CSIN Threshold for CSIP-SGATE
Going High
8
13
CSIP-CSIN Threshold Hysteresis
2
5
8
mV
FN6499.1
July 19, 2007
8
ISL6256, ISL6256A
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C
= 1µF, I = 0mA,
VDD
VDD
T
= -10°C to +100°C, T ≤ +125°C, Unless Otherwise Noted. (Continued)
J
A
PARAMETER
LOGIC INTERFACE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
EN Input Voltage Range
EN Threshold Voltage
0
1.030
0.985
30
VDD
1.100
1.025
90
V
V
Rising
1.06
Falling
1.000
60
V
Hysteresis
EN = 2.5V
mV
µA
mA
µA
mA
µA
%
EN Input Bias Current
ACPRN Sink Current
ACPRN Leakage Current
DCPRN Sink Current
DCPRN Leakage Current
ICM Output Accuracy
1.8
3
2.0
8
2.2
11
ACPRN = 0.4V
ACPRN = 5V
-0.5
3
0.5
11
DCPRN = 0.4V
8
DCPRN = 5V
-0.5
-3
0.5
+3
CSIP-CSIN = 100mV
CSIP-CSIN = 75mV
CSIP-CSIN = 50mV
0
0
(V
= 19.9 x (V
-V ))
ICM
CSIP CSIN
-4
+4
%
-5
0
+5
%
Thermal Shutdown Temperature
150
25
°C
°C
Thermal Shutdown Temperature
Hysteresis
NOTE:
6. This is the sum of currents in these pins (CSIP, CSIN, BGATE, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V. No current in pins EN,
ACSET, DCSET, VADJ, CELLS, ACLIM, CHLIM.
FN6499.1
July 19, 2007
9
ISL6256, ISL6256A
Typical Operating Performance
DCIN = 20V, 4S2P Li-Battery, T = +25°C, Unless Otherwise Noted.
A
0.6
0.10
0.08
0.06
0.04
0.02
0.3
0.0
-0.3
-0.6
0.00
0
5
10
15
20
40
0
100
200
300
400
LOAD CURRENT (mA)
LOAD CURRENT (μA)
FIGURE 4. VDD LOAD REGULATION
FIGURE 5. VREF LOAD REGULATION
10
9
8
7
6
5
4
3
2
1
0
100
96
92
88
84
80
76
VCSON = 8.4V
2 CELLS
VCSON = 12.6V
3 CELLS
VCSON = 16.8V
4 CELLS
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
10
20
30
40
50
60
70
80
90 100
CSIP-CSIN (mV)
LOAD CURRENT (A)
FIGURE 6. ACCURACY vs AC ADAPTER CURRENT
FIGURE 7. SYSTEM EFFICIENCY vs CHARGE CURRENT
LOAD
CURRENT
5A/div
DCIN
10V/div
ADAPTER
CURRENT
5A/div
ACSET
1V/div
CHARGE
CURRENT
2A/div
DCSET
1V/div
LOAD STEP: 0A TO 4A
CHARGE CURRENT: 3A
AC ADAPTER CURRENT LIMIT: 5.15A
BATTERY
VOLTAGE
2V/div
DCPRN
5V/div
ACPRN
5V/div
FIGURE 8. AC AND DC ADAPTER DETECTION
FIGURE 9. LOAD TRANSIENT RESPONSE
FN6499.1
July 19, 2007
10
ISL6256, ISL6256A
Typical Operating Performance
DCIN = 20V, 4S2P Li-Battery, T = +25°C, Unless Otherwise Noted. (Continued)
A
CSON
5V/div
INDUCTOR
CURRENT
2A/div
EN
5V/div
BATTERY
REMOVAL
I
INSERTION
BATTERY
CSON
10V/div
INDUCTOR
CURRENT
2A/div
VCOMP
2V/div
VCOMP
CHARGE
CURRENT
2A/div
ICOMP
ICOMP
2V/div
FIGURE 10. CHARGE ENABLE AND SHUTDOWN
FIGURE 11. BATTERY INSERTION AND REMOVAL
CHLIM = 0.2V
CSON = 8V
PHASE
10V/div
PHASE
10V/div
INDUCTOR
CURRENT
1A/div
UGATE
2V/div
UGATE
5V/div
LGATE
2V/div
FIGURE 12. AC ADAPTER REMOVAL
FIGURE 13. AC ADAPTER INSERTION
BGATE-CSIP
2V/div
SGATE-CSIP
2V/div
ADAPTER REMOVAL
SYSTEM BUS
VOLTAGE
10V/div
SYSTEM BUS
VOLTAGE
10V/div
SGATE-CSIP
2V/div
BGATE-CSIP
2V/div
INDUCTOR
CURRENT
2A/div
INDUCTOR
CURRENT
2A/div
ADAPTER INSERTION
FIGURE 14. SWITCHING WAVEFORMS AT DIODE EMULATION
FIGURE 15. SWITCHING WAVEFORMS IN CC MODE
FN6499.1
July 19, 2007
11
ISL6256, ISL6256A
Typical Operating Performance
DCIN = 20V, 4S2P Li-Battery, T = +25°C, Unless Otherwise Noted. (Continued)
A
CHARGE
CURRENT
1A/div
CHLIM
1V/div
FIGURE 16. TRICKLE TO FULL-SCALE CHARGING
FN6499.1
July 19, 2007
12
ISL6256, ISL6256A
ACPRN
Functional Pin Descriptions
Open-drain output signals AC adapter is present. ACPRN
pulls low when ACSET is higher than 1.26V; and pulled high
when ACSET is lower than 1.26V.
BOOT
Connect BOOT to a 0.1µF ceramic capacitor to PHASE pin
and connect to the cathode of the bootstrap schottky diode.
DCSET
UGATE
DCSET is a lower voltage adapter detection input (like
aircraft power 15V). Allows the adapter to power the system
where battery charging has been disabled.
UGATE is the high side MOSFET gate drive output.
SGATE
SGATE is the AC adapter power source select output. The
SGATE pin drives an external P-MOSFET used to switch to
AC adapter as the system power source.
DCPRN
Open-drain output signals DC adapter is present. DCPRN
pulls low when DCSET is higher than 1.26V; and pulled high
when DCSET is lower than 1.26V.
BGATE
Battery power source select output. This pin drives an
external P-Channel MOSFET used to switch the battery as
the system power source. When the voltage at CSON pin is
higher than the AC adapter output voltage at DCIN, BGATE
is driven to low and selects the battery as the power source.
EN
EN is the Charge Enable input. Connecting EN to high
enables the charge control function, connecting EN to low
disables charging functions. Use with a thermistor to detect
a hot battery and suspend charging.
LGATE
ICM
LGATE is the low side MOSFET gate drive output; swing
between 0V and VDDP.
ICM is the adapter current output. The output of this pin
produces a voltage proportional to the adapter current.
PHASE
PGND
The Phase connection pin connects to the high side
MOSFET source, output inductor, and low side MOSFET
drain.
PGND is the power ground. Connect PGND to the source of
the low side MOSFET.
VDD
CSOP/CSON
VDD is an internal LDO output to supply IC analog circuit.
Connect a 1μF ceramic capacitor to ground.
CSOP/CSON is the battery charging current sensing
positive/negative input. The differential voltage across CSOP
and CSON is used to sense the battery charging current,
and is compared with the charging current limit threshold to
regulate the charging current. The CSON pin is also used as
the battery feedback voltage to perform voltage regulation.
VDDP
VDDP is the supply voltage for the low-side MOSFET gate
driver. Connect a 4.7Ω resistor to VDD and a 1μF ceramic
capacitor to power ground.
CSIP/CSIN
ICOMP
CSIP/CSIN is the AC adapter current sensing
positive/negative input. The differential voltage across CSIP
and CSIN is used to sense the AC adapter current, and is
compared with the AC adapter current limit to regulate the
AC adapter current.
ICOMP is a current loop error amplifier output.
VCOMP
VCOMP is a voltage loop amplifier output.
CELLS
GND
This pin is used to select the battery voltage. CELLS = VDD
for a 4S battery pack, CELLS = GND for a 3S battery pack,
CELLS = Float for a 2S battery pack.
GND is an analog ground.
DCIN
VADJ
The DCIN pin is the input of the internal 5V LDO. Connect it
to the AC adapter output. Connect a 0.1µF ceramic
capacitor from DCIN to CSON.
VADJ adjusts battery regulation voltage. VADJ = VREF for
4.2V+5%/cell; VADJ = Floating for 4.2V/cell; VADJ = GND
for 4.2V-5%/cell. Connect to a resistor divider to program the
desired battery cell voltage between 4.2V-5% and 4.2V+5%.
ACSET
ACSET is an AC adapter detection input. Connect to a
resistor divider from the AC adapter output.
CHLIM
CHLIM is the battery charge current limit set pin. CHLIM
input voltage range is 0.1V to 3.6V. When CHLIM = 3.3V, the
FN6499.1
July 19, 2007
13
ISL6256, ISL6256A
set point for CSOP-CSON is 165mV. The charger shuts
R sets the charging current. The DC/DC converter
1
down if CHLIM is forced below 88mV.
generates the control signals to drive two external
N-Channel MOSFETs to regulate the voltage and current set
by the ACLIM, CHLIM, VADJ and CELLS inputs.
ACLIM
ACLIM is the adapter current limit set pin. ACLIM = VREF for
100mV, ACLIM = Floating for 75mV, and ACLIM = GND for
50mV. Connect a resistor divider to program the adapter
current limit threshold between 50mV and 100mV.
The ISL6256 features a voltage regulation loop (VCOMP)
and two current regulation loops (ICOMP). The VCOMP
voltage regulation loop monitors CSON to ensure that its
voltage never exceeds the voltage and regulates the battery
charge voltage set by VADJ. The ICOMP current regulation
loops regulate the battery charging current delivered to the
battery to ensure that it never exceeds the charging current
limit set by CHLIM; and the ICOMP current regulation loops
also regulate the input current drawn from the AC adapter to
ensure that it never exceeds the input current limit set by
ACLIM, and to prevent a system crash and AC adapter
overload.
VREF
VREF is a 2.39V reference output pin. It is internally
compensated. Do not connect a decoupling capacitor.
Theory of Operation
Introduction
Note: Unless otherwise noted, all descriptions that refer to
the ISL6256 also refer to the ISL6256A.
PWM Control
The ISL6256 includes all of the functions necessary to
charge 2 to 4 cell Li-Ion and Li-polymer batteries. A high
efficiency synchronous buck converter is used to control the
charging voltage and charging current up to 10A. The
ISL6256 has input current limiting and analog inputs for
setting the charge current and charge voltage; CHLIM inputs
are used to control charge current and VADJ inputs are used
to control charge voltage.
The ISL6256 employs a fixed frequency PWM current mode
control architecture with a feed-forward function. The
feed-forward function maintains a constant modulator gain of
11 to achieve fast line regulation as the buck input voltage
changes. When the battery charge voltage approaches the
input voltage, the DC/DC converter operates in dropout
mode, where there is a timer to prevent the frequency from
dropping into the audible frequency range. It can achieve
duty cycle of up to 99.6%.
The ISL6256 charges the battery with constant charge
current, set by CHLIM input, until the battery voltage rises up
to a programmed charge voltage set by VADJ input; then the
charger begins to operate at a constant voltage charge mode.
The charger also drives an adapter isolation P-Channel
MOSFET to efficiently switch in the adapter supply.
To prevent boosting of the system bus voltage, the battery
charger operates in standard-buck mode when CSOP-CSON
drops below 4.25mV. Once in standard-buck mode, hysteresis
does not allow synchronous operation of the DC/DC converter
until CSOP-CSON rises above 12.5mV.
ISL6256 is a complete power source selection controller for
single battery systems and also aircraft power applications.
It drives a battery selector P-Channel MOSFET to efficiently
select between a single battery and the adapter. It controls
the battery discharging MOSFET and switches to the battery
when the AC adapter is removed, or, switches to the AC
adapter when the AC adapter is inserted for single battery
system.
An adaptive gate drive scheme is used to control the dead
time between two switches. The dead time control circuit
monitors the LGATE output and prevents the upper side
MOSFET from turning on until LGATE is fully off, preventing
cross-conduction and shoot-through. In order for the dead
time circuit to work properly, there must be a low resistance,
low inductance path from the LGATE driver to MOSFET
gate, and from the source of MOSFET to PGND. The
external Schottky diode is between the VDDP pin and BOOT
pin to keep the bootstrap capacitor charged.
The EN input allows shutdown of the charger through a
command from a micro-controller. It also uses EN to safely
shutdown the charger when the battery is in extremely hot
conditions. The amount of adapter current is reported on the
ICM output. Figure 1 shows the IC functional block diagram.
Setting the Battery Regulation Voltage
The ISL6256 uses a high-accuracy trimmed band-gap
voltage reference to regulate the battery charging voltage.
The VADJ input adjusts the charger output voltage, and the
VADJ control voltage can vary from 0 to VREF, providing a
10% adjustment range (from 4.2V-5% to 4.2V+5%) on
CSON regulation voltage. An overall voltage accuracy of
better than 0.5% is achieved.
The synchronous buck converter uses external N-Channel
MOSFETs to convert the input voltage to the required
charging current and charging voltage. Figure 2 shows the
ISL6256 typical application circuit with charging current and
charging voltage fixed at specific values. The typical
application circuit shown in Figure 3 shows the ISL6256
typical application circuit which uses a micro-controller to
adjust the charging current set by CHLIM input for aircraft
power applications. The voltage at CHLIM and the value of
FN6499.1
July 19, 2007
14
ISL6256, ISL6256A
The per-cell battery termination voltage is a function of the
battery chemistry. Consult the battery manufacturers to
determine this voltage.
Unlike VADJ and ACLIM, CHLIM does not have an internal
resistor divider network. The charge current limit threshold is
given by Equation 3:
V
165mV
CHLIM
3.3V
⎛
⎝
⎞ ⎛
⎞
⎠
------------------- ---------------------
• Float VADJ to set the battery voltage V
number of the cells,
= 4.2V ×
I
=
(EQ. 3)
CSON
CHG
⎠ ⎝
R
1
To set the trickle charge current for the dumb charger, an
A/D output controlled by the micro-controller is connected to
CHLIM pin. The trickle charge current is determined by
• Connect VADJ to VREF to set 4.41V × number of cells,
• Connect VADJ to ground to set 3.99V × number of the
cells.
Equation 4:
V
165mV
⎞ ⎛
CHLIM,trickle
⎛
⎝
⎞
⎠
(EQ. 4)
------------------- ---------------------------------------
I
=
So, the maximum battery voltage of 17.6V can be achieved.
Note that other battery charge voltages can be set by
connecting a resistor divider from VREF to ground. The resistor
divider should be sized to draw no more than 100µA from
VREF; or connect a low impedance voltage source like the D/A
converter in the micro-controller. The programmed battery
voltage per cell can be determined by Equation 1:
CHG
⎠ ⎝
R
3.3V
1
When the CHLIM voltage is below 88mV (typical), it will
disable the battery charge. When choosing the current
sensing resistor, note that the voltage drop across the
sensing resistor causes further power dissipation, reducing
efficiency. However, adjusting CHLIM voltage to reduce the
voltage across the current sense resistor R1 will degrade
accuracy due to the smaller signal to the input of the current
sense amplifier. There is a trade-off between accuracy and
power dissipation. A low pass filter is recommended to
eliminate switching noise. Connect the resistor to the CSOP
pin instead of the CSON pin, as the CSOP pin has lower
bias current and less influence on current-sense accuracy
and voltage regulation accuracy.
(EQ. 1)
V
= 0.175 ⋅ V
+ 3.99V
VADJ
CELL
An external resistor divider from VREF sets the voltage at
VADJ according to Equation 2:
||
R
514kΩ
bot_VADJ
----------------------------------------------------------------------------------------------------------------
= VREF ×
V
VADJ
||
||
514kΩ
R
514kΩ + R
top_VADJ
bot_VADJ
(EQ. 2)
Charge Current Limit Accuracy
To minimize accuracy loss due to interaction with VADJ's
internal resistor divider, ensure the AC resistance looking
back into the external resistor divider is less than 25k.
The “Electrical Specifications” table on page 6 gives
minimum and maximum values for the CSOP-CSON voltage
resulting from IC variations at 3 different CHLIM voltages
(CSOP to CSON Full-Scale Current Sense Voltage on page
4). It also gives formulae for calculating the minimum and
maximum CSOP-CSON voltage at any CHLIM voltage.
Equation 5 shows the formula for the max full scale
CSOP-CSON voltage (in mV) for the ISL6256A:
ISL6256A
Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+
cells. When charging other cell chemistries, use CELLS to
select an output voltage range for the charger. The internal
error amplifier gm1 maintains voltage regulation. The voltage
error amplifier is compensated at VCOMP. The component
values shown in Figure 3 provide suitable performance for most
applications. Individual compensation of the voltage regulation
and current-regulation loops allows for optimal compensation.
(EQ. 5)
(CSOP – CSON)
= CHLIM • 50.28 + 2.4
= CHLIM • 49.72 – 2.4
MAX
(CSOP – CSON)
MIN
TABLE 1. CELL NUMBER PROGRAMMING
Equation 5 shows the formula for the max full scale CSOP-
CSON voltage (in mV) for the ISL6256:
ISL6256
CELLS
VDD
CELL NUMBER
4
3
2
(EQ. 6)
MAX(CSOP – CSON) = CHLIM • 50 + 5
MIN(CSOP – CSON) = CHLIM • 50 – 5
GND
Float
With CHLIM = 1.5V, the maximum CSOP-CSON voltage is
78mV and the minimum CSOP-CSON voltage is 72mV.
Setting the Battery Charge Current Limit
When ISL6256A is in charge current limiting mode, the
maximum charge current is the maximum CSOP-CSON
voltage divided by the minimum sense resistor. This can be
calculated for ISL6256A with Equation 7:
The CHLIM input sets the maximum charging current. The
current set by the current sense-resistor connects between
CSOP and CSON. The full-scale differential voltage between
CSOP and CSON is 165mV for CHLIM = 3.3V, so the
maximum charging current is 4.125A for a 40mΩ sensing
resistor. Other battery charge current-sense threshold
values can be set by connecting a resistor divider from
VREF or 3.3V to ground, or by connecting a low impedance
voltage source like a D/A converter in the micro-controller.
ISL6256A
I
I
= (CHLIM • 50.28 + 2.4) ⁄ R
= (CHLIM • 49.72 – 2.4) ⁄ R
CHG, MAX
1min
(EQ. 7)
CHG, MIN
1max
FN6499.1
July 19, 2007
15
ISL6256, ISL6256A
Maximum charge current can be calculated for ISL6256 with
Equation 8:
When choosing the current sense resistor, note that the
voltage drop across this resistor causes further power
dissipation, reducing efficiency. The AC adapter current
sense accuracy is very important. Use a 1% tolerance
current-sense resistor. The highest accuracy of ±3% is
achieved with 100mV current-sense threshold voltage for
ACLIM = VREF, but it has the highest power dissipation. For
example, it has 400mW power dissipation for rated 4A AC
adapter and 1Ω sensing resistor may have to be used. ±4%
and ±6% accuracy can be achieved with 75mV and 50mV
current-sense threshold voltage for ACLIM = Floating and
ACLIM = GND, respectively.
ISL6256
I
= (CHLIM • 50 + 5) ⁄ R
(EQ. 8)
CHG, MAX
1min
I
= (CHLIM • 50 – 5) ⁄ R
1max
CHG, MIN
With CHLIM = 0.7V and R = 0.02Ω, 1%:
1
ISL6256A
I
= (1.5V • 50.28 + 2.4) ⁄ 0.0198 = 3930mA
= (1.5V • 49.72 – 2.4) ⁄ 0.0202 = 3573mA
CHG, MAX
(EQ. 9)
I
CHG, MIN
A low pass filter is suggested to eliminate the switching
noise. Connect the resistor to CSIN pin instead of CSIP pin
because CSIN pin has lower bias current and less influence
on the current-sense accuracy.
Setting the Input Current Limit
The total input current from an AC adapter, or other DC
source, is a function of the system supply current and the
battery-charging current. The input current regulator limits
the input current by reducing the charging current, when the
input current exceeds the input current limit set point.
System current normally fluctuates as portions of the system
are powered up or down. Without input current regulation,
the source must be able to supply the maximum system
current and the maximum charger input current
AC Adapter Detection
Connect the AC adapter voltage through a resistor divider to
ACSET to detect when AC power is available, as shown in
Figure 2. ACPRN is an open-drain output and is high when
ACSET is less than V
, and active low when ACSET is
th,rise
above V
. V
th,fall th,rise
and V
are given by Equation 12
th,fall
and Equation 13:
simultaneously. By using the input current limiter, the current
capability of the AC adapter can be lowered, reducing
system cost.
R
⎛
⎜
⎝
⎞
8
(EQ. 12)
------
V
V
=
+ 1 ⋅ V
⎟
th, rise
th, fall
ACSET
R
9
⎠
The ISL6256 limits the battery charge current when the input
current-limit threshold is exceeded, ensuring the battery
charger does not load down the AC adapter voltage. This
constant input current regulation allows the adapter to fully
power the system and prevent the AC adapter from
overloading and crashing the system bus.
R
⎛
⎜
⎝
⎞
8
------
(EQ. 13)
=
+ 1 ⋅ V
– I
⋅ R
hys 8
⎟
ACSET
R
9
⎠
where:
• I
hys
is the ACSET input bias current hysteresis, and
= 1.24V (min), 1.26V (typ) and 1.28V (max).
• V
ACSET
An internal amplifier gm3 compares the voltage between
CSIP and CSIN to the input current limit threshold voltage
set by ACLIM. Connect ACLIM to REF, Float and GND for
the full-scale input current limit threshold voltage of 100mV,
75mV and 50mV, respectively, or use a resistor divider from
VREF to ground to set the input current limit as Equation 10:
The hysteresis is I R , where I
hys hys
3.4µA (typ) and 4.4µA (max).
= 2.2µA (min),
8
DC Adapter Detection
Connect the DC adapter voltage like aircraft power through a
resistor divider to DCSET to detect when DC power is
available, as shown in Figure 3. DCPRN is an open-drain
output and is high when DCSET is less than V
active low when DCSET is above V
are given by Equations 14 and 15:
1
0.05
VREF
⎛
⎞
------ ----------------
I
=
⋅
⋅ V
+ 0.05
ACLIM
(EQ. 10)
INPUT
⎝
⎠
R
2
, and
and V
th,rise
. V
th,fall th,rise
th,fall
An external resistor divider from VREF sets the voltage at
ACLIM according to Equation 11:
R
⎛
⎜
⎝
⎞
14
---------
V
=
+ 1 • V
⎟
(EQ. 14)
||
th, rise
th, fall
DCSET
R
152kΩ
⎛
⎜
⎝
⎞
⎟
⎠
R
bot, ACLIM
⎠
15
-----------------------------------------------------------------------------------------------------------------------
V
= VREF ⋅
ACLIM
||
||
152kΩ
R
152kΩ + R
top, ACLIM
bot, ACLIM
R
⎛
⎜
⎝
⎞
14
(EQ. 11)
---------
V
=
+ 1 • V
– I
R
⎟
(EQ. 15)
DCSET
hys 14
R
⎠
15
where R
ACLIM.
and R
are external resistors at
bot_ACLIM
top_ACLIM
Where I
is the DCSET input bias current hysteresis and
= 1.24V (min), 1.26V (typ) and 1.28V (max). The
hys
V
DCSET
hysteresis is I
R
, where I
= 2.2µA (min), 3.4µA (typ)
hys 14 hys
To minimize accuracy loss due to interaction with ACLIM's
internal resistor divider, ensure the AC resistance looking
back into the resistor divider is less than 25k.
and 4.4µA (max).
FN6499.1
July 19, 2007
16
ISL6256, ISL6256A
by SGATE turns off and BGATE turns on the battery discharge
Current Measurement
P-Channel MOSFET to minimize the power loss. Also, the
charging function is disabled. If designing for airplane power,
DCSET is tied to a resistor divider sensing the adapter voltage.
When a user is plugged into the 15V airplane supply and the
battery voltage is lower than 15V, the MOSFET driven by
BGATE (See Figure 3) is turned off which keeps the battery
from supplying the system bus. The comparator looking at
CSON and DCIN has 300mV of hysteresis to avoid chattering.
Only 2S and 3S are supported for DC aircraft power
Use ICM to monitor the input current being sensed across
CSIP and CSIN. The output voltage range is 0V to 2.5V. The
voltage of ICM is proportional to the voltage drop across
CSIP and CSIN, and is given by Equation 16:
(EQ. 16)
ICM = 19.9 • I
• R
2
INPUT
where I
is the DC current drawn from the AC adapter.
INPUT
ICM has ±3% accuracy. It is recommended to have an RC
filter at the ICM output for minimizing the switching noise.
applications. For 4S battery packs, set DCSET = 0.
LDO Regulator
Short Circuit Protection and 0V Battery Charging
VDD provides a 5.0V supply voltage from the internal LDO
regulator from DCIN and can deliver up to 30mA of current.
The MOSFET drivers are powered by VDDP, which must be
connected to VDDP as shown in Figure 2. VDDP connects
to VDD through an external low pass filter. Bypass VDDP
and VDD with a 1µF capacitor.
Since the battery charger will regulate the charge current to
the limit set by CHLIM, it automatically has short circuit
protection and is able to provide the charge current to wake
up an extremely discharged battery.
Over-Temperature Protection
If the die temp exceeds +150°C, it stops charging. Once the
die temp drops below +125°C, charging will start up again.
Shutdown
The ISL6256 features a low-power shutdown mode. Driving
EN low shuts down the ISL6256. In shutdown, the DC/DC
converter is disabled, and VCOMP and ICOMP are pulled to
ground. The ICM, ACPRN and DCPRN outputs continue to
function.
Overvoltage Protection
ISL6256 has an Overvoltage Protection circuit that limits the
output voltage when the battery is removed or disconnected
by a pulse charging circuit. If CSON exceeds the output
voltage set point by more than V
an internal comparator
OVP
EN can be driven by a thermistor to allow automatic
shutdown of the ISL6256 when the battery pack is hot. Often
a NTC thermistor is included inside the battery pack to
measure its temperature. When connected to the charger,
the thermistor forms a voltage divider with a resistive pull-up
to the VREF. The threshold voltage of EN is 1.0V with 60mV
hysteresis. The thermistor can be selected to have a
resistance vs temperature characteristic that abruptly
decreases above a critical temperature. This arrangement
automatically shuts down the ISL6256 when the battery pack
is above a critical temperature.
pulls VCOMP down and turns off both upper and lower FETs
of the buck as in Figure 17. The trip point for Overvoltage
Protection is always above the nominal output voltage and
can be calculated from Equation 17:
V
ADJ
⎛
⎞
⎠
---------------
V
= V
+ N
× 42.2mV – 22.2mV ×
OVP
OUT, NOM
CELLS
⎝
2.39V
(EQ. 17)
For example, if the CELLS pin is connected to ground
(N
V
V
= 3) and V
is floating (V = 1.195V) then
CELLS
ADJ
ADJ
= 12.6V and VOVP = 12.693V or
+ 93mV.
OUT,NOM
OUT,NOM
Another method for inhibiting charging is to force CHLIM
below 85mV (typ).
Supply Isolation
If the voltage across the adapter sense resistor R is
2
typically greater than 8mV, the P-Channel MOSFET
controlled by SGATE is turned on reducing the power
dissipation. If the voltage across the adapter sense resistor
R is less than 3mV, SGATE turns off the P-Channel
2
MOSFET isolating the adapter from the system bus.
Battery Power Source Selection and Aircraft
Power Application
The battery voltage is monitored by CSON. If the battery
voltage measured on CSON is less than the adapter voltage
measured on DCIN, then the P-Channel MOSFET controlled
by BGATE turns off and the P-Channel MOSFET controlled by
SGATE is allowed to turn on when the adapter current is high
enough. If it is greater, then the P-Channel MOSFET controlled
FN6499.1
July 19, 2007
17
ISL6256, ISL6256A
There is a delay of approximately 400ns between V
The inductor ripple current ΔI is found from Equation 19:
OUT
exceeding the OVP trip point and pulling VCOMP, LGATE
and UGATE low.
(EQ. 19)
I
= 0.3 ⋅ I
L, MAX
RIPPLE
where the maximum peak-to-peak ripple current is 30% of
the maximum charge current is used.
V
VCOMP
OUT
For V
= 19V, V
BAT
= 16.8V, I
= 2.6A, and
BAT,MAX
IN,MAX
WHEN V
OUT
THE OVP THRESHOLD
EXCEEDS
f = 300kHz, the calculated inductance is 8.3µH. Choosing
s
the closest standard value gives L = 10µH. Ferrite cores are
often the best choice since they are optimized at 300kHz to
600kHz operation with low core loss. The core must be large
VCOMP IS PULLED LOW
AND FETS TURN OFF
ICOMP
enough not to saturate at the peak inductor current I
Equation 20:
in
Peak
BATTERY
REMOVAL
CURRENT FLOWS IN THE
LOWER FET BODY DIODE
1
--
I
= I
+
⋅ I
RIPPLE
(EQ. 20)
PEAK
L, MAX
2
UNTIL INDUCTOR CURRENT
REACHES ZERO
Inductor saturation can lead to cascade failures due to very
high currents. Conservative design limits the peak and RMS
current in the inductor to less than 90% of the rated
saturation current.
PHASE
Cross over frequency is heavily dependant on the inductor
value. f
should be less than 20% of the switching
CO
frequency and a conservative design has f
less than 10%
CO
is in voltage
FIGURE 17. OVERVOLTAGE PROTECTION IN ISL6256
of the switching frequency. The highest f
CO
control mode with the battery removed and may be
calculated (approximately) from Equation 21:
Application Information
The following battery charger design refers to the typical
application circuit in Figure 2, where typical battery
configuration of 4S2P is used. This section describes how to
select the external components including the inductor, input
and output capacitors, switching MOSFETs, and current
sensing resistors.
5 ⋅ 11 ⋅ R
SENSE
(EQ. 21)
------------------------------------------
=
f
CO
2π ⋅ L
Output Capacitor Selection
The output capacitor in parallel with the battery is used to
absorb the high frequency switching ripple current and
smooth the output voltage. The RMS value of the output
ripple current I
is given by Equation 22:
rms
Inductor Selection
V
(EQ. 22)
IN, MAX
The inductor selection has trade-offs between cost, size,
cross over frequency and efficiency. For example, the lower
the inductance, the smaller the size, but ripple current is
higher. This also results in higher AC losses in the magnetic
core and the windings, which decrease the system
efficiency. On the other hand, the higher inductance results
in lower ripple current and smaller output filter capacitors,
but it has higher DCR (DC resistance of the inductor) loss,
lower saturation current and has slower transient response.
So, the practical inductor design is based on the inductor
ripple current being ±15% to ±20% of the maximum
---------------------------------
⋅ D ⋅ (1 – D)
I
=
RMS
12 ⋅ L ⋅ f
SW
where the duty cycle D is the ratio of the output voltage
(battery voltage) over the input voltage for continuous
conduction mode which is typical operation for the battery
charger. During the battery charge period, the output voltage
varies from its initial battery voltage to the rated battery
voltage. So, the duty cycle change can be in the range of
between 0.53 and 0.88 for the minimum battery voltage of
10V (2.5V/Cell) and the maximum battery voltage of 16.8V.
The maximum RMS value of the output ripple current occurs
at the duty cycle of 0.5 and is expressed as Equation 23:
operating DC current at maximum input voltage. Maximum
ripple is at 50% duty cycle or V
required inductance can be calculated from Equation 18:
= V
/2. The
V
BAT
IN,MAX
IN, MAX
-------------------------------------------
I
=
(EQ. 23)
RMS
4 ⋅ 12 ⋅ L ⋅ F
SW
V
(EQ. 18)
IN, MAX
⋅ I
---------------------------------------------
L =
For V
= 19V, VBAT = 16.8V, L = 10µH, and
IN,MAX
4 ⋅ f
SW RIPPLE
f = 300kHz, the maximum RMS current is 0.19A. A typical
s
Where V
and f
are the maximum input voltage,
SW
IN,MAX
10F ceramic capacitor is a good choice to absorb this
current and also has very small size. Organic polymer
capacitors have high capacitance with small size and have a
significant equivalent series resistance (ESR). Although
ESR adds to ripple voltage, it also creates a high frequency
zero that helps the closed loop operation of the buck
regulator.
and switching frequency, respectively.
FN6499.1
July 19, 2007
18
ISL6256, ISL6256A
EMI considerations usually make it desirable to minimize
ripple current in the battery leads. Beads may be added in
series with the battery pack to increase the battery
impedance at 300kHz switching frequency. Switching ripple
current splits between the battery and the output capacitor
depending on the ESR of the output capacitor and battery
impedance. If the ESR of the output capacitor is 10mΩ and
battery impedance is raised to 2Ω with a bead, then only
0.5% of the ripple current will flow in the battery.
threshold voltage, stray inductance, pull-up and pull-down
resistance of the gate driver.
The following switching loss calculation (Equation 25)
provides a rough estimate.
P
=
Q1, Switching
(EQ. 25)
Q
Q
gd
⎛
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
1
2
1
2
gd
--
------------------------
--
-----------------
V
I
f
+
V
I
f
+ Q V f
rr IN sw
⎜
⎝
IN LV sw
IN LP sw
I
I
g, source
g, sink
where the following are the peak gate-drive source/sink
current of Q , respectively:
MOSFET Selection
1
The Notebook battery charger synchronous buck converter
has the input voltage from the AC adapter output. The
maximum AC adapter output voltage does not exceed 25V.
Therefore, 30V logic MOSFET should be used.
• Q : drain-to-gate charge,
gd
• Q : total reverse recovery charge of the body-diode in
rr
low-side MOSFET,
• I : inductor valley current,
LV
The high side MOSFET must be able to dissipate the
conduction losses plus the switching losses. For the battery
charger application, the input voltage of the synchronous
buck converter is equal to the AC adapter output voltage,
which is relatively constant. The maximum efficiency is
achieved by selecting a high side MOSFET that has the
conduction losses equal to the switching losses. Switching
losses in the low-side FET are very small. The choice of
low-side FET is a trade off between conduction losses
• I : Inductor peak current,
LP
• I
g,sink
• I ,
g source
Low switching loss requires low drain-to-gate charge Q
.
gd
Generally, the lower the drain-to-gate charge, the higher the
ON-resistance. Therefore, there is a trade-off between the
ON-resistance and drain-to-gate charge. Good MOSFET
selection is based on the figure of Merit (FOM), which is a
product of the total gate charge and ON-resistance. Usually,
the smaller the value of FOM, the higher the efficiency for
the same application.
(r
) and cost. A good rule of thumb for the r
of
DS(ON)
the low-side FET is 2X the r
DS(ON)
of the high-side FET.
DS(ON)
The LGATE gate driver can drive sufficient gate current to
switch most MOSFETs efficiently. However, some FETs may
exhibit cross conduction (or shoot through) due to current
For the low-side MOSFET, the worst-case power dissipation
occurs at minimum battery voltage and maximum input
voltage (Equation 26):
injected into the drain-to-source parasitic capacitor (C ) by
gd
the high dV/dt rising edge at the phase node when the high-
side MOSFET turns on. Although LGATE sink current (1.8A
typical) is more than enough to switch the FET off quickly,
voltage drops across parasitic impedances between LGATE
and the MOSFET can allow the gate to rise during the fast
rising edge of voltage on the drain. MOSFETs with low
V
⎛
⎜
⎝
⎞
⎟
⎠
2
OUT
(EQ. 26)
---------------
P
=
1 –
⋅ I
⋅ r
BAT DS(ON)
Q2
V
IN
Choose a low-side MOSFET that has the lowest possible
ON-resistance with a moderate-sized package like the SO-8
and is reasonably priced. The switching losses are not an
issue for the low-side MOSFET because it operates at
zero-voltage-switching.
threshold voltage (<1.5V) and low ratio of C /C (<5) and
gs gd
high gate resistance (>4Ω) may be turned on for a few ns by
the high dV/dt (rising edge) on their drain. This can be
avoided with higher threshold voltage and C /C ratio.
gs gd
Another way to avoid cross conduction is slowing the turn-on
speed of the high-side MOSFET by connecting a resistor
between the BOOT pin and the boot strap cap.
Choose a Schottky diode in parallel with low-side MOSFET
Q with a forward voltage drop low enough to prevent the
2
low-side MOSFET Q body-diode from turning on during the
2
dead time. This also reduces the power loss in the high-side
MOSFET associated with the reverse recovery of the
low-side MOSFET Q body diode.
2
For the high-side MOSFET, the worst-case conduction
losses occur at the minimum input voltage as shown in
Equation 24:
V
2
OUT
As a general rule, select a diode with DC current rating equal
to one-third of the load current. One option is to choose a
combined MOSFET with the Schottky diode in a single
package. The integrated packages may work better in
practice because there is less stray inductance due to a
short connection. This Schottky diode is optional and may be
removed if efficiency loss can be tolerated. In addition,
ensure that the required total gate drive current for the
(EQ. 24)
---------------
P
=
⋅ I
⋅ r
BAT DS(ON)
Q1, conduction
V
IN
The optimum efficiency occurs when the switching losses
equal the conduction losses. However, it is difficult to
calculate the switching losses in the high-side MOSFET
since it must allow for difficult-to-quantify factors that
influence the turn-on and turn-off times. These factors
include the MOSFET internal gate resistance, gate charge,
FN6499.1
July 19, 2007
19
ISL6256, ISL6256A
selected MOSFETs should be less than 24mA. So, the total
gate charge for the high-side and low-side MOSFETs is
Table 2 shows the component lists for the typical application
circuit in Figure 2.
limited by Equation 27:
TABLE 2. COMPONENT LIST
1
GATE
(EQ. 27)
------------------
sw
Q
≤
GATE
PARTS
C , C
PART NUMBERS AND MANUFACTURER
f
10μF/25V ceramic capacitor, Taiyo Yuden
1
10
TMK325 MJ106MY X5R (3.2mmx2.5mmx1.9mm)
Where I
is the total gate drive current and should be
less than 24mA. Substituting I = 24mA and f = 300kHz
GATE
GATE
s
C , C , C
0.1μF/50V ceramic capacitor
2
4
8
9
into Equation 27 yields that the total gate charge should be
less than 80nC. Therefore, the ISL6256 easily drives the
battery charge current up to 10A.
C , C , C
1μF/10V ceramic capacitor, Taiyo Yuden
LMK212BJ105MG
3
7
C
C
10nF ceramic capacitor
5
Snubber Design
6.8nF ceramic capacitor
6
ISL6256's buck regulator operates in discontinuous current
mode (DCM) when the load current is less than half the
peak-to-peak current in the inductor. After the low-side FET
turns off, the phase voltage rings due to the high impedance
with both FETs off. This can be seen in Figure 9. Adding a
snubber (resistor in series with a capacitor) from the phase
node to ground can greatly reduce the ringing. In some
situations a snubber can improve output ripple and
regulation.
C
3300pF ceramic capacitor
11
D
30V/3A Schottky diode, EC31QS03L (optional)
100mA/30V Schottky Diode, Central Semiconductor
10μH/3.8A/26mΩ, Sumida, CDRH104R-100
30V/35mΩ, FDS6912A, Fairchild
-30V/30mΩ, SI4835BDY, Siliconix
Signal P-Channel MOSFET, NDS352AP
Signal N-Channel MOSFET, 2N7002
40mΩ, ±1%, LRC-LR2512-01-R040-F, IRC
20mΩ, ±1%, LRC-LR2010-01-R020-F, IRC
18Ω, ±5%, (0805)
1
D
2
L
Q , Q
1
2
4
Q , Q
3
Q
Q
5
6
1
2
3
4
5
6
7
The snubber capacitor should be approximately twice the
parasitic capacitance on the phase node. This can be
estimated by operating at very low load current (100mA) and
measuring the ringing frequency.
R
R
R
R
R
R
R
CSNUB and RSNUB can be calculated from Equations 28
and 29:
2.2Ω, ±5%, (0805)
2
------------------------------------
C
=
100kΩ, ±5%, (0805)
SNUB
(EQ. 28)
2
(2πF
) ⋅ L
ring
4.7k, ±5%, (0805)
100Ω, ±5%, (0805)
2 ⋅ L
R
=
-------------------
(EQ. 29)
SNUB
C
R , R
130k, ±1%, (0805)
SNUB
8
11
R
10.2kΩ, ±1%, (0805)
9
Input Capacitor Selection
R
R
R
4.7Ω, ±5%, (0805)
10
12
13
The input capacitor absorbs the ripple current from the
synchronous buck converter, which is given by Equation 30:
20kΩ, ±1%, (0805)
1.87kΩ, ±1%, (0805)
V
⋅ (V – V
)
OUT
OUT
IN
(EQ. 30)
-------------------------------------------------------------
I
= I
BAT
RMS
V
IN
LOOP COMPENSATION DESIGN
This RMS ripple current must be smaller than the rated RMS
current in the capacitor datasheet. Non-tantalum chemistries
(ceramic, aluminum, or OSCON) are preferred due to their
resistance to power-up surge currents when the AC adapter
is plugged into the battery charger. For Notebook battery
charger applications, it is recommend that ceramic
capacitors or polymer capacitors from Sanyo be used due to
their small size and reasonable cost.
ISL6256 has three closed loop control modes. One controls
the output voltage when the battery is fully charged or
absent. A second controls the current into the battery when
charging and the third limits current drawn from the adapter.
The charge current and input current control loops are
compensated by a single capacitor on the ICOMP pin. The
voltage control loop is compensated by a network on the
VCOMP pin. Descriptions of these control loops and
guidelines for selecting compensation components will be
given in the following sections. Which loop controls the
output is determined by the minimum current buffer and the
minimum voltage buffer shown in Figure 1. These three
loops will be described separately.
FN6499.1
July 19, 2007
20
ISL6256, ISL6256A
TRANSCONDUCTANCE AMPLIFIERS GM1, GM2 AND
GM3
The output capacitor creates a pole at a very high frequency
due to the small resistance in parallel with it. The frequency
of this pole is calculated in Equation 32:
1
ISL6256 uses several transconductance amplifiers (also
known as gm amps). Most commercially available op amps
are voltage controlled voltage sources with gain expressed
--------------------------------------
=
f
POLE2
(EQ. 32)
2π ⋅ C ⋅ R
o
BAT
as A = V
/V . gm amps are voltage controlled current
sources with gain expressed as gm = I /V . gm will
OUT IN
Charge Current Control Loop
OUT IN
When the battery voltage is less than the fully charged
voltage, the voltage error amplifier goes to it’s maximum
output (limited to 1.2V above ICOMP) and the ICOMP
voltage controls the loop through the minimum voltage
buffer. Figure 19 shows the charge current control loop.
appear in some of the equations for poles and zeros in the
compensation.
PWM GAIN F
M
The Pulse Width Modulator in the ISL6256 converts voltage
at VCOMP to a duty cycle by comparing VCOMP to a
L
PHASE
triangle wave (duty = VCOMP/V
). The low-pass
PP RAMP
filter formed by L and C convert the duty cycle to a DC
11
O
R
R
FET_r
DS(ON)
L_DCR
R
output voltage (Vo = V
*duty). In ISL6256, the triangle
DCIN
wave amplitude is proportional to V
. Making the ramp
DCIN
+
0.25
CSOP
CSON
F2
amplitude proportional to DCIN makes the gain from
VCOMP to the PHASE output a constant 11 and is
independent of DCIN. For small signal AC analysis, the
battery is modeled by it’s internal resistance. The total output
resistance is the sum of the sense resistor and the internal
resistance of the MOSFETs, inductor and capacitor. Figure
18 shows the small signal model of the pulse width
modulator (PWM), power stage, output filter and battery.
Σ
+
-
-
20
CA2
C
R
R
F2
S2
ICOMP
-
gm2
BAT
C
+
O
C
CHLIM
+
-
ICOMP
R
ESR
FIGURE 19. CHARGE CURRENT LIMIT LOOP
VDD
The compensation capacitor (C
) gives the error
ICOMP
RAMP GEN
amplifier (GMI) a pole at a very low frequency (<<1Hz) and a
a zero at fZ1. fZ1 is created by the 0.25*CA2 output added to
ICOMP. The frequency of can be calculated from Equation 33.
4 ⋅ gm2
V
= VDD/11
RAMP
L
-
---------------------------------------
f
=
gm2 = 50μA ⁄ V
(EQ. 33)
+
ZERO
(2π ⋅ C
)
CO
ICOMP
Placing this zero at a frequency equal to the pole calculated
in Equation 31 will result in maximum gain at low frequencies
and phase margin near 90degrees. If the zero is at a higher
PWM
INPUT
frequency (smaller C
), the DC gain will be higher but
ICOMP
the phase margin will be lower. Use a capacitor on ICOMP
that is equal to or greater than the value calculated in
Equation 34:
PWM
GAIN = 11
L
R
SENSE
CO
11
4 ⋅ (50μA ⁄ V)
-----------------------------------------------------------------------------------------
=
C
(EQ. 34)
R
R
ICOMP
L_DCR
FET_r
DS(ON)
(R + r
+ R
+ R
)
BAT
S2
DS(ON)
DCR
R
BAT
PWM
A filter should be added between RS2 and CSOP and CSON
to reduce switching noise. The filter roll off frequency should
be between the cross over frequency and the switching
frequency (~100kHz). RF2 should be small (<10Ω) to
minimize offsets due to leakage current into CSOP. The filter
cut off frequency is calculated using Equation 35:
INPUT
R
ESR
FIGURE 18. SMALL SIGNAL AC MODEL
In most cases the Battery resistance is very small (<200mΩ)
resulting in a very low Q in the output filter. This results in a
frequency response from the input of the PWM to the
inductor current with a single pole at the frequency
calculated in Equation 31:
1
(EQ. 35)
------------------------------------------
f
=
FILTER
(2π ⋅ C ⋅ R
)
F2
F2
(R
+ r
+ R
+ R
)
BAT
(EQ. 31)
SENSE
DS(ON)
DCR
------------------------------------------------------------------------------------------------------
=
f
POLE1
The cross over frequency is determined by the DC gain of
the modulator and output filter and the pole in Equation 23.
2π ⋅ L
FN6499.1
July 19, 2007
21
ISL6256, ISL6256A
The DC gain is calculated in Equation 36 and the cross over
frequency is calculated with Equation 37.
The loop response equations, bode plots and the selection
of CICOMP are the same as the charge current control loop
with loop gain reduced by the duty cycle and the ratio of
11 ⋅ R
S2
(EQ. 36)
(EQ. 37)
---------------------------------------------------------------------------------------------------------
=
A
DC
(R + r
+ R
+ R
)
BATTERY
R
/R . In other words, if R = R and the duty cycle
S1 S2 S1 S2
S2
DS(ON)
DCR
D = 50%, the loop gain will be 6dB lower than the loop gain
in Figure 21. This gives lower cross over frequency and
11 ⋅ R
S2
---------------------
=
DC POLE
f
= A
⋅ f
CO
2π ⋅ L
higher phase margin in this mode. If R /R = 2 and the
S1 S2
The Bode plot of the loop gain, the compensator gain and
the power stage gain is shown in Figure 20:
duty cycle is 50% then the adapter current loop gain will be
identical to the gain in Figure 21.
A filter should be added between RS1 and CSIP and CSIN to
reduce switching noise. The filter roll off frequency should be
between the cross over frequency and the switching
frequency (~100kHz).
60
COMPENSATOR
f
ZERO
MODULATOR
LOOP
40
20
Voltage Control Loop
When the battery is charged to the voltage set by CELLS and
VADJ the voltage error amplifier (gm1) takes control of the
output (assuming that the adapter current is below the limit set
by ACLIM). The voltage error amplifier (gm1) discharges the
cap on VCOMP to limit the output voltage. The current to the
battery decreases as the cells charge to the fixed voltage and
the voltage across the internal battery resistance decreases.
As battery current decreases the 2 current error amplifiers
(gm2 and gm3) output their maximum current and charge the
capacitor on ICOMP to its maximum voltage (limited to 1.2V
above VCOMP). With high voltage on ICOMP, the minimum
voltage buffer output equals the voltage on VCOMP.
0
-20
-40
-60
f
POLE1
f
FILTER
f
POLE2
0.01k
0.1k
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 20. CHARGE CURRENT LOOP BODE PLOTS
The voltage control loop is shown in Figure 22.
Adapter Current Limit Control Loop
L
If the combined battery charge current and system load
current draws current that equals the adapter current limit
set by the ACLIM pin, ISL6256 will reduce the current to the
battery and/or reduce the output voltage to hold the adapter
current at the limit. Above the adapter current limit, the
minimum current buffer equals the output of gm3 and
ICOMP controls the charger output. Figure 21 shows the
adapter current limit control loop.
PHASE
11
R
R
L_DCR
FET_r
DS(ON)
CA2
20
R
+
CSOP
F2
0.25
+
Σ
-
C
R
R
F2
S2
-
CSON
R3
DCIN
VCOMP
BAT
-
C
R
O
gm1
L
PHASE
+
R4
R
S1
ESR
11
C
R
VCOMP
VCOMP
+
-
R
R
L_DCR
FET_r
DS(ON)
R
F1
2.1V
C
F1
R
CSOP
+
F2
FIGURE 22. VOLTAGE CONTROL LOOP
0.25
+
Σ
-
20
C
F2
R
-
CSIN
CSIP
CA2
CSON
-
20
C
O
+
CA1
R
ESR
-
gm3
+
ICOMP
ACLIM
+
-
C
ICOMP
FIGURE 21. ADAPTER CURRENT LIMIT LOOP
FN6499.1
July 19, 2007
22
ISL6256, ISL6256A
The compensation network consists of the voltage error
Output LC Filter Transfer Functions
amplifier gm1 and the compensation network R
,
VCOMP
which give the loop very high DC gain, a very low
The gain from the phase node to the system output and
battery depend entirely on external components. Typical
output LC filter response is shown in Figure 23. Transfer
function ALC(s) is shown in Equation 38:
C
VCOMP
frequency pole and a zero at f
. Inductor current
ZERO1
information is added to the feedback to create a second zero
. The low pass filter R , C between R and
f
ZERO2 F2 F2 SENSE
s
⎛
⎝
⎞
⎠
---------------
1 –
ISL6256 add a pole at f . R and R are internal divider
FILTER
3
4
ω
ESR
----------------------------------------------------------
A
=
resistors that set the DC output voltage. For a 3-cell battery,
(EQ. 38)
LC
2
⎛
⎜
⎝
⎞
s
ω
s
R = 320kΩ and R = 64kΩ. Equations 39, 40, 41, 42, 43 and
----------- ------------------------
+
+ 1
⎟
3
4
(ω ⋅ Q)
LC
⎠
DP
44 relate the compensation network’s poles, zeros and gain to
the components in Figure 22. Figure 2424 shows an
asymptotic bode plot of the DC/DC converter’s gain vs
1
1
L
C
o
-----------------------
ω
=
--------------------------------
ω
=
Q = R
⋅
o
------
LC
ESR
(R
⋅ C )
o
( L ⋅ C )
ESR
o
frequency. It is strongly recommended that f
approximately 30% of f and f
LC ZERO2
is
is approximately 70%
ZERO1
of f
.
NO BATTERY
LC
COMPENSATOR
f
LC
MODULATOR
LOOP
f
R
= 200mΩ
POLE1
BATTERY
40
20
R
= 50mΩ
BATTERY
0
f
FILTER
-20
-40
-60
f
ZERO1
f
ZERO2
f
ESR
FREQUENCY
0.1k
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 23. FREQUENCY RESPONSE OF THE LC OUTPUT
FILTER
FIGURE 24. ASYMPTOTIC BODE PLOT OF THE VOLTAGE
CONTROL LOOP GAIN
The resistance RO is a combination of MOSFET r
,
DS(ON)
inductor DCR, R
SENSE
and the internal resistance of the
COMPENSATION BREAK FREQUENCY EQUATIONS
battery (normally between 50mΩ and 200mΩ). The worst case
for voltage mode control is when the battery is absent. This
results in the highest Q of the LC filter and the lowest phase
margin.
1
----------------------------------------------------------------------
f
=
ZERO1
(2π ⋅ C
⋅ R
)
1COMP
(EQ. 39)
VCOMP
R
R
⎛
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
gm1
5
VCOMP
4
⎛
⎝
⎞
⎠
-------------------------------------------------------
--------------------
------------
f
f
=
⋅
⋅
⎜
⎝
ZERO2
2π ⋅ R
⋅ C
R
+ R
3
SENSE
4
OUT
(EQ. 40)
(EQ. 41)
1
-------------------------------
(2π L ⋅ C )
=
LC
o
1
------------------------------------------
=
f
f
(EQ. 42)
(EQ. 43)
FILTER
POLE1
(2π ⋅ R ⋅ C
)
F2
F2
1
---------------------------------------------------
=
(2π ⋅ R
⋅ C )
o
SENSE
1
--------------------------------------------
f
=
(EQ. 44)
ESR
(2π ⋅ C ⋅ R
)
ESR
o
FN6499.1
July 19, 2007
23
ISL6256, ISL6256A
LGATE Pin
TABLE 3.
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
CELLS
R
R
4
3
2
3
4
288kΩ
320kΩ
336kΩ
48kΩ
64kΩ
96kΩ
Choose R
VCOMP
equal or lower than the value calculated
from Equation 45.
PGND Pin
R
+ R
4
R
4
⎛
⎜
⎝
⎞
⎟
⎠
5
gm1
3
⎛
⎝
⎞
⎠
PGND pin should be laid out to the negative side of the
relevant output cap with separate traces.The negative side
of the output capacitor must be close to the source node of
the bottom MOSFET. This trace is the return path of LGATE.
-----------
--------------------
R
= (0.7 ⋅ F ) ⋅ (2π ⋅ C ⋅ R ) ⋅
SENSE
⋅
VCOMP
LC
o
(EQ. 45)
Next, choose C
equal or higher than the value
VCOMP
calculated from Equation 46.
PHASE Pin
1
--------------------------------------------------------------------------
=
C
(EQ. 46)
This trace should be short, and positioned away from other
weak signal traces. This node has a very high dv/dt with a
voltage swing from the input voltage to ground. No trace
should be in parallel with it. This trace is also the return path
for UGATE. Connect this pin to the high-side MOSFET
source.
VCOMP
(0.3 ⋅ F ) ⋅ (2π ⋅ R
)
VCOMP
LC
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
UGATE Pin
This pin has a square shape waveform with high dv/dt. It
provides the gate drive current to charge and discharge the
top MOSFET with high di/dt. This trace should be wide,
short, and away from other traces similar to the LGATE.
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
2. Signal Ground
BOOT Pin
3. Power Layers: Power Ground
This pin’s di/dt is as high as the UGATE; therefore, this trace
should be as short as possible.
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
CSOP, CSON Pins
Accurate charge current and adapter current sensing is
critical for good performance. The current sense resistor
connects to the CSON and the CSOP pins through a low
pass filter with the filter cap very near the IC (see Figure 2).
Traces from the sense resistor should start at the pads of the
sense resistor and should be routed close together,
throughout the low pass filter and to the CSON and CSON
pins (see Figure 25). The CSON pin is also used as the
battery voltage feedback. The traces should be routed away
from the high dv/dt and di/dt pins like PHASE, BOOT pins. In
general, the current sense resistor should be close to the IC.
These guidelines should also be followed for the adapter
current sense resistor and CSIP and CSIN. Other layout
arrangements should be adjusted accordingly.
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under the
IC has less noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
GND and VDD Pin
At least one high quality ceramic decoupling cap should be
used to cross these two pins. The decoupling cap can be put
close to the IC.
FN6499.1
July 19, 2007
24
ISL6256, ISL6256A
SENSE
RESISTOR
R
HIGH
CURRENT
TRACE
HIGH
CURRENT
TRACE
KELVIN CONNECTION TRACES
TO THE LOW PASS FILTER
AND
CSOP AND CSON
FIGURE 25. CURRENT SENSE RESISTOR LAYOUT
EN Pin
This pin stays high at enable mode and low at idle mode and
is relatively robust. Enable signals should refer to the signal
ground.
DCIN Pin
This pin connects to AC adapter output voltage, and should
be less noise sensitive.
Copper Size for the Phase Node
The capacitance of PHASE should be kept very low to
minimize ringing. It would be best to limit the size of the
PHASE node copper in strict accordance with the current
and thermal management of the application.
Identify the Power and Signal Ground
The input and output capacitors of the converters, the source
terminal of the bottom switching MOSFET PGND should
connect to the power ground. The other components should
connect to signal ground. Signal and power ground are tied
together at one point.
Clamping Capacitor for Switching MOSFET
It is recommended that ceramic caps be used closely
connected to the drain of the high-side MOSFET, and the
source of the low-side MOSFET. This capacitor reduces the
noise and the power loss of the MOSFET.
FN6499.1
July 19, 2007
25
ISL6256, ISL6256A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)
2X
0.15
C A
D
A
MILLIMETERS
9
D/2
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
D1
A
A1
A2
A3
b
0.80
0.90
-
D1/2
2X
-
-
0.02
-
N
0.15 C
B
6
0.65
9
INDEX
AREA
0.20 REF
9
1
2
3
E1/2
E/2
9
0.18
2.95
2.95
0.25
0.30
3.25
3.25
5,8
E1
E
B
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
2X
3.10
7,8
0.15 C
B
2X
5.00 BSC
-
TOP VIEW
0.15 C
A
E1
E2
e
4.75 BSC
9
0
A2
4X
C
3.10
7,8
A
/ /
0.10 C
0.08 C
0.50 BSC
-
k
0.20
0.50
-
0.60
28
7
-
-
SEATING PLANE
A1
A3
SIDE VIEW
L
0.75
8
9
N
2
5
NX b
Nd
Ne
P
3
0.10 M C A B
4X P
7
3
D2
D2
8
7
NX k
-
-
-
0.60
12
9
(DATUM B)
2
N
θ
-
9
4X P
Rev. 1 11/04
1
(DATUM A)
2
3
NOTES:
(Ne-1)Xe
REF.
E2
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
7
8
E2/2
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
NX L
8
N
e
9
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
(Nd-1)Xe
REF.
CORNER
OPTION 4X
BOTTOM VIEW
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
A1
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
C
L
C
L
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
L
L
10
10
L1
L1
e
e
C
C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
FN6499.1
July 19, 2007
26
ISL6256, ISL6256A
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M28.15
N
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
INDEX
AREA
0.25(0.010)
M
B M
H
E
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
-B-
SYMBOL
MAX
0.069
0.010
0.061
0.012
0.010
0.394
0.157
MIN
1.35
0.10
-
MAX
1.75
0.25
1.54
0.30
0.25
10.00
3.98
NOTES
A
A1
A2
B
0.053
0.004
-
-
1
2
3
-
L
0.25
0.010
SEATING PLANE
A
-
-A-
0.008
0.007
0.386
0.150
0.20
0.18
9.81
3.81
9
D
h x 45°
C
D
E
-
-C-
3
α
4
A2
e
A1
C
e
0.025 BSC
0.635 BSC
-
B
0.10(0.004)
H
h
0.228
0.0099
0.016
0.244
0.0196
0.050
5.80
0.26
0.41
6.19
0.49
1.27
-
0.17(0.007) M
C
A M B S
5
L
6
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
N
α
28
28
7
0°
8°
0°
8°
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 1 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual in-
dex feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6499.1
July 19, 2007
27
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