ISL6261IR7Z-T [INTERSIL]
Single-Phase Core Regulator for IMVP-6 Mobile CPUs; 单相核心稳压器，用于IMVP - 6移动处理器
| 型号： | ISL6261IR7Z-T |
| 厂家： | 
Intersil |
| 描述： | Single-Phase Core Regulator for IMVP-6 Mobile CPUs |
| 文件： | 总34页 (文件大小：1197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6261
®
Data Sheet
September 27, 2006
FN9251.1
®
Single-Phase Core Regulator for IMVP-6
Mobile CPUs
Features
• Precision single-phase CORE voltage regulator
- 0.5% system accuracy over temperature
- Enhanced load line accuracy
The ISL6261 is a single-phase buck regulator implementing
lntel® IMVP-6® protocol, with embedded gate drivers.
The heart of the ISL6261 is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional multi-phase buck regulator, the R3
Technology™ has faster transient response. This is due to
the R3 modulator commanding variable switching frequency
during a load transient.
• Internal gate driver with 2A driving capability
• Microprocessor voltage identification input
- 7-Bit VID input
- 0.300V to 1.500V in 12.5mV steps
- Support VID change on-the-fly
• Multiple current sensing schemes supported
- Lossless inductor DCR current sensing
- Precision resistive current sensing
lntel® Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology effectively reducing power dissipation
in lntel® Pentium processors. To boost battery life, the
ISL6261 supports DPRSLRVR (deeper sleep) function and
maximizes the efficiency via automatically changing
operation modes. At heavy load in the active mode, the
regulator commands the continuous conduction mode
(CCM) operation. When the CPU enters deeper sleep mode,
the ISL6261 enables diode emulation to maximize the
efficiency at light load. Asserting the FDE pin of the ISL6261
in deeper sleep mode will further decrease the switching
frequency at light load and increase the regulator efficiency.
• Thermal monitor
• User programmable switching frequency
• Differential remote voltage sensing at CPU die
• Overvoltage, undervoltage, and overcurrent protection
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
TEMP
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
The ISL6261 has 0.5% system voltage accuracy over
temperature.
PART NUMBER
PART
MARKING
RANGE PACKAGE PKG.
(°C) (Pb-FREE) DWG. #
(NOTE)
ISL6261CRZ
ISL6261CRZ -10 to +100 40 Ld 6x6 L40.6x6
QFN
A unity-gain differential amplifier provides remote voltage
sensing at the CPU die. This allows the voltage on the CPU
die to be accurately measured and regulated per lntel®
IMVP-6 specification. Current sensing can be implemented
through either lossless inductor DCR sensing or precise
resistor sensing. If DCR sensing is used, an NTC thermistor
network will thermally compensates the gain and the time
constant variations caused by the inductor DCR change.
ISL6261CRZ-T ISL6261CRZ -10 to +100 40 Ld 6x6 L40.6x6
QFN, T&R
ISL6261CR7Z
ISL6261CR7Z -10 to +100 48 Ld 7x7 L48.7x7
QFN
ISL6261CR7Z-T ISL6261CR7Z -10 to +100 48 Ld 7x7 L48.7x7
QFN, T&R
ISL6261IRZ
ISL6261IRZ-T
ISL6261IR7Z
ISL6261IRZ
-40 to +100 40 Ld 6x6 L40.6x6
QFN
ISL6261IRZ
-40 to +100 40 Ld 6x6 L40.6x6
QFN, T&R
ISL6261IR7Z -40 to +100 48 Ld 7x7 L48.7x7
QFN
ISL6261IR7Z-T ISL6261IR7Z -40 to +100 48 Ld 7x7 L48.7x7
QFN, T&R
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL6261
Pinouts
ISL6261
(40 LD QFN)
40 39 38 37 36 35 34 33 32 31
FDE
PGD_IN
RBIAS
VR_TT#
NTC
1
2
3
4
5
6
7
8
9
30 VID2
29 VID1
28 VID0
27
26
25
24
23
22
VCCP
LGATE
VSSP
GND PAD
(BOTTOM)
SOFT
OCSET
VW
PHASE
UGATE
BOOT
COMP
FB 10
21 NC
11 12 13 14 15 16 17 18 19 20
ISL6261
(48 LD QFN)
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
PGOOD
FDE
NC
NC
NC
NC
3
PGD_IN
RBIAS
VR_TT#
NTC
4
5
32 NC
6
31
30
29
VCCP
LGATE
VSSP
GND PAD
(BOTTOM)
7
SOFT
OCSET
VW
8
9
28 PHASE
UGATE
27
COMP
10
FB 11
NC 12
26 BOOT
25 NC
13 14 15 16 17 18 19 20 21 22 23 24
FN9251.1
September 27, 2006
2
ISL6261
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V
Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
. . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V
HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kV
Thermal Resistance (Typical)
θ
JA (°C/W)
θ
JC (°C/W)
6x6 QFN Package (Notes 1, 2) . . . . . . 33
7x7 QFN Package (Notes 1, 2) . . . . . . 30
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
5.5
5.5
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified.
PARAMETER
INPUT POWER SUPPLY
+5V Supply Current
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
IVDD
VR_ON = 3.3V
-
3.1
3.6
1
mA
µA
µA
µA
V
VR_ON = 0V
-
-
-
+3.3V Supply Current
I3V3
IVIN
No load on CLK_EN# pin
VR_ON = 0, VIN = 25V
VDD Rising
-
1
Battery Supply Current at VIN pin
POR (Power-On Reset) Threshold
-
-
-
1
PORr
PORf
4.35
4.1
4.5
-
VDD Falling
3.85
V
SYSTEM AND REFERENCES
System Accuracy
%Error
(Vcc_core
No load, close loop, active mode,
TA = 0°C to +100°C,
-0.5
-
0.5
%
)
VID = 0.75-1.5V
VID = 0.5-0.7375V
VID = 0.3-0.4875V
RRBIAS = 147kΩ
-8
-15
1.45
1.188
-
-
-
8
15
mV
mV
V
RBIAS Voltage
RRBIAS
VBOOT
1.47
1.2
1.5
1.49
1.212
-
Boot Voltage
V
Maximum Output Voltage
VCC_CORE
(max)
VID = [0000000]
VID = [1100000]
VID = [1111111]
V
Minimum Output Voltage
VCC_CORE
(min)
-
-
0.3
0.0
-
-
V
V
VID Off State
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW
RFSET = 7kΩ,
-
333
-
-
kHz
kHz
V
comp = 2V
Adjustment Range
200
500
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain (Note 3)
-0.3
-
0.3
-
mV
dB
AV0
90
FN9251.1
September 27, 2006
3
ISL6261
Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Error Amp Gain-Bandwidth Product
(Note 3)
GBW
CL = 20pF
CL = 20pF
-
18
-
MHz
Error Amp Slew Rate (Note 3)
FB Input Current
SR
-
-
5.0
10
-
V/µs
nA
IIN(FB)
150
SOFT-START CURRENT
Soft-start Current
ISS
IGV
-46
±175
-46
-41
±200
-41
-36
±225
-36
µA
µA
µA
µA
µA
Soft Geyserville Current
Soft Deeper Sleep Entry Current
Soft Deeper Sleep Exit Current
Soft Deeper Sleep Exit Current
|SOFT - REF|>100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
IC4
IC4EA
IC4EB
36
41
46
175
200
225
GATE DRIVER DRIVING CAPABILITY (Note 4)
UGATE Source Resistance
UGATE Source Current
UGATE Sink Resistance
UGATE Sink Current
RSRC(UGATE)
500mA Source Current
VUGATE_PHASE = 2.5V
500mA Sink Current
VUGATE_PHASE = 2.5V
500mA Source Current
VLGATE = 2.5V
-
-
-
-
-
-
-
-
-
1
2
1.5
Ω
A
ISRC(UGATE)
RSNK(UGATE)
ISNK(UGATE)
RSRC(LGATE)
ISRC(LGATE)
RSNK(LGATE)
ISNK(LGATE)
RP(UGATE)
-
1.5
-
1
Ω
A
2
LGATE Source Resistance
LGATE Source Current
LGATE Sink Resistance
LGATE Sink Current
1
1.5
-
Ω
A
2
500mA Sink Current
VLGATE = 2.5V
0.5
4
0.9
-
Ω
A
UGATE to PHASE Resistance
1.1
-
kΩ
GATE DRIVER SWITCHING TIMING (Refer to Timing Diagram)
UGATE Turn-on Propagation Delay
LGATE Turn-on Propagation Delay
BOOTSTRAP DIODE
Forward Voltage
tPDHU
tPDHL
PVCC = 5V, Output Unloaded
PVCC = 5V, Output Unloaded
20
7
30
15
44
30
ns
ns
V
V
DDP = 5V, Forward Bias Current = 2mA
R = 16V
0.43
-
0.58
-
0.67
1
V
Leakage
μA
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
VOL
IOH
IPGOOD = 4mA
-
0.11
-
0.4
1
V
PGOOD = 3.3V
-1
µA
ms
mV
V
tpgd
OVH
OVHS
CLK_EN# Low to PGOOD High
VO rising above setpoint >1ms
VO rising above setpoint >0.5µs
I(Rbias) = 10µA
5.5
6.8
200
1.7
10
8.1
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OC Threshold Offset
160
1.675
9.8
240
1.725
10.2
3.5
µA
mV
mV
DROOP rising above OCSET >120µs
VO below set point for >1ms
-3.5
-360
Undervoltage Threshold
(VDIFF-SOFT)
UVf
-300
-240
LOGIC THRESHOLDS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VIL(3.3V)
-
-
-
1
-
V
V
VR_ON, DPRSLPVR and PGD_IN
Input High
VIH(3.3V)
2.3
FN9251.1
September 27, 2006
4
ISL6261
Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
IIL
TEST CONDITIONS
Logic input is low
MIN
TYP
MAX
UNITS
μA
Leakage Current on VR_ON and
PGD_IN
-1
-
0
0
-
1
IIH
Logic input is high
μA
Leakage Current on DPRSLPVR
IIL_DPRSLP
IIH_DPRSLP
VIL(1.0V)
DPRSLPVR logic input is low
DPRSLPVR logic input is high
-1
-
0
-
μA
0.45
-
1
μA
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
-
0.3
V
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH(1.0V)
0.7
-
-
V
Leakage Current of DAC(VID0-
VID6) and DPRSTP#
IIL
DPRSLPVR logic input is low
DPRSLPVR logic input is high
-1
-
0
-
μA
μA
IIH
0.45
1
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
V(NTC) falling
I = 20mA
53
1.17
-
60
1.2
5
67
1.25
9
µA
V
Over-temperature Threshold
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
CLK_EN# High Output Voltage
CLK_EN# Low Output Voltage
RTT
VOH
VOL
3V3 = 3.3V, I = -4mA
ICLK_EN# = 4mA
2.9
-
3.1
-
V
V
0.18
0.4
NOTES:
3. Guaranteed by characterization.
4. Guaranteed by design.
Gate Driver Timing Diagram
PWM
t
PDHU
t
FU
t
RU
1V
UGATE
LGATE
1V
t
RL
t
FL
t
PDHL
FN9251.1
September 27, 2006
5
ISL6261
Functional Pin Description
40 39 38 37 36 35 34 33 32 31
FDE
PGD_IN
RBIAS
VR_TT#
NTC
1
2
3
4
5
6
7
8
9
30 VID2
29 VID1
28 VID0
27
26
25
24
23
22
VCCP
LGATE
VSSP
GND PAD
(BOTTOM)
SOFT
OCSET
VW
PHASE
UGATE
BOOT
COMP
FB 10
21 NC
11 12 13 14 15 16 17 18 19 20
FDE
VW
Forced diode emulation enable signal. Logic high of FDE
with logic low of DPRSTP# forces the ISL6261 to operate in
diode emulation mode with an increased VW-COMP voltage
window.
A resistor from this pin to COMP programs the switching
frequency (eg. 6.81K = 300kHz).
COMP
The output of the error amplifier.
PGD_IN
FB
Digital Input. Suggest connecting to MCH_PWRGD, which
indicates that VCC_MCH voltage is within regulation.
The inverting input of the error amplifier.
VDIFF
RBIAS
The output of the differential amplifier.
A 147K resistor to VSS sets internal current reference.
VSEN
VR_TT#
Remote core voltage sense input.
Thermal overload output indicator with open-drain output.
Over-temperature pull-down resistance is 10.
RTN
Remote core voltage sense return.
NTC
Thermistor input to VR_TT# circuit and a 60µA current
source is connected internally to this pin.
DROOP
The output of the droop amplifier. DROOP-VO voltage is the
droop voltage.
SOFT
A capacitor from this pin to GND pin sets the maximum slew
rate of the output voltage. The SOFT pin is the non-inverting
input of the error amplifier.
DFB
The inverting input of the droop amplifier.
VO
OCSET
An input to the IC that reports the local output voltage.
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
FN9251.1
September 27, 2006
6
ISL6261
VSUM
NC
This pin is connected to one terminal of the capacitor in the
current sensing R-C network.
Not connected. Ground this pin in the practical layout.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VIN
VID input with VID0 as the least significant bit (LSB) and
VID6 as the most significant bit (MSB).
Power stage input voltage. It is used for input voltage feed
forward to improve the input line transient performance.
VR_ON
VSS
VR enable pin. A logic high signal on this pin enables the
regulator.
Signal ground. Connect to controller local ground.
VDD
DPRSLPVR
5V control power supply.
Deeper sleep enable signal. A logic high indicates that the
microprocessor is in Deeper Sleep Mode and also indicates
a slow Vo slew rate with 41μA discharging or charging the
SOFT cap.
BOOT
Upper gate driver supply voltage. An internal bootstrap diode
is connected to the VCCP pin.
DPRSTP#
UGATE
Deeper sleep slow wake up signal. A logic low signal on this
pin indicates that the microprocessor is in Deeper Sleep
Mode.
The upper-side MOSFET gate signal.
PHASE
The phase node. This pin should connect to the source of
upper MOSFET.
CLK_EN#
Digital output for system PLL clock. Goes active 20µs after
PGD_IN is active and Vcore is within 10% of boot voltage.
VSSP
The return path of the lower gate driver.
3V3
3.3V supply voltage for CLK_EN#.
LGATE
The lower-side MOSFET gate signal.
PGOOD
Power good open-drain output. Needs to be pulled up
externally by a 680 resistor to VCCP or 1.9k to 3.3V.
VCCP
5V power supply for the gate driver.
FN9251.1
September 27, 2006
7
ISL6261
Function Block Diagram
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6261
FN9251.1
September 27, 2006
8
ISL6261
Simplified Application Circuit for DCR Current Sensing
V
+5
V+3.3
Vin
R
4
C
4
3V3 VDD VCCP
R
5
RBIAS
NTC
VIN
R
6
C
8
C
5
UGATE
BOOT
SOFT
VR_TT#
Lo
C
6
VR_TT#
Vo
PHASE
VID<0:6>
DPRSTP#
VIDs
Co
DPRSTP#
DPRSLPVR
FDE
DPRSLPVR
LGATE
VSSP
MCH_PWRGD
CLK_ENABLE#
VR_ON
PGD_IN
CLK_EN#
VR_ON
PGOOD
VSEN
R
8
VSUM
VO
IMVP6_PWRGD
VCC-SENSE
VSS-SENSE
R
9
C
9
NTC
Network
RTN
R
7
ISL6261
C
R
10
7
C
3
R
VW
11
OCSET
C
2
R
C
10
2
COMP
FB
DFB
R
12
C
1
R
3
DROOP
VDIFF
R
1
VSS
FIGURE 2. ISL6261-BASED IMVP-6® SOLUTION WITH INDUCTOR DCR CURRENT SENSING
FN9251.1
September 27, 2006
9
ISL6261
Simplified Application Circuit for Resistive Current Sensing
V
+5
V+3.3
Vin
R
4
C
4
3V3 VDD VCCP
R
R
C
5
RBIAS
NTC
VIN
6
5
C
8
UGATE
BOOT
SOFT
VR_TT#
Lo
C
6
Rsen
VR_TT#
Vo
PHASE
VID<0:6>
DPRSTP#
VIDs
Co
DPRSTP#
DPRSLPVR
FDE
DPRSLPVR
LGATE
VSSP
MCH_PWRGD
CLK_ENABLE#
VR_ON
PGD_IN
CLK_EN#
VR_ON
PGOOD
VSEN
R
8
VSUM
VO
IMVP6_PWRGD
VCC-SENSE
VSS-SENSE
C
9
RTN
R
7
ISL6261
C
R
10
7
C
3
R
R
VW
11
OCSET
C
2
R
C
10
2
COMP
FB
DFB
12
C
1
R
3
DROOP
VDIFF
R
1
VSS
FIGURE 3. ISL6261-BASED IMVP-6® SOLUTION WITH RESISTIVE CURRENT SENSING
FN9251.1
September 27, 2006
10
ISL6261
Theory of Operation
The ISL6261 is a single-phase regulator implementing Intel®
IMVP-6® protocol and includes an integrated gate driver for
reduced system cost and board area. The ISL6261 IMVP-6®
solution provides optimum steady state and transient
performance for microprocessor core voltage regulation
applications up to 25A. Implementation of diode emulation
mode (DEM) operation further enhances system efficiency.
VDD
10mV/us
Vboot
VR_ON
100us
2mV/us
SOFT &VO
~20us
The heart of the ISL6261 is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. The R3™
modulator combines the best features of fixed frequency and
hysteretic PWM controllers while eliminating many of their
shortcomings. The ISL6261 modulator internally synthesizes
an analog of the inductor ripple current and uses hysteretic
comparators on those signals to establish PWM pulses.
Operating on the large-amplitude and noise-free synthesized
signals allows the ISL6261 to achieve lower output ripple
and lower phase jitter than either conventional hysteretic or
fixed frequency PWM controllers. Unlike conventional
hysteretic converters, the ISL6261 has an error amplifier that
allows the controller to maintain 0.5% voltage regulation
accuracy throughout the VID range from 0.75V to 1.5V.
PGD_IN
CLK_EN#
~7ms
IMVP-VI PGOOD
FIGURE 4. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
Static Operation
After the startup sequence, the output voltage will be
regulated to the value set by the VID inputs per Table 1,
which is presented in the lntel® IMVP-6® specification. The
ISL6261 regulates the output voltage with ±0.5% accuracy
over the range of 0.7V to 1.5V.
The hysteretic window voltage is with respect to the error
amplifier output. Therefore the load current transient results
in increased switching frequency, which gives the R3™
regulator a faster response than conventional fixed
frequency PWM regulators.
A true differential amplifier remotely senses the core voltage
to precisely control the voltage at the microprocessor die.
VSEN and RTN pins are the inputs to the differential
amplifier.
Start-up Timing
With the controller’s VDD pin voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. In approximately
100μs, SOFT and VO start ramping to the boot voltage of
1.2V. At startup, the regulator always operates in continuous
current mode (CCM), regardless of the control signals.
During this interval, the SOFT cap is charged by a 41μA
current source. If the SOFT capacitor is 20nF, the SOFT
ramp will be 2mV/μs for a soft-start time of 600μs. Once VO
is within 10% of the boot voltage and PGD_IN is HIGH for six
PWM cycles (20µs for 300kHz switching frequency),
CLK_EN# is pulled LOW, and the SOFT cap is
As the load current increases from zero, the output voltage
droops from the VID value proportionally to achieve the
IMVP-6® load line. The ISL6261 can sense the inductor
current through the intrinsic series resistance of the
inductors, as shown in Figure 2, or through a precise resistor
in series with the inductor, as shown in Figure 3. The
inductor current information is fed to the VSUM pin, which is
the non-inverting input to the droop amplifier. The DROOP
pin is the output of the droop amplifier, and DROOP-VO
voltage is a high-bandwidth analog representation of the
inductor current. This voltage is used as an input to a
differential amplifier to achieve the IMVP-6® load line, and
also as the input to the overcurrent protection circuit.
charged/discharged by approximate 200µA and VO slews at
10mV/μs to the voltage set by the VID pins. In approximately
7ms, PGOOD is asserted HIGH. Figure 4 shows typical
startup timing.
When using inductor DCR current sensing, an NTC
thermistor is used to compensate the positive temperature
coefficient of the copper winding resistance to maintain the
load-line accuracy.
PGD_IN Latch
It should be noted that PGD_IN going low will cause the
converter to latch off. Toggling PGD_IN won’t clear the latch.
Toggling VR_ON will clear it. This feature allows the
converter to respond to other system voltage outages
immediately.
The switching frequency of the ISL6261 controller is set by
the resistor RFSET between pins VW and COMP, as shown in
Figures 2 and 3.
FN9251.1
September 27, 2006
11
ISL6261
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Vo (V)
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Vo (V)
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
1.1750
1.1625
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
1.0000
0.9875
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FN9251.1
September 27, 2006
12
ISL6261
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Vo (V)
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
0.3625
0.3500
0.3375
0.3250
0.3125
0.3000
0.2875
0.2750
0.2625
0.2500
0.2375
0.2250
0.2125
0.2000
0.1875
0.1750
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Vo (V)
0.1625
0.1500
0.1375
0.1250
0.1125
0.1000
0.0875
0.0750
0.0625
0.0500
0.0375
0.0250
0.0125
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATIONAL MODES OF ISL6261
VW-COMP WINDOW
VOLTAGE INCREASE
DPRSTP#
FDE
DPRSLPVR
OPERATIONAL MODE
Forced CCM
0
0
0
0%
Control
Signal
Logic
0
0
1
0
1
x
1
x
x
Diode Emulation Mode
Enhanced Diode Emulation Mode
Forced CCM
0%
33%
0%
FN9251.1
September 27, 2006
13
ISL6261
based on load current. Light-load efficiency is increased in
High Efficiency Operation Mode
both active mode and deeper sleep mode.
The operational modes of the ISL6261 depend on the
control signal states of DPRSTP#, FDE, and DPRSLPVR, as
shown in Table 2. These control signals can be tied to lntel®
IMVP-6® control signals to maintain the optimal system
configuration for all IMVP-6® conditions.
CPU mode-transition sequences often occur in concert with
VID changes. The ISL6261 employs carefully designed
mode-transition timing to work in concert with the VID
changes.
DPRSTP# = 0, FDE = 0 and DPRSLPVR = 1 enables the
ISL6261 to operate in diode emulation mode (DEM) by
monitoring the low-side FET current. In diode emulation
mode, when the low-side FET current flows from source to
drain, it turns on as a synchronous FET to reduce the
conduction loss. When the current reverses its direction
trying to flow from drain to source, the ISL6261 turns off the
low-side FET to prevent the output capacitor from
discharging through the inductor, therefore eliminating the
extra conduction loss. When DEM is enabled, the regulator
works in automatic discontinuous conduction mode (DCM),
meaning that the regulator operates in CCM in heavy load,
and operates in DCM in light load. DCM in light load
decreases the switching frequency to increase efficiency.
This mode can be used to support the deeper sleep mode of
the microprocessor.
The ISL6261 is equipped with internal counters to prevent
control signal glitches from triggering unintended mode
transitions. For example: Control signals lasting less than
seven switching periods will not enable the diode emulation
mode.
Dynamic Operation
The ISL6261 responds to VID changes by slewing to new
voltages with a dv/dt set by the SOFT capacitor and the logic
of DPRSLPVR. If CSOFT = 20nF and DPRSLPVR = 0, the
output voltage will move at a maximum dv/dt of ±10mV/μs
for large changes. The maximum dv/dt can be used to
achieve fast recovery from Deeper Sleep to Active mode. If
CSOFT = 20nF and DPRSLPVR = 1, the output voltage will
move at a dv/dt of ±2mV/μs for large changes. The slow
dv/dt into and out of deeper sleep mode will minimize the
audible noise. As the output voltage approaches the VID
command value, the dv/dt moderates to prevent overshoot.
The ISL6261 is IMVP-6® compliant for DPRSTP# and
DPRSLPVR logic.
DPRSTP# = 0 and FDE = 1 enables the enhanced diode
emulation mode (EDEM), which increases the VW-COMP
window voltage by 33%. This further decreases the
switching frequency at light load to boost efficiency in the
deeper sleep mode.
Intersil R3™ has an intrinsic voltage feed forward function.
High-speed input voltage transients have little effect on the
output voltage.
For other combinations of DPRSTP#, FDE, and
DPRSLPVR, the ISL6261 operates in forced CCM.
Intersil R3™ commands variable switching frequency during
transients to achieve fast response. Upon load application,
the ISL6261 will transiently increase the switching frequency
to deliver energy to the output more quickly. Compared with
steady state operation, the PWM pulses during load
application are generated earlier, which effectively increases
the duty cycle and the response speed of the regulator.
Upon load release, the ILS6261 will transiently decrease the
switching frequency to effectively reduce the duty cycle to
achieve fast response.
The ISL6261 operational modes can be set according to
CPU mode signals to achieve the best performance. There
are two options: (1) Tie FDE to DPRSLPVR, and tie
DPRSTP# and DPRSLPVR to the corresponding CPU mode
signals. This configuration enables EDEM in deeper sleep
mode to increase efficiency. (2) Tie FDE to “1” and
DPRSTP# to “0” permanently, and tie DPRSLPVR to the
corresponding CPU mode signal. This configuration sets the
regulator in EDEM all the time. The regulator will enter DCM
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6261
FAULT DURATION PRIOR
TO PROTECTION
FAULT TYPE
Overcurrent fault
PROTECTION ACTIONS
PWM tri-state, PGOOD latched low
PWM tri-state, PGOOD latched low
FAULT RESET
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
VDD toggle
120μs
Way-Overcurrent fault
Overvoltage fault (1.7V)
< 2μs
Immediately
Low-side FET on until Vcore < 0.85V, then PWM tri-
state, PGOOD latched low (OV-1.7V always)
Overvoltage fault
(+200mV)
1ms
PWM tri-state, PGOOD latched low
PWM tri-state, PGOOD latched low
VR_TT# goes high
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
N/A
Undervoltage fault
(-300mV)
1ms
Over-temperature fault
(NTC<1.18)
Immediately
FN9251.1
September 27, 2006
14
ISL6261
threshold, the VR_TT# pin is pulled low indicating the need
Protection
for thermal throttling to the system oversight processor. No
other action is taken within the ISL6261.
The ISL6261 provides overcurrent (OC), overvoltage (OV),
undervoltage (UV) and over-temperature (OT) protections as
shown in Table 3.
Component Selection and Application
Overcurrent is detected through the droop voltage, which is
designed as described in the “Component Selection and
Application” section. The OCSET resistor sets the
overcurrent protection level. An overcurrent fault will be
declared when the droop voltage exceeds the overcurrent
set point for more than 120µs. A way-overcurrent fault will be
declared in less than 2µs when the droop voltage exceeds
twice the overcurrent set point. In both cases, the UGATE
and LGATE outputs will be tri-stated and PGOOD will go low.
Soft-Start and Mode Change Slew Rates
The ISL6261 commands two different output voltage slew
rates for various modes of operation. The slow slew rate
reduces the inrush current during startup and the audible
noise during the entry and the exit of Deeper Sleep Mode.
The fast slew rate enhances the system performance by
achieving active mode regulation quickly during the exit of
Deeper Sleep Mode. The SOFT current is bidirectional ⎯
charging the SOFT capacitor when the output voltage is
commanded to rise, and discharging the SOFT capacitor
when the output voltage is commanded to fall.
The over-current condition is detected through the droop
voltage. The droop voltage is equal to Icore×Rdroop, where
Rdroop is the load line slope. A 10μA current source flows out
Figure 5 shows the circuitry on the SOFT pin. The SOFT pin,
the non-inverting input of the error amplifier, is connected to
ground through capacitor CSOFT. ISS is an internal current
source connected to the SOFT pin to charge or discharge
of the OCSET pin and creates a voltage drop across ROCSET
(shown as R10 in Figure 2). Overcurrent is detected when
the droop voltage exceeds the voltage across ROCSET
.
Equation 1 gives the selection of ROCSET
.
C
SOFT. The ISL6261 controls the output voltage slew rate by
IOC × Rdroop
10μA
(EQ. 1)
connecting or disconnecting another internal current source
IZ to the SOFT pin, depending on the state of the system, i.e.
Startup or Active mode, and the logic state on the
DPRSLPVR pin. The SOFT-START CURRENT section of
the Electrical Specification Table shows the specs of these
two current sources.
ROCSET
=
For example: The desired over current trip level, Ioc, is 30A,
droop is 2.1mΩ, Equation 1 gives ROCSET = 6.3k.
R
Undervoltage protection is independent of the overcurrent
limit. A UV fault is declared when the output voltage is lower
than (VID-300mV) for more than 1ms. The gate driver
outputs will be tri-stated and PGOOD will go low. Note that a
practical core regulator design usually trips OC before it trips
UV.
ISS
IZ
Internal to
ISL6261
There are two levels of overvoltage protection and response.
An OV fault is declared when the output voltage exceeds the
VID by +200mV for more than 1ms. The gate driver outputs
will be tri-stated and PGOOD will go low. The inductor
current will decay through the low-side FET body diode.
Toggling of VR_ON or bringing VDD below 4V will reset the
fault latch. A way-overvoltage (WOV) fault is declared
immediately when the output voltage exceeds 1.7V. The
ISL6261 will latch PGOOD low and turn on the low-side
FETs. The low-side FETs will remain on until the output
voltage drops below approximately 0.85V, then all the FETs
are turned off. If the output voltage again rises above 1.7V,
the protection process repeats. This mechanism provides
maximum protection against a shorted high-side FET while
preventing the output from ringing below ground. Toggling
VR_ON cannot reset the WOV protection; recycling VDD will
reset it. The WOV detector is active all the time, even when
other faults are declared, so the processor is still protected
against the high-side FET leakage while the FETs are
commanded off.
Error
Ampliflier
CSOFT
VREF
FIGURE 5. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
I
SS is 41μA typical and is used during startup and mode
changes. When connected to the SOFT pin, IZ adds to ISS to
get a larger current, labelled IGV in the Electrical
Specification Table, on the SOFT pin. IGV is typically 200μA
with a minimum of 175μA.
The IMVP-6® specification reveals the critical timing
associated with regulating the output voltage. SLEWRATE,
The ISL6261 has a thermal throttling feature. If the voltage
on the NTC pin goes below the 1.2V over-temperature
FN9251.1
September 27, 2006
15
ISL6261
10uA
R
ocset
OCSET
I
phase
L
OC
DCR
V
o
R
s
VSUM
DFB
C
o
Internal to
ISL6261
DROOP
ESR
DROOP
VO
1
1000pF
0~10
VSEN
RTN
VCC-SENSE
VSS-SENSE
To Processor
Socket Kelvin
Conections
1
1000pF
330pF
VDIFF
FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING
given in the IMVP-6® specification, determines the choice of
Startup Operation - CLK_EN# and PGOOD
the SOFT capacitor, CSOFT, through the following equation:
The ISL6261 provides a 3.3V logic output pin for CLK_EN#.
IGV
The system 3.3V voltage source connects to the 3V3 pin,
which powers internal circuitry that is solely devoted to the
CLK_EN# function. The output is a CMOS signal with 4mA
sourcing and sinking capability. CMOS logic eliminates the
need for an external pull-up resistor on this pin, eliminating
the loss on the pull-up resistor caused by CLK_EN# being
low in normal operation. This prolongs battery run time. The
3.3V supply should be decoupled to digital ground, not to
analog ground, for noise immunity.
(EQ. 2)
CSOFT
=
SLEWRATE
If SLEWRATE is 10mV/μs, and IGV is typically 200μA, CSOFT
is calculated as
(EQ. 3)
CSOFT = 200μA
(
10mV μs = 20nF
)
Choosing 0.015μF will guarantee 10mV/μs SLEWRATE at
minimum IGV value. This choice of CSOFT controls the
startup slew rate as well. One should expect the output
voltage to slew to the Boot value of 1.2V at a rate given by
the following equation:
At startup, CLK_EN# remains high until 20μs after PGD_IN
going high, and Vcc-core is regulated at the Boot voltage.
The ISL6261 triggers an internal timer for the
IMVP6_PWRGD signal (PGOOD pin). This timer allows
PGOOD to go high approximately 7ms after CLK_EN# goes
low.
dVsoft
dt
Iss
41μA
mV
(EQ. 4)
=
=
= 2.8
μs
CSOFT 0.015μF
Selecting Rbias
Static Mode of Operation - Processor Die Sensing
To properly bias the ISL6261, a reference current needs to be
derived by connecting a 147k, 1% tolerance resistor from the
RBIAS pin to ground. This provides a very accurate 10μA
current source from which OCSET reference current is derived.
Remote sensing enables the ISL6261 to regulate the core
voltage at a remote sensing point, which compensates for
various resistive voltage drops in the power delivery path.
The VSEN and RTN pins of the ISL6261 are connected to
Kelvin sense leads at the die of the processor through the
processor socket. (The signal names are Vcc_sense and
Vss_sense respectively). Processor die sensing allows the
voltage regulator to tightly control the processor voltage at
the die, free of the inconsistencies and the voltage drops due
Caution should used in layout: This resistor should be
placed in the close proximity of the RBIAS pin and be
connected to good quality signal ground. Do not connect any
other components to this pin, as they will negatively impact
the performance. Capacitance on this pin may create
instabilities and should be avoided.
FN9251.1
September 27, 2006
16
ISL6261
to layouts. The Kelvin sense technique provides for
extremely tight load line regulation at the processor die side.
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor should be laid out away from rapidly rising voltage
nodes (switching nodes) and other noisy traces. Common
mode and differential mode filters are recommended as
shown in Figure 6. The recommended filter resistance range
is 0~10Ω so it does not interact with the 50k input resistance
of the differential amplifier. The filter resistor may be inserted
between VCC-SENSE and the VSEN pin. Another option is
to place one between VCC-SENSE and the VSEN pin and
another between VSS-SENSE and the RTN pin. The need of
these filters also depends on the actual board layout and the
noise environment.
54uA
6uA
Internal to
ISL6261
VR_TT#
NTC
SW1
VNTC
RNTC
SW2
RS
1.23V
1.20V
FIGURE 7. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE
Since the voltage feedback is sensed at the processor die, if
the CPU is not installed, the regulator will drive the output
voltage all the way up to damage the output capacitors due
to lack of output voltage feedback. Ropn1 and Ropn2 are
recommended, as shown in Figure 6, to prevent this
potential issue. Ropn1 and Ropn2, typically ranging
20~100Ω, provide voltage feedback from the regulator local
output in the absence of the CPU.
Figure 7 shows the circuitry associated with the thermal
throttling feature of the ISL6261. At low temperature, SW1 is
on and SW2 connects to the 1.20V side. The total current
going into the NTC pin is 60µA. The voltage on the NTC pin
is higher than 1.20V threshold voltage and the comparator
output is low. VR_TT# is pulled up high by an external
resistor. Temperature increase will decrease the NTC
thermistor resistance. This decreases the NTC pin voltage.
When the NTC pin voltage drops below 1.2V, the comparator
output goes high to pull VR_TT# low, signalling a thermal
throttle. In addition, SW1 turns off and SW2 connects to
1.23V, which decreases the NTC pin current by 6µA and
increases the threshold voltage by 30mV. The VR_TT#
signal can be used by the system to change the CPU
operation and decrease the power consumption. As the
temperature drops, the NTC pin voltage goes up. If the NTC
pin voltage exceeds 1.23V, VR_TT# will be pulled high.
Figure 8 illustrates the temperature hysteresis feature of
Setting the Switching Frequency - FSET
3
The R modulator scheme is not a fixed frequency PWM
architecture. The switching frequency increases during the
application of a load to improve transient performance.
It also varies slightly depending on the input and output
voltages and output current, but this variation is normally
less than 10% in continuous conduction mode.
Resistor R
(R in Figure 2), connected between the VW
7
fset
and COMP pins of the ISL6261, sets the synthetic ripple
window voltage, and therefore sets the switching frequency.
This relationship between the resistance and the switching
frequency in CCM is approximately given by the following
equation.
VR_TT#. T and T (T >T ) are two threshold temperatures.
1
2
1
2
VR_TT# goes low when the temperature is higher than T
1
and goes high when the temperature is lower than T .
2
VR_TT#
Logic_1
(EQ. 5)
Rfset
(
kΩ
)
=
(
period(μs) − 0.29 × 2.33
)
In diode emulation mode, the ISL6261 stretches the
switching period. The switching frequency decreases as the
load becomes lighter. Diode emulation mode reduces the
switching loss at light load, which is important in conserving
battery power.
Logic_0
T 2
T 1
T (oC)
Voltage Regulator Thermal Throttling
FIGURE 8. VR_TT# TEMPERATURE HYSTERISIS
®
®
lntel IMVP-6 technology supports thermal throttling of the
processor to prevent catastrophic thermal damage to the
voltage regulator. The ISL6261A features a thermal monitor
sensing the voltage across an externally placed negative
temperature coefficient (NTC) thermistor. Proper selection
and placement of the NTC thermistor allows for detection of
a designated temperature rise by the system.
FN9251.1
September 27, 2006
17
ISL6261
The NTC thermistor’s resistance is approximately given by
the following formula:
Once R
and R is designed, the actual NTC resistance
NTCTo s
at T and the actual T temperature can be found in:
2
2
1
1
(EQ. 13)
(EQ. 14)
RNTC _T 2 = 2.78kΩ + RNTC _T
b⋅(
⋅e
−
)
(EQ. 6)
1
T + 273 To + 273
R
(T) = R
NTC
NTCTo
1
T2 _ actual
=
− 273
T is the temperature of the NTC thermistor and b is a
constant determined by the thermistor material. T is the
reference temperature at which the approximation is
R
1
NTC _T2
ln(
) +1 (273 +To )
o
b
RNTCTo
derived. The most commonly used T is 25°C. For most
commercial NTC thermistors, there is b = 2750k, 2600k,
4500k or 4250k.
One example of using Equations 10, 11 and 12 to design a
thermal throttling circuit with the temperature hysteresis
o
100°C to 105°C is illustrated as follows. Since T = 105°C
1
and T = 100°C, if we use a Panasonic NTC with b = 4700,
Equation 9 gives the required NTC nominal resistance as
2
From the operation principle of VR_TT#, the NTC resistor
satisfies the following equation group:
RNTC_To = 431kΩ
1.20V
(EQ. 7)
RNTC(T ) + Rs =
= 20kΩ
1
60μA
The NTC thermistor datasheet gives the resistance ratio as
0.03956 at 100°C and 0.03322 at 105°C. The b value of
4700k in Panasonic datasheet only covers up to 85°C;
therefore, using Equation 11 is more accurate for 100°C
design and the required NTC nominal resistance at 25°C is
438kΩ. The closest NTC resistor value from manufacturers
is 470kΩ. So Equation 12 gives the series resistance as
follows:
1.23V
54μA
(EQ. 8)
RNTC(T2 ) + Rs =
= 22.78kΩ
From Equation 7 and Equation 8, the following can be
derived:
(EQ. 9)
RNTC(T2 )− RNTC(T ) = 2.78kΩ
1
Substitution of Equation 6 into Equation 9 yields the required
nominal NTC resistor value:
Rs = 20kΩ − RNTC _105C = 20kΩ −15.61kΩ = 4.39kΩ
The closest standard value is 4.42kΩ. Furthermore,
1
b⋅(
)
To +273
Equation 13 gives the NTC resistance at T :
2
2.78kΩ⋅e
(EQ. 10)
RNTCTo
=
1
1
RNTC _T 2 = 2.78kΩ + RNTC _T =18.39kΩ
b⋅(
b⋅(
)
1
T2 +273
T +273
1
e
) −e
The NTC branch is designed to have a 470k NTC and a
4.42k resistor in series. The part number of the NTC
thermistor is ERTJ0EV474J. It is a 0402 package. The NTC
thermistor should be placed in the spot that gives the best
indication of the temperature of the voltage regulator. The
actual temperature hysteretic window is approximately
105°C to 100°C.
In some cases, the constant b is not accurate enough to
approximate the resistor value; manufacturers provide the
resistor ratio information at different temperatures. The
nominal NTC resistor value may be expressed in another
way as follows:
2.78kΩ
RNTCTo
=
Λ
Λ
(EQ. 11)
RNTC (T2 )− RNTC (T )
1
Λ
where R NTC (T) is the normalized NTC resistance to its
nominal value. The normalized resistor value on most NTC
thermistor datasheets is based on the value at 25°C.
Once the NTC thermistor resistor is determined, the series
resistor can be derived by:
1.20V
(EQ. 12)
Rs =
− RNTC(T1 ) = 20kΩ − R
NTC_T1
60μA
FN9251.1
September 27, 2006
18
ISL6261
10uA
R
ocset
OCSET
VO
OC
R
s
VSUM
DFB
Internal to
ISL6261
DROOP
V
Io DCR
DROOP
VO
dcr
R
R
series
ntc
R
1
par
(Rntc+Rseries) Rpar
Rntc+Rseries+Rpar
R
n
FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DCR SENSING
G1, the gain of V to V
temperature of the NTC thermistor:
, is also dependent on the
Static Mode of Operation - Static Droop Using DCR
Sensing
n
DCR
Δ
The ISL6261 has an internal differential amplifier to
accurately regulate the voltage at the processor die.
Rn (T)
G1(T)=
(EQ. 17)
Rn (T) + Rs
For DCR sensing, the process to compensate the DCR
resistance variation takes several iterative steps. Figure 2
shows the DCR sensing method. Figure 9 shows the
simplified model of the droop circuitry. The inductor DC
current generates a DC voltage drop on the inductor DCR.
Equation 15 gives this relationship.
The inductor DCR is a function of the temperature and is
approximately given by
(EQ. 18)
DCR(T) = DCR25C ⋅(1+ 0.00393*(T − 25))
in which 0.00393 is the temperature coefficient of the copper.
The droop amplifier output voltage divided by the total load
current is given by:
(EQ. 15)
VDCR = Io × DCR
An R-C network senses the voltage across the inductor to
Rdroop = G1(T)⋅ DCR(T)⋅kdroopamp
(EQ. 19)
get the inductor current information. R represents the NTC
n
network consisting of R , R
and R . The choice of R
par s
R
is the actual load line slope. To make R
droop
ntc
series
droop
will be discussed in the next section.
independent of the inductor temperature, it is desired to
have:
The first step in droop load line compensation is to choose
(EQ. 20)
G1 (T)⋅(1+ 0.00393*(T − 25)) ≅ G1
R and R such that the correct droop voltage appears even
n
s
t arget
at light loads between the VSUM and VO nodes. As a rule of
thumb, the voltage drop across the R network, V , is set to
where G
is the desired ratio of V /V
. Therefore, the
1target
n
DCR
n
n
temperature characteristics G is described by:
be 0.5-0.8 times V
. This gain, defined as G1, provides a
1
DCR
fairly reasonable amount of light load signal from which to
derive the droop voltage.
G1
t arget
(EQ. 21)
G1(T) =
(1+ 0.00393*(T − 25)
The NTC network resistor value is dependent on the
temperature and is given by:
For different G1 and NTC thermistor preference, Intersil
provides a design spreadsheet to generate the proper value
(Rseries + Rntc )⋅ Rpar
(EQ. 16)
of R , R
, R
.
Rn (T) =
ntc
series
par
Rseries + Rntc + Rpar
FN9251.1
September 27, 2006
19
ISL6261
R
(R in Figure 2) and R
(R in Figure 2) sets the
The droop capacitor refers to C in Figure 9. If C is
n n
drp1
11
drp2
12
droop amplifier gain, according to Equation 22:
designed correctly, its voltage will be a high-bandwidth
analog voltage of the inductor current. If C is not designed
correctly, its voltage will be distorted from the actual
waveform of the inductor current and worsen the transient
n
Rdrp2
kdroopamp =1+
Rdrp1
(EQ. 22)
response. Figure 11 shows the transient response when C
n
After determining R and R networks, use Equation 23 to
s
n
is too small. V
may sag excessively upon load
core
calculate the droop resistances R
and R
.
drp1
drp2
application to create a system failure. Figure 12 shows the
transient response when C is too large. V is sluggish in
n
core
Rdroop
DCR⋅G1(25o C)
(EQ. 23)
Rdrp2 = (
−1)⋅ Rdrp1
drooping to its final value. There will be excessive overshoot
if a load occurs during this time, which may potentially hurt
the CPU reliability.
®
®
R
is 2.1mV/A per lntel IMVP-6 specification.
droop
The effectiveness of the R network is sensitive to the
n
ΔIcore
icore
coupling coefficient between the NTC thermistor and the
inductor. The NTC thermistor should be placed in close
proximity of the inductor.
ΔVcore
Vcore
To verify whether the NTC network successfully compensates
the DCR change over temperature, one can apply full load
current, and wait for the thermal steady state, and see how
much the output voltage deviates from the initial voltage
reading. Good thermal compensation can limit the drift to less
than 2mV. If the output voltage decreases when the
Vcore
ΔVcore= ΔIcore×Rdroop
FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
temperature increases, that ratio between the NTC thermistor
value and the rest of the resistor divider network has to be
increased. Following the evaluation board value and layout of
NTC placement will minimize the engineering time.
icore
Vcore
Vcore
The current sensing traces should be routed directly to the
inductor pads for accurate DCR voltage drop measurement.
However, due to layout imperfection, the calculated R
drp2
FIGURE 11. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
SMALL
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust R after the system
drp2
has achieved thermal equilibrium at full load. For example, if
the max current is 20A, one should apply 20A load current
and look for 42mV output voltage droop. If the voltage droop
icore
is 40mV, the new value of R
is calculated by:
dpr2
Vcore
Vcore
42 mV
Rdrp 2 _ new
=
(Rdrp 1 + Rdrp 2 ) − Rdrp 1
40 mV
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
LARGE
(EQ. 24)
The current sensing network consists of R , R and C . The
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. The
n
s
n
effective resistance is the parallel of R and R . The RC time
n
s
constant of the current sensing network needs to match the
L/DCR time constant of the inductor to get correct
representation of the inductor current waveform. Equation 25
shows this equation:
effective resistance on the VSUM pin is the parallel of R and
s
R , and the effective resistance on the DFB pin is the parallel
n
of R
and R
.
drp2
drp1
Dynamic Mode of Operation – Droop Capacitor
Design in DCR Sensing
Figure 10 shows the desired waveforms during load
⎛
⎞
Rn × Rs
Rn + Rs
L
(EQ. 25)
⎜
⎜
⎟
⎟
=
×Cn
DCR
⎝
⎠
transient response. V
needs to be as square as possible
response is determined by several
core
at I
change. The V
core
core
factors, namely the choice of output inductor and output
capacitor, the compensator design, and the droop capacitor
design.
FN9251.1
September 27, 2006
20
ISL6261
Solving for Cn yields
The user can choose the actual resistor and capacitor values
based on the recommendation and input them in the
spreadsheet, then see the actual loop gain curves and the
regulator output impedance curve.
L
DCR
Rn × Rs
Rn + Rs
(EQ. 26)
Cn =
Caution needs to be used in choosing the input resistor to
the FB pin. Excessively high resistance will cause an error to
the output voltage regulation due to the bias current flowing
in the FB pin. It is recommended to keep this resistor below
3k.
For example: L = 0.45μH, DCR = 1.1mΩ, R = 7.68kΩ, and
R = 3.4kΩ
s
n
0.45μH
0.0011
parallel(7.68k,3.4k)
Droop using Discrete Resistor Sensing -
Static/Dynamic Mode of Operation
(EQ. 27)
Cn =
=174nF
Figure 3 shows a detailed schematic using discrete resistor
sensing of the inductor current. Figure 14 shows the
equivalent circuit. Since the current sensing resistor voltage
Since the inductance and the DCR typically have 20% and
7% tolerance respectively, the L/DCR time constant of each
individual inductor may not perfectly match the RC time
constant of the current sensing network. In mass production,
this effect will make the transient response vary a little bit
from board to board. Compared with potential long-term
damage on CPU reliability, an immediate system failure is
worse. So it is desirable to avoid the waveforms shown in
represents the actual inductor current information, R and C
s
n
simply provide noise filtering. The most significant noise
comes from the ESL of the current sensing resistor. A low
low ESL sensing resistor is strongly recommended. The
recommended R is 100Ω and the recommended C is
s
n
220pF. Since the current sensing resistance does not
appreciably change with temperature, the NTC network is
not needed for thermal compensation.
Figure 11. It is recommended to choose the minimum C
value based on the maximum inductance so only the
n
scenarios of Figures 10 and 12 may happen. It should be
Droop is designed the same way as the DCR sensing
approach. The voltage on the current sensing resistor is
given by the following equation:
noted that, after calculation, fine-tuning of C value may still
n
be needed to account for board parasitics. C also needs to
n
be a high-grade cap like X7R with low tolerance. Another
good option is the NPO/COG (class-I) capacitor, featuring
only 5% tolerance and very good thermal characteristics. But
the NPO/COG caps are only available in small capacitance
values. In order to use such capacitors, the resistors and
thermistors surrounding the droop voltage sensing and
droop amplifier need to be scaled up 10X to reduce the
capacitance by 10X. Attention needs to be paid in balancing
the impedance of droop amplifier.
(EQ. 28)
Vrsen = Rsen ⋅ Io
Equation 21shows the droop amplifier gain. So the actual
droop is given by
⎛
⎞
⎟
⎟
⎠
Rdrp2
Rdrp1
(EQ. 29)
⎜
Rdroop = Rsen ⋅ 1+
⎜
⎝
Solving for R
yields:
drp2
Dynamic Mode of Operation - Compensation
Parameters
R
⎛
⎞
droop
(EQ. 30)
= 1k,
⎜
⎜
⎟
⎟
Rdrp2 = Rdrp1
⋅
−1
Rsen
⎝
⎠
The voltage regulator is equivalent to a voltage source equal
to VID in series with the output impedance. The output
impedance needs to be 2.1mΩ in order to achieve the
2.1mV/A load line. It is highly recommended to design the
compensation such that the regulator output impedance is
2.1mΩ. A type-III compensator is recommended to achieve
the best performance. Intersil provides a spreadsheet to
design the compensator parameters. Figure 13 shows an
example of the spreadsheet. After the user inputs the
parameters in the blue font, the spreadsheet will calculate
the recommended compensator parameters (in the pink
font), and show the loop gain curves and the regulator output
impedance curve. The loop gain curves need to be stable for
regulator stability, and the impedance curve needs to be
equal to or smaller than 2.1mΩ in the entire frequency range
to achieve good transient response.
For example: R
= 2.1mΩ. If R
= 1m and R
is 1.1k.
droop
sen drp1
easy calculation gives that R
drp2
The current sensing traces should be routed directly to the
current sensing resistor pads for accurate measurement.
However, due to layout imperfections, the calculated R
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust R
drp2
after the system
drp2
has achieved thermal equilibrium at full load.
FN9251.1
September 27, 2006
21
ISL6261
FIGURE 13. AN EXAMPLE OF ISL6261 COMPENSATION SPREADSHEET
FN9251.1
September 27, 2006
22
ISL6261
10uA
R
ocset
OCSET
VO
OC
R
s
VSUM
DFB
Internal to
ISL6261
DROOP
V
rsen
DROOP
VO
Io Rsen
1
FIGURE 14. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR SENSING
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board)
FIGURE 16. CCM LOAD LINE AND THE SPEC, VID = 1.1V,
IN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 15. CCM EFFICIENCY, VID = 1.1V,
IN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
V
V
FIGURE 17. DEM EFFICIENCY, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 18. DEM LOAD LINE AND THE SPEC, VID = 0.7625V,
IN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
V
FN9251.1
September 27, 2006
23
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
FIGURE 19. ENHANCED DEM EFFICIENCY, VID = 0.7625V,
IN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 20. ENHANCED DEM LOAD LINE, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
V
FIGURE 22. ENHANCED DEM LOAD LINE, VID = 1.1V,
FIGURE 21. ENHANCED DEM EFFICIENCY, VID = 1.1V,
IN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
V
IN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
V
5V/div
0.5V/div
10V/div
FIGURE 23. SOFT-START, VIN = 19V, Io = 0A, VID = 1.5V,
Ch1: VR_ON, Ch2: Vo, Ch4: PHASE
FIGURE 24. SOFT-START, VIN = 19V, Io = 0A, VID = 1.1V,
Ch1: VR_ON, Ch2: Vo, Ch4: PHASE
FN9251.1
September 27, 2006
24
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
5V/div
0.2V/div
0.2V/div
5V/div
5V/div
5V/div
10V/div
5V/div
FIGURE 25. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 1.5V,
Ch1: PGD_IN, Ch2: Vo, Ch3: CLK_EN#,
Ch4: PHASE
FIGURE 26. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 0.7625V,
Ch1: PGD_IN, Ch2: Vo, Ch3: PGOOD,
Ch4: CLK_EN
5V/div
0.5V/div
7.5ms
5V/div
10V/div
FIGURE 27. CLK_EN AND PGOOD ASSERTION DELAY,
FIGURE 28. SHUT DOWN, VIN = 19V, Io = 0.5A, VID = 1.5V,
Ch1: VR_ON, Ch2: Vo, Ch3: PGOOD,
Ch4: PHASE
V
IN=19V, Io=2A, VID=1.1V, Ch1: CLK_EN#,
Ch2: Vo, Ch3: PGOOD, Ch4: PHASE
FIGURE 29. SOFT START INRUSH CURRENT, VIN = 19V,
Io = 0.5A, VID = 1.1V, Ch1: DROOP-VO
FIGURE 30. VIN TRANSIENT TEST, VIN = 8Æ19V, Io = 2A,
VID = 1.1V, Ch1: Vo, Ch3: VIN, Ch4: PHASE
(2.1mV = 1A), Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
FN9251.1
September 27, 2006
25
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
FIGURE 31. C4 ENTRY/EXIT, VIN = 12.6V, Io = 0.7A,
HFM VID = 1.1V, LFM VID = 0.9V, C4
VID = 0.7625V, FDE = DPRSLPVR,
Ch1: DPRSTP#, Ch2: Vo, Ch3: DPRSLPVR/FDE,
Ch4: PHASE
FIGURE 32. VID TOGGLING, VIN = 12.6V, Io= 0.7A,
HFM VID = 1.1V, LFM VID = 0.9V,
Ch1: SOFT, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
100A/us
50A/us
FIGURE 33. LOAD STEP UP RESPONSE IN CCM,
FIGURE 34. LOAD STEP DOWN RESPONSE IN CCM
V
IN = 8V, Io = 2AÆ20A at 100A/us, VID = 1.1V,
V
IN = 8V, Io = 20AÆ2A at 100A/us, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
50A/us
100A/us
50A/us
100A/us
FIGURE 35. LOAD TRANSIENT RESPONSE IN CCM
IN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
FIGURE 36. LOAD TRANSIENT RESPONSE IN ENHANCED
DEM, VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
V
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
FN9251.1
September 27, 2006
26
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
50A/us
100A/us
FIGURE 37. LOAD TRANSIENT RESPONSE IN ENHANCED
DEM, VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
FIGURE 38. LOAD TRANSIENT RESPONSE IN ENHANCED
DEM, VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
120us
FIGURE 39. OVERCURRENT PROTECTION, VIN = 12.6V,
Io = 0AÆ28A, VID = 1.1V, Ch1: DROOP-VO
(2.1mV = 1A), Ch2: Vo, Ch3: PGOOD,
Ch4: PHASE
FIGURE 40. OVERVOLTAGE (>1.7V) PROTECTION,
V
IN = 12.6V, Io = 2A, VID = 1.1V,
Ch2: Vo, Ch3: PGOOD, Ch4: PHASE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9251.1
September 27, 2006
27
ISL6261
ISL6261 Eval1 Rev. C Evaluation Board Schematic
1 0 0
R 4 7
1 0 U F
C 3 1
1 0
R 4 6
1 0 K
J 1
R 4 2
1 0 U F
C 3 0
1 0 K
R 4 1
1 0 K
1 U F
C 2 9
1 0
R 3 9
R 4 0
1 0 K
0 . 0 1 U F
C 2 8
R 3 8
1 0 K
P 3 4
R 3 7
1 0 K
R 3 6
1 0 K
R 3 2
P 3 3
P 3 1
P 2 8
P 2 7
P 2 5
P 2 4
P 2 3
1 U F
C 2 7
P 3 2
P 2 9
P 2 6
0 . 2 2 U F
C 2 6
V I D 3
V D D
V S S
V I N
V S U M
V O
3 1
2 0
1 9
1 8
1 7
1 6
1 5
1 3
1 2
V I D 4
V I D 5
V I D 6
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
V R _ O N
D P R S L P V R
D F B
D P R S T P
D R O O P
P22
1 4
C L K _ E N
D N P P 3 0
R T N
3 V 3
V S E N
P G O O D
V D I F F
1 1
C 2 5
D N P
P 2 0
P 1 9
P 1 8
P 1 6
P 1 3
P21
R 3 1
N T C 1 0 K
3 . 5 7 K
R 2 9
4 . 5 3 K
R 2 7
R 2 8
P17
P 1 4
P 2
P 1 5
P 1 1
8 2 0 0 P F
1
C 2 1
D N P
0 . 0 6 8 U F
C 1 9
C 1 7
1 4 7 K
0 . 1 2 U F
O U T
R 2 2
C 1 6
P 1
0
1
0 . 1 U F
C 1 5
1 0 K
4 9 9
R 2 0
R 2 1
1 0 K
1 0 0 0 P F
D N P
R 1 7
R 1 8
1 0 K
1 0 0 0 P F
C 1 1
C 1 3
R 1 6
D N P
C 1 0
6 . 8 1 K
R 1 4
R 1 3
D N P
1 0 K
0 . 0 1 5 U F
R 1 0
1 0 K
R 1 0 3
C 8
R 9
P 1 0
P 7
P 4
P 5
P 9
P8
P 6
1 0 K
R 3
5 1 0
1 0 U F
C 2
S S L _ L X A 3 0 2 5 I G C
P 3
R 1
1
R E D
G R N
2
2 1
2
J 9 1
3
4 3
2
5 1 0
R 2
D 3
FN9251.1
September 27, 2006
28
ISL6261
ISL6261 Eval1 Rev. C Evaluation Board Schematic (Continued)
2 2 U F
C 7 0
2 2 U F
C 7 1
2 2 U F
C 6 4
2 2 U F
C 6 5
2 2 U F
C 6 6
2 2 U F
C 6 7
2 2 U F
C 6 8
2 2 U F
C 6 9
2 2 U F
C 5 8
2 2 U F
C 5 9
2 2 U F
C 6 0
2 2 U F
C 6 1
2 2 U F
C 6 2
2 2 U F
C 6 3
2 2 U F
C 5 2
2 2 U F
C 4 6
2 2 U F
C 3 6
2 2 U F
C 5 3
2 2 U F
C 4 7
2 2 U F
C 3 7
2 2 U F
C 5 4
2 2 U F
C 4 8
2 2 U F
2 2 U F
C 5 5
2 2 U F
C 4 9
2 2 U F
C 3 9
2 2 U F
C 5 6
2 2 U F
C 5 0
2 2 U F
C 4 2
2 2 U F
C 5 7
2 2 U F
C 5 1
2 2 U F
3 3 0 U F
C 8 9
3 3 0 U F
C 4 1
3 3 0 U F
C 4 0
3 3 0 U F
C 9 0
3 3 0 U F
C 4 4
3 3 0 U F
C 4 3
C 3 8
C 4 5
0 . 1 U F
C 9 1
0 . 1 U F
P 4 1
C 3 5
3
0
P 4 0
OUT
R 5 3
V C C _ P R M
0
7 . 6 8 K
R 5 1
P 3 9
OUT
R 5 0
V S U M
P 3 8
P 3 7
0 . 1 U F
C 3 4
5 6 U F
3
R 8 3
5 6 U F
C 5 B R 8 2
3
1 0 U F
C 5
1 0 U F
D N P
1 0 U F
1
2
C 4
D 2
D N P
R 4 9
1 U F
C 3 2
D N P
C 3 3
P 3 5
P 3 6
FN9251.1
September 27, 2006
29
ISL6261
ISL6261 Eval1 Rev. C Evaluation Board Schematic (Continued)
V S S S E N S E
O U T
A E 4
A E 7
N 2 6
N 2 3
VSS
VSSSENSE
VSS
A E 8
VSS
A E 1 1
VSS
VSS
A E 1 4
N 4
VSS
VSS
A E 1 6
N 1
M 2 5
M 2 G2 ND_POWER
M 5
M 2
L 2 4
L 2 1
L 6
L 3
K 2 6
K 2 3
K 4
K 1
VSS
VSS
I N
A E 1 9
VSS
VSS
A E 2 3
VSS
VSS
A E 2 6
INTEL_IMPV6
SOCKET1
VSS
VSS
A F 3
VSS
VSS
A F 6
VSS
VSS
A F 8
VSS
VSS
A F 1 1
VSS
VSS
A F 1 3
VSS
VSS
A F 1 6
VSS
VSS
A F 1 9
VSS
VSS
A F 2 1
VSS
VSS
A F 2 4
VSS
VSS
W 2 2
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
P 2
P 1
S
S
A A 6
A A 2 1
N 2 5
S
A A 2 3
N 2 4
S
A A 2 4
N 2 2
S
A A 2 6
N 5
S
A B 2
A B 3
A B 5
A B 6
N 3
S
S
S
S
N 2
M 2 6
M 2 4
A B 2 1
M 2 3
S
A B 2 2
M 4
S
A B 2 4
M 3
S
A B 2 5
M 1
S
A C 1
A C 2
A C 4
A C 5
L 2 6
S
S
S
S
L 2 5
L 2 3
L 2 2
A C 2 0
L 5
S
A C 2 2
L 4
L 2
L 1
S
A C 2 3
S
A C 2 5
S
A C 2 6
K 2 5
S
A D 1
A D 3
A D 4
K 2 4
S
S
S
K 2 2
K 5
A D 2 0
K 3
K 2
S
A D 2 1
S
A D 2 3
J 2 6
S
A D 2 4
J 2 4
S
A E 2 1
J 2 3
S
A E 2 2
J 4
S
A E 2 4
J 3
S
A E 2 5
J 1
S
A F 1
H 2 6
S
A F 2 2
H 2 5
H 2 3
H 2 2
S
A F 2 3
S
A F 2 5
S
A F 2 6
H 5
H 4
H 2
H 1
V I D 0
V I D 1
O U T
O U T
O U T
O U T
O U T
O U T
O U T
A D 6
A F 5
A E 5
A F 4
A E 3
A F 2
A E 2
A D 2 6
A E 6
V I D 0
V I D 1
V I D 2
V I D 3
V I D 4
V I D 5
V I D 6
V I D 2
V I D 3
V I D 4
V I D 5
V I D 6
G T L R E F
G 2 5
G 2 4
G 2 2
G 6
G 5
G 3
G 2
P S I
O U T
P S I #
F 2 6
INTEL_IMPV6
SOCKET1
FN9251.1
September 27, 2006
30
ISL6261
ISL6261 Eval1 Rev. C Evaluation Board Schematic (Continued)
3
0 . 1 2
R 7 6
0 . 1
R 7 5
2
3
1 0 U F
C 8 1
J 1 1
J 1 2
4 9 . 9 K
R 7 1
3
2
FN9251.1
September 27, 2006
31
ISL6261
ISL6261 Eval1 Rev. C Evaluation Board Schematic (Continued)
B A V 9 9
0
R 8 0
R 7 9
1
D N P
C 8 8
3
1 X 3
2
0
S 9
3
1
3
2
2
1
J 7
1 5 P F
C 8 7
P 4 5
P 4 2
P 4 4
1 5 P F
C 8 5
P 4 3
0 . 0 1 U F
B A V 9 9
D N P
C 8 4
0
0
R 7 8
R 7 0
1
C 7 9
3
2
S 3
0
D N P
R 6 8
R 1 0 5
0 . 1 U F
C 7 7
1 0 K
R 6 5
1 0 K
R 6 6
1 0 K
R 1 0 2
0 . 1 U F
C 7 5
0 . 1 U F
C 7 6
1 0 K
R 6 3
1 0 K
R 6 4
1 0 K
1 0 K
1 0 K
R 9 9
R 1 0 0
R 1 0 1
1 0 K
1 0 K
1 0 K
R 9 6
1 0 K
R 9 7
1 0 K
R 9 8
1 0 K
R 9 3
R 9 4
R 9 5
1 0 K
1 0 K
1 0 K
R 9 0
1 0 K
R 9 1
1 0 K
R 9 2
1 0 K
R 8 7
R 8 8
R 8 9
1 0 K
1 0 K
1 0 K
R 8 4
1 0 K
R 8 5
1 0 K
R 8 6
1 0 K
R 8 1
R 8 2
R 8 3
FN9251.1
September 27, 2006
32
ISL6261
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 9/06
4X
4.5
6.00
0.50
36X
A
6
B
31
40
PIN #1 INDEX AREA
6
30
1
PIN 1
INDEX AREA
4 . 10 ± 0 . 15
21
10
(4X)
0.15
11
20
0.10 M C A B
TOP VIEW
40X 0 . 4 ± 0 . 1
4
0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 90 ± 0 . 1
BASE PLANE
( 5 . 8 TYP )
(
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
5
C
0 . 2 REF
( 40X 0 . 23 )
0 . 00 MIN.
0 . 05 MAX.
( 40X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between .015mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN9251.1
September 27, 2006
33
ISL6261
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 9/06
4X
5.5
7.00
A
44X
6
0.50
B
PIN #1 INDEX AREA
37
48
6
1
36
PIN 1
INDEX AREA
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4
0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
C
C
0.10
0 . 90 ± 0 . 1
BASE PLANE
( 6 . 80 TYP )
4 . 30 )
SEATING PLANE
0.08 C
(
SIDE VIEW
( 44X 0 . 5 )
0 . 2 REF
5
C
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between .015mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN9251.1
September 27, 2006
34
相关型号：
ISL6262CRZ
Two-Phase Core Regulator for IMVP-6 Mobile CPUs; QFN48; Temp Range: See Datasheet
RENESAS
©2020 ICPDF网 联系我们和版权申明