ISL6296DRZ-T [INTERSIL]
FlexiHash⑩ For Battery Authentication; FlexiHash ™对于电池认证
| 型号： | ISL6296DRZ-T |
| 厂家： | 
Intersil |
| 描述： | FlexiHash⑩ For Battery Authentication |
| 文件： | 总19页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6296
®
eet
January 17, 2007
FN9201.1
FlexiHash™ For Battery Authentication
Features
The ISL6296 is a highly cost-effective fixed-secret hash
engine based on Intersil’s FlexiHash™ technology. The
device authentication is achieved through a challenge-
response scheme customized for low-cost applications,
where cloning via eavesdropping without knowledge of the
device’s secret code is not economically viable. When used
for its intended applications, the ISL6296 offers the same
level of effectiveness as other significantly more expensive
high maintenance monetary-grade hash algorithm and
authentication schemes.
• Challenge-response based authentication scheme using
32-Bit challenge code and 8-Bit authentication code.
• Fast and flexible authentication process. Multi-pass
authentication can be used to achieve the highest security
level if necessary.
• 16x8 OTP ROM stores up to three sets of 32-Bit host-
selectable secrets with additional programmable memory
for storage of up to 48 bits of ID code and/or pack
information.
• FlexiHash engine uses two sets of 32-Bit secrets for
authentication code generation.
The ISL6296 has a wide operating voltage range, and is
suitable for direct powering from a 1-cell Li-Ion/Li-Poly or a
3-cell series NiMH battery pack. The ISL6296 can also be
powered by the XSD bus when the bus pull-up voltage is
3.3V or higher. The device connects directly to the cell
terminals of a battery pack, and includes on-chip voltage
regulation circuit, POR, and a non-crystal based oscillator for
bus timing reference.
• Non-unique mapping of the secret key to an 8-Bit
authentication code maximizes hacking difficulty due to
need for exhaustive key search (superior to SHA-1).
• Supports 1-cell Li-Ion/Li-Poly and 3-cell series NiMH
battery packs (2.6V ~ 4.8V operation), or powered by the
XSD bus.
Communication with the host is achieved through a single-
wire XSD interface - a light-weight subset of Intersil’s ISD bus
interface. The XSD bus is compatible for use with serial ports
offered by all 8250 compatible UART’s or a single GPIO
(general purpose input and output) pin of a microprocessor.
• XSD single-wire host bus interface communicates with all
8250-compatible UART’s or a single GPIO. Supports CRC
on read data and transfer bit-rate up to 23kbps.
• True “Zero Power” Sleep mode - automatically entered
after a bus inactivity time-out period
A clone prevention solution utilizing the ISL6296 offers
safety and revenue protection at the lowest cost and power,
and is suitable for protection against after-market
• 5 Ld SOT-23 and 8 Ld TDFN (2mm x 3mm) packages
• -20°C to +85°C operating temperature range
• Pb-free plus anneal available (RoHS compliant)
replacement for a wide variety of low-cost applications.
Pinouts
ISL6296
Applications
(5 LD SOT-23)
TOP VIEW
• Battery Pack Authentication
• Printer Cartridges
VSS
N/C
1
2
3
5
4
XSD
TIO
• Add-on Accessories
• Other Non-Monetary Authentication Applications
VDD
Related Literature
• Application Note AN1165 “ISL6296 Evaluation Kit”
ISL6296
• Application Note AN1166 “FlexiHash™ Engine Algorithm”
(8 LD 2X3TDFN)
TOP VIEW
• Application Note AN1167 “Implementing XSD Host Using
a GPIO”
VSS
XSD
1
2
3
4
8
7
6
5
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)
NC
NC
NC
NC
TIO
VDD
”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved.
1
FlexiHash is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
ISL6296
Ordering Information
PART
NUMBER
(Note)
TEMP.
RANGE
(°C)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6296DHZ-T 296Z
ISL6296DRZ-T 96Z
-20 to +85 5 Ld SOT-23 Tape and Reel
P5.064
-20 to +85 8 Ld 2x3 TDFN Tape and Reel L8.2X3A
ISL6296EVAL1 ISL6296 Evaluation Kit
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN9201.1
January 17, 2007
2
ISL6296
Absolute Maximum Ratings (Reference to GND)
Thermal Information
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to VDD+0.5V
ESD Rating
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°C/W)
N/A
10.5
JA
JC
SOT-23 Package (Note 1) . . . . . . . . . .
2x3 TDFN Package (Notes 2, 3) . . . . .
200
70
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .4000V
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .400V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000V
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range. . . . . . . . . .-40°C to +125°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-20°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: T = -20°C to +85°C; V
= 2.6V to 4.8V.
A
DD
PARAMETER
DC CHARACTERISTICS
Supply Voltage
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
During normal operation
During OTP ROM programming
2.6
2.8
-
-
4.8
4.8
140
160
0.5
500
2.7
13
V
V
DD
DD
-
Run Mode Supply Current
(exclude I/O current)
I
V
V
V
= 4.2V
110
120
0.15
250
2.5
12
μA
μA
μA
μA
V
DD
DD
DD
= 4.8V
-
Sleep Mode Supply Current
OTP Programming Mode Supply Current
Internal Regulated Supply Voltage
Internal OTP ROM Programming Voltage
POR Release Threshold
I
I
= 4.2V, XSD pin floating
-
DDS
DDP
For ~ 1.8ms duration per write operation
Observable only in test mode
-
V
2.3
11
1.9
1.5
RG
V
Observable only in test mode
V
PP
V
2.2
1.8
2.4
2.1
V
POR+
POR Assertion Threshold
V
V
POR-
XSD PIN CHARACTERISTICS
XSD Input Low Voltage
V
-0.4
1.5
-
-
0.5
V
V
IL
XSD Input High Voltage
V
V
+
DD
IH
0.4V
XSD Input Hysteresis
V
-
-
-
-
-
-
-
-
400
0.8
1.2
1.8
-
-
mV
μA
μA
μA
V
HYS
XSD Internal Pull-Down Current
I
V
V
V
= 2.6V
= 4.2V
= 4.8V
-
PD
DD
DD
DD
2.0
2.5
0.4
2
XSD Output Low Voltage
XSD Input Transition Time
XSD Output Fall Time
XSD Pin Capacitance
V
I
= 1mA
OL
OL
10% to 90% transition time
90% to 10%, C = 12pF
t
-
μs
ns
pF
X
t
-
50
-
F
LOAD
C
6
PIN
XSD BUS TIMING CHARACTERISTICS (Refer to XSD Bus Symbol Timing Definitions Tables)
Programming Bit Rate
x = 0.5 to 4
2.89
7
-
-
23.12
20
kHz
XSD Input Deglitch Time
T
Pulse width narrower than the deglitch time will not
cause the device to wake up
μs
WDG
FN9201.1
January 17, 2007
3
ISL6296
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: T = -20°C to +85°C; V
= 2.6V to 4.8V. (Continued)
A
DD
PARAMETER
Device Wake-Up Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
T
From falling-edge of break command issued by host to
falling-edge of break command returned by device
35
60
100
μs
WKE
Device Sleep Wait Time
Auto-Sleep Time-Out Period
OTP ROM Write Time
Hash Calculation Time
Soft-Reset Time
T
From when the ‘11’ Opcode is detected to the shut-off
of the internal regulator
4
0.9
-
-
-
μs
s
SLP
T
From the last transition detected on the XSD bus to the
device going into sleep mode
-
1.1
1.9
-
ASLP
T
From the last BT of the 2nd write data frame to when
device is ready to accept the next instruction
1.8
1
ms
BT
μs
EEW
T
From the last BT of the Challenge Code Word from the
host to the Authentication Code being available for read
-
HASH
T
From the last BT of the Soft-Reset instruction issued by
the host to the falling-edge of break command returned
by device
-
-
30
SRST
AC CHARACTERISTICS
Oscillator Clock Frequency
Charge Pump Clock Frequency
f
Internal bus reference clock
Internal high speed clock (observable only in test mode)
Low-speed mode
505
532
560
kHz
OSC
f
CP
3.6
16
5
6
MHz
MHz
High-speed mode
20
24
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
2
3
4
5
VSS
System ground.
No connection.
Supply voltage.
NC
VDD
TIO
Production test I/O pin. Used only during production testing. Must be left floating during normal operation.
XSD
Communication bus with weak internal pull-down to VSS. This pin is a Schmitt-trigger input and an open-drain
output. An appropriate pull-up resistor is required on the host side.
FN9201.1
January 17, 2007
4
ISL6296
Typical Applications
PACK+
R
100Ω
2
R
100Ω
1
XSD
VDD
ISL9269
VSS
PROTECTION
XSD
C
1
D
5.1V
1
0.1µF
PACK-
FIGURE 1. TYPICAL APPLICATION WITH THE ISL6296 POWERED BY THE BATTERY
PACK+
R
1
100Ω
XSD
VDD
ISL9269
VSS
PROTECTION
XSD
C
0.1µF
1
D
1
5.1V
PACK-
FIGURE 2. TYPICAL APPLICATION WITH THE ISL6296 POWERED BY THE XSD BUS
Block Diagram
VDD
POR/2.5V
OSCILLATOR
REGULATOR
ANALOG
DIGITAL
DCFG (1 BYTE)
DTRM (1 BYTE)
XSD
COMM
XSD
INTERFACE
SECRET #1
(4 BYTES)
SECRET #2
(4 BYTES)
AUTH
SESL
CHLG
SECRET #3
(4 BYTES)
GENERAL PURPOSE
(2 BYTES)
TM
16 BYTES
OTPROM
FLEXIHASH+
ENGINE
CONTROL/STATUS/
TEST INTERFACE
MSCR
STAT
TIO
VSS
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN9201.1
January 17, 2007
5
ISL6296
Theory of Operation
60µs
TYP
HOST BREAK
The ISL6296 contains all circuitry required to support battery
pack authentication based on a challenge-response
scheme. It provides a 16-Byte One-Time Programmable
Read-Only Memory (OTPROM) space for the storage of up
to 96-Bit of secret for the authentication and other user
information. A 32-Bit CRC-based hash engine (FlexiHash™)
calculates the authentication result immediately after
receiving a 32-Bit random challenge code. The
communication between the ISL6296 and the host is
implemented through the XSD single-wire communication
bus.
1.391
DEVICE BREAK
BT
D
XSD BUS
WAVEFORM
(A) WHEN THE HOST POWER-ON BREAK IS WIDER THAN 60µs.
HOST BREAK
DEVICE BREAK
XSD BUS
WAVEFORM
Major functions within the ISL6296 include the following, as
shown in Figure 3.
(B) WHEN THE HOST POWER-ON BREAK IS NARROWER THAN 60µs.
• Power-on reset (POR) and a 2.5V regulator to power all
internal logic circuits.
FIGURE 4. POWER-ON BREAK SIGNAL TO WAKE-UP THE
ISL6296 FROM SLEEP MODE
• 16 x 8-Bit (16-Byte) OTP ROM as shown in Table 8. The
first part (two bytes) contains the device default
Note that the ISL6296 will initiate the power-on sequence
without waiting for the power-on ‘break’ signal to return to
the high state. If the host sends an initial ‘break’ pulse wider
than 60μs, the device-ready ‘break’ returned by the ISL6296
will likely be merged with the pulse sent by the host and,
therefore, may not be detectable. Figure 4 illustrates the
waveforms during the Power-on Reset. Figure 4 (A)
represents the case when the power-on ‘break’ rising edge
occurs after the device starts sending the ‘break’.
Figure 4 (B) represents the case when the power-on ‘break’
finishes before the device sends its ‘break’. The device
break signal is always 1.391 times of the device bit-time (BT,
see XSD Bus Interface section for more details). Either case
in Figure 4 will wake up the device successfully if the device
is in the sleep mode.
configuration (DCFG) information (such as the device
address and the XSD communication speed) and the
default trimming (DTRM) information (such as the internal
oscillator frequency trimming). The second part contains
two groups (12-Byte) of memory that can be
independently locked out for the storage of up to three
sets of secret. The last part provides two additional bytes
of space for general-purpose information.
• Control functions, including master control (MSCR) and
status (STAT) registers (as shown in Table 9), interrupt
generation, and the test-related interface.
• FlexiHash™ engine that includes the 32-Bit CRC-based
hash engine, secret selection register, challenge code
register, and the authentication result register. Table 10
shows all the registers.
• XSD communication bus Interface. The XSD device
address and the communication speed are configured in
the DCFG address in the OTPROM, as given in Table 8.
It is important to keep in mind that a narrow ‘break’ signal will
be taken as a normal bit signal and cause errors, if the
device is not in the sleep mode. For this reason, the narrow
power-on ‘break’ signal should be used only if the user has
to see the returned ‘break’ signal.
• Time Base Reference.
The following explain in detail the operation of the ISL6296.
Auto-Sleep
Power-On Reset (POR)
While the ISL6296 is powered up and there is no bus activity
for more than about 1 second, the device will automatically
return to Sleep mode. Sleep mode can be entered
independent of whether the XSD bus is held high or low.
While the ISL6296 is in Sleep mode, it is recommended that
the XSD bus be held low to eliminate current drain through
the XSD-pin internal pull-down current.
The ISL6296 powers up in Sleep mode. It remains in Sleep
mode until a power-on ‘break’ command is received from the
host through the XSD bus. The initial power-on ’break’ can
be of any pulse width as long as it is wider than the XSD
input deglitch time (20μs). Once the ‘break’ command is
received, the internal regulator is powered up. About 20μs
after the falling edge of the power-on ‘break’, an internal
POR circuit releases the reset to the digital block, and a
POR sequence is started. During the POR sequence, the
ISL6296 initializes itself by loading the default device
configuration information from pre-assigned locations within
the OTP ROM memory. After initialization, a ‘break’
Auto-Sleep mode can be disabled by clearing the ASLP bit
in the MSCR register. By default, Auto-Sleep is always
enabled at power-up and after a soft reset. Auto-sleep
function can be permanently disabled by clearing the 0-00[2]
bit (the ASLP bit in DCFG) during OTP ROM programming.
command is returned to the host to indicate that the ISL6296
is ready and waiting for a bus transaction from the host.
FN9201.1
January 17, 2007
6
ISL6296
(STAT) registers. Functions that are configured by OTP
OTP ROM
ROM settings include:
The 16-Byte OTP ROM memory is based on EEPROM
technology and is incorporated into the ISL6296 for storage
of non-volatile information. OTP ROM contents (refer to
Table 8) can include but not limited to:
a) device address (DAB[1:0])
b) XSD bus speed (SPD[1:0])
c) register default settings (eINT and ASLP)
d) ROM read/write lock-out (SLO[1:0])
1) Device default settings (address 0-00)
2) Factory programmed trim parameters (address 0-01)
3) Device authentication secrets (address 0-02 to 0-0D)
4) Pack information and ID (address 0-0E and 0-0F)
The ISL6296 incorporates interrupt functions to allow the
host to be quickly informed of device status and error
conditions. Available interrupts are summarized in Table 1.
When an interrupt enable bit is set, a ’break’ command is
sent to the host whenever its corresponding interrupt status
bit is set. After this, the host should read the STAT register
immediately. If the following instruction frame from the host
does not access the STAT register, another ‘break’ will be
sent immediately after receiving the full instruction frame.
This process is repeated until the host reads from the STAT
register. Upon reading of the STAT register, all status bits will
be cleared.
The memory can be written multiple times before two lock-
out bits (SLO[1:0] in DCFG, see Table 8) being set. The
SLO[1] (bit 1) locks out the memory between 0-02 and 0-09
and the SLO[0] (bit 0) locks out the memory between 0-0A to
0-0D. These two bits can be set independently. Prior to lock-
out, the memory can be written and read directly through the
XSD bus interface. After lock-out, writing to all ROM
addresses and reading from secret code locations will be
permanently disabled after performing a reset cycle.
Refer to the MSCR and STAT register descriptions for
detailed explanation of the interrupt functions.
Writing to the EEPROM requires the supply voltage at the VDD
pin be maintained at a minimum of 2.8V. Failure to do so may
result in unreliable ROM programming or total write failure.
FlexiHash™ Engine
The FlexiHash™ engine contains a 32-Bit CRC-based hash
engine and three registers. Table 10 lists the three registers.
The 1-Byte secret selection (SESL) register select two sets
of secret (32-Bit each) from the OTP ROM to program the
hash engine. The 4-Byte challenge code register (CHLG)
receives the challenge code from the host through the XSD
bus. Once the challenge code is received, the hash engine
generates a 1-Byte authentication result code and stores in
the AUTH register for the host to read. Figure 5 shows the
data flow of the authentication process. The following
sections describe the authentication process and
The OTP ROM must be written two bytes at a time, but 2, 4
or 16-Bytes of data can be read by the host in a single bus
transaction. Only even addresses are allowed in OTP ROM
read/write. A 16-Byte read with CRC allows the entire ROM
content to be quickly verified by simply checking the CRC
byte. The DTRM address stores the default trimming
parameters and is a read-only address. The DCFG and
DTRM (0-00 and 0-01 addresses) need be written
simultaneously but the data to the DRTM address is ignored.
The OTP ROM writing process takes approximately 1.8ms
per two-Byte. While the write process is taking place, no bus
transaction is allowed. Attempt to access the ISL6296 during
an on-going write process will result in the device ignoring
the access instruction and issuing an interrupt to the host.
The OTP ROM programming is register-based, and may be
performed at the pack manufacturer’s facility.
FlexiHash™ encoding scheme in detail.
THE DEVICE AUTHENTICATION PROCESS
To start an authentication process, the host sends a ‘break’
command to wake up the ISL6296. Then host writes to the
SESL register to select the two sets of secrets to be used for
authentication code generation. After that, the host
Device Control and Status
generates a pseudo-random 4-Byte challenge code to input
into the CHLG register to initiate the authentication process.
Upon receiving the fourth byte of the challenge code, the
ISL6296 immediately starts computing the authentication
code. Once the computation is completed, the 8-Bit
authentication code is made available at the AUTH register
for the host to read out. The host reads this code and,
concurrently, calculates the correct authentication code
based on the challenge code it generated and the same
secrets chosen, and finally compares the result with the
authentication code read from the device. If the codes do not
match up, the device is a fake device and the host may shut
itself down. The flow chart in Figure 6 summarizes the above
process that the host needs to execute.
The ISL6296 has a control and a status register. The control
register can be read and written by the host but the status
register is read only. Both registers contain the device
configuration information (see Table 9). The status register
also contains the device status information that may lead to
an interrupt signal to the host.
Following a host-initiated power-on ‘break’ signal or soft
reset command, the ISL6296 will configure its default mode
of operation based on information stored within DCFG
address of the OTP ROM. The default configuration is
loaded into the master control (MSCR) and the status
FN9201.1
January 17, 2007
7
ISL6296
START
32-bit pseudo-random
challenge word from host
WAKE UP ISL6296 USING A
64-bit Secret
REGULAR BREAK SIGNAL
32-bit Hash Function
FlexiHash
Engine
SELECT HASH FUNCTION AND SEED
BY WRITING TO SESL REGISTER
32-bit Hash Seed
SEND A 32-BIT RANDOM
CHALLENGE TO CHLG REGISTER
8-bit authentication
code
READ THE AUTHENTICATION
RESULT FROM AUTH REGISTER,
FIGURE 5. AUTHENTICATION PROCESS FLOW DIAGRAM
AFTER WAITING FOR 1 BT
D
It is recommended that device authentication be done once
in a while to maximize its effectiveness. Before a new
challenge code can be accepted by the device, the SESL
register must be re-written again to ensure that the original
seeds are re-loaded from the OTP ROM into the hash
engine prior to performing the next authentication code
CALCULATE THE EXPECTED
AUTHENTICATION RESULT
BASED ON THE SAME SECRETS
NO
calculation. Failure to follow the sequence will result is a bus
error, causing the sBER flag to be set in the STAT register.
THE TWO RESULTS MATCH?
YES
SET-UP FOR DEVICE AUTHENTICATION SUPPORT
SHUT DOWN
THE SYSTEM
To configure the host and the ISL6296 to support device
authentication function, the pack manufacturer will need to
select at least 2 sets of 32-Bit secret codes. For greater
security, a third set of 32-Bit secret may be used. The
FlexiHash™ engine requires two sets of 32-Bit secrets for
use in its hash calculation: the first set to define its hash
function, and the second set to initialize its seed for hash
calculation. These two sets can be selected from the same
secret location. The chosen secret codes are to be kept by
the pack manufacturer and maintained at utmost
confidentiality.
END
FIGURE 6. FLOW CHART FOR AUTHENTICATION PROCESS
THE HASH ENGINE
The hash engine consists of 4 separate programmable 8-Bit
CRC calculators. Two sets of 32-Bit secret codes are use by
the hash engine for authentication code generation. The first
set is used to define the CRC polynomial as well as the input
selection for each of the CRC calculators. The second is
used as initial seeds for the CRC calculations. Outputs of the
4 CRC calculators are logically combined to produce the
8-Bit output of the overall FlexiHash™ engine. Block
diagram of the FlexiHash engine is illustrated in Figure 7.
More detailed description on the hash engine can be found
in the application note AN1166.
After the secrets have been determined, they are written into
the device’s OTP ROM. After verification that the codes have
been written in correctly, the relevant secrets lock-out bits at
ROM address location 0-00 should be set. Once set, the
lock-out bits can no longer be cleared. Thereafter, read/write
access to the secret information will no longer be possible,
and the secret codes are made available only to the
FlexiHash™ engine for generation of authentication code
based on a challenge code input from the host.
On the host side, the same secret codes will need to be kept,
and the same FlexiHash™ engine will have to be
implemented in firmware. Refer to the application note
AN1166 for detailed information of firmware implementation.
It is important that the secret codes be stored scrambled in
the host’s non-volatile memory so that the secret information
cannot be easily revealed by monitoring signal transfer on
the host PCB.
FN9201.1
January 17, 2007
8
ISL6296
NA[7:0]
8
Xi
Bn
Cn
8-bit CRC Calculator
An
Dn
8
XA[7:0]
Polynom = 1 + XMA[2:0] - XMA[5:3] + X8
MA[7:6]
MB[7:6]
MC[7:6]
MD[7:6]
NB[7:0]
8
An
Xi
Cn
Dn
8-bit CRC Calculator
Bn
8
XB[7:0]
Polynom = 1 + XMB[2:0] - XMB[5:3] + X8
NC[7:0]
8
An
Bn
Xi
Cn
8-bit CRC Calculator
Dn
8
XC[7:0]
Polynom = 1 + XMC[2:0] - XMC[5:3] + X8
ND[7:0]
8
An
Bn
Cn
Dn
8-bit CRC Calculator
Xi
8
XD[7:0]
Polynom = 1 + XMD[2:0] - XMD[5:3] + X8
Y[7:0] = XA[7:0] ⊕ S2R{XB[7:0]} ⊕ S4R{XC[7:0]} ⊕ S6R{XD[7:0]}
Legend:
Xi
32-bit Challenge Code Word serial bit-stream
CRC calculator serial outputs
An,Bn,Cn,Dn
XA,XB,XC,XD
MA,MB,MC,MD
NA,NB,NC,ND
SnR{ }
CRC calculator 8-bit parallel outputs
CRC polynomial and input selection codes
CRC register initialization seeds
n-bit cyclical right shift function
Y[7:0]
8-bit Authentication Code output
FIGURE 7. BLOCK DIAGRAM OF THE FLEXIHASH ENGINE
FN9201.1
January 17, 2007
9
ISL6296
place with the LSB first. The following explains the bus
XSD Host Bus Interface
symbols and the transaction frames are introduced in later
sections.
Communication with the host is achieved through XSD, a
light-weight subset of Intersil’s ISD single-wire bus interface.
XSD is a programmable-rate pseudo-synchronous
BUS SIGNALING SYMBOLS
bidirectional host-initiated instruction-based serial
The XSD bus is nominally held high. Various bus symbols
and commands are generated by active-low pulse width
modulation. Following are the set of valid bus signaling
symbols supported by the XSD interface:
communication interface that allows up to two slave devices
to be attached and addressed separately. It includes
features to enable quick and reliable communication. The
communication protocol is optimized for efficient transfer of
data between the device and the host. The list below
outlines the features supported by the XSD bus interface:
1) break (issued by host):
• used to wake the device up from Sleep mode (Note: a
narrow ‘break’ can also be used to wake up the device
from the Sleep mode, as described in the Power-on Reset
section)
• Programmable bit rate up to 23kbps
• Up to 2 devices can be connected to the host and
addressed separately
• used to reset the device’s XSD bit counters and time
qualifiers
• 16-Bit host instruction frame supports multi-Byte register
read and write
• used to signal a change in communication channel (from
one slave device to another)
• Built-in communication error detection
• CRC generation capability
2) break (issued by device):
• used as ‘device-ready’ indication to the host (after a
Soft-reset or wake up from Sleep mode)
• Supports interrupt signaling
• Integrated bus inactivity detector for automatic activation
of sleep mode
• used as an interrupt indicator
3) ‘1’ symbol:
XSD BUS PHYSICAL MODEL
• used for instruction and data coding
The physical model of the XSD bus is shown in Figure 8.
The model shows a single-wire connection between the host
and the device, not including the ground signal. The input
logic on the device side is designed to be compatible with
any voltage between 1.8V to 5.0V. The host interface should
contain an open-drain or open-collector output. The pull-up
4) ‘0’ symbol:
• used for instruction and data coding
SYMBOL TIMING DEFINITIONS
Symbol timings are defined in terms of bit-time (BT),
determined by the selected bus transfer bit-rate pre-
programmed into the device’s OTP ROM location 0-00[5:4].
Selectable bus speeds are: 2.89kHz (x = 0.5), 5.78kHz
(x = 1), 11.56kHz (x = 2) and 23.12kHz (x = 4).
resister R
can be connected either to the host supply
PU
voltage V
or the device supply voltage V
. Typically
DDH
DDD
the host supply voltage should be used for pull-up.
DATA TRANSFER PROTOCOL
To initiate a transaction, the host first sends a 16-Bit
instruction frame to the device, followed by data byte
frame(s) if the instruction is a write operation. The instruction
frame consists of a chip-select code, operation code,
register bank and address pointer, and number of data bytes
information, as shown in Figure 10. If the instruction is a
read operation, the device will return 1 to 17 byte frames of
data back to the host. The serial data transfer always takes
An instruction or data frame consists of a sequence of ‘1’
and/or ‘0’ symbols. Figure 9 illustrates the timing definitions.
A ‘1’ symbol is nominally 0.3 BT wide while a ‘0’ symbol is
nominally 0.7 BT wide. One ‘1’ or ‘0’ symbol is represented
in each BT period. Any detected pulse width less than 0.124
BT wide will be interpreted as a glitch and will result in a bus
error. Tables 2 and 3 summarize the timing definitions of all
the supported symbols and bus signaling.
TABLE 1. INTERRUPT EVENT SUMMARY
INTERRUPT
INTERRUPT
ENABLE BIT STATUS FLAG
CONDITION
INTERRUPT EVENT
OTP ROM Write-in-Progress
eEEW
(fixed)
sEEW
sBER
sACC
Accessing the ISL6296 during an on-going ROM write process (used only
during initial OTP ROM programming).
XSD Bus Error
eINT
XSD bus error or invalid instruction frame detected. Improper authentication
sequence detected.
Register Access Error
eINT
Accessing protected registers.
FN9201.1
January 17, 2007
10
ISL6296
VDDH
VDDD
DEVICE
HOST
TX
ESD
Diode
RPU
Open-Drain
Port Pin
RX
TX
1.5μA 6pF
ESD
Diode
RX
FIGURE 8. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS
tb
t0
t1
tg
XSD
glitch
1
0
Break
BT
FIGURE 9. THE BUS SIGNAL TIMING DIAGRAM
TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING
PARAMETER
Bit Time
SYM
BT
DESCRIPTION
MIN
TYP
MAX
UNIT
x = 0.5, 1, 2, or 4
173.6/x
μs
H
Deglitch period
‘1’ pulse width
‘0’ pulse width
‘break’ time
tg
PW (Pulse Width) less than this will result in a frame error
PW in this range will be interpreted as a ‘1’ code
PW in this range will be interpreted as a ‘0’ code
PW in this range will be interpreted as a ‘break’ command
0.124
0.453
0.824
100
BT
BT
BT
BT
H
H
H
H
t1
0.227
0.591
1
H
H
H
t0
tb
NOTE: Unless otherwise stated, all pulse width (PW) referenced are with respect to an active-low pulse.
TABLE 3. DEVICE TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING
PARAMETER
Bit Time
SYM
BT
DESCRIPTION
MIN
TYP
172.8/x
0.304
0.696
1.391
MAX
UNIT
x = 0.5, 1, 2, or 4
164.2/x
181.4/x
μs
D
‘1’ pulse width
‘0’ pulse width
‘break’ time
t1
t0
tb
‘1’ code transmit pulse width
BT
BT
BT
D
D
D
D
‘0’ code transmit pulse width
D
D
PW in this range will be interpreted as a ‘break’ command
FN9201.1
January 17, 2007
11
ISL6296
15
0
BYTES
ADDRESS
BANK OPCODE CS
FIGURE 10. THE 16-BIT INSTRUCTION FRAME FIELD DEFINITION
TABLE 4. DEFINITION OF THE OPCODE FIELD
OPCODE
DESCRIPTION
Write Operation
Read Operation (normal)
Read Operation (with CRC) Read from device register. Append 1-Byte CRC to the end of the last read frame.
ACTION
00
01
10
11
Write to device register
Read from device register
Sleep Mode Activation
Immediately sets the device in Sleep mode.
Note: After detecting the ‘11’ Opcode, the device immediately enters sleep mode. If more than 3
bits sent, subsequent pulses may wake the device up again.
Access Instruction Frame
TABLE 5. BANK FIELD DEFINITION.
The XSD access instruction frame is shown in Figure 10.
The instruction frame consists of 16 bits of digital signal with
the contents described as following.
BANK
00
MEMORY/REGISTER BANK SELECTION
OTP ROM
01
Control and Status Registers
Device Authentication Registers
Test Registers (Reserved)
CS FIELD
10
The CS field is a 1-Bit Chip Address Selection. An initial
1-Bit Chip Address code of ‘0’ is pre-programmed into the
device’s OTP ROM address location 0-00[7:6] at the time of
chip manufacture, and may be re-programmed by the pack
manufacturer if needed. If the CS code in the instruction
does not match the device’s Chip Address code, the
instruction, and any subsequent frames that follow, will be
ignored until a break command is received.
11
ADDRESS FIELD
The address field indicates the starting address of a memory
or register read or write sequence. Keep in mind that only odd
starting addresses are allowed for the OTP ROM access.
BYTES FIELD
OPCODE FIELD
The bytes field indicates the number of data bytes to read or
write, not including the CRC byte. Not all BYTES Field
settings are supported. Only settings marked with an ‘X’ is
valid for a particular bus instruction, as indicated in Table 6.
Attempt to read or write with an invalid BYTES setting may
yield unpredictable results.
The OPCODE is a 2-Bit field defines the operation of the
transaction following the instruction frame. The operations
are described in Table 4.
BANK FIELD
The memories in the ISL6296 are divided into four banks.
The BANK field is defined in Table 5.
Writing to OTP ROM can occur at only two bytes at a time,
but reading from OTP ROM can happen at 2, 4 or 16 bytes
at a time. Writing to and reading from OTP ROM in any other
byte denomination will yield unpredictable result, and should
therefore be strictly prohibited.
TABLE 6. DEFINITION OF THE BYTES FIELD
DATA BYTES OTP ROM OTP ROM REG READ CHLG CODE
BYTES
FIELD
TO FOLLOW
WRITE
READ
OR WRITE
WRITE
COMMENTS
0
1
0
1
Invalid selection. Causes a bus error.
X
X
Must use 1-Byte read for clearing of the STAT register.
2
2
X
X
X
X
3
N/A
4
Invalid selection. Causes a bus error.
4
X
5 - 6
7
N/A
16
Invalid selection. Causes a bus error.
For reading from OTP ROM only (prior to lock-out).
FN9201.1
January 17, 2007
12
ISL6296
Passive CRC Support
Bus Transaction Protocol
The CRC feature only supports the read transaction in the
ISL6296. When the OPCODE in the instruction is ‘10’, an
8-bit CRC is automatically calculated for the data bytes
being transferred out. The CRC result is then appended after
the last data byte is read out.
The XSD bus for the ISL6296 defines three types of bus
transactions. Figure 11 shows the bus transaction protocol.
The blue color represents the signal sent by the host and the
green color stands for the signal sent by the device. Before
the transaction starts, the host should make sure that the
XSD device is not in the sleep mode. One method is to
always send a ‘break’ signal before starting the transaction,
as shown in Figure 11. If the device is not in the sleep mode,
the ‘break’ signal is not mandatory. The ‘break’ pulse width
may appear to be wider than what the host sends out
because of the reason explained in Figure 4. The symbols in
Figure 11 are explained in Table 7.
CRC is generated using the DOW CRC polynomial as
follows:
4
5
8
Polynom = 1 + X + X + X
The CRC generation algorithm is logically illustrated in
Figure 12. Prior to a new CRC calculation, the LFSR (linear
feedback shift register) is initialized to zero. The read data to
be transmitted out is concurrently shifted into the CRC
calculator. After the actual data is transmitted out, the final
content of the LFSR is the resulting CRC value. This value is
transmitted out after the read data, with LSB being
transmitted out first.
TABLE 7. SYMBOLS IN THE BUS TRANSACTION PROTOCOL
SYM
DESCRIPTION
Host inter-frame gap
MIN
TYP
MAX
IFG
IFG
0 BT
1 BT
800ms
H
D
H
H
Device inter-frame gap
Host turn-around time
Device turn-around time
1 BT
1 BT
D
D
TA
TA
800ms
H
D
(A) Multi-Byte Write Instruction.
break
IFG
IFG
H
H
TSD
Write Instruction Frame
Data Frame 1
Data Frame 2
(B) Multi-Byte Read Instruction.
break
IFG
TA
D
D
TSD
Read Instruction Frame
Data Frame 2
Data Frame 1
(output from slave)
(output from slave)
(C) Back-to-Back Transaction (Read Followed by Write).
Next Instruction
Frame
break
TA
TA
H
D
TSD
Read Instruction Frame
Data Frame
(output from slave)
FIGURE 11. XSD BUS TRANSACTION PROTOCOL. THE ‘BREAK’ SIGNAL IS OPTIONAL IF THE DEVICE IS AWAKE
Serial
Output
1st
2nd
3rd
4th
5th
6th
7th
8th
Stage
Stage
Stage
Stage
Stage
Stage
Stage
Stage
LSB
MSB
FIGURE 12. THE CRC CALCULATOR FOR THE PASSIVE CRC SUPPORT
FN9201.1
January 17, 2007
13
ISL6296
addressable registers are used nor implemented. Accessing
Analog Biasing Components and Clock
Generation
an unimplemented register will result in the access
instruction being ignored. A bus error indication may or may
not be flagged.
The analog section in the ISL6296 mainly includes the Time
Base Generator and the internal regulator for powering the
circuits in the ISL6296.
Bank 0 is dedicated for the OTP ROM. There are 16 memory
locations implemented in the array. Writing to the OTP ROM
has no immediate effect on the chip operation until a
Power-on Reset occurred, or a soft reset is issued. Table 8
describes the OTP ROM memory assignment. The default
factory setting for address [0:00] is given in Table 11.
TIME BASE GENERATOR
A time base generator is included on-chip to provide timing
reference for serial data encoding and decoding at the XSD
bus interface. This eliminates the need for an external
crystal. The time base oscillator is trimmed during
manufacturing to a nominal frequency of 532.5kHz. It has a
frequency tolerance better than 5% over operating supply
voltage and temperature range.
Bank 1 contains the Control and Status registers. Only 2
registers are implemented. Table 9 shows the register map
of the Bank 1 registers. Detailed description of register
settings is given in Table 14 and 15.
INTERNAL VOLTAGE REGULATOR
Bank 2 contains the Authentication registers. Only 3
registers are implemented. These registers are used during
the battery pack authentication process. Table 10 describes
the mapping of the Authentication registers.
The ISL6296 incorporates an internal voltage regulator that
maintains a nominal operating voltage of 2.5V within the
device. The regulator draws power directly from the VDD
input. No external component is required to regulate circuit
voltage. The regulator is shut off during Sleep mode.
Bank 3 is reserved for Intersil production testing only, and
will not be accessible during normal operation. Accessing
the Test and Trim Registers when not in test mode will result
in a bus error.
Memory/Operational Register Description
The ISL6296 memory and register structure is organized into
4 banks of 256 addressable locations. However, not all of the
TABLE 8. OTP ROM MEMORY MAP (BANK 0)
BIT 7 BIT 6 BIT 5 BIT 4
DAB[1:0] SPD[1:0]
HSF TIBB[2:0]
ADDRESS
0-00
NAME
DCFG
DTRM
SE1A
SE1B
SE1C
SE1D
SE2A
SE2B
SE2C
SE2D
SE3A
SE3B
SE3C
SE3D
INF1
DESCRIPTION
Default Configuration
Default Trimming
Auth Secret #1A
Auth Secret #1B
Auth Secret #1C
Auth Secret #1D
Auth Secret #2A
Auth Secret #2B
Auth Secret #2C
Auth Secret #2D
Auth Secret #3A
Auth Secret #3B
Auth Secret #3C
Auth Secret #3D
General Purpose
General Purpose
BIT3
BIT 2
BIT 1
BIT 0
eINT
ASLP
SLO[1:0]
0-01
TOSC[3:0]
0-02
S1A[7:0]
0-03
S1B[7:0]
S1C[7:0]
S1D[7:0]
S2A[7:0]
S2B[7:0]
S2C[7:0]
S2D[7:0]
S3A[7:0]
S3B[7:0]
S3C[7:0]
S3D[7:0]
0-04
0-05
0-06
0-07
0-08
0-09
0-0A
0-0B
0-0C
0-0D
0-0E
0-0F
General purpose non-volatile memory for storage of model ID, date code, and other
cell information
INF2
NOTE: Information stored in address 0-0E (INF1) and 0-0F (INF2) is for use by the host firmware only. Actual content depends on the host firmware
customization preference.
FN9201.1
January 17, 2007
14
ISL6296
TABLE 9. CONTROL AND STATUS REGISTERS (BANK 1)
ADDRESS
1-00
NAME
MSCR
STAT
DESCRIPTION
Master Control
Device Status
BIT 7
eEEW
sEEW
BIT 6
eINT
BIT 5
--
BIT 4
BIT3
BIT 2
BIT 1
BIT 0
--
--
--
--
ASLP
SRST
1-01
sBER
sACC
DAB[1:0]
SLO[1:0]
TABLE 10. AUTHENTICATION REGISTERS (BANK 2)
ADDRESS
2-00
NAME
SESL
CHLG
AUTH
DESCRIPTION
Secrets Selection
BIT 7
BIT 6
BIT 5
BIT 4
BIT3
BIT 2
BIT 1
BIT 0
--
--
--
--
CSL[1:0]
SSL[1:0]
2-01
Challenge Code Register
Authentication Code Register
CHLG[31:0]
AUTH[7:0]
2-05
TABLE 11. DEFAULT CONFIGURATION (DCFG) REGISTER SETTINGS
BIT
NAME
TYPE
DEFAULT
DESCRIPTION
7:6
DAB[1:0]
RW
00
Device Address Bit Setting:
00 : device responds only when CS field in instruction frame is’0’
01 : device responds to any CS field value in instruction frame
10 : device responds to any CS field value in instruction frame
11 : device responds only when CS field in instruction frame is ‘1’
5:4
SPD[1:0]
RW
01
XSD Bus Speed Setting: Configures the bit rate of the XSD bus interface.
00 : 0.5x (2.89kbps)
01 : 1x (5.78kbps)
10 : 2x (11.56kbps)
11 : 4x (23.12kbps)
3
2
eINT
ASLP
RW
RW
RW
1
1
Power-on default setting of eINT bit in the MSCR register.
Power-on default setting of ASLP bit in the MSCR register.
Secrets Lock-out Bits:
1:0
SLO[1:0]
00
Bit 1 : Read/Write lock-out bit for address locations 0-02 to 0-09 (Secret Set #1 & #2)
Bit 0 : Read/Write lock-out bit for address locations 0-0A to 0-0D (Secret Set #3)
NOTE: Once Bit 0 or Bit 1 is set, writing to the OTP ROM will permanently be disabled
(after a reset cycle).
TABLE 12. DEFAULT TRIMMING (DTRM) REGISTER SETTINGS
BIT
7
NAME
HSF
TYPE
DEFAULT
DESCRIPTION
R
R
R
0
--
--
Unused
6:4
3:0
TIBB[2:0]
TOSC[3:0]
Reference Current Trim Setting
Oscillator Frequency Trim Setting
ADDRESS 0-00: DEFAULT CONFIGURATION (DCFG)
TABLE 13. LEGEND FOR THE TYPE COLUMN
This address location stores the default configuration when
the ISL6296 is manufactured. Table 11 describes each bit in
detail. The legend for the TYPE column is given in Table 13.
TYPE
READ ACTION
Data read
WRITE ACTION
Data ignored
Data written
R
Read-only
Write-only
W
Zeros read
ADDRESS 0-01: DEFAULT TRIM SETTING (DTRM)
RW Read/Write
Data read
Data written
This address location is writable only when the device is in
test mode. During normal operation, any data written to it will
be ignored. Table 12 describes the DTRM address in detail.
RC Clear after read Data read, then
cleared
Data ignored
WC Clear after write Zeros read
Data written, then
cleard
ADDRESS 0-02/03/04/05: AUTHENTICATION SECRET
SET #1 (SE1A/B/C/D)
<> Default setting loaded from designated OTP ROM bit
locations
These address locations store the first set of secrets to be
used for hash calculation. Reading and writing to this
register can be disabled by setting the SLO[1] bit at OTP
ROM location 0-00[1].
W
Writing disabled after lock-out
FN9201.1
January 17, 2007
15
ISL6296
ADDRESS 0-06/07/08/09: AUTHENTICATION SECRET
SET #2 (SE2A/B/C/D)
ADDRESS 0-0A/0B/0C/0D: AUTHENTICATION SECRET
SET #3 (SE3A/B/C/D)
These address locations store the second set of secrets to
be used for hash calculation. Reading and writing to this
register can be disabled by setting the SLO[1] bit at OTP
ROM location 0-00[1].
These address locations store the optional third set of
secrets to be used for hash calculation. Reading and writing
to this register can be disabled by setting the SLO[0] bit at
OTP ROM location 0-00[0].
Alternately, this memory space can be used to store
additional cell information which can be accessed by the
host. In this case, the SLO[0] bit should not be set.
TABLE 14. MASTER CONTROL REGISTER (MSCR)
BIT
NAME
TYPE
DEFAULT
DESCRIPTION
7
eEEW
R
0
OTP ROM Write-in-Progress Interrupt Enable: When enabled, it allows the sEEW bit to flag an
interrupt whenever the sEEW bit is set by its interrupt event. The eEEW bit is fixed at ‘1’ when none
of the OTP ROM lock-out bits is set. When any or both of the lock-out bits are set, the eEEW bit will
become permanently ‘0’ after a reset.
<1/0>
6
eINT
RW
0
<1>
Global Interrupt Enable: When enabled, it allows the sBER or sACC bit to flag an interrupt to the
host whenever any of the respective interrupt event occurred.
(Default setting loaded from OTP ROM location 0-00[3])
5:2
1
--
R
0
Unused.
ASLP
RW
0
<1>
Auto Sleep Mode enable: When set, the ISL6296 will automatically enter Sleep mode after about
1s of XSD bus inactivity. When cleared, the device can only enter Sleep mode on Opcode
command.
(Default setting loaded from OTP ROM location 0-00[2])
0
SRST
WC
0
Soft Reset: When a ‘1’ is written, and all registers are reset to their default states, all bus counters
and timers are reset to their start-up conditions, and device configuration information is reloaded
from OTP ROM. After the reset sequence is completed, a ‘break’ pulse is sent to the host.
TABLE 15. DEVICE STATUS REGISTER (STAT)
DESCRIPTION
BIT
NAME
TYPE
DEFAULT
7
sEEW
RC
0
OTP ROM Write-in-Progress Flag: This bit is set when attempt is made by the host to read from or
write to the ISL6296 while the ROM is still processing the previous write instruction.
6
sBER
RC
0
XSD Bus Error Flag: This bit is set when one or more of the following occurred at the bus interface:
a) An invalid pulse width is received
b) Bus activity is detected before the device completes its power-up sequence
c) An invalid BYTES field in the instruction frame
d) Improper authentication sequence is detected
e) Reading secret information after the corresponding lock-out bits are set
5
sACC
RC
0
0
Register Access Error Flag: This bit is set whenever an instruction frame attempts to access a
protected register as follows:
a) Writing to OTP ROM after the ISL6296 has been locked out (any or both of the lock-out bits set)
b) Accessing the ISL6296ís Test and Trim Registers when the device is not in test mode
4
--
R
R
Unused
3:2
DAB[1:0]
00
Device Address Bit Setting:
<00>
Loaded from OTP ROM location 0-00[7:6] during power-up.
1:0
SLO[1:0]
R
00
Secrets Lock-out Bits Setting:
<00>
Loaded from OTP ROM location 0-00[1:0] during power-up.
FN9201.1
January 17, 2007
16
ISL6296
TABLE 16. SECRETS SELECTION REGISTER (SESL)
BIT
7:4
3:2
NAME
--
TYPE
R
DEFAULT
DESCRIPTION
0000
01
Unused
CSL[1:0]
RW
Coefficient Definition Secret Selection: Selects the authentication secret code word stored in
OTP ROM to be used as the coefficient definition code for the FlexiHash engine.
00: invalid selection
01: Authentication Secret Set #1
10: Authentication Secret Set #2
11: Authentication Secret Set #3
1:0
SSL[1:0]
RW
10
Seed Secret Selection: Selects the authentication secret code word stored in OTP ROM to be
used as the secret seed for the FlexiHash engine.
00: invalid selection
01: Authentication Secret Set #1
10: Authentication Secret Set #2
11: Authentication Secret Set #3
ADDRESS 0-0E/0F: GENERAL PURPOSE MEMORY
(INF1/2)
Applications Information
XSD Bus Implementation
These address locations can be used to store information
like model ID, date code, and other cell information which
can be read by the host.
There are two ways to implement the XSD host in a micro-
processor. One way is to use a spare UART (Universal
Asynchronous Receiver/Transmitter). A GPIO (general
purpose input/output) can be used if no UART is available
for the XSD communication. Refer to application note
AN1167 available from Intersil for more information
regarding how to implement the XSD bus within a
microprocessor.
ADDRESS 1-00: MASTER CONTROL REGISTER (MSCR)
The Master Control Register is defined in Table 14. The
MSCR register can be both read or written by the host
through the XSD bus.
ADDRESS 1-01: DEVICE STATUS REGISTER (STAT)
Pull Up Resistor Selection
The STAT register is defined in Table 15. All status bits will
be cleared upon a read to this register. The STAT is a read-
only register.
Since there is an internal pull-down current on the XSD pin,
as shown in Figure 8, it is important to choose a pull-up
resistor value that is low enough so that the small amount of
pull-down current through the resistor does not cause the
DDRESS 2-00: SECRETS SELECTION REGISTER (SESL)
This register must be written to re-load the hash engine with
secrets stored in OTP ROM prior to presenting a new
challenge code word input.
bus voltage to droop below the V specification under any
condition. 5kΩ is a typical resistance used for pull up.
IH
Powered by XSD Bus
ADDRESS 2-01: CHALLENGE CODE INPUT REGISTER
(CHLG)
In applications that the device supply voltage is lower than
2.6V (such as an application powered by a single-cell NiMH
battery), or a device that has no power source at all, the
ISL6296 can be powered by the XSD bus. The application
circuit is shown in Figure 2. The condition for such
This register is used to input the 32-Bit challenge code
generated by the host for device authentication. All four
bytes of the challenge code should be written sequentially to
this register, starting with the least-significant byte. After the
fourth challenge byte is received, the authentication code
generation process will start. This CHLG is a write-only
register.
application circuit to function properly is that the bus pull-up
voltage is 3.3V or 5V. The bus pull-up voltage will charge the
capacitor C through an internal ESD diode, as shown in
1
Figure 8. The ESD diode has 0.4V drop typically.
ADDRESS 2-05: AUTHENTICATION CODE OUTPUT
REGISTER (AUTH)
ESD Rating
The ISL6296 ESD specification is rated at 4kV of the human
body model. When the ISL6296 is used in a hand-held
accessory, higher ESD rating is typically required. External
components are required to enhance the ESD performance.
This register is used to output the 8-Bit authentication code
calculated from the 32-Bit challenge code. The register
content may be read only once after each challenge code
word is written to the device. Subsequent read to this
register without a new challenge being input will result in an
error condition.
Additional Application Information
See Related Literature referenced on the first page for
additional application information.
FN9201.1
January 17, 2007
17
ISL6296
Small Outline Transistor Plastic Packages (SOT23-5)
D
P5.064
VIEW C
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
e1
SYMBOL
MAX
0.057
0.0059
0.051
0.020
0.018
0.009
0.008
0.118
0.118
0.067
MIN
0.90
0.00
0.90
0.30
0.30
0.08
0.08
2.80
2.60
1.50
MAX
1.45
0.15
1.30
0.50
0.45
0.22
0.20
3.00
3.00
1.70
NOTES
5
1
4
A
A1
A2
b
0.036
0.000
0.036
0.012
0.012
0.003
0.003
0.111
0.103
0.060
-
-
-
-
E
C
L
C
E1
L
2
3
b
b1
c
e
6
6
3
-
C
L
α
c1
D
0.20 (0.008) M
C
C
C
L
E
E1
e
3
-
SEATING
PLANE
0.0374 Ref
0.0748 Ref
0.014 0.022
0.95 Ref
1.90 Ref
0.35 0.55
A2
A1
A
e1
L
-
-C-
4
L1
L2
N
0.024 Ref.
0.010 Ref.
5
0.60 Ref.
0.25 Ref.
5
0.10 (0.004)
C
5
b
WITH
R
0.004
-
0.10
-
PLATING
b1
R1
α
0.004
0.010
0.10
0.25
o
o
o
o
0
8
0
8
-
c
c1
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
GAUGE PLANE
SEATING
PLANE
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
L
C
α
L2
L1
4X θ1
VIEW C
FN9201.1
January 17, 2007
18
ISL962096
Thin Dual Flat No-Lead Plastic Package (TDFN)
2X
L8.2x3A
0.15
C A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
0.15
C B
SYMBOL
MIN
0.70
NOMINAL
MAX
0.80
NOTES
A
A1
A3
b
0.75
-
-
0.20
1.50
1.65
-
0.20 REF
0.25
0.05
-
E
-
6
INDEX
AREA
0.32
1.75
1.90
5,8
D
2.00 BSC
1.65
-
B
A
D2
E
7,8
TOP VIEW
3.00 BSC
1.80
-
// 0.10
0.08
C
E2
e
7,8
0.50 BSC
-
-
C
k
0.20
0.30
-
-
SIDE VIEW
A3
C
SEATING
PLANE
L
0.40
0.50
8
N
8
2
D2
D2/2
2
7
8
Nd
4
3
(DATUM B)
Rev. 0 6/04
NOTES:
1
NX k
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
3. Nd refers to the number of terminals on D.
(DATUM A)
E2
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
NX L
8
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
e
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10
M
C A B
(Nd-1)Xe
REF.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
(A1)
NX (b)
5
L
SECTION "C-C"
C C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9201.1
January 17, 2007
19
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