ISL6327IRZ-T_技术文档

ISL6327

®

Data Sheet

December 20, 2006

FN9276.2

Enhanced 6-Phase PWM Controller with

8-Bit VID Code and Differential Inductor

DCR or Resistor Current Sensing

Features

• Proprietary Active Pulse Positioning and Adaptive Phase

Alignment Modulation Scheme

The ISL6327 controls microprocessor core voltage regulation

by driving up to 6 synchronous-rectified buck channels in

parallel. Multiphase buck converter architecture uses

interleaved timing to multiply channel ripple frequency and

reduce input and output ripple currents. Lower ripple results in

fewer components, lower component cost, reduced power

dissipation, and smaller implementation area.

• Precision Multiphase Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over Life, Load, Line and

Temperature

- Adjustable Precision Reference-Voltage Offset

• Precision Resistor or DCR Current Sensing

- Accurate Load-Line Programming

- Accurate Channel-Current Balancing

- Differential Current Sense

Microprocessor loads can generate load transients with

extremely fast edge rates. The ISL6327 utilizes Intersil’s

proprietary Active Pulse Positioning (APP) and Adaptive

Phase Alignment (APA) modulation scheme to achieve the

extremely fast transient response with fewer output

capacitors.

• Microprocessor Voltage Identification Input

- Dynamic VID™ Technology

- 8-Bit VID Input with Selectable VR11 code and

Extended VR10 Code at 6.25mV Per Bit

Today’s microprocessors require a tightly regulated output

voltage position versus load current (droop). The ISL6327

senses the output current continuously by utilizing patented

techniques to measure the voltage across the dedicated

current sense resistor or the DCR of the output inductor.

Current sensing provides the needed signals for precision

droop, channel-current balancing, and overcurrent

protection. A programmable integrated temperature

compensation function is implemented to effectively

compensate the temperature variation of the current sense

element. The current limit function provides the overcurrent

protection for the individual phase.

- 0.5V to 1.600V Operation Range

• Thermal Monitoring

• Integrated Programmable Temperature Compensation

• Overcurrent Protection and Channel Current Limit

• Overvoltage Protection with OVP Output Indication

• 2, 3, 4, 5 or 6 Phase Operation

• Adjustable Switching Frequency up to 1MHz Per Phase

• Package Option

- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad

Flat No Leads - Product Outline

A unity gain, differential amplifier is provided for remote

voltage sensing. Any potential difference between remote

and local grounds can be completely eliminated using the

remote-sense amplifier. Eliminating ground differences

improves regulation and protection accuracy. The threshold-

sensitive enable input is available to accurately coordinate

the start up of the ISL6327 with any other voltage rail.

Dynamic-VID™ technology allows seamless on-the-fly VID

changes. The offset pin allows accurate voltage offset

settings that are independent of VID setting.

- QFN Near Chip Scale Package Footprint; Improves

PCB Efficiency, Thinner in Profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Ordering Information

PART

NUMBER

(Note)

PART

MARKING

TEMP.

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL6327CRZ ISL6327CRZ

0 to70 48 Ld 7x7 QFN L48.7x7

ISL6327IRZ ISL6327IRZ -40 to 85 48 Ld 7x7 QFN L48.7x7

Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6327

Pinout

ISL6327

(48 LD QFN)

TOP VIEW

48 47 46 45 44 43 42 41 40 39 38 37

1

2

36

35

34

33

32

31

30

29

28

27

26

25

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VRSEL

OFS

PWM3

ISEN3+

ISEN3-

ISEN1-

ISEN1+

PWM1

PWM4

ISEN4+

ISEN4-

ISEN2-

ISEN2+

PWM2

3

4

5

6

GND

7

8

9

10

11

12

IOUT

DAC

13 14 15 16 17 18 19 20 21 22 23 24

FN9276.2

December 20, 2006

2

ISL6327

ISL6327 Block Diagram

VDIFF VR_RDY

OVP

VCC

0.875V

RGND

VSEN

POWER-ON

x1

EN_VTT

RESET (POR)

OVP

R

S

DRIVE

Q

EN_PWR

FS

OVP

THREE-STATE

SOFT-START

AND

FAULT LOGIC

CLOCK AND

RAMP

GENERATOR

+175mV

APP and APA

MODULATOR

SS

PWM1

PWM2

APP and APA

MODULATOR

OFS

OFFSET

REF

DAC

APP and APA

MODULATOR

PWM3

PWM4

VRSEL

VID7

VID6

VID5

VID4

APP and APA

MODULATOR

APP and APA

MODULATOR

PWM5

PWM6

DYNAMIC

VID

VID3

VID2

VID1

VID0

D/A

E/A

APP and APA

MODULATOR

CHANNEL CURRENT

BALANCE AND

CURRENT LIMIT

CHANNEL

DETECT

COMP

FB

ISEN1+

ISEN1-

ISEN2+

2V

I_TRIP

OC2

OC1

ISEN2-

ISEN3+

ISEN3-

TEMPERATURE

COMPENSATION

CHANNEL

1

∑

N

CURRENT

SENSE

IOUT

ISEN4+

ISEN4-

ISEN5+

ISEN5-

ISEN6+

ISEN6-

I_TOT

IDROOP

TEMPERATURE

COMPENSATION

GAIN

THERMAL

MONITORING

GND

TM VR_FAN VR_HOT

TCOMP

FN9276.2

December 20, 2006

3

ISL6327

Typical Application - 6-Phase Buck Converter with DCR Sensing and External TCOMP

+5V

VIN

VCC

BOOT

UGATE

NTC2

PHASE

LGATE

ISL6609

DRIVER

EN

EXTERNAL TCOMP

COMPENSATION

NETWORK

PWM

GND

+5V

VIN

VCC

BOOT

+5V

UGATE

PHASE

LGATE

EN

ISL6609

DRIVER

FB

COMP

REF

DAC

PWM

GND

IDROOP

VDIFF

VSEN

VCC

GND

RGND

EN_VTT

+5V

VTT

VIN

VCC

BOOT

VR_RDY

VID7

ISL6327

UGATE

PWM6

VID6

ISEN6-

ISEN6+

PHASE

LGATE

ISL6609

DRIVER

EN

VID5

VID4

VID3

VID2

PWM

GND

PWM4

ISEN4-

ISEN4+

VID1

VID0

VRSEL

PWM2

ISEN2-

ISEN2+

+5V

VIN

VCC

BOOT

OVP

μP

LOAD

PWM1

ISEN1-

ISEN1+

UGATE

IOUT

PHASE

LGATE

EN

ISL6609

DRIVER

R

IOUT

PWM3

ISEN3-

ISEN3+

PWM

GND

VR_FAN

VR_HOT

PWM5

ISEN5-

ISEN5+

+5V

VIN

VCC

BOOT

TM

EN_PWR

UGATE

TCOMP

OFS FS

SS

+5V

PHASE

LGATE

EN

ISL6609

DRIVER

R

SS

VIN

OFS

T

PWM

GND

NTC

+5V

VIN

VCC

BOOT

UGATE

PHASE

LGATE

EN

ISL6609

DRIVER

PWM

GND

FN9276.2

December 20, 2006

4

ISL6327

Typical Application - 6-Phase Buck Converter with DCR Sensing and Integrated TCOMP

+5V

VIN

VCC

BOOT

UGATE

PHASE

LGATE

EN

ISL6609

DRIVER

PWM

GND

+5V

VIN

VCC

BOOT

+5V

UGATE

PHASE

LGATE

EN

ISL6609

DRIVER

FB

COMP

REF

DAC

PWM

GND

IDROOP

VDIFF

VSEN

VCC

GND

RGND

EN_VTT

+5V

VTT

VIN

VCC

BOOT

VR_RDY

VID7

ISL6327

UGATE

PWM6

VID6

ISEN6-

ISEN6+

PHASE

LGATE

EN

ISL6609

DRIVER

VID5

VID4

VID3

VID2

PWM

GND

PWM4

ISEN4-

ISEN4+

VID1

VID0

VRSEL

PWM2

ISEN2-

ISEN2+

+5V

VIN

VCC

BOOT

OVP

μP

LOAD

PWM1

ISEN1-

ISEN1+

UGATE

IOUT

PHASE

LGATE

R

EN

ISL6609

DRIVER

IOUT

PWM3

ISEN3-

ISEN3+

PWM

GND

VR_FAN

VR_HOT

PWM5

ISEN5-

ISEN5+

+5V

VIN

VCC

BOOT

TM

EN_PWR

UGATE

OFS FS

TCOMP

SS

+5V

PHASE

LGATE

EN

ISL6609

DRIVER

+5V

R

OFS

T

SS

VIN

PWM

GND

NTC

+5V

VIN

VCC

BOOT

UGATE

PHASE

LGATE

EN

ISL6609

DRIVER

PWM

GND

FN9276.2

December 20, 2006

5

ISL6327

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V

All Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V + 0.3V

Thermal Resistance (Typical, Notes 1, 2)

θ

(°C/W)

32

θ

(°C/W)

3.5

JA

JC

CC

QFN Package. . . . . . . . . . . . . . . . . . . .

ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV

ESD (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V

ESD (Charged Device Model) . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Ambient Temperature (ISL6327CRZ) . . . . . . . . . . . . . 0°C to +70°C

Ambient Temperature (ISL6327IRZ) . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational section of this specification is not implied.

+150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may trigger the shutdown of

the device even before +150°C, since this number is specified as typical.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified

PARAMETER

VCC SUPPLY CURRENT

Nominal Supply

TEST CONDITIONS

MIN

TYP MAX UNITS

VCC = 5VDC; EN_PWR = 5VDC; R = 100kΩ,

-

18

14

26

21

mA

T

ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = -70μA

Shutdown Supply

VCC = 5VDC; EN_PWR = 0VDC; R = 100kΩ

T

POWER-ON RESET AND ENABLE

POR Threshold

VCC Rising

VCC Falling

Rising

4.3

3.7

4.5

3.9

4.7

4.2

V

EN_PWR Threshold

EN_VTT Threshold

0.850 0.875 0.910

130

V

Hysteresis

Falling

-

mV

V

0.720 0.745 0.775

0.850 0.875 0.910

Rising

V

Hysteresis

Falling

-

130

-

mV

V

0.720 0.745 0.775

REFERENCE VOLTAGE AND DAC

System Accuracy of ISL6327CRZ

(VID = 1V-1.6V), T = 0°C to +70°C

J

(Note 3)

-0.5

-0.9

-0.6

-1

-

0.5

0.9

0.6

1

%VID

System Accuracy of ISL6327CRZ

(VID = 0.5V-1V), T = 0°C to +70°C

J

System Accuracy of ISL6327IRZ

(VID = 1V-1.6V), T = -40°C to +85°C

J

System Accuracy of ISL6327IRZ

(VID = 0.5V-1V), T = -40°C to +85°C

J

VID Pull-up

-60

-

-40

-20

0.4

-

μA

V

VID Input Low Level

VID Input High Level

VRSEL Input Low Level

VRSEL Input High Level

-

0.8

-

V

0.4

-

V

0.8

V

FN9276.2

December 20, 2006

6

ISL6327

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued)

PARAMETER

DAC Source Current

TEST CONDITIONS

MIN

-

TYP MAX UNITS

4

-

7

mA

μA

DAC Sink Current

-

300

55

REF Source Current

REF Sink Current

45

50

55

PIN-ADJUSTABLE OFFSET

Voltage at OFS Pin

Offset resistor connected to ground

Voltage below VCC, offset resistor connected to VCC

380

400

420

mV

V

1.55

1.60

1.65

OSCILLATORS

Accuracy of Switching Frequency Setting

R

= 100kΩ

225

0.08

-

250

275

1.0

-

kHz

MHz

T

Adjustment Range of Switching Frequency (Note 4)

Soft-Start Ramp Rate (Notes 5, 6) = 100kΩ

-

1.563

-

R

mV/μs

SS

Adjustment Range of Soft-Start Ramp Rate (Note 4)

PWM GENERATOR

0.625

6.25 mV/μs

Sawtooth Amplitude

-

1.25

-

V

ERROR AMPLIFIER

Open-Loop Gain

R

C

= 10kΩ to ground (Note 4)

-

96

80

25

4.3

-

dB

MHz

V/μs

V

L

Open-Loop Bandwidth

Slew Rate

= 100pF, R = 10kΩ to ground (Note 4)

L

= 100pF (Note 4)

-

Maximum Output Voltage

Output High Voltage @ 2mA

Output Low Voltage @ 2mA

REMOTE-SENSE AMPLIFIER

Bandwidth

3.8

3.6

-

4.9

-

V

-

1.8

V

(Note 4)

-

20

-

MHz

μA

Output High Current

VSEN - RGND = 2.5V

VSEN - RGND = 0.6V

-500

500

Output High Current

-

μA

PWM OUTPUT

PWM Output Voltage LOW Threshold

PWM Output Voltage HIGH Threshold

Iload = ±500μA

-

0.5

-

V

4.3

CURRENT SENSE AND OVERCURRENT PROTECTION

Sensed Current Tolerance

ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = 60μA

57

72

60

85

63

98

μA

V

Overcurrent Trip Level for Average Current

Peak Current Limit for Individual Channel

100

1.85

120

2.0

140

2.15

Maximum Voltage at IDROOP and IOUT

Pins

THERMAL MONITORING

TM Input Voltage for VR_FAN Trip

TM Input Voltage for VR_FAN Reset

TM Input Voltage for VR_HOT Trip

TM Input Voltage for VR_HOT Reset

Leakage Current of VR_HOT

1.55

1.85

1.3

1.55

-

1.65

1.95

1.4

1.65

-

1.75

2.05

1.5

V

1.75

30

V

With external pull-up resistor connected to VCC

μA

FN9276.2

December 20, 2006

7

ISL6327

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued)

PARAMETER

VR_HOT Low Voltage

TEST CONDITIONS

With 1.25kΩ resistor pull up to VCC, I

MIN

TYP MAX UNITS

= 4mA

-

0.4

30

V

μA

V

VR_HOT

With external pull-up resistor connected to VCC

With 1.25kΩ resistor pull up to Vcc, I = 4mA

Leakage Current of VR_FAN

VR_FAN Low Voltage

0.4

VR_FAN

VR READY AND PROTECTION MONITORS

Leakage Current of VR_RDY

With externally pull-up resistor connected to VCC

= 4mA

-

30

0.4

52

62

μA

V

VR_RDY Low Voltage

I

-

VR_RDY

Undervoltage Threshold

VR_RDY Reset Voltage

Overvoltage Protection Threshold

VDIFF Falling

48

58

50

60

%VID

V

VDIFF Rising

Before valid VID

1.250 1.275 1.300

After valid VID, the voltage above VID

150

175

100

-

200

-

mV

V

Overvoltage Protection Reset Hysteresis

OVP Output Low Voltage

NOTES:

-

IOVP = 4mA

0.4

3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

4. Spec guaranteed by design.

5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID input.

6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.

and the switching frequency will be described by an

approximate equation.

Functional Pin Description

VCC - Supplies the power necessary to operate the chip.

The controller starts to operate when the voltage on this pin

exceeds the rising POR threshold and shuts down when the

voltage on this pin drops below the falling POR threshold.

Connect this pin directly to a +5V supply.

SS - Use this pin to set up the desired start-up oscillator

frequency. A resistor, placed from SS to ground will set up

the soft-start ramp rate. The relationship between the value

of the resistor and the soft-start ramp up time will be

described by an approximate equation.

GND - Bias and reference ground for the IC. The bottom

metal base of ISL6327 is the GND.

VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0 -

These are the inputs to the internal DAC that generates the

reference voltage for output regulation. Connect these pins

either to open-drain outputs with or without external pull-up

resistors or to active-pull-up outputs. All VID pins have 40uA

internal pull-up current sources that diminish to zero as the

voltage rises above the logic-high level. These inputs can be

pulled up externally as high as VCC plus 0.3V.

EN_PWR - This pin is a threshold-sensitive enable input for

the controller. Connecting the 12V supply to EN_PWR

through an appropriate resistor divider provides a means to

synchronize power-up of the controller and the MOSFET

driver ICs. When EN_PWR is driven above 0.875V, the

ISL6327 is active depending on status of EN_VTT, the

internal POR, and pending fault states. Driving EN_PWR

below 0.745V will clear all fault states and prime the ISL6327

to soft-start when re-enabled.

VRSEL - VRSEL is the pin used to select the internal VID

code. When it is connected to GND, the extended VR10

code is selected. VRSEL pin has 40µA internal pull-up

current sources that diminish to zero as the voltage rises

above the logic-high level. When it’s floated or pulled to high,

VR11 code is selected. This input can be pulled up as high

as VCC plus 0.3V.

EN_VTT - This pin is another threshold-sensitive enable

input for the controller. It’s typically connected to VTT output

of VTT voltage regulator in the computer mother board.

When EN_VTT is driven above 0.875V, the ISL6327 is active

depending on status of ENLL, the internal POR, and pending

fault states. Driving EN_VTT below 0.745V will clear all fault

states and prime the ISL6327 to soft-start when re-enabled.

VDIFF, VSEN, and RGND - VSEN and RGND form the

precision differential remote-sense amplifier. This amplifier

converts the differential voltage of the remote output to a

single-ended voltage referenced to local ground. VDIFF is

the amplifier’s output and the input to the regulation and

protection circuitry. Connect VSEN and RGND to the sense

FS - Use this pin to set up the desired switching frequency. A

resistor, placed from FS to ground will set the switching

frequency. The relationship between the value of the resistor

FN9276.2

December 20, 2006

8

ISL6327

pins of the remote load. VDIFF is connected to FB through a

resistor.

OVP occurs, VR_RDY will be pulled to low. It will also be

pulled low if the output voltage is below the undervoltage

threshold.

FB and COMP - The inverting input and the output of the

error amplifier respectively. FB can be connected to VDIFF

through a resistor. A properly chosen resistor between

VDIFF and FB can set the load line (droop), when IDROOP

pin is tied to FB pin. The droop scale factor is set by the ratio

of the ISEN resistors and the inductor DCR or the dedicated

current sense resistor. COMP is tied back to FB through an

external R-C network to compensate the regulator.

OFS - The OFS pin provides a means to program a DC

offset current for generating a DC offset voltage at the REF

input. The offset current is generated via an external resistor

and precision internal voltage references. The polarity of the

offset is selected by connecting the resistor to GND or VCC.

For no offset, the OFS pin should be left unterminated.

TCOMP - Temperature compensation scaling input. The

voltage sensed on the TM pin is utilized as the temperature

input to adjust ldroop and the overcurrent protection limit to

effectively compensate for the temperature coefficient of the

current sense element. To implement the integrated

temperature compensation, a resistor divider circuit is

needed with one resistor being connected from TCOMP to

VCC of the controller and another resistor being connected

from TCOMP to GND. Changing the ratio of the resistor

values will set the gain of the integrated thermal

DAC and REF - The DAC pin is the output of the precision

internal DAC reference. The REF pin is the positive input of

the Error Amp. In typical applications, a 1kΩ, 1% resistor is

used between DAC and REF to generate a precision offset

voltage. This voltage is proportional to the offset current

determined by the offset resistor from OFS to ground or

VCC. A capacitor is used between REF and ground to

smooth the voltage transition during Dynamic VID™

operations.

compensation. When integrated temperature compensation

function is not used, connect TCOMP to GND.

PWM1, PWM2, PWM3, PWM4, PWM5, PWM6 - Pulse

width modulation outputs. Connect these pins to the PWM

input pins of the Intersil driver IC. The number of active

channels is determined by the state of PWM3, PWM4,

PWM5, and PWM6. For 2-phase operation, connect PWM3

to VCC; similarly, PWM4 for 3-phase, PWM5 for 4-phase,

and PWM6 for 5-phase operation.

OVP - The Overvoltage protection output indication pin. This

pin can be pulled to VCC and is latched when an overvoltage

condition is detected. When the OVP indication is not used,

keep this pin open.

IDROOP - IDROOP is the output pin of the sensed average

channel current which is proportional to the load current. In

the application which does not require loadline, leave this pin

open. In the application which requires load line, connect

this pin to FB so that the sensed average current will flow

through the resistor between FB and VDIFF to create a

voltage drop which is proportional to the load current.

TABLE 1. PHASE FIRING SEQUENCE

CONFIGURATION

6-Phase

PHASE SEQUENCE

1 - 2 - 3 - 4 - 5 - 6

1 - 2 - 3 - 4 - 5

1 - 2 - 4 - 3

5-Phase

4-Phase

IOUT - IOUT has the same output as IDROOP with

additional OCP adjustment function. In actual application, a

resistor needs to be placed between IOUT and GND to

ensure the proper operation. The voltage at IOUT pin will be

proportional to the load current. If the voltage is higher than

2V, ISL6327 will go into the OCP mode, this means it will

shut down first and then hiccup. The additional OCP trip

level can be adjusted by changing the resistor value.

3-Phase

1 - 2 - 3

ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;

ISEN4+, ISEN4-; ISEN5+, ISEN5-; ISEN6+, ISEN6- - The

ISEN+ and ISEN- pins are current sense inputs to individual

differential amplifiers. The sensed current is used for

channel current balancing, overcurrent protection, and droop

regulation. Inactive channels should have their respective

current sense inputs left open (for example, open ISEN6+

and ISEN6- for 5-phase operation).

TM - TM is an input pin for VR temperature measurement.

Connect this pin through NTC thermistor to GND and a

resistor to Vcc of the controller. The voltage at this pin is

reverse proportional to the VR temperature. ISL6327

monitors the VR temperature based on the voltage at the TM

pin and the output signals at VR_HOT and VR_FAN.

For DCR sensing, connect each ISEN- pin to the node

between the RC sense elements. Tie the ISEN+ pin to the

other end of the sense capacitor through a resistor, R

The voltage across the sense capacitor is proportional to the

inductor current. Therefore, the sense current is proportional

to the inductor current, and scaled by the DCR of the

.

ISEN

VR_HOT - VR_HOT is used as an indication of high VR

temperature. It is an open-drain logic output. It will be open

when the measured VR temperature reaches a certain level.

inductor and R

ISEN

.

VR_RDY - VR_RDY indicates that the soft-start is completed

and the output voltage is within the regulated range around

VID setting. It is an open-drain logic output. When OCP or

VR_FAN - VR_FAN is an output pin with open-drain logic

output. It will be open when the measured VR temperature

reaches a certain level.

FN9276.2

December 20, 2006

9

ISL6327

To understand the reduction of the ripple current amplitude in

the multiphase circuit, examine the equation representing an

individual channel’s peak-to-peak inductor current.

Operation

Multiphase Power Conversion

Microprocessor load current profiles have changed to the

point that the advantages of multiphase power conversion

are impossible to ignore. The technical challenges

associated with producing a single-phase converter which is

both cost-effective and thermally viable, have forced a

change to the cost-saving approach of multiphase. The

ISL6327 controller helps reduce the complexity of

implementation by integrating vital functions and requiring

minimal output components. The block diagrams on pages

3, 4, and 5 provide top level views of multiphase power

conversion using the ISL6327 controller.

(V – V

) V

OUT

IN

OUT

(EQ. 1)

I

= -----------------------------------------------------

PP

Lf

V

S

IN

In Equation 1, V and V

IN

are the input and the output

OUT

voltages respectively, L is the single-channel inductor value,

and f is the switching frequency.

S

INPUT-CAPACITOR CURRENT 10A/DIV

CHANNEL 3

INPUT CURRENT

10A/DIV

Interleaving

The switching of each channel in a multiphase converter is

timed to be symmetrically out of phase with each of the other

channels. In a 3-phase converter, each channel switches 1/3

cycle after the previous channel and 1/3 cycle before the

following channel. As a result, the three-phase converter has

a combined ripple frequency three times greater than the

ripple frequency of any one phase. In addition, the peak-to-

peak amplitude of the combined inductor current is reduced

in proportion to the number of phases (Equations 1 and 2).

The increased ripple frequency and the lower ripple

amplitude mean that the designer can use less per-channel

inductance and lower total output capacitance for any

performance specification.

CHANNEL 2

INPUT CURRENT

10A/DIV

CHANNEL 1

INPUT CURRENT

10A/DIV

1µs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 3-PHASE

CONVERTER

The output capacitors conduct the ripple component of the

inductor current. In the case of multiphase converters, the

capacitor current is the sum of the ripple currents from each

of the individual channels. Compare Equation 1 to the

expression for the peak-to-peak current after the summation

of N symmetrically phase-shifted inductor currents in

Equation 2. Peak-to-peak ripple current decreases by an

amount proportional to the number of channels. Output-

voltage ripple is a function of capacitance, capacitor

equivalent series resistance (ESR), and inductor ripple

current. Reducing the inductor ripple current allows the

designer to use fewer or less costly output capacitors.

Figure 1 illustrates the multiplicative effect on output ripple

frequency. The three channel currents (IL1, IL2, and IL3)

combine to form the AC ripple current and the DC load

current. The ripple component has three times the ripple

frequency of each individual channel current. Each PWM

pulse is triggered 1/3 of a cycle after the start of the PWM

pulse of the previous phase. The DC components of the

inductor currents combine to feed the load.

(V – N V

) V

OUT

IN

OUT

IL1 + IL2 + IL3, 7A/DIV

IL3, 7A/DIV

I

= -----------------------------------------------------------

(EQ. 2)

C, PP

Lf

V

S

IN

Another benefit of interleaving is to reduce the input ripple

current. The input capacitance is determined in part by the

maximum input ripple current. Multiphase topologies can

improve the overall system cost and size by lowering the

input ripple current and allowing the designer to reduce the

cost of input capacitance. The example in Figure 2 illustrates

the input currents from a three-phase converter combining to

reduce the total input ripple current.

PWM3, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL1, 7A/DIV

PWM1, 5V/DIV

1µs/DIV

The converter depicted in Figure 2 delivers 36A to a 1.5V load

from a 12V input. The RMS input capacitor current is 5.9A.

Compare this to a single-phase converter also stepping down

12V to 1.5V at 36A. The single-phase converter has 11.9A

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

FN9276.2

December 20, 2006

10

ISL6327

RMS input capacitor current. The single-phase converter

must use an input capacitor bank with twice the RMS current

capacity as the equivalent three-phase converter.

Connecting the PWM4 to VCC selects 3-phase operation

and the pulse times are spaced in 1/3 cycle increments.

Connecting the PWM3 to VCC selects 2-phase operation

and the pulse times are spaced in 1/2 cycle increments.

Figures 19, 20 and 21 in the section titled Input Capacitor

Selection can be used to determine the input-capacitor RMS

current based on the load current, the duty cycle, and the

number of channels. They are provided as aids in

determining the optimal input capacitor solution. Figure 22

shows the single phase input-capacitor RMS current for

comparison.

Switching Frequency

The switching frequency is determined by the selection of

the frequency-setting resistor, R , which is connected from

FS pin to GND (see the figures labelled Typical Applications

on pages 4 and 5). Equation 3 is provided to assist in

selecting the correct resistor value.

T

10

PWM Modulation Scheme

2.5X10

-------------------------

R

=

– 600

(EQ. 3)

T

F

The ISL6327 adopts Intersil's proprietary Active Pulse

Positioning (APP) modulation scheme to improve the

transient performance. APP control is a unique dual-edge

PWM modulation scheme with both PWM leading and

trailing edges being independently moved to provide the

best response to the transient loads. The PWM frequency,

however, is constant and set by the external resistor

between the FS pin and GND.

SW

where F

SW

is the switching frequency of each phase.

Current Sensing

ISL6327 senses the current continuously for fast response.

ISL6327 supports inductor DCR sensing, or resistive

sensing techniques. The associated channel current sense

amplifier uses the ISEN inputs to reproduce a signal

proportional to the inductor current, I . The sensed current,

, is used for the current balance, the load-line

regulation, and the overcurrent protection.

To further improve the transient response, the ISL6327 also

implements Intersil's proprietary Adaptive Phase Alignment

(APA) technique. APA, with sufficiently large load step

currents, can turn on all phases together.

L

I

SEN

The internal circuitry, shown in Figures 3 and 4, represents

one channel of an N-channel converter. This circuitry is

repeated for each channel in the converter, but may not be

active depending on the status of the PWM3, PWM4,

PWM5, and PWM6 pins, as described in the PWM Operation

section.

With both APP and APA control, ISL6327 can achieve

excellent transient performance and reduce the demand on

the output capacitors.

Under the steady state conditions the operation of the

ISL6327 PWM modulator appears to be that of a

conventional trailing edge modulator. Conventional analysis

and design methods can therefore be used for steady state

and small signal operation.

INDUCTOR DCR SENSING

An inductor’s winding is characteristic of a distributed

resistance as measured by the DCR (Direct Current

Resistance) parameter. Consider the inductor DCR as a

separate lumped quantity, as shown in Figure 3. The

PWM Operation

The timing of each converter is set by the number of active

channels. The default channel setting for the ISL6327 is six.

The switching cycle is defined as the time between PWM

pulse termination signals of each channel. The cycle time of

the pulse termination signal is the inverse of the switching

frequency set by the resistor between the FS pin and

ground. The PWM signals command the MOSFET drivers to

turn on/off the channel MOSFETs.

channel current I , flowing through the inductor, will also

L

pass through the DCR. Equation 4 shows the s-domain

equivalent voltage across the inductor V .

L

(EQ. 4)

V

= I ⋅ (s ⋅ L + DCR)

L

A simple R-C network across the inductor extracts the DCR

voltage, as shown in Figure 3.

In the default 6-phase operation, the PWM2 pulse happens

1/6 of a cycle after PWM1, the PWM3 pulse happens 1/6 of

a cycle after PWM2, the PWM4 pulse happens 1/6 of a cycle

after PWM3, the PWM5 pulse happens 1/6 of a cycle after

PWM4, and the PWM6 pulse happens 1/6 of a cycle after

PWM5.

The voltage on the capacitor V , can be shown to be

proportional to the channel current I , see Equation 5.

L

C

L

⎛

⎝

⎞

-------------

s ⋅

+ 1 ⋅ (DCR ⋅ I )

L

⎠

(EQ. 5)

DCR

V

= --------------------------------------------------------------------

C

(s ⋅ RC + 1)

The ISL6327 works in 2, 3, 4, 5, or 6 phase configuration.

Connecting the PWM6 to VCC selects 5-phase operation

and the pulse times are spaced in 1/5 cycle increments.

Connecting the PWM5 to VCC selects 4-phase operation

and the pulse times are spaced in 1/4 cycle increments.

FN9276.2

December 20, 2006

11

ISL6327

The same capacitor C is needed to match the time delay

V

T

IN

I

(s)

L

between ISEN- and ISEN+ signals. Select the proper C to

T

keep the time constant of R

to 27ns.

and C (R x C ) close

ISEN T

L

ISEN

T

DCR

V

OUT

ISL6609

INDUCTOR

-

C

OUT

Equation 7 shows the ratio of the channel current to the

V

L

sensed current I

.

SEN

-

(s)

V

C

R

SENSE

-----------------------

I

= I

⋅

R

(EQ. 7)

C

SEN

L

R

ISEN

PWM(n)

I

L

ISL6327 INTERNAL CIRCUIT

L

R

V

OUT

SENSE

R

ISEN(n)

(PTC)

C

OUT

I

n

ISL6327 INTERNAL CIRCUIT

CURRENT

SENSE

R

ISEN(n)

ISEN-(n)

I

n

+

-

CURRENT

SENSE

ISEN-(n)

ISEN+(n)

C

T

+

-

DCR

I

-----------------

= I

SEN

L

R

C

T

ISEN

R

SENSE

I

= I --------------------------

SEN

FIGURE 3. DCR SENSING CONFIGURATION

L

R

ISEN

FIGURE 4. SENSE RESISTOR IN SERIES WITH INDUCTORS

If the R-C network components are selected such that the

RC time constant (= R*C) matches the inductor time

constant (= L/DCR), the voltage across the capacitor V is

equal to the voltage drop across the DCR, i.e., proportional

to the channel current.

The inductor DCR value will increase as the temperature

increases. Therefore the sensed current will increase as the

temperature of the current sense element increases. In order

to compensate the temperature effect on the sensed current

signal, a Positive Temperature Coefficient (PTC) resistor can

C

With the internal low-offset current amplifier, the capacitor

voltage V is replicated across the sense resistor R

.

C

ISEN

, is proportional

be selected for the sense resistor R

, or the integrated

ISEN

Therefore the current out of ISEN+ pin, I

to the inductor current.

SEN

temperature compensation function of ISL6327 should be

utilized. The integrated temperature compensation function

is described in the Temperature Compensation section.

Because of the internal filter at ISEN- pin, one capacitor C

is needed to match the time delay between the ISEN- and

T

Channel-Current Balance

ISEN+ signals. Select the proper C to keep the time

T

The sensed current I from each active channel are summed

n

together and divided by the number of active channels. The

constant of R

ISEN

and C (R x C ) close to 27ns.

ISEN T

T

Equation 6 shows that the ratio of the channel current to the

sensed current I is driven by the value of the sense

resulting average current I

provides a measure of the

AVG

SEN

total load current. Channel current balance is achieved by

comparing the sensed current of each channel to the

average current to make an appropriate adjustment to the

PWM duty cycle of each channel with Intersil’s patented

current-balance method.

resistor and the DCR of the inductor.

DCR

-----------------

I

= I

⋅

(EQ. 6)

SEN

L

R

ISEN

RESISTIVE SENSING

For accurate current sense, a dedicated current-sense

resistor R in series with each output inductor can

serve as the current sense element (see Figure 4). This

technique is more accurate, but reduces overall converter

efficiency due to the additional power loss on the current

Channel current balance is essential in achieving the

thermal advantage of multiphase operation. With good

current balance, the power loss is equally dissipated over

multiple devices and a greater area.

SENSE

sense element R

.

SENSE

FN9276.2

December 20, 2006

12

ISL6327

Voltage Regulation

Load-Line Regulation

The compensation network shown in Figure 5 assures that

the steady-state error in the output voltage is limited only to

the error in the reference voltage (output of the DAC) and

offset errors in the OFS current source, remote-sense and

error amplifiers. Intersil specifies the guaranteed tolerance of

the ISL6327 to include the combined tolerances of each of

these elements.

Some microprocessor manufacturers require a precisely-

controlled output resistance. This dependence of the output

voltage on the load current is often termed “droop” or “load

line” regulation. By adding a well controlled output

impedance, the output voltage can effectively be level shifted

in a direction which works to achieve the load-line regulation

required by these manufacturers.

The output of the error amplifier, V

, is compared to the

COMP

In other cases, the designer may determine that a more

cost-effective solution can be achieved by adding droop.

Droop can help to reduce the output-voltage spike that

results from the fast changes of the load-current demand.

sawtooth waveforms to generate the PWM signals. The

PWM signals control the timing of the Intersil MOSFET

drivers and regulate the converter output to the specified

reference voltage. The internal and external circuitries which

control the voltage regulation are illustrated in Figure 5.

The magnitude of the spike is dictated by the ESR and ESL

of the output capacitors selected. By positioning the no-load

voltage level near the upper specification limit, a larger

negative spike can be sustained without crossing the lower

limit. By adding a well controlled output impedance, the

output voltage under load can effectively be level shifted

down so that a larger positive spike can be sustained without

crossing the upper specification limit.

The ISL6327 incorporates an internal differential remote-sense

amplifier in the feedback path. The amplifier removes the

voltage error encountered when measuring the output voltage

relative to the local controller ground reference point resulting in

a more accurate means of sensing output voltage. Connect the

microprocessor sense pins to the non-inverting input, VSEN,

and inverting input, RGND, of the remote-sense amplifier. The

remote-sense output, V

of the error amplifier through an external resistor.

, is connected to the inverting input

DIFF

TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION)

VID4

VID3

VID2

VID1

VID0

VID5

VID6 VOLTAGE

A digital-to-analog converter (DAC) generates a reference

voltage based on the state of logic signals at pins VID7

through VID0. The DAC decodes the 8-bit logic signal (VID)

into one of the discrete voltages shown in Table 1. Each VID

input offers a 45µA pull-up to an internal 2.5V source for use

with open-drain outputs. The pull-up current diminishes to

zero above the logic threshold to protect voltage-sensitive

output devices. External pull-up resistors can augment the

pull-up current sources in case the leakage into the driving

device is greater than 45µA.

400mV 200mV 100mV 50mV

25mV 12.5mV 6.25mV

(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.6

1.59375

1.5875

1.58125

1.575

1.56875

1.5625

1.55625

1.55

EXTERNAL CIRCUIT

ISL6327 INTERNAL CIRCUIT

R

C

COMP

DAC

1.54375

1.5375

1.53125

1.525

R

REF

C

REF

+

-

V

FB

COMP

1.51875

1.5125

1.50625

1.5

ERROR AMPLIFIER

I

IDROOP

VDIFF

+

V

-

AVG

R

FB

DROOP

VSEN

RGND

1.49375

1.4875

1.48125

1.475

V

+

OUT

+

-

OUT

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

1.46875

1.4625

FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

FN9276.2

December 20, 2006

13

ISL6327

TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION) (Continued)

VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE

400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V)

TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION) (Continued)

VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE

400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV

(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.45625

1.45

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.2

1.19375

1.1875

1.18125

1.175

1.44375

1.4375

1.43125

1.425

1.16875

1.1625

1.15625

1.15

1.41875

1.4125

1.40625

1.4

1.14375

1.1375

1.13125

1.125

1.39375

1.3875

1.38125

1.375

1.11875

1.1125

1.10625

1.1

1.36875

1.3625

1.35625

1.35

1.09375

OFF

1.34375

1.3375

1.33125

1.325

OFF

1.31875

1.3125

1.30625

1.3

1.0875

1.08125

1.075

1.06875

1.0625

1.05625

1.05

1.29375

1.2875

1.28125

1.275

1.04375

1.0375

1.03125

1.025

1.26875

1.2625

1.25625

1.25

1.01875

1.0125

1.00625

1

1.24375

1.2375

1.23125

1.225

0.99375

0.9875

0.98125

0.975

1.21875

1.2125

1.20625

FN9276.2

December 20, 2006

14

ISL6327

TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION) (Continued)

VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE

400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V)

TABLE 3. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.96875

0.9625

0.95625

0.95

0.94375

0.9375

0.93125

0.925

0.91875

0.9125

0.90625

0.9

0.89375

0.8875

0.88125

0.875

0.86875

0.8625

0.85625

0.85

0.84375

0.8375

0.83125

TABLE 3. VR11 VID 8 BIT

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OFF

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

FN9276.2

December 20, 2006

15

ISL6327

TABLE 3. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

TABLE 3. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

FN9276.2

December 20, 2006

16

ISL6327

TABLE 3. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

TABLE 3. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

1

0

1

OFF

As shown in Figure 5, a current proportional to the average

current of all active channels, I , flows from FB through a

AVG

load-line regulation resistor R . The resulting voltage drop

FB

across R is proportional to the output current, effectively

creating an output voltage droop with a steady-state value

defined as:

FB

V

= I

R

AVG FB

(EQ. 8)

DROOP

The regulated output voltage is reduced by the droop voltage

. The output voltage as a function of load current is

V

DROOP

derived by combining Equation 8 with the appropriate

sample current expression defined by the current sense

method employed.

I

R

X

⎛

⎞

⎟

⎠

OUT

V

= V

– V

– ------------- ----------------- R

⎜

OFS FB

(EQ. 9)

OUT

REF

N

R

ISEN

⎝

Where V

is the reference voltage, V

is the

REF

programmed offset voltage, I

OFS

is the total output current

OUT

is the sense resistor connected to

of the converter, R

the ISEN+ pin, and R is the feedback resistor, N is the

active channel number, and R is the DCR, or R

X

depending on the sensing method.

ISEN

FB

SENSE

Therefore the equivalent loadline impedance, i.e. Droop

impedance, is equal to:

R

X

R

ISEN

FB

R

= ------------ -----------------

(EQ. 10)

LL

N

Output-Voltage Offset Programming

The ISL6327 allows the designer to accurately adjust the

offset voltage. When a resistor, R , is connected between

OFS

OFS to VCC, the voltage across it is regulated to 1.6V. This

causes a proportional current (I ) to flow into OFS. If

OFS

is connected to ground, the voltage across it is

R

OFS

regulated to 0.4V, and I

flows out of OFS. A resistor

OFS

between DAC and REF, R

, is selected so that the

REF

product (I

x R

) is equal to the desired offset voltage.

OFS

These functions are shown in Figure 6.

Once the desired output offset voltage has been determined,

use the following formulae to set R

:

OFS

For Positive Offset (connect R

to VCC):

OFS

1.6 × R

REF

(EQ. 11)

(EQ. 12)

-----------------------------

R

=

OFS

V

OFFSET

For Negative Offset (connect R

to GND):

OFS

0.4 × R

REF

-----------------------------

R

=

OFS

V

OFFSET

FN9276.2

December 20, 2006

17

ISL6327

Operation Initialization

FB

Prior to converter initialization, proper conditions must exist on

the enable inputs and VCC. When the conditions are met, the

controller begins soft-start. Once the output voltage is within

the proper window of operation, VR_RDY asserts logic high.

DAC

DYNAMIC

VID D/A

Enable and Disable

R

REF

While in shutdown mode, the PWM outputs are held in a

high-impedance state to assure the drivers remain off. The

following input conditions must be met before the ISL6327 is

released from shutdown mode.

E/A

REF

1. The bias voltage applied at VCC must reach the internal

power-on reset (POR) rising threshold. Once this

threshold is reached, proper operation of all aspects of

the ISL6327 is guaranteed. Hysteresis between the rising

and falling thresholds assure that once enabled, the

ISL6327 will not inadvertently turn off unless the bias

voltage drops substantially (see Electrical

VCC

OR

GND

-

R

1.6V

OFS

+

-

Specifications).

0.4V

OFS

2. The ISL6327 features an enable input (EN_PWR) for

power sequencing between the controller bias voltage and

another voltage rail. The enable comparator holds the

ISL6327 in shutdown until the voltage at EN_PWR rises

above 0.875V. The enable comparator has about 130mV

of hysteresis to prevent bounce. It is important that the

driver ICs reach their POR level before the ISL6327

becomes enabled. The schematic in Figure 7

ISL6327

GND

VCC

FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING

Dynamic VID

Modern microprocessors need to make changes to their core

voltage as part of the normal operation. They direct the core-

voltage regulator to do this by making changes to the VID

inputs during the regulator operation. The power management

solution is required to monitor the DAC inputs and respond to

on-the-fly VID changes in a controlled manner. Supervising

the safe output voltage transition within the DAC range of the

processor without discontinuity or disruption is a necessary

function of the core-voltage regulator.

demonstrates sequencing the ISL6327 with the ISL66xx

family of Intersil MOSFET drivers, which require 12V bias.

3. The voltage on EN_VTT must be higher than 0.875V to

enable the controller. This pin is typically connected to the

output of VTT VR.

ISL6327 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

+12V

VCC

In order to ensure the smooth transition of output voltage

during VID change, a VID step change smoothing network,

10kΩ

POR

ENABLE

COMPARATOR

composed of R

and C

, can be used. The selection of

REF

CIRCUIT

R

is based on the desired offset voltage as detailed

EN_PWR

REF

above in Output-Voltage Offset Programming. The selection

of C is based on the time duration for 1 bit VID change

+

-

REF

910Ω

and the allowable delay time.

0.875V

Assuming the microprocessor controls the VID change at 1

bit every T , the relationship between the time constant of

VID

EN_VTT

+

-

R

and C

network and T

VID

is given by Equation 13.

(EQ. 13)

REF

= T

C

R

REF REF

VID

0.875V

SOFT-START

AND

FAULT LOGIC

FIGURE 7. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (EN) FUNCTION

FN9276.2

December 20, 2006

18

ISL6327

When all conditions above are satisfied, ISL6327 begins the

soft-start and ramps the output voltage to 1.1V first. After

remaining at 1.1V for some time, ISL6327 reads the VID

code at VID input pins. If the VID code is valid, ISL6327 will

regulate the output to the final VID setting. If the VID code is

OFF code, ISL6327 will shut down, and cycling VCC,

EN_PWR or EN_VTT is needed to restart.

soft-start ramp times TD2 and TD4 can be calculated based

on the following equations:

1.1xR

SS

-----------------------

TD2 =

(μs)

(EQ. 15)

(EQ. 16)

6.25x25

(V – 1.1)xR

VID

SS

------------------------------------------------

TD4 =

(μs)

6.25x25

Soft-Start

For example, when VID is set to 1.5V and the R is set at

SS

100kΩ, the first soft-start ramp time TD2 will be 704µs and

the second soft-start ramp time TD4 will be 256µs.

ISL6327 based VR has 4 periods during soft-start as shown

in Figure 8. After VCC, EN_VTT and EN_PWR reach their

POR/enable thresholds, The controller will have fixed delay

period TD1. After this delay period, the VR will begin first

soft-start ramp until the output voltage reaches 1.1V Vboot

voltage. Then, the controller will regulate the VR voltage at

1.1V for another fixed period TD3. At the end of TD3 period,

ISL6327 reads the VID signals. If the VID code is valid,

ISL6327 will initiate the second soft-start ramp until the

voltage reaches the VID voltage minus offset voltage.

After the DAC voltage reaches the final VID setting,

VR_RDY will be set to high with the fixed delay TD5. The

typical value for TD5 is 85µs.

Fault Monitoring and Protection

The ISL6327 actively monitors output voltage and current to

detect fault conditions. Fault monitors trigger protective

measures to prevent damage to a microprocessor load. One

common power good indicator is provided for linking to

external system monitors. The schematic in Figure 9 outlines

the interaction between the fault monitors and the VR_RDY

signal.

VOUT, 500mV/DIV

VR_RDY Signal

The VR_RDY pin is an open-drain logic output to indicate

that the soft-start period is completed and the output voltage

is within the regulated range. VR_RDY is pulled low during

shutdown and releases high after a successful soft-start and

a fix delay time,TD5. VR_RDY will be pulled low when an

undervoltage, overvoltage, or overcurrent condition is

detected, or the controller is disabled by a reset from

EN_PWR, EN_VTT, POR, or VID OFF-code.

TD1

TD5

TD3 TD4

TD2

EN_VTT

VR_RDY

500µs/DIV

VR_RDY

FIGURE 8. SOFT-START WAVEFORMS

The soft-start time is the sum of the 4 periods as shown in

the following equation:

UV

T

= TD1 + TD2 + TD3 + TD4

(EQ. 14)

SS

50%

TD1 is a fixed delay with the typical value as 1.36ms. TD3 is

determined by the fixed 85µs plus the time to obtain valid

VID voltage. If the VID is valid before the output reaches the

1.1V, the minimum time to validate the VID input is 500ns.

Therefore the minimum TD3 is about 86µs.

85µA

-

DAC

SOFT-START, FAULT

AND CONTROL LOGIC

OC

+

I

AVG

During TD2 and TD4, ISL6327 digitally controls the DAC

voltage change at 6.25mV per step. The time for each step is

determined by the frequency of the soft-start oscillator which

VDIFF

+

OV

-

is defined by the resistor R from SS pin to GND. The two

SS

VID + 0.175V

FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY

FN9276.2

December 20, 2006

19

ISL6327

start. If the fault remains, the trip-retry cycles will continue

Undervoltage Detection

indefinitely (as shown in Figure 10) until either controller is

disabled or the fault is cleared. Note that the energy

delivered during trip-retry cycling is much less than during

full-load operation, so there is no thermal hazard during this

kind of operation.

The undervoltage threshold is set at 50% of the VID voltage.

When the output voltage at VSEN is below the undervoltage

threshold, VR_RDY gets pulled low. When the output

voltage comes back to 60% of the VID voltage, VR_RDY will

return back to high.

Overvoltage Protection

Regardless of the VR being enabled or not, the ISL6327

overvoltage protection (OVP) circuit will be active after its

POR. The OVP thresholds are different under different

operation conditions. When VR is not enabled and before

the 2nd soft-start, the OVP threshold is 1.275V. Once the

controller detects a valid VID input, the OVP trip point will be

changed to the VID voltage plus 175mV.

OUTPUT CURRENT

0A

Two actions are taken by the ISL6327 to protect the

microprocessor load when an overvoltage condition occurs.

OUTPUT VOLTAGE

At the inception of an overvoltage event, all PWM outputs

are commanded low instantly (less than 20ns). This causes

the Intersil drivers to turn on the lower MOSFETs and pull

the output voltage below a level to avoid damaging the load.

When the VDIFF voltage falls below the DAC plus 75mV,

PWM signals enter a high-impedance state. The Intersil

drivers respond to the high-impedance input by turning off

both upper and lower MOSFETs. If the overvoltage condition

reoccurs, the ISL6327 will again command the lower

MOSFETs to turn on. The ISL6327 will continue to protect

the load in this fashion as long as the overvoltage condition

occurs.

0V

2ms/DIV

FIGURE 10. OVERCURRENT BEHAVIOR IN HICCUP MODE.

F

= 500kHz

SW

For the individual channel overcurrent protection, the

ISL6327 continuously compares the sensed current signal of

each channel with the 120µA reference current. If one

channel current exceeds the reference current, ISL6327 will

pull PWM signal of this channel to low for the rest of the

switching cycle. This PWM signal can be turned on next

cycle if the sensed channel current is less than the 120µA

reference current. The peak current limit of individual

channel will not trigger the converter to shutdown.

Once an overvoltage condition is detected, normal PWM

operation ceases until the ISL6327 is reset. Cycling the

voltage on EN_PWR, EN_VTT or VCC below the POR-

falling threshold will reset the controller. Cycling the VID

codes will not reset the controller.

The overcurrent protection level for the above two OCP

modes can be adjusted by changing the value of current

sensing resistors. In addition, ISL6327 can also adjust the

average OCP threshold level by adjusting the value of the

resistor from IOUT to GND. This provides additional safety

for the voltage regulator.

Overcurrent Protection

ISL6327 has two levels of overcurrent protection. Each

phase is protected from a sustained overcurrent condition by

limiting its peak current, while the combined phase currents

are protected on an instantaneous basis.

The following equation can be used to calculate the value of the

resistor R

IOUT

based on the desired OCP level I

.

In instantaneous protection mode, the ISL6327 utilizes the

AVG, OCP2

sensed average current I

to detect an overcurrent

2

AVG

-------------------------------

R

=

(EQ. 17)

IOUT

I

condition. See the Channel-Current Balance section for

more detail on how the average current is measured. The

average current is continually compared with a constant

85µA reference current as shown in Figure 9. Once the

average current exceeds the reference current, a

comparator triggers the converter to shutdown.

AVG, OCP2

Current Sense Output

The ISL6327 has 2 current sense output pins IDROOP and

IOUT; They are identical. In typical application, IDROOP pin

is connected to FB pin for the application where load line is

required. IOUT pin was designed for load current

measurement. As shown in typical application schematics

on pages 4 and 5, load current information can be obtained

by measuring the voltage at IOUT pin with a resistor

connecting IOUT pin to the ground. When the programmable

temperature compensation function of ISL6327 is properly

At the beginning of overcurrent shutdown, the controller

places all PWM signals in a high-impedance state within

20ns commanding the Intersil MOSFET driver ICs to turn off

both upper and lower MOSFETs. The system remains in this

state a period of 4096 switching cycles. If the controller is still

enabled at the end of this wait period, it will attempt a soft-

FN9276.2

December 20, 2006

20

ISL6327

used, the output current at IOUT pin is proportional to the

load current as shown in Figure 11.

VCC

VR_FAN

VR_HOT

V_IOUT, 200mV/DIV

0.33V_CC

R_TM1

TM

^oc

R_NTC

0.28V_CC

FIGURE 12. BLOCK DIAGRAM OF THERMAL MONITORING

FUNCTION

0A

50A

100A

FIGURE 11. VOLTAGE AT IOUT PIN WITH A NTC NETWORK

PLACED BETWEEN IOUT TO GROUND WHEN

LOAD CURRENT CHANGES

V_TM/ V_CCvs. Temperature

100%

90%

80%

70%

60%

50%

40%

30%

20%

Thermal Monitoring (VR_HOT/VR_FAN)

There are two thermal signals to indicate the temperature

status of the voltage regulator: VR_HOT and VR_FAN. Both

VR_FAN and VR_HOT are open-drain outputs, and external

pull-up resistors are required. Those signals are valid only

after the controller is enabled.

VR_FAN signal indicates that the temperature of the voltage

regulator is high and more cooling airflow is needed.

VR_HOT signal can be used to inform the system that the

temperature of the voltage regulator is too high and the CPU

should reduce its power consumption. VR_HOT signal may

be tied to the CPU’s PROCHOT# signal.

0

20

40

60

80

100

120

140

Temperature (^oC)

FIGURE 13. THE RATIO OF TM VOLTAGE TO NTC

TEMPERATURE WITH RECOMMENDED PARTS

The diagram of thermal monitoring function block is shown in

Figure 12. One NTC resistor should be placed close to the

power stage of the voltage regulator to sense the operational

temperature, and one pull-up resistor is needed to form the

voltage divider for TM pin. As the temperature of the power

stage increases, the resistance of the NTC will reduce,

resulting in the reduced voltage at TM pin. Figure 13 shows

the TM voltage over the temperature for a typical design with

a recommended 6.8kΩ NTC (P/N: NTHS0805N02N6801

from Vishay) and 1kΩ resistor RTM1. We recommend using

those resistors for the accurate temperature compensation.

TM

0.39*Vcc

0.33*Vcc

0.28*Vcc

VR_FAN

VR_HOT

There are two comparators with hysteresis to compare the

TM pin voltage to the fixed thresholds for VR_FAN and

VR_HOT signals respectively. VR_FAN signal is set to high

when TM voltage is lower than 33% of VCC voltage, and is

pulled to GND when TM voltage increases to above 39% of

Vcc voltage. VR_HOT is set to high when TM voltage goes

below 28% of VCC voltage, and is pulled to GND when TM

voltage goes back to above 33% of VCC voltage. Figure 14

shows the operation of those signals.

Temperature

T1

T2

T3

FIGURE 14. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE

FN9276.2

December 20, 2006

21

ISL6327

Based on the NTC temperature characteristics and the

desired threshold of VR_HOT signal, the pull-up resistor

RTM1 of TM pin is given by:

When the TM NTC is placed close to the current sense

component (inductor), the temperature of the NTC will track

the temperature of the current sense component. Therefore,

the TM voltage can be utilized to obtain the temperature of

the current sense component.

R

= 2.75xR

NTC(T3)

(EQ. 18)

TM1

R

is the NTC resistance at the VR_HOT threshold

NTC(T3)

Based on VCC voltage, ISL6327 converts the TM pin voltage

to a 6-bit TM digital signal for temperature compensation.

With the non-linear A/D converter of ISL6327, TM digital

signal is linearly proportional to the NTC temperature. For

accurate temperature compensation, the ratio of the TM

voltage to the NTC temperature of the practical design

should be similar to that in Figure 13.

temperature T3.

The NTC resistance at the set point T2 and release point T1

of VR_FAN signal can be calculated as:

R

= 1.267xR

(EQ. 19)

NTC(T2)

NTC(T3)

R

= 1.644xR

(EQ. 20)

NTC(T1)

NTC(T3)

Depending on the location of the NTC and the air-flowing,

the NTC may be cooler or hotter than the current sense

component. TCOMP pin voltage can be utilized to correct

the temperature difference between NTC and the current

sense component. When a different NTC type or different

voltage divider is used for the TM function, TCOMP voltage

can also be used to compensate for the difference between

the recommended TM voltage curve in Figure 14 and that of

the actual design. According to the VCC voltage, ISL6327

converts the TCOMP pin voltage to a 4-bit TCOMP digital

signal as TCOMP factor N.

With the NTC resistance value obtained from Equations 19

and 20, the temperature value T2 and T1 can be found from

the NTC datasheet.

Temperature Compensation

ISL6327 supports inductor DCR sensing, or resistive

sensing techniques. The inductor DCR have the positive

temperature coefficient, which is about +0.38%/°C. Because

the voltage across inductor is sensed for the output current

information, the sensed current has the same positive

temperature coefficient as the inductor DCR.

TCOMP factor N is an integer between 0 and 15. The

integrated temperature compensation function is disabled for

N = 0. For N = 4, the NTC temperature is equal to the

temperature of the current sense component. For N < 4, the

NTC is hotter than the current sense component. The NTC is

cooler than the current sense component for N > 4. When

N > 4, the larger TCOMP factor N, the larger the difference

between the NTC temperature and the temperature of the

current sense component.

In order to obtain the correct current information, there

should be a way to correct the temperature impact on the

current sense component. ISL6327 provides two methods:

integrated temperature compensation and external

temperature compensation.

Integrated Temperature Compensation

When TCOMP voltage is equal or greater than Vcc/15,

ISL6327 will utilize the voltage at TM and TCOMP pins to

compensate the temperature impact on the sensed current.

The block diagram of this function is shown in Figure 15.

ISL6327 multiplexes the TCOMP factor N with the TM digital

signal to obtain the adjustment gain to compensate the

temperature impact on the sensed channel current. The

compensated channel current signal is used for droop and

overcurrent protection functions.

V_CC

R_TM1

I_sen6

Design Procedure

I_sen5

I_sen4

1. Properly choose the voltage divider for TM pin to match

the TM voltage vs. temperature curve with the

recommended curve in Figure 13.

Channel current sense

I_sen3

I_sen2

I_sen1

Non-linear

A/D

TM

^oc

R_NTC

2. Run the actual board under the full load and the desired

cooling condition.

I₆

I₅

I₄

I₃

I₂

I₁

k

i

3. After the board reaches the thermal steady state, record

D/A

V_CC

the temperature (T

) of the current sense component

CSC

(inductor) and the voltage at TM and VCC pins.

R_TC1

4. Use the following equation to calculate the resistance of

the TM NTC, and find out the corresponding NTC

TCOMP

4-bit

A/D

Droop, Iout &

Over current protection

temperature T

from the NTC datasheet.

NTC

V

R

TC2

xR

TM

TM1

R

= -------------------------------

(EQ. 21)

NTC(T

)

V

– V

NTC

CC

TM

FIGURE 15. BLOCK DIAGRAM OF INTEGRATED

TEMPERATURE COMPENSATION

FN9276.2

December 20, 2006

22

ISL6327

5. Use the following equation to calculate the TCOMP factor N:

The external temperature compensation network can only

compensate the temperature impact on the droop, while it

has no impact to the sensed current inside ISL6327.

Therefore this network cannot compensate for the

temperature impact on the overcurrent protection function.

209x(T

– T

)

NTC

CSC

-------------------------------------------------------

N =

+ 4

(EQ. 22)

3xT

+ 400

NTC

6. Choose an integral number close to the above result for

the TCOMP factor. If this factor is higher than 15, use

N = 15. If it is less than 1, use N = 1.

General Design Guide

7. Choose the pull-up resistor R

TC1

(typical 10kΩ);

This design guide is intended to provide a high-level

explanation of the steps necessary to create a multiphase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced below. In

addition to this guide, Intersil provides complete reference

designs that include schematics, bills of materials, and

example board layouts for all common microprocessor

applications.

8. If N = 15, do not need the pull-down resistor R

,

TC2

otherwise obtain R

by the following equation:

TC2

NxR

TC1

15 – N

----------------------

=

R

(EQ. 23)

TC2

9. Run the actual board under full load again with the proper

resistors to TCOMP pin.

10. Record the output voltage as V1 immediately after the

output voltage is stable with the full load; Record the

output voltage as V2 after the VR reaches the thermal

steady state.

Power Stages

The first step in designing a multiphase converter is to

determine the number of phases. This determination

depends heavily on the cost analysis which in turn depends

on system constraints that differ from one design to the next.

Principally, the designer will be concerned with whether

components can be mounted on both sides of the circuit

board; whether through-hole components are permitted; and

the total board space available for power-supply circuitry.

Generally speaking, the most economical solutions are

those in which each phase handles between 15A and 20A.

All surface-mount designs will tend toward the lower end of

this current range. If through-hole MOSFETs and inductors

can be used, higher per-phase currents are possible. In

cases where board space is the limiting constraint, current

can be pushed as high as 40A per phase, but these designs

require heat sinks and forced air to cool the MOSFETs,

inductors, and heat-dissipating surfaces.

11. If the output voltage increases over 2mV as the

temperature increases, i.e. V2-V1>2mV, reduce N and

redesign R

; if the output voltage decreases over 2mV

TC2

as the temperature increases, i.e. V1-V2>2mV, increase

N and redesign R

.

TC2

The design spreadsheet is available for those calculations.

External Temperature Compensation

By pulling the TCOMP pin to GND, the integrated

temperature compensation function is disabled. And one

external temperature compensation network, shown in

Figure 16, can be used to cancel the temperature impact on

the droop (i.e. load line).

ISL6327

Internal

circuit

COMP

MOSFETS

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct; the switching

frequency; the capability of the MOSFETs to dissipate heat;

and the availability and nature of heat sinking and air flow.

IDROOP

^oC

FB

LOWER MOSFET POWER CALCULATION

The calculation for heat dissipated in the lower MOSFET is

simple, since virtually all of the heat loss in the lower

MOSFET is due to current conducted through the channel

VDIFF

resistance (R

). In Equation 24, I is the maximum

FIGURE 16. EXTERNAL TEMPERATURE COMPENSATION

DS(ON)

M

continuous output current; I is the peak-to-peak inductor

PP

The sensed current will flow out of IDROOP pin and develop

current (see Equation 1); d is the duty cycle (V

/V ); and

OUT IN

the droop voltage across the resistor (R ) between FB and

FB

L is the per-channel inductance.

VDIFF pins. If R resistance reduces as the temperature

FB

increases, the temperature impact on the droop can be

compensated. An NTC resistor can be placed close to the

2

I

(1 – d)

⎛

⎜

⎝

⎞

⎟

⎠

I

L, PP

(EQ. 24)

M

P

= r

(1 – d) + --------------------------------

-----

LOW, 1

DS(ON)

12

N

power stage and used to form R . Due to the non-linear

FB

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the dead

time when inductor current is flowing through the lower-

MOSFET body diode. This term is dependent on the diode

temperature characteristics of the NTC, a resistor network is

needed to make the equivalent resistance between FB and

VDIFF pin reverse proportional to the temperature.

FN9276.2

December 20, 2006

23

ISL6327

forward voltage at I , V

; the switching frequency, f ; and

equations depend on MOSFET parameters, choosing the

M

D(ON)

S

the length of dead times, t and t , at the beginning and the

end of the lower-MOSFET conduction interval respectively.

correct MOSFETs can be an iterative process involving

repetitive solutions to the loss equations for different

MOSFETs and different switching frequencies.

d1 d2

⎛

⎜

⎝

⎞

⎟

⎠

I

M

N

I

(EQ. 25)

⎛

⎝

⎞

⎠

M

PP

2

PP

2

P

= V

f

D(ON) S

t

d2

+

--------

----- –

----- + --------

LOW, 2

d1

Current Sensing Resistor

N

The resistors connected to the Isen+ pins determine the

gains in the load-line regulation loop and the channel-current

balance loop as well as setting the overcurrent trip point.

Select values for these resistors by the Equation 30.

Thus the total maximum power dissipated in each lower

MOSFET is approximated by the summation of P

and

LOW,1

P

.

LOW,2

UPPER MOSFET POWER CALCULATION

In addition to R losses, a large portion of the upper-

R

I

OCP

X

(EQ. 30)

R

= ----------------------- -------------

–

ISEN

6

N

85 ×10

DS(ON)

MOSFET losses are due to currents conducted across the

where R

ISEN

is the sense resistor connected to the ISEN+

input voltage (V ) during switching. Since a substantially

pin, N is the active channel number, R is the resistance of

IN

X

higher portion of the upper-MOSFET losses are dependent on

switching frequency, the power calculation is more complex.

Upper MOSFET losses can be divided into separate

the current sense element, either the DCR of the inductor or

R

depending on the sensing method, and I

is the

SENSE

desired overcurrent trip point. Typically, I

OCP

can be chosen

OCP

components involving the upper-MOSFET switching times;

to be 1.3 times the maximum load current of the specific

the lower-MOSFET body-diode reverse-recovery charge, Q ;

application.

rr

and the upper MOSFET R

DS(ON)

conduction loss.

With integrated temperature compensation, the sensed

current signal is independent on the operational temperature

of the power stage, i.e. the temperature effect on the current

When the upper MOSFET turns off, the lower MOSFET does

not conduct any portion of the inductor current until the

voltage at the phase node falls below ground. Once the

lower MOSFET begins conducting, the current in the upper

MOSFET falls to zero as the current in the lower MOSFET

ramps up to assume the full inductor current. In Equation 26,

sense element R is cancelled by the integrated

X

temperature compensation function. R in Equation 30

X

should be the resistance of the current sense element at the

room temperature.

the required time for this commutation is t and the

1

When the integrated temperature compensation function is

disabled by pulling the TCOMP pin to GND, the sensed

current will be dependent on the operational temperature of

the power stage, since the DC resistance of the current

sense element may be changed according to the operational

approximated associated power loss is P

.

UP,1

t

I

⎛

⎜

⎝

⎞

⎟

⎠

1

M

PP

2

⎛

⎝

⎞

(EQ. 26)

P

≈ V

f

S

----

----- + --------

UP,1

IN

⎠

2

N

At turn on, the upper MOSFET begins to conduct and this

temperature. R in Equation 30 should be the maximum DC

resistance of the current sense element at all the operational

temperature.

X

transition occurs over a time t . In Equation 27, the

2

approximate power loss is P

.

UP,2

I

t

⎞

2

⎠

⎛I

⎞ ⎛

In certain circumstances, it may be necessary to adjust the

value of one or more ISEN resistors. When the components

of one or more channels are inhibited from effectively

dissipating their heat so that the affected channels run hotter

than desired, choose new, smaller values of RISEN for the

affected phases (see the section titled Channel-Current

PP

2

M

(EQ. 27)

P

≈ V

f

--------⎟ ⎜ ---- ⎟

S

⎜

⎝

----- –

UP,2

IN

N

⎠ ⎝

A third component involves the lower MOSFET’s reverse-

recovery charge, Q . Since the inductor current has fully

commutated to the upper MOSFET before the lower-

MOSFET’s body diode can draw all of Q , it is conducted

through the upper MOSFET across VIN. The power

dissipated as a result is P

rr

Balance). Choose R

in proportion to the desired

ISEN,2

decrease in temperature rise in order to cause proportionally

less current to flow in the hotter phase.

and is approximately

UP,3

P

= V

Q

f

ΔT

(EQ. 28)

UP,3

IN rr S

2

(EQ. 31)

R

= R

----------

ISEN,2

ISEN

ΔT

1

Finally, the resistive part of the upper MOSFET’s is given in

In Equation 31, make sure that ΔT is the desired temperature

2

Equation 29 as P

.

UP,4

rise above the ambient temperature, and ΔT is the measured

1

2

I

⎛

⎞

⎟

⎠

I

temperature rise above the ambient temperature. While a

single adjustment according to Equation 31 is usually

PP

M

(EQ. 29)

P

≈ r

d +

d

---------

12

⎜

⎝

-----

UP,4

DS(ON)

N

sufficient, it may occasionally be necessary to adjust R

two or more times to achieve optimal thermal balance

between all channels.

ISEN

The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results

from Equations 26, 27, 28 and 29. Since the power

FN9276.2

December 20, 2006

24

ISL6327

poles and the ESR zero of the voltage-mode approximation

Load-Line Regulation Resistor

yields a solution that is always stable with very close to ideal

transient performance.

The load-line regulation resistor is labelled R in Figure 5.

FB

Its value depends on the desired loadline requirement of the

application.

C

(OPTIONAL)

2

The desired loadline can be calculated by the following

equation:

C

R

C

V

COMP

FB

DROOP

R

= ------------------------

(EQ. 32)

LL

I

FL

where I is the full load current of the specific application,

FL

and VR

load condition.

is the desired voltage droop under the full

DROOP

+

IDROOP

VDIFF

R

FB

V

DROOP

-

Based on the desired loadline R , the loadline regulation

LL

resistor can be calculated by the following equation:

N

R

LL

ISEN

R

X

(EQ. 33)

R

= ---------------------------------

FB

FIGURE 17. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL6327 CIRCUIT

where N is the active channel number, R

is the sense

resistor connected to the ISEN+ pin, and R is the

ISEN

X

The feedback resistor, R , has already been chosen as

FB

outlined in Load-Line Regulation Resistor. Select a target

resistance of the current sense element, either the DCR of

the inductor or R depending on the sensing method.

SENSE

bandwidth for the compensated system, f . The target

0

If one or more of the current sense resistors are adjusted for

thermal balance, as in Equation 31, the load-line regulation

resistor should be selected based on the average value of

the current sensing resistors, as given in the following

equation:

bandwidth must be large enough to assure adequate

transient performance, but smaller than 1/3 of the per-

channel switching frequency. The values of the

compensation components depend on the relationships of f

0

to the L-C pole frequency and the ESR zero frequency. For

each of the three cases in Equation 35, there are a separate

set of equations for the compensation components.

R

LL

R

= ----------

R

ISEN(n)

(EQ. 34)

∑

FB

R

X

n

where R

the n ISEN+ pin.

is the current sensing resistor connected to

ISEN(n)

1

th

------------------- > f

Case 1:

0

2π LC

Compensation

2πf V

LC

pp

0

R

C

= R -----------------------------------

C

FB

0.75V

IN

The two opposing goals of compensating the voltage

regulator are stability and speed. Depending on whether the

regulator employs the optional load-line regulation as

described in Load-Line Regulation, there are two distinct

methods for achieving these goals.

0.75V

IN

= ------------------------------------

2πV

R

f

PP FB 0

1

-------------------

2π LC

≤ f < -----------------------------

0

2πC(ESR)

Case 2:

COMPENSATING LOAD-LINE REGULATED

CONVERTER

2

V

(2π)

f

LC

0

PP

R

C

= R --------------------------------------------

(EQ. 35)

The load-line regulated converter behaves in a similar

manner to a peak-current mode controller because the two

poles at the output-filter L-C resonant frequency split with

the introduction of current information into the control loop.

The final location of these poles is determined by the system

function, the gain of the current signal, and the value of the

C

FB

0.75 V

IN

0.75V

IN

= ------------------------------------------------------------

2

(2π)

f

V

R

LC

0

PP FB

1

Case 3:

f > -----------------------------

0

2πC(ESR)

compensation components, R and C .

C

2π f V

L

pp

0

Since the system poles and zero are affected by the values

of the components that are meant to compensate them, the

solution to the system equation becomes fairly complicated.

Fortunately there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator by compensating the L-C

R

C

= R

-----------------------------------------

FB

C

0.75 V (ESR)

IN

0.75V (ESR)

C

IN

= -------------------------------------------------

2πV

R

f

L

PP FB 0

FN9276.2

December 20, 2006

25

ISL6327

In Equation 35, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent-series resistance of

In the solutions to the compensation equations, there is a

single degree of freedom. For the solutions presented in

Equation 36, R is selected arbitrarily. The remaining

FB

the bulk output-filter capacitance; and V is the peak-to-

peak sawtooth signal amplitude as described in Electrical

Specifications.

compensation components are then selected according to

Equation 36.

PP

C(ESR)

LC – C(ESR)

R

C

= R ----------------------------------------

FB

1

The optional capacitor C , is sometimes needed to bypass

2

noise away from the PWM comparator (see Figure 18). Keep

a position available for C , and be prepared to install a high-

LC – C(ESR)

2

= ----------------------------------------

R

frequency capacitor of between 22pF and 150pF in case any

leading-edge jitter problem is noted.

FB

0.75V

IN

C

R

= ------------------------------------------------------------------

Once selected, the compensation values in Equation 35

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

(EQ. 36)

2

(2π) f f

LCR

V

0 HF

FB PP

2

improved by making adjustments to R . Slowly increase the

⎛

⎝

⎞

f f LCR

C

V

2π

0 HF

FB

PP

⎠

= --------------------------------------------------------------------

value of R while observing the transient performance on an

C

oscilloscope until no further improvement is noted. Normally,

C

⎛

⎞

LC–1

2πf

0.75 V

⎝

HF

⎠

IN

C

will not need adjustment. Keep the value of C from

C

Equation 35 unless some performance issue is noted.

⎛

⎞

LC–1

0.75V

2πf

IN

⎝

HF

⎠

COMPENSATION WITHOUT LOAD-LINE REGULATION

C

= ------------------------------------------------------------------

C

2

(2π) f f

LCR

V

FB PP

0 HF

The non load-line regulated converter is accurately modeled

as a voltage-mode regulator with two poles at the L-C

resonant frequency and a zero at the ESR frequency. A

type III controller, as shown in Figure 18, provides the

necessary compensation.

In Equation 36, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent-series resistance of

the bulk output-filter capacitance; and V is the peak-to-

PP

peak sawtooth signal amplitude as described in Electrical

Specifications.

C

2

Output Filter Design

C

R

C

The output inductors and the output capacitor bank together

form a low-pass filter responsible for smoothing the pulsating

voltage at the phase nodes. The output filter also must

provide the transient energy until the regulator can respond.

Because it has a low bandwidth compared to the switching

frequency, the output filter necessarily limits the system

transient response. The output capacitor must supply or sink

load current while the current in the output inductors

increases or decreases to meet the demand.

COMP

FB

C

1

IDROOP

VDIFF

R

FB

1

In high-speed converters, the output capacitor bank is

usually the most costly (and often the largest) part of the

circuit. Output filter design begins with minimizing the cost of

this part of the circuit. The critical load parameters in

choosing the output capacitors are the maximum size of the

load step, ΔI; the load-current slew rate, di/dt; and the

maximum allowable output-voltage deviation under transient

FIGURE 18. COMPENSATION CIRCUIT FOR ISL6327 BASED

CONVERTER WITHOUT LOAD-LINE

REGULATION

The first step is to choose the desired bandwidth, f , of the

0

compensated system. Choose a frequency high enough to

assure adequate transient performance but not higher than

1/3 of the switching frequency. The type-III compensator has

loading, ΔV

. Capacitors are characterized according to

MAX

an extra high-frequency pole, f . This pole can be used for

added noise rejection or to assure adequate attenuation at

their capacitance, ESR, and ESL (equivalent series

inductance).

HF

the error-amplifier high-order pole and zero frequencies. A

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

initially deviate by an amount approximated by the voltage

drop across the ESL. As the load current increases, the

good general rule is to choose f = 10f , but it can be

HF

0

higher if desired. Choosing f to be lower than 10f can

HF

0

cause problems with too much phase shift below the system

bandwidth.

FN9276.2

December 20, 2006

26

ISL6327

voltage drop across the ESR increases linearly until the load

Input Supply Voltage Selection

current reaches its final value. The capacitors selected must

have sufficiently low ESL and ESR so that the total output-

voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

response, the output voltage initially deviates by an amount:

The VCC input of the ISL6327 can be connected either

directly to a +5V supply or through a current limiting resistor

to a +12V supply. An integrated 5.8V shunt regulator

maintains the voltage on the VCC pin when a +12V supply is

used. A 300Ω resistor is suggested for limiting the current

into the VCC pin to a worst-case maximum of approximately

25mA.

di

(EQ. 37)

ΔV ≈ (ESL) ---- + (ESR) ΔI

dt

Switching Frequency

The filter capacitor must have sufficiently low ESL and ESR

so that ΔV < ΔV

There are a number of variables to consider when choosing

the switching frequency, as there are considerable effects on

the upper-MOSFET loss calculation. These effects are

outlined in MOSFETs, and they establish the upper limit for

the switching frequency. The lower limit is established by the

requirement for fast transient response and small output-

voltage ripple as outlined in Output Filter Design. Choose the

lowest switching frequency that allows the regulator to meet

the transient-response requirements.

.

MAX

Most capacitor solutions rely on a mixture of high-frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

Switching frequency is determined by the selection of the

The ESR of the bulk capacitors also creates the majority of

the output-voltage ripple. As the bulk capacitors sink and

source the inductor AC ripple current (see Interleaving and

Equation 2), a voltage develops across the bulk-capacitor

frequency-setting resistor, R (see the figures labelled

T

Typical Application on pages 4 and 5). Equation 3 is

provided to assist in selecting the correct value for R .

T

Input Capacitor Selection

ESR equal to I

(ESR). Thus, once the output capacitors

are selected, the maximum allowable ripple voltage,

C,PP

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper

MOSFETs. Their RMS current capacity must be sufficient to

handle the AC component of the current drawn by the upper

MOSFETs that is related to duty cycle and the number of

active phases.

V , determines the lower limit on the inductance.

PP(MAX)

⎛

⎝

⎞

V

– N V

IN

OUT

⎠

(EQ. 38)

L

(ESR)

≥

-----------------------------------------------------------

f V

V

IN PP(MAX)

S

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

0.3

0.2

0.1

ΔV

. This places an upper limit on inductance.

MAX

Equation 39 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 40

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually

less than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of

the two results. In each equation, L is the per-channel

inductance, C is the total output capacitance, and N is the

number of active channels.

I

= 0

L,PP

= 0.5 I

O

= 0.75 I

O

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V /V

)

IN

O

2NCV

O

FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT

vs DUTY CYCLE FOR 2-PHASE CONVERTER

(EQ. 39)

L ≤ --------------------- ΔV

– ΔI(ESR)

MAX

2

(

)

ΔI

(EQ. 40)

(

)

1.25 NC

⎛

⎝

⎞

– V

O

L ≤ ------------------------- ΔV

– ΔI(ESR)

V

MAX

IN

2

⎠

(

ΔI

FN9276.2

December 20, 2006

27

ISL6327

current slew rates produced by the upper MOSFETs turning

0.3

0.2

0.1

0

I

= 0

I

= 0.5 I

O

L,PP

on and off. Select low ESL ceramic capacitors and place one

as close as possible to each upper MOSFET drain to

minimize board parasitic impedances and maximize

suppression.

= 0.25 I

= 0.75 I

O

L,PP

O

L,PP

MULTIPHASE RMS IMPROVEMENT

Figure 22 is provided as a reference to demonstrate the

dramatic reductions in input-capacitor RMS current upon the

implementation of the multiphase topology. For example,

compare the input RMS current requirements of a two-phase

converter versus that of a single phase. Assume both

converters have a duty cycle of 0.25, maximum sustained

output current of 40A, and a ratio of I

to I of 0.5. The

L,PP

O

single phase converter would require 17.3Arms current

capacity while the two-phase converter would only require

10.9Arms. The advantages become even more pronounced

when output current is increased and additional phases are

added to keep the component cost down relative to the

single phase approach.

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

O/ IN

FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT

vs DUTY CYCLE FOR 3-PHASE CONVERTER

For a two phase design, use Figure 19 to determine the

input-capacitor RMS current requirement given the duty

0.6

0.4

0.2

cycle, maximum sustained output current (I ), and the ratio

O

of the per-phase peak-to-peak inductor current (I

) to I .

L,PP

O

Select a bulk capacitor with a ripple current rating which will

minimize the total number of input capacitors required to

support the RMS current calculated. The voltage rating of

the capacitors should also be at least 1.25 times greater

than the maximum input voltage.

Figures 20 and 21 provide the same input RMS current

information for three and four phase designs respectively.

Use the same approach to selecting the bulk capacitor type

and number as described above.

I

= 0

= 0.5 I

= 0.75 I

L,PP

O

0.3

I

= 0

= 0.25 I

I

= 0.5 I

O

L,PP

0

= 0.75 I

0

0.2

0.4

0.6

0.8

1.0

O

DUTY CYCLE (V

V

)

O/ IN

FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS

0.2

0.1

0

CURRENT vs DUTY CYCLE FOR SINGLE-PHASE

CONVERTER

Layout Considerations

The following layout strategies are intended to minimize the

impact of board parasitic impedances on converter

performance and to optimize the heat-dissipating capabilities

of the printed-circuit board. These sections highlight some

important practices which should not be overlooked during the

layout process.

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

O/ IN

Component Placement

FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS CURRENT

vs DUTY CYCLE FOR 4-PHASE CONVERTER

Within the allotted implementation area, orient the switching

components first. The switching components are the most

critical because they carry large amounts of energy and tend

to generate high levels of noise. Switching component

placement should take into account power dissipation. Align

the output inductors and MOSFETs such that spaces

Low capacitance, high-frequency ceramic capacitors are

needed in addition to the bulk capacitors to suppress leading

and falling edge voltage spikes. They result from the high

FN9276.2

December 20, 2006

28

ISL6327

between the components are minimized while creating the

PHASE plane. Place the Intersil MOSFET driver IC as close

as possible to the MOSFETs they control to reduce the

parasitic impedances due to trace length between critical

driver input and output signals. If possible, duplicate the

same placement of these components for each phase.

Plane Allocation and Routing

Dedicate one solid layer, usually a middle layer, for a ground

plane. Make all critical component ground connections with

vias to this plane. Dedicate one additional layer for power

planes; breaking the plane up into smaller islands of

common voltage. Use the remaining layers for signal wiring.

Next, place the input and output capacitors. Position one

high-frequency ceramic input capacitor next to each upper

MOSFET drain. Place the bulk input capacitors as close to

the upper MOSFET drains as dictated by the component

size and dimensions. Long distances between input

capacitors and MOSFET drains result in too much trace

inductance and a reduction in capacitor performance. Locate

the output capacitors between the inductors and the load,

while keeping them in close proximity to the microprocessor

socket.

Route phase planes of copper filled polygons on the top and

bottom once the switching component placement is set. Size

the trace width between the driver gate pins and the

MOSFET gates to carry 4A of current. When routing

components in the switching path, use short wide traces to

reduce the associated parasitic impedances.

The ISL6327 can be placed off to one side or centered

relative to the individual phase switching components.

Routing of sense lines and PWM signals will guide final

placement. Critical small signal components to place close

to the controller include the ISEN resistors, R resistor,

T

feedback resistor, and compensation components.

Bypass capacitors for the ISL6327 and ISL66XX driver bias

supplies must be placed next to their respective pins. Trace

parasitic impedances will reduce their effectiveness.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9276.2

December 20, 2006

29

ISL6327

Package Outline Drawing

L48.7x7

48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 4, 10/06

4X

5.5

7.00

A

44X

6

0.50

B

PIN #1 INDEX AREA

37

48

6

1

36

PIN 1

INDEX AREA

4. 30 ± 0 . 15

12

25

(4X)

0.15

13

24

0.10 M C A B

48X 0 . 40± 0 . 1

TOP VIEW

4

0.23 +0.07 / -0.05

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

0 . 90 ± 0 . 1

BASE PLANE

( 6 . 80 TYP )

4 . 30 )

SEATING PLANE

0.08 C

(

SIDE VIEW

( 44X 0 . 5 )

0 . 2 REF

5

C

( 48X 0 . 23 )

( 48X 0 . 60 )

0 . 00 MIN.

0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN9276.2

December 20, 2006

30


型号：	ISL6327IRZ-T
厂家：	Intersil
描述：	Enhanced 6-Phase PWM Controller with 8-Bit VID Code and Differential Inductor DCR or Resistor Current Sensing 增强型6相PWM控制器，具有8位VID代码和差分电感DCR或电阻电流检测开关控制器
文件：	总30页 (文件大小：660K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6327IRZ-T [INTERSIL]

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