ISL6420BIAZ_技术文档

ISL6420B

®

Data Sheet

April 27, 2009

FN6901.0

Advanced Single Synchronous Buck

Features

Pulse-Width Modulation (PWM) Controller

• Operates From:

- 4.5V to 5.5V Input

- 5.5V to 28V Input

The ISL6420B simplifies the implementation of a complete

control and protection scheme for a high-performance

DC/DC buck converter. It is designed to drive N-channel

MOSFETs in a synchronous rectified buck topology, the

ISL6420B integrates control, output adjustment, monitoring

and protection functions into a single package. Additionally,

the IC features an external reference voltage tracking mode

for externally referenced buck converter applications and

DDR termination supplies, as well as a voltage margining

mode for system testing in networking DC/DC converter

applications.

• 0.6V Internal Reference Voltage

- ±2.0% Reference Accuracy

• Resistor-Selectable Switching Frequency

- 100kHz to 1.4MHz

• Voltage Margining and External Reference Tracking

Modes

• Output Can Sink or Source Current

• Lossless, Programmable Overcurrent Protection

The ISL6420B provides simple, single feedback loop,

voltage mode control with fast transient response. The

output voltage of the converter can be precisely regulated to

as low as 0.6V.

- Uses Upper MOSFET’s r

DS(ON)

• Programmable Soft-Start

• Drives N-Channel MOSFETs

The operating frequency is fully adjustable from 100kHz to

1.4MHz. High frequency operation offers cost and space

savings.

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast Transient Response

The error amplifier features a 15MHz gain-bandwidth

product and 6V/µs slew rate that enables high converter

bandwidth for fast transient response. The PWM duty cycle

ranges from 0% to 100% in transient conditions. Selecting

the capacitor value from the ENSS pin to ground sets a fully

adjustable PWM soft-start. Pulling the ENSS pin LOW

disables the controller.

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Cycle

• Extensive Circuit Protection Functions

- PGOOD, Overvoltage, Overcurrent, Shutdown

• Diode Emulation during Startup for Pre-Biased Load

Applications

The ISL6420B monitors the output voltage and generates a

PGOOD (power good) signal when soft-start sequence is

complete and the output is within regulation. A built-in

overvoltage protection circuit prevents the output voltage

from going above typically 115% of the set point. Protection

from overcurrent conditions is provided by monitoring the

• Offered in 20 Ld QFN and QSOP Packages

• QFN (4x4) Package

- QFN compliant to JEDEC PUB95 MO-220 QFN - Quad

Flat No Leads - Product Outline

- QFN Near Chip Scale Package Footprint; Improves

PCB Efficiency, Thinner in Profile

r

of the upper MOSFET to inhibit the PWM operation

DS(ON)

appropriately. This approach simplifies the implementation

and improves efficiency by eliminating the need for a current

sensing resistor.

• Pb-Free (RoHS Compliant)

Applications

• Power Supplies for Microprocessors/ASICs

- Embedded Controllers

- DSP and Core Processors

- DDR SDRAM Bus Termination

• Ethernet Routers and Switchers

• High-Power DC/DC Regulators

• Distributed DC/DC Power Architecture

• Personal Computer Peripherals

• Externally Referenced Buck Converters

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6420B

Ordering Information

PART NUMBER

(Note)

PART

MARKING

TEMP.

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL6420BIAZ

6420 BIAZ

-40 to +85

20 Ld QSOP

M20.15

ISL6420BIAZ-TK*

ISL6420BIRZ

6420 BIAZ

6420 BIRZ

M20.15

L20.4x4

20 Ld 4x4 QFN

ISL6420BIRZ-TK*

*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Pinouts

ISL6420B

(20 LD QFN)

TOP VIEW

ISL6420B

(20 LD QSOP)

TOP VIEW

1

2

3

4

5

6

7

8

9

PGOOD

ENSS

CDEL

PGND

20

19

20 19 18 17 16

LGATE

18 COMP

17 FB

PVCC

GPIO2

GPIO1/REFIN

OCSET

1

2

3

4

5

15 PGND

14 CDEL

13 PGOOD

12 ENSS

11 COMP

PHASE

16 RT

UGATE

SGND

VIN

15

14

BOOT

GPIO2

13 VCC5

12

REFOUT

GPIO1/REFIN

VMSET/MODE

OCSET 10

11 REFOUT

6

7

8

9

10

FN6901.0

April 27, 2009

2

ISL6420B

Functional Block Diagram

VIN

VCC5

OCSET

SGND

LDO

OVERCURRENT

COMP

+

-

PHASE

OCFLT

BOOT

REFERENCE

0.6V

SS

UGATE

OVFLT

UVFLT

FAULT

LOGIC

PHASE

ERROR

AMP

PHASE

LOGIC

+

-

+

-

FB

PWM

LOGIC

PWM

COMP

PVCC

LGATE

PGND

GPIO1/REFIN

GPIO2

RAMP

GENERATOR

REFOUT

VOLTAGE

MARGINING

VMSET/MODE

OV/UV

VOLTAGE

MONITOR

OVFLT

UVFLT

FB

PGOOD

CDEL

EN/SS

ENSS

OSC

RT

Typical 5V Input DC/DC Application Schematic

5V

C1

C6

C3

C2

C5

R1

C4

PVCC

VIN

VCC5

D1

C9

OCSET

BOOT

MONITOR AND

PROTECTION

ENSS

RT

Q1

UGATE

PHASE

PGOOD

CDEL

OSC

C7

0.1µF

R2

C8

L1

REF

3.3V

SGND

FB

Q2

LGATE

PGND

C10

-

+

-

+

R3

COMP

GPIO1/REFIN

GPIO2

C11

R6

REFOUT

C12

R5

C13

R4

VMSET/MODE

FN6901.0

April 27, 2009

3

ISL6420B

Typical 12V Input DC/DC Application Schematic

12V

C6

C1

C5

R1

C3

C2

C4

VIN PVCC

VCC5

D1

C9

OCSET

MONITOR AND

PROTECTION

ENSS

BOOT

RT

PGOOD

CDEL

Q1

UGATE

PHASE

OSC

R2

C7

L1

REF

3.3V

C8

SGND

FB

Q2

LGATE

PGND

-

+

C10

+

-

R3

COMP

GPIO1/REFIN

GPIO2

C11

R6

REFOUT

C12

R5

C13

R4

VMSET/MODE

Typical 5V Input DC/DC Application Schematic

5V

C6

C1

C3

C5

R1

C2

C4

D1

C8

PVCC

VIN

VCC5

OCSET

MONITOR AND

PROTECTION

SS/EN

BOOT

RT

CDEL

Q1

UGATE

PHASE

OSC

R2

C7

L1

PGOOD

REF

2.5V/1.25V

SGND

FB

Q2

LGATE

PGND

-

+

C9

+

-

R3

COMP

GPIO1/REFIN <-- VREF = VDDQ/2

GPIO2

C10

REFOUT

C11

R5

1.25V VREF

TO REFIN OF VTT SUPPLY

C12

VMSET/MODE

VCC5

R4

CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS

FN6901.0

April 27, 2009

4

ISL6420B

Typical 12V Input DC/DC Application Schematic

12V

C6

C1

C2

C3

C5

R1

C4

VIN PVCC

VCC5

D1

C8

OCSET

MONITOR AND

PROTECTION

SS/EN

BOOT

RT

CDEL

Q1

UGATE

PHASE

OSC

R2

C7

L1

PGOOD

REF

2.5V/1.25V

VDDQ/VTT

SGND

FB

Q2

LGATE

PGND

-

+

C9

+

-

COMP

R5

R3

GPIO1/REFIN <-- VREF = VDDQ/2

GPIO2

C10

C11

REFOUT

C12

1.25V VREF

TO REFIN OF VTT SUPPLY

VMSET/MODE

VCC5

R4

CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS

FN6901.0

April 27, 2009

5

ISL6420B

Absolute Maximum Ratings (Note 1)

Thermal Information

Bias Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30V

BOOT and UGATE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36V

Thermal Resistance (Typical)

θ

(°C/W)

θ

(°C/W)

JC

JA

QFN Package (Notes 2, 3). . . . . . . . . .

QSOP Package (Note 2) . . . . . . . . . . .

47

90

8.5

NA

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Ambient Temperature Range. . . . . . . . -40°C to +85°C (for “I” suffix)

Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. All voltages are with respect to GND.

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions: V = 12V, PV shorted with V

, T = +25°C; Parameters with MIN and/or MAX

A

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

IN

CC

CC5

and are not production tested.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VIN SUPPLY

Input Voltage Range

5.6

12

28

V

VIN SUPPLY CURRENT

Shutdown Current (Note 4)

Operating Current (Notes 4, 5)

VCC5 SUPPLY (Notes 5, 6)

Input Voltage Range

ENSS = GND

-

1.4

2.0

-

mA

3.0

VIN = VCC5 for 5V configuration

4.5

50

5.0

-

5.5

-

V

Output Voltage

VIN = 5.6V to 28V, I = 3mA to 50mA

L

Maximum Output Current

POWER-ON RESET

VIN = 12V

mA

Rising V

CC5

Threshold

VIN connected to VCC5, 5V input

operation

4.310

4.400

4.475

V

Falling V

CC5

Threshold

4.090

0.16

4.100

-

4.250

-

V

UVLO Threshold Hysteresis

PWM CONVERTERS

Maximum Duty Cycle

Minimum Duty Cycle

FB Pin Bias Current

Undervoltage Protection

Overvoltage Protection

OSCILLATOR

f

= 300kHz

90

-

96

-

0

%

SW

-

80

-

nA

%

V

Fraction of the set point; ~3µs noise filter

Fraction of the set point; ~1µs noise filter

75

112

85

120

UV

V

-

%

OVP

Free Running Frequency

Total Variation

RT = VCC5, T = -40°C to +85°C

270

-

300

330

-

kHz

%

A

T

= -40°C to +85°C, with frequency set

±10%

A

by external resistor at RT

Frequency Range (Set by RT)

Ramp Amplitude (Note 7)

VIN = 12V

100

-

1400

-

kHz

ΔV

1.25

V

P-P

OSC

FN6901.0

April 27, 2009

6

ISL6420B

Electrical Specifications Operating Conditions: V = 12V, PV shorted with V

, T = +25°C; Parameters with MIN and/or MAX

A

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

IN

CC

CC5

and are not production tested. (Continued)

PARAMETER

REFERENCE AND SOFT-START/ENABLE

Internal Reference Voltage

Soft-Start Current

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V

0.594

-

10

-

0.606

V

µA

V

REF

I

-

1.0

-

SS

Soft-Start Threshold

V

SOFT

Enable Low (Converter Disabled)

PWM CONTROLLER GATE DRIVERS

Gate Drive Peak Current

Rise Time

-

1.0

V

-

0.7

20

-

A

Co = 1000pF

ns

Fall Time

Dead Time Between Drivers

ERROR AMPLIFIER

DC Gain (Note 7)

-

88

15

6

-

dB

Gain-Bandwidth Product (Note 7)

Slew Rate (Note 7)

GBW

SR

MHz

V/µs

OVERCURRENT PROTECTION

OCSET Current Source

POWER GOOD AND CONTROL FUNCTIONS

Power-Good Lower Threshold

Power-Good Higher Threshold

PGOOD Leakage Current

PGOOD Voltage Low

I

V

= 4.5V

OCSET

80

100

120

µA

OCSET

V

Fraction of the set point; ~3µs noise filter

-14

-10

-8

16

1

%

PG-

V

9

-

PG+

V

= 5.0V (Note 8)

µA

V

PGLKG

PULLUP

I

= 4mA

-

0.5

-

PGOOD

PGOOD Delay

CDEL = 0.1µF

-

125

2

ms

µA

V

CDEL Current for PGOOD

CDEL Threshold

CDEL threshold = 2.5V

-

2.5

-

EXTERNAL REFERENCE

Min External Reference Input at

GPIO1/REFIN

VMSET/MODE = H, C

= 2.2µF

-

0.600

-

V

REFOUT

Max External Reference Input at

GPIO1/REFIN

1.250

REFERENCE BUFFER

Buffered Output Voltage - Internal Reference

V

I

= 1mA,

0.583

0.575

1.227

1.219

0.595

0.587

1.246

1.238

0.607

0.599

1.265

1.257

V

REFOUT

VMSET/MODE = High,

C

= 2.2µF, T = -40°C to +85°C

A

REFOUT

Buffered Output Voltage - Internal Reference

Buffered Output Voltage - External Reference

I

= 20mA,

REFOUT

VMSET/MODE = High,

= 2.2µF, T = -40°C to +85°C

C

REFOUT

A

V

= 1.25V, I

= 1mA,

REFIN

REFOUT

VMSET2/MODE = High,

= 2.2µF

C

REFOUT

V

= 1.25V, I

= 20mA,

REFIN

REFOUT

VMSET2/MODE = High,

= 2.2µF

C

REFOUT

FN6901.0

April 27, 2009

7

ISL6420B

Electrical Specifications Operating Conditions: V = 12V, PV shorted with V

, T = +25°C; Parameters with MIN and/or MAX

A

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

IN

CC

CC5

and are not production tested. (Continued)

PARAMETER

Current Drive Capability

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

C

= 2.2µF

20

-

mA

REFOUT

VOLTAGE MARGINING

Voltage Margining Range (Note 7)

CDEL Current for Voltage Margining

Slew Time

-10

-

+10

%

-

100

2.5

-

µA

ms

µA

CDEL = 0.1µF, VMSET = 330kΩ

ISET1 on FB Pin

VMSET = 330k,

GPIO1 = L

7.48

GPIO2 = H

ISET2 on FB Pin

VMSET = 330k,

GPIO1 = H

-

7.48

-

µA

GPIO2 = L

THERMAL SHUTDOWN

Shutdown Temperature (Note 7)

Thermal Shutdown Hysteresis (Note 7)

NOTES:

-

150

20

-

°C

4. The operating supply current and shutdown current specifications for 5V input are the same as VIN supply current specifications, i.e., 5.6V to

28V input conditions. These should also be tested with part configured for 5V input configuration, i.e., VIN = VCC5 = PVCC = 5V.

5. This is the V

CC

current consumed when the device is active but not switching. Does not include gate drive current.

6. When the input voltage is 5.6V to 28V at VIN pin, the VCC5 pin provides a 5V output capable of 50mA (max) total from the internal LDO. When

the input voltage is 5V, VCC5 pin will be used as a 5V input, the internal LDO regulator is disabled and the VIN must be connected to the VCC5.

In both cases the PVCC pin should always be connected to VCC5 pin (refer to “Pin Descriptions” on page 10 for more details).

7. Limits established by characterization and are not production tested.

8. It is recommended to use VCC5 as the pull-up source.

Typical Performance Curves

0.604

0.602

0.600

0.598

0.596

0.594

320

310

300

290

280

270

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

FIGURE 1. V

vs TEMPERATURE

REF

FIGURE 2. V

vs TEMPERATURE

SW

FN6901.0

April 27, 2009

8

ISL6420B

Typical Performance Curves (Continued)

94

92

90

88

86

84

82

80

1.15

I

= 5A

OUT

1.05

0.95

0.85

0

5

10

15

(V)

20

25

30

-40

-15

10

35

60

85

V

TEMPERATURE (°C)

IN

FIGURE 3. I

vs TEMPERATURE

FIGURE 4. EFFICIENCY vs V

IN

OCSET

+25°C, V = 28V, I = 1.367, I

= 10A

IN

OUT

FIGURE 5.

FIGURE 6.

98

96

94

92

90

88

86

84

82

80

V

= 5V

IN

V

= 12V

IN

0

1

2

3

4

5

6

7

8

9

10

LOAD (A)

FIGURE 7. EFFICIENCY vs LOAD CURRENT (V

= 3.3V)

OUT

FN6901.0

April 27, 2009

9

ISL6420B

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

Pin Descriptions

VIN

This pin powers the controller and must be decoupled to

ground using a ceramic capacitor as close as possible to the

VIN pin.

TABLE 1. INPUT SUPPLY CONFIGURATION

INPUT

PIN CONFIGURATION

5.5V to 28V Connect the input to the VIN pin. The VCC5 pin will

provide a 5V output from the internal LDO. Connect

PVCC to VCC5.

5V ±10% Connect the input to the VCC5 pin. Connect the PVCC

and VIN pins to VCC5.

0

25

50

75

100

125

150

RT (kΩ)

FIGURE 8. OSCILLATOR FREQUENCY vs RT

SGND

100kHz to 1.4MHz. Figure 8 shows the oscillator frequency

vs the RT resistance.

This pin provides the signal ground for the IC. Tie this pin to

the ground plane through the lowest impedance connection.

CDEL

LGATE

The PGOOD signal can be delayed by a time proportional to

a CDEL current of 2µA and the value of the capacitor

connected between this pin and ground. A 0.1µF will

typically provide 125ms delay. When in the Voltage

Margining mode, the CDEL current is 100µA typical and

provides the delay for the output voltage slew rate, 2.5ms

typical for the 0.1µF capacitor.

This pin provides the PWM-controlled gate drive for the lower

MOSFET.

PHASE

This pin is the junction point of the output filter inductor, the

upper MOSFET source and the lower MOSFET drain. This

pin is used to monitor the voltage drop across the upper

MOSFET for overcurrent protection. This pin also provides a

return path for the upper gate drive.

PGND

This pin provides the power ground for the IC. Tie this pin to

the ground plane through the lowest impedance connection.

UGATE

This pin provides the PWM-controlled gate drive for the upper

MOSFET.

PVCC

This pin is the power connection for the gate drivers.

Connect this pin to the VCC5 pin.

BOOT

This pin powers the upper MOSFET driver. Connect this pin

to the junction of the bootstrap capacitor and the cathode of

the bootstrap diode. The anode of the bootstrap diode is

connected to the VCC5 pin.

VCC5

This pin is the output of the internal 5V LDO. Connect a

minimum of 4.7µF ceramic decoupling capacitor as close to

the IC as possible at this pin. Refer to Table 1.

FB

ENSS

This pin is connected to the feedback resistor divider and

provides the voltage feedback signal for the controller. This

pin sets the output voltage of the converter.

This pin provides enable/disable function and soft-start for

the PWM output. The output drivers are turned off when this

pin is held below 1V.

COMP

OCSET

This pin is the error amplifier output pin. It is used as the

compensation point for the PWM error amplifier.

Connect a resistor (R ) and a capacitor from this pin to

the drain of the upper MOSFET. R , an internal 100µA

current source (I

resistance r

point.

OCSET

PGOOD

), and the upper MOSFET on

OCSET

set the converter overcurrent (OC) trip

This pin provides a power good status. It is an open collector

output used to indicate the status of the output voltage.

DS(ON)

RT

This is the oscillator frequency selection pin. Connecting this

pin directly to VCC5 will select the oscillator free running

frequency of 300kHz. By placing a resistor from this pin to

GND, the oscillator frequency can be programmed from

FN6901.0

April 27, 2009

10

ISL6420B

TABLE 2. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION

PIN CONFIGURATIONS

GPIO1/REFIN

GPIO2

FUNCTION/MODES

VMSET/MODE

REFOUT

(Note 9)

Enable Voltage Margining

Pin Connected to GND Connect a 2.2µF capacitor Serves as a general

Serves as a general

purpose I/O. Refer to

Table 3.

with resistor. It is used for bypass of external

purpose I/O. Refer to

Table 3.

as VMSET.

reference.

No Voltage Margining. Normal operation

with internal reference. Buffered

H

Connect a 2.2µF capacitor

to GND.

H (Note 10)

L

V

= 0.6V.

REFOUT

No Voltage Margining. External

Connect a 2.2µF capacitor Connect to an external

L

reference. Buffered V

= V

to GND.

reference voltage source

(0.6V to 1.25V)

REFOUT

REFIN

NOTES:

9. The GPIO1/REFIN and GPIO2 pins cannot be left floating.

10. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.

GPIO1/REFIN

TABLE 3. VOLTAGE MARGINING CONTROLLED BY GPIO1

AND GPIO2

This is a dual function pin. If VMSET/MODE is not connected

to VCC5 then this pin serves as GPIO1. Refer to Table 3 for

GPIO commands interpretation.

GPIO1

GPIO2

VOUT

No Change

+ΔVOUT

-ΔVOUT

Ignored

L

H

L

If VMSET/MODE is connected to VCC5 then this pin will

serve as REFIN. As REFIN, this pin is the non-inverting input

to the error amplifier. Connect the desired reference voltage

to this pin in the range of 0.6V to 1.25V.

H

Functional Description

Connect this pin to VCC5 to use internal reference.

Initialization

REFOUT

The ISL6420B automatically initializes upon receipt of power.

The Power-On Reset (POR) function monitors the internal bias

voltage generated from LDO output (VCC5) and the ENSS pin.

The POR function initiates the soft-start operation after the

VCC5 exceeds the POR threshold. The POR function inhibits

operation with the chip disabled (ENSS pin <1V).

It provides buffered reference output for REFIN. Connect

2.2µF decoupling capacitor to this pin.

VMSET/MODE

This pin is a dual function pin. Tie this pin to VCC5 to disable

voltage margining. When not tied to VCC5, this pin serves as

VMSET. Connect a resistor from this pin to ground to set

delta for voltage margining. If voltage margining and external

reference tracking mode are not needed, this pin can be tied

directly to ground.

The device can operate from an input supply voltage of 5.6V

to 28V connected directly to the VIN pin using the internal 5V

linear regulator to bias the chip and supply the gate drivers.

For 5V ±10% applications, connect VIN to VCC5 to bypass

the linear regulator.

GPIO2

This is general purpose IO pin for voltage margining. Refer

to Table 3.

Soft-Start/Enable

The ISL6420B soft-start function uses an internal current

source and an external capacitor to reduce stresses and

surge current during start-up.

Exposed Thermal Pad

This pad is electrically isolated. Connect this pad to the

signal ground plane using at least five vias for a robust

thermal conduction path.

When the output of the internal linear regulator reaches the

POR threshold, the POR function initiates the soft-start

sequence. An internal 10µA current source charges an

external capacitor on the ENSS pin linearly from 0V to 3.3V.

When the ENSS pin voltage reaches 1V typically, the

internal 0.6V reference begins to charge following the dv/dt

of the ENSS voltage. As the soft-start pin charges from 1V to

1.6V, the reference voltage charges from 0V to 0.6V.

Figure 9 shows a typical soft-start sequence.

FN6901.0

April 27, 2009

11

ISL6420B

During soft-start, pulse termination current limiting is

V

= 28V, V

OUT

= 3.3V, I = 10A

OUT

IN

enabled, but the 8-cycle hiccup counter is held in reset until

soft-start is completed. Figure 10 shows the overcurrent

hiccup mode.

The overcurrent function will trip at a peak inductor current

(I ) determined from Equation 1, where I

is the

OC

OCSET

internal OCSET current source.

I

• R

OCSET

(EQ. 1)

---------------------------------------------------

I

=

OC

r

DS(ON)

The OC trip point varies mainly due to the upper MOSFETs

variations. To avoid overcurrent tripping in the normal

r

DS(ON)

operating load range, find the R

with:

resistor from Equation 1

OCSET

FIGURE 9. TYPICAL SOFT-START WAVEFORM

1. The maximum r

temperature.

at the highest junction

DS(ON)

2. Determine I

for I

OC

> I

+ (ΔI) ⁄ 2 ,

OUT(MAX)

OC

VOUT

where ΔI is the output inductor ripple current.

A small ceramic capacitor should be placed in parallel with

IOUT

R

to smooth the voltage across R in the

OCSET

PHASE

presence of switching noise on the input voltage.

Voltage Margining

ENSS

The ISL6420B has a voltage margining mode that can be

used for system testing. The voltage margining percentage

is resistor selectable up to ±10%. The voltage margining

mode can be enabled by connecting a margining set resistor

from VMSET pin to ground and using the control pins

GPIO1/2 to toggle between positive and negative margining

(Refer to Table 2). With voltage margining enabled, the

VMSET resistor to ground will set a current, which is

switched to the FB pin. The current will be equal to 2.468V

divided by the value of the external resistor tied to the

VMSET pin.

FIGURE 10. TYPICAL OVERCURRENT HICCUP MODE

Overcurrent Protection

The overcurrent function protects the converter from a shorted

output by using the upper MOSFET’s ON-resistance, r

DS(ON)

to monitor the current. This method enhances the converter’s

efficiency and reduces cost by eliminating a current sensing

resistor.

2.468V

The overcurrent function cycles the soft-start function in a

hiccup mode to provide fault protection. A resistor connected

to the drain of the upper FET and the OCSET pin programs

the overcurrent trip level. The PHASE node voltage will be

compared against the voltage on the OCSET pin, while the

upper FET is on. A current (100µA typically) is pulled from the

OCSET pin to establish the OCSET voltage. If PHASE is

lower than OCSET while the upper FET is on then an

overcurrent condition is detected for that clock cycle. The

upper gate pulse is immediately terminated, and a counter is

incremented. If an overcurrent condition is detected for

8 consecutive clock cycles, and the circuit is not in soft-start,

the ISL6420B enters into the soft-start hiccup mode. During

hiccup, the external capacitor on the ENSS pin is discharged.

After the capacitor is discharged, it is released and a soft-start

cycle is initiated. There are three dummy soft-start delay

cycles to allow the MOSFETs to cool down, to keep the

average power dissipation in hiccup mode at an acceptable

level. At the fourth soft-start cycle, the output starts a normal

soft-start cycle, and the output tries to ramp.

-----------------------

I

=

(EQ. 2)

VM

R

VMSET

R

FB

-----------------------

ΔV

= 2.468V

VM

R

(EQ. 3)

VMSET

The power supply output increases when GPIO2 is HIGH

and decreases when GPIO1 is HIGH. The amount that the

output voltage of the power supply changes with voltage

margining, will be equal to 2.468V times the ratio of the

external feedback resistor and the external resistor tied to

VMSET. Figure 11 shows the positive and negative

margining for a 3.3V output, using a 20.5kΩ feedback

resistor and using various VMSET resistor values.

FN6901.0

April 27, 2009

12

ISL6420B

V

= 12V, V

= 3.3V, I

= 10A

OUT

IN

OUT

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3.0

2.9

2.8

150 175 200 225 250 275 300 325 350 375 400

RVMSET (kΩ)

FIGURE 11. VOLTAGE MARGINING vs VMSET RESISTANCE

FIGURE 13. PGOOD DELAY

V

IN

= 12V, V

OUT

= 3.3V, NO LOAD

The slew time of the current is set by an external capacitor on

the CDEL pin, which is charged and discharged with a 100µA

current source. The change in voltage on the capacitor is 2.5V.

This same capacitor is used to set the PGOOD active delay

after soft-start. When PGOOD is low, the internal PGOOD

circuitry uses the capacitor and when PGOOD is high, the

voltage margining circuit uses the capacitor. The slew time for

voltage margining can be in the range of 300µs to 2ms.

External Reference/DDR Supply

The voltage margining can be disabled by connecting the

VMSET/MODE to VCC5. In this mode, the chip can be

configured to work with an external reference input and

provide a buffered reference output.

If the VMSET/MODE pin and the GPIO1/REFIN pin are both

tied to VCC5, then the internal 0.6V reference is used as the

error amplifier non-inverting input. The buffered reference

output on REFOUT will be 0.6V ±0.01V, capable of sourcing

20mA and sinking up to 50µA current with a 2.2µF capacitor

connected to the REFOUT pin.

FIGURE 12A.

V

IN

= 12V, V

= 3.3V, NO LOAD

OUT

If the VMSET/MODE pin is tied to high but GPIO1/REFIN is

connected to an external voltage source between 0.6V to

1.25V, then this external voltage is used as the reference

voltage at the positive input of the error amplifier. The

buffered reference output on REFOUT will be Vrefin ±0.01V,

capable of sourcing 20mA and sinking up to 50µA current

with a 2.2µF capacitor on the REFOUT pin.

Power-Good

The PGOOD pin can be used to monitor the status of the

output voltage. PGOOD will be true (open drain) when the

FB pin is within ±10% of the reference and the ENSS pin has

completed its soft-start ramp.

FIGURE 12B.

Additionally, a capacitor on the CDEL pin will set a delay for the

PGOOD signal. After the ENSS pin completes its soft-start

ramp, a 2µA current begins charging the CDEL capacitor to

2.5V. The capacitor will be quickly discharged before PGOOD

goes high. The programmable delay can be used to sequence

multiple converters or as a LOW-true reset signal.

FN6901.0

April 27, 2009

13

ISL6420B

If the voltage on the FB pin exceeds ±10% of the reference,

then PGOOD will go low after 1µs of noise filtering.

negative during soft-start and thus will not discharge the

pre-biased load. The waveform for this condition is shown in

Figure 14.

Over-Temperature Protection

V

= 12V, V = 3.3V at 25mA LOAD

OUT

The IC is protected against over-temperature conditions.

When the junction temperature exceeds +150°C, the PWM

shuts off. Normal operation is resumed when the junction

temperature is cooled down to +130°C.

IN

Shutdown

When ENSS pin is below 1V, the regulator is disabled with

the PWM output drivers tri-stated. When disabled, the IC

power will be reduced.

Undervoltage

If the voltage on the FB pin is less than 15% of the reference

voltage for 8 consecutive PWM cycles, then the circuit enters

into soft-start hiccup mode. This mode is identical to the

overcurrent hiccup mode.

Overvoltage Protection

FIGURE 14. PREBIASED OUTPUT AT 25mA LOAD

If the voltage on the FB pin exceeds the reference voltage by

15%, the lower gate driver is turned on continuously to

discharge the output voltage. If the overvoltage condition

continues for 32 consecutive PWM cycles, then the chip is

turned off with the gate drivers tri-stated. The voltage on the

FB pin will fall and reach the 15% undervoltage threshold.

After 8 clock cycles, the chip will enter soft-start hiccup mode.

This mode is identical to the overcurrent hiccup mode.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding.

Gate Control Logic

The gate control logic translates generated PWM control

signals into the MOSFET gate drive signals providing

necessary amplification, level shifting and shoot-through

protection. Also, it has functions that help optimize the IC

performance over a wide range of operational conditions.

Figure 16 shows the critical power components of the

converter. To minimize the voltage overshoot the

interconnecting wires indicated by heavy lines should be part

of ground or power plane in a printed circuit board. The

components shown in Figure 16 should be located as close

Since MOSFET switching time can vary dramatically from

type to type and with the input voltage, the gate control logic

provides adaptive dead time by monitoring the gate-to-

source voltages of both upper and lower MOSFETs. The

lower MOSFET is not turned on until the gate-to-source

voltage of the upper MOSFET has decreased to less than

approximately 1V. Similarly, the upper MOSFET is not turned

on until the gate-to-source voltage of the lower MOSFET has

decreased to less than approximately 1V. This allows a wide

variety of upper and lower MOSFETs to be used without a

concern for simultaneous conduction, or shoot-through.

together as possible. Please note that the capacitors C

IN

and C each represent numerous physical capacitors.

O

Locate the ISL6420B within 3 inches of the MOSFETs, Q1

and Q2. The circuit traces for the MOSFETs’ gate and

source connections from the ISL6420B must be sized to

handle up to 1A peak current.

Figure 15 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

current paths on the SS PIN and locate the capacitor, C

close to the SS pin because the internal current source is

Startup into Pre-Biased Load

The ISL6420B is designed to power-up into a pre-biased

load. This is achieved by transitioning from Diode Emulation

mode to a Forced Continuous Conduction mode during

startup. The lower gate turns ON for a short period of time

and the voltage on the phase pin is sensed. When this goes

negative the lower gate is turned OFF and remains OFF till

the next cycle. As a result, the inductor current will not go

ss

only 10µA. Provide local V

decoupling between VCC and

CC

GND pins. Locate the capacitor, C

to the BOOT and PHASE pins.

as close as practical

BOOT

FN6901.0

April 27, 2009

14

ISL6420B

+V

Q1

IN

V

BOOT

IN

D1

OSC

DRIVER

C

L

O

BOOT

PHASE

+5V

PWM

V

OUT

L

ISL6420B

O

COMPARATOR

V

OUT

-

SS/EN

PHASE

+

ΔV

OSC

C

Q2

O

ESR

(PARASITIC)

VCC

C

VCC

C

SS

Z

FB

V

E/A

GND

Z

-

IN

+

REFERENCE

ERROR

AMP

FIGURE 15. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

DETAILED COMPENSATION COMPONENTS

Z

FB

V

IN

V

OUT

C2

Z

IN

C1

C3

R3

R2

ISL6420B

R1

COMP

UGATE

Q1

Q2

L

O

FB

V

OUT

-

+

PHASE

R

4

C

IN

ISL6420B

C

D2

O

REF

LGATE

GND

R

⎛

⎞

1

V

= V

× 1 + ------

⎜

⎟

OUT

REF

R

⎝

⎠

4

RETURN

FIGURE 17. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

FIGURE 16. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

Modulator Break Frequency Equations

Feedback Compensation

1

--------------------------------------

F

=

(EQ. 4)

(EQ. 5)

Figure 17 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(Vout) is regulated to the Reference voltage level. The error

amplifier (Error Amp) output (V ) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width

LC

2π •

L

• C

O

1

--------------------------------------------

F

=

ESR

E/A

2π • (ESR • C

)

O

modulated (PWM) wave with an amplitude of V at the

PHASE node. The PWM wave is smoothed by the output filter

IN

The compensation network consists of the error amplifier

(internal to the ISL6420B) and the impedance networks Z

IN

(L and C ).

O

and Z . The goal of the compensation network is to provide

FB

The modulator transfer function is the small-signal transfer

a closed loop transfer function with the highest 0dB crossing

function of Vout/V . This function is dominated by a DC

frequency (f

) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f and

E/A

0dB

Gain and the output filter (L and C ), with a double pole

O

0dB

180°. The following equations relate the compensation

break frequency at F and a zero at F

. The DC Gain of

LC

ESR

the modulator is simply the input voltage (V ) divided by the

IN

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 17. Use the following

guidelines for locating the poles and zeros of the

compensation network.

peak-to-peak oscillator voltage ΔV

.

OSC

FN6901.0

April 27, 2009

15

ISL6420B

The compensation gain uses external impedance networks

and Z to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin.

Compensation Break Frequency Equations

Z

FB

IN

1

----------------------------------

F

=

(EQ. 6)

(EQ. 7)

Z1

P1

2π • R2 • C1

1

------------------------------------------------------

C1 • C2

⎛

⎞

----------------------

2π • R2 •

⎝

⎠

C1 + C2

Component Selection Guidelines

1

-----------------------------------------------------

F

=

Output Capacitor Selection

(EQ. 8)

(EQ. 9)

Z2

P2

2π • (R1 + R3) • C3

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

1

----------------------------------

=

2π • R3 • C3

1. Pick Gain (R2/R1) for desired converter bandwidth

ST

2. Place 1 Zero Below Filter’s Double Pole

(~75% F

ND

3. Place 2

)

LC

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

Zero at Filter’s Double Pole

ST

4. Place 1 Pole at the ESR Zero

ND

5. Place 2

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 18 shows an asymptotic plot of the DC/DC

converter’s gain vs frequency. The actual Modulator Gain

has a high gain peak due to the high Q factor of the output

filter and is not shown in Figure 18. Using the previously

mentioned guidelines should give a Compensation Gain

similar to the curve plotted. The open loop error amplifier

gain bounds the compensation gain. Check the

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements. For example, Intel

recommends that the high frequency decoupling for the

Pentium Pro be composed of at least forty (40) 1.0µF

ceramic capacitors in the 1206 surface-mount package.

compensation gain at F with the capabilities of the error

P2

amplifier. The Loop Gain is constructed on the log-log graph

of Figure 18 by adding the Modulator Gain (in dB) to the

Compensation Gain (in dB). This is equivalent to multiplying

the modulator transfer function to the compensation transfer

function and plotting the gain.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors.

The bulk capacitor’s ESR will determine the output ripple

voltage and the initial voltage drop after a high slew-rate

transient. An aluminum electrolytic capacitor's ESR value is

related to the case size with lower ESR available in larger

case sizes. However, the equivalent series inductance (ESL)

of these capacitors increases with case size and can reduce

the usefulness of the capacitor to high slew-rate transient

loading. Unfortunately, ESL is not a specified parameter.

Work with your capacitor supplier and measure the

capacitor’s impedance with frequency to select a suitable

component. In most cases, multiple electrolytic capacitors of

small case size perform better than a single large case

capacitor.

100

F

P1

F

Z2

Z1

P2

80

60

40

20

0

OPEN LOOP

ERROR AMP GAIN

20LOG

(R2/R1)

20LOG

(V /ΔV

)

OSC

IN

COMPENSATION

GAIN

MODULATOR

GAIN

-20

-40

-60

CLOSED LOOP

GAIN

F

LC

F

ESR

Output Inductor Selection

10

100

1k

10k

100k

1M

10M

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transients. The inductor value determines

the converter’s ripple current and the ripple voltage is a

function of the ripple current and the output capacitors ESR.

FREQUENCY (Hz)

FIGURE 18. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

FN6901.0

April 27, 2009

16

ISL6420B

The ripple voltage and current are approximated by

Equations 10 and 11:

guideline. The RMS current rating requirement for the input

capacitor of a buck regulator is approximately 1/2 the DC

load current. Equation 14 shows a more specific formula for

determining the input ripple:

V

- V

V

OUT OUT

IN

------------------------------- ---------------

ΔI =

⋅

(EQ. 10)

(EQ. 11)

L

Fs x L

V

IN

2

I

= I

⋅

MAX

(D – D )

(EQ. 14)

RMS

ΔV

= ΔI ⋅ ESR

OUT

L

For a through hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo

MV-GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge current

rating. These capacitors must be capable of handling the

surge-current at power-up. The TPS series available from

AVX, and the 593D series from Sprague are both surge

current tested.

Increasing the value of inductance reduces the ripple current

and voltage. However, larger inductance values reduce the

converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6420B will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

MOSFET Selection/Considerations

The ISL6420B requires 2 N-Channel power MOSFETs.

These should be selected based upon r

, gate supply

DS(ON)

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

components; conduction loss and switching loss. The

conduction losses are the largest component of power

dissipation for both the upper and the lower MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor (see Equations 15 and 16). Only the

upper MOSFET has switching losses, since the Schottky

rectifier clamps the switching node before the synchronous

rectifier turns on.

The response time to a transient is different for the

application of load and the removal of load. Equations 12

and 13 give the approximate response time interval for

application and removal of a transient load:

L

× I

TRAN

O

-------------------------------

t

=

(EQ. 12)

(EQ. 13)

RISE

FALL

V

– V

OUT

IN

L

× I

O

TRAN

------------------------------

V

OUT

2

O

1

2

where: I

is the transient load current step, t

is the

TRAN

response time to the application of load, and t

RISE

is the

--

P

= I ⋅ r

⋅ D +

I

⋅ V ⋅ t ⋅ f

IN sw sw

(EQ. 15)

(EQ. 16)

UFET

LFET

DS(ON)

O

FALL

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the

output voltage setting. Be sure to check both of these

equations at the minimum and maximum output levels for

the worst case response time.

2

P

= I ⋅ r

⋅ (1 – D)

O

DS(ON)

Where D is the duty cycle = Vo/Vin, t

interval, and f

SW

is the switching

is the switching frequency.

SW

These equations assume linear voltage-current transitions

and do not adequately model power loss due the reverse

recovery of the lower MOSFET’s body diode. The gate-charge

losses are dissipated by the ISL6420B and don't heat the

MOSFETs. However, large gate-charge increases the

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q1 turns on. Place the

small ceramic capacitors physically close to the MOSFETs

and between the drain of Q1 and the source of Q2.

switching interval, t

which increases the upper MOSFET

SW

switching losses. Ensure that both MOSFETs are within their

maximum junction temperature at high ambient temperature

by calculating the temperature rise according to package

thermal-resistance specifications. A separate heatsink may be

necessary depending upon MOSFET power, package type,

ambient temperature and air flow.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25x greater than the maximum input

voltage and a voltage rating of 1.5x is a conservative

FN6901.0

April 27, 2009

17

ISL6420B

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor

swing during the dead time between turning off the lower

MOSFET and turning on the upper MOSFET. The diode must

be a Schottky type to prevent the parasitic MOSFET body

diode from conducting. It is acceptable to omit the diode and

let the body diode of the lower MOSFET clamp the negative

inductor swing, but efficiency will drop one or two percent as a

result. The diode's rated reverse breakdown voltage must be

greater than the maximum input voltage.

FN6901.0

April 27, 2009

18

ISL6420B

Package Outline Drawing

L20.4x4

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 11/06

4X

2.0

4.00

0.50

16X

A

6

B

16

20

PIN #1 INDEX AREA

6

PIN 1

INDEX AREA

1

15

2 . 10 ± 0 . 15

11

5

(4X)

0.15

6

10

0.10 M

C

A B

4

0.25 +0.05 / -0.07

TOP VIEW

20X 0.6 +0.15 / -0.25

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

0 . 90 ± 0 . 1

C

BASE PLANE

( 3. 6 TYP )

(

SEATING PLANE

0.08 C

( 20X 0 . 5 )

2. 10 )

SIDE VIEW

0 . 2 REF

( 20X 0 . 25 )

( 20X 0 . 8)

5

C

0 . 00 MIN.

0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN6901.0

April 27, 2009

19

ISL6420B

Shrink Small Outline Plastic Packages (SSOP)

Quarter Size Outline Plastic Packages (QSOP)

M20.15

N

20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

(0.150” WIDE BODY)

INDEX

AREA

0.25(0.010)

M

B M

H

E

GAUGE

PLANE

INCHES

MIN

MILLIMETERS

-B-

SYMBOL

MAX

0.069

0.010

0.061

0.012

0.010

0.344

0.157

MIN

1.35

0.10

-

MAX

1.75

0.25

1.54

0.30

0.25

8.74

3.98

NOTES

A

A1

A2

B

0.053

0.004

-

1

2

3

-

L

0.25

0.010

SEATING PLANE

A

-

-A-

0.008

0.007

0.337

0.150

0.20

0.18

8.56

3.81

9

D

h x 45°

C

D

E

-

-C-

3

α

4

A2

e

A1

C

e

0.025 BSC

0.635 BSC

-

B

0.10(0.004)

H

h

0.228

0.0099

0.016

0.244

0.0196

0.050

5.80

0.26

0.41

6.19

0.49

1.27

-

0.17(0.007) M

C

A M B S

5

NOTES:

L

6

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

N

α

20

7

0°

8°

0°

8°

-

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

Rev. 1 6/04

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable dam-

bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” di-

mension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6901.0

April 27, 2009

20


型号：	ISL6420BIAZ
厂家：	Intersil
描述：	Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller 高级单同步降压脉宽调制（ PWM ）控制器开关光电二极管控制器
文件：	总20页 (文件大小：530K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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