ISL6439CR_技术文档

ISL6439

®

Data Sheet

July 2004

FN9057.4

Single Sync Buck PWM Controller for

Broadband Gateway Applications

Features

• Operates from 3.3V to 5V Input

The ISL6439 makes easy work out of implementing a

complete control and protection scheme for a DC-DC

stepdown converter. Designed to drive N-Channel

MOSFETs in a synchronous buck topology, the ISL6439

integrates the control, output adjustment, monitoring and

protection functions into a single package.

• 0.8V to V Output Range

IN

- 0.8V Internal Reference

- ±1.5% Over Load, Line Voltage and Temperature

• Drives N-Channel MOSFETs

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

The ISL6439 provides simple, single feedback loop, voltage-

mode control with fast transient response. The output

voltage can be precisely regulated to as low as 0.8V, with a

maximum tolerance of ±1.5% over temperature and line

voltage variations. A fixed frequency oscillator reduces

design complexity, while balancing typical application cost

and efficiency.

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Cycle

• Lossless, Programmable Overcurrent Protection

- Uses Upper MOSFET’s r

DS(on)

The error amplifier features a 15MHz gain-bandwidth

product and 6V/µs slew rate which enables high converter

bandwidth for fast transient performance. The resulting PWM

duty cycles range from 0% to 100%.

• Converter can Source and Sink Current

• Small Converter Size

- Internal Fixed Frequency Oscillator

-

ISL6439: 300kHz

ISL6439A: 600kHz

Protection from overcurrent conditions is provided by

monitoring the r

of the upper MOSFET to inhibit PWM

DS(ON)

• Internal Soft-Start

operation appropriately. This approach simplifies the

implementation and improves efficiency by eliminating the

need for a current sense resistor.

• 14 Pin SOIC or 16 Lead 5x5 QFN

• QFN Package:

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

No Lead - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

• Pb-free available

Applications

• Cable Modems, Set Top Boxes, and DSL Modems

• DSP and Core Communications Processor Supplies

• Memory Supplies

• Personal Computer Peripherals

• Industrial Power Supplies

• 3.3V-Input DC-DC Regulators

• Low-Voltage Distributed Power Supplies

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL6439

Ordering Information

Pinouts

14 LEAD SOIC

TEMP

TOP VIEW

o

PART NUMBER RANGE ( C)

PACKAGE

PKG DWG. #

M14.15

GND

1

2

3

4

5

6

7

14 UGATE

ISL6439CB

0 to 70

14 lead SOIC

BOOT

PHASE

VCC

13

12

11

LGATE

CPVOUT

CT1

ISL6439CBZ

(See Note)

14 lead SOIC

(Pb-free)

M14.15

ISL6439IB

-40 to 85

14 lead SOIC

M14.15

10 CPGND

CT2

ISL6439IBZ

(See Note)

14 lead SOIC

(Pb-free)

9

8

ENABLE

COMP

OCSET

FB

ISL6439AIB

-40 to 85

14 lead SOIC

M14.15

ISL6439AIBZ

(See Note)

14 lead SOIC

(Pb-free)

16 LEAD 5x5 QFN

TOP VIEW

ISL6439IR

-40 to 85

16 Lead 5x5 QFN L16.5x5B

ISL6439IRZ

(See Note)

16 Lead 5x5 QFN L16.5x5B

(Pb-free)

16 15 14 13

ISL6439AIR

-40 to 85

16 Lead 5x5 QFN L16.5x5B

CPVOUT

1

2

3

4

12 PHASE

11 VCC

ISL6439AIRZ

(See Note)

16 Lead 5x5 QFN L16.5x5B

(Pb-free)

CT1

CT2

ISL6439EVAL1 ISL6439 SOIC Evaluation Board

ISL6439EVAL2 ISL6439 QFN Evaluation Board

ISL6439AEVAL1 ISL6439A SOIC Evaluation Board

ISL6439AEVAL2 ISL6439A QFN Evaluation Board

Add “-T” suffix to part number for tape and reel packaging.

10

9

CPGND

NC

OCSET

5

6

7

8

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which is compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J Std-020B.

2

ISL6439

Typical Application - 3.3V Input

3.3V

V

IN

C

IN

C

BULK

VCC

OCSET

CT1

CT2

R

OCSET

C

PUMP

CPVOUT

ISL6439

D

C

BOOT

C

DCPL

C

HF

BOOT

CPGND

GND

BOOT

UGATE

PHASE

Q

1

L

OUT

C

V

OUT

ENABLE

COMP

LGATE

OUT

2

FB

DISABLE

C

I

R

FB

R

C

F

R

OFFSET

3

ISL6439

Typical Application - 5V Input

+5V

V

IN

C

BULK

VCC

OCSET

CT1

CT2

R

OCSET

CPVOUT

ISL6439

D

C

BOOT

N/C

C

IN

C

HF

BOOT

CPGND

GND

UGATE

PHASE

Q

1

L

OUT

C

V

OUT

ENABLE

COMP

LGATE

OUT

2

FB

DISABLE

C

I

R

FB

R

C

F

R

OFFSET

Block Diagram

VCC

CPVOUT

CT1

CT2

CHARGE

PUMP

POWER-ON

ENABLE

RESET (POR)

CPGND

OCSET

BOOT

+

-

SOFTSTART

OC

UGATE

COMPARATOR

20µA

PHASE

PWM

COMPARATOR

ERROR

AMP

GATE

CONTROL

LOGIC

+

-

+

-

+

-

PWM

0.8V

LGATE

FB

OSCILLATOR

COMP

FIXED 300kHz or 600kHz

GND

4

ISL6439

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V

Absolute Boot Voltage, V . . . . . . . . . . . . . . . . . . . . . . . +15.0V

Thermal Resistance

θ

( C/W)

θ

( C/W)

JA

JC

BOOT

Upper Driver Supply Voltage, V

SOIC Package (Note 1) . . . . . . . . . . . .

QFN Package (Note 2). . . . . . . . . . . . .

67

35

N/A

5

- V

. . . . . . . . . . . +6.0V

BOOT

PHASE

o

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

o

(SOIC - Lead Tips Only)

For Recommended soldering conditions see Tech Brief TB389.

Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ±10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -40 C to 85 C

Junction Temperature Range. . . . . . . . . . . . . . . . . . -40 C to 125 C

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ

the

JA

JC,

“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted V

= 3.3V±5% and T = 25°C

A

CC

PARAMETER

VCC SUPPLY CURRENT

Nominal Supply

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

6.1

6.9

7.7

mA

BIAS

POWER-ON RESET

Rising CPVOUT POR Threshold

POR

Commercial

Industrial

4.25

4.10

0.3

4.30

0.6

4.42

4.50

0.9

V

CPVOUT POR Threshold Hysteresis

OSCILLATOR

Frequency

f

IC = ISL6439C, Commercial

IC = ISL6439I, Industrial

275

250

575

550

-

300

600

1.5

325

340

625

640

-

kHz

OSC

IC = ISL6439AC, Commercial

IC = ISL6439AI, Industrial

Ramp Amplitude

∆V

V

P-P

OSC

REFERENCE

Reference Voltage Tolerance

Nominal Reference Voltage

Charge Pump

-

1.5

-

%

V

0.800

REF

Nominal Charge Pump Output

Charge Pump Output Regulation

ERROR AMPLIFIER

DC Gain

V

= 3.3V, No Load

VCC

-

5.1

2

-

V

CPVOUT

%

Guaranteed by Design

-

88

15

6

-

dB

Gain-Bandwidth Product

Slew Rate

GBWP

SR

MHz

V/µs

SOFT START

Soft Start Slew Rate

Commercial

Industrial

6.2

7.3

7.6

ms

5

ISL6439

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted V

= 3.3V±5% and T = 25°C (Continued)

A

CC

PARAMETER

GATE DRIVERS

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Upper Gate Source Current

Upper Gate Sink Current

Lower Gate Source Current

Lower Gate Sink Current

PROTECTION / DISABLE

OCSET Current Source

I

V

- V

PHASE

= 5V, V = 4V

UGATE

-

-1

1

-

A

UGATE-SRC

BOOT

I

UGATE-SNK

I

= 3.3V, V = 4V

LGATE

-1

2

LGATE-SRC

VCC

I

LGATE-SNK

I

Commercial

Industrial

18

16

-

20

-

22

µA

V

OCSET

Disable Threshold

V

0.8

DISABLE

PHASE

Functional Pin Description

Connect this pin to the upper MOSFET’s source. This pin is

used to monitor the voltage drop across the upper MOSFET

for overcurrent protection.

14 LEAD SOIC

GND

1

2

3

4

5

6

7

14 UGATE

BOOT

13

LGATE

CPVOUT

CT1

PHASE

VCC

12

11

10

9

UGATE

Connect this pin to the upper MOSFET’s gate. This pin

provides the PWM-controlled gate drive for the upper

MOSFET. This pin is also monitored by the adaptive

shoot-through protection circuitry to determine when the

upper MOSFET has turned off.

CPGND

ENABLE

COMP

CT2

OCSET

FB

8

16 LEAD 5x5 QFN

BOOT

This pin provides ground referenced bias voltage to the

upper MOSFET driver. A bootstrap circuit is used to create a

voltage suitable to drive a logic-level N-Channel MOSFET.

16 15 14 13

CPVOUT

CT1

1

2

3

4

12 PHASE

11 VCC

LGATE

Connect this pin to the lower MOSFET’s gate. This pin provides

the PWM-controlled gate drive for the lower MOSFET. This pin

is also monitored by the adaptive shoot-through protection

circuitry to determine when the lower MOSFET has turned off.

CT2

10 CPGND

OCSET

9

NC

5

6

7

8

OCSET

Connect a resistor (R

upper MOSFET (V ). R

IN OCSET

) from this pin to the drain of the

, an internal 20µA current

OCSET

source (I

), and the upper MOSFET on-resistance

OCSET

VCC

(r ) set the converter overcurrent (OC) trip point

DS(ON)

according to the following equation:

This pin provides the bias supply for the ISL6439. Connect a

well-decoupled 3.3V supply to this pin.

I

xR

OCSET

I

= -------------------------------------------------

COMP and FB

PEAK

r

DS(ON)

COMP and FB are the available external pins of the error

amplifier. The FB pin is the inverting input of the internal

error amplifier and the COMP pin is the error amplifier

output. These pins are used to compensate the voltage-

control feedback loop of the converter.

An overcurrent trip cycles the soft-start function.

ENABLE

This pin is the open-collector enable pin. Pulling this pin to a

level below 0.8V will disable the controller. Disabling the

ISL6439 causes the oscillator to stop, the LGATE and

UGATE outputs to be held low, and the softstart circuitry to

re-arm.

GND

This pin represents the signal and power ground for the IC.

Tie this pin to the ground island/plane through the lowest

impedance connection available.

6

ISL6439

Figure 1 shows the soft-start sequence for a typical application.

CT1 and CT2

At t0, the +3.3V VCC voltage starts to ramp. At time t1, the

Charge Pump begins operation and the +5V CPVOUT IC bias

voltage starts to ramp up. Once the voltage on CPVOUT

crosses the POR threshold at time t2, the output begins the

soft-start sequence. The triangle waveform from the PWM

oscillator is compared to the rising error amplifier output

voltage. As the error amplifier voltage increases, the pulse-

width on the UGATE pin increases to reach the steady-state

duty cycle at time t3.

These pins are the connections for the external charge pump

capacitor. A minimum of a 0.1µF ceramic capacitor is

recommended for proper operation of the IC.

CPVOUT

This pin represents the output of the charge pump. The

voltage at this pin is the bias voltage for the IC. Connect a

decoupling capacitor from this pin to ground. The value of

the decoupling capacitor should be at least 10x the value of

the charge pump capacitor. This pin may be tied to the

bootstrap circuit as the source for creating the BOOT

voltage.

Shoot-Through Protection

A shoot-through condition occurs when both the upper

MOSFET and lower MOSFET are turned on simultaneously,

effectively shorting the input voltage to ground. To protect

the regulator from a shoot-through condition, the ISL6439

incorporates specialized circuitry which insures that the

complementary MOSFETs are not ON simultaneously.

CPGND

This pin represents the signal and power ground for the

charge pump. Tie this pin to the ground island/plane through

the lowest impedance connection available.

Functional Description

The adaptive shoot-through protection utilized by the

ISL6439 looks at the lower gate drive pin, LGATE, and the

upper gate drive pin, UGATE, to determine whether a

MOSFET is ON or OFF. If the voltage from UGATE or from

LGATE to GND is less than 0.8V, then the respective

MOSFET is defined as being OFF and the complementary

MOSFET is turned ON. This method of shoot-through

protection allows the regulator to sink or source current.

Initialization

The ISL6439 automatically initializes upon receipt of power.

Special sequencing of the input supplies is not necessary.

The Power-On Reset (POR) function continually monitors the

the output voltage of the charge pump. During POR, the charge

pump operates on a free running oscillator. Once the POR level

is reached, the charge pump oscillator is synched to the PWM

oscillator. The POR function also initiates the soft-start

operation after the charge pump output voltage exceeds its

POR threshold.

Since the voltage of the lower MOSFET gate and the upper

MOSFET gate are being measured to determine the state of

the MOSFET, the designer is encouraged to consider the

repercussions of introducing external components between

the gate drivers and their respective MOSFET gates before

actually implementing such measures. Doing so may

interfere with the shoot-through protection.

Soft-Start

The POR function initiates the digital soft-start sequence. The

PWM error amplifier reference is clamped to a level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator generates PHASE pulses of

increasing width that charge the output capacitor(s). This

method provides a rapid and controlled output voltage rise. The

soft start sequence typically takes about 6.5ms.

Output Voltage Selection

The output voltage can be programmed to any level between

V

and the internal reference, 0.8V. An external resistor

IN

divider is used to scale the output voltage relative to the

reference voltage and feed it back to the inverting input of

the error amplifier, see Figure 2. However, since the value of

R1 affects the values of the rest of the compensation

components, it is advisable to keep its value less than 5kΩ.

R4 can be calculated based on the following equation:

(1V/DIV)

CPVOUT (5V)

VCC (3.3V)

R1 × 0.8V

R4 = -------------------------------------

V

– 0.8V

OUT1

If the output voltage desired is 0.8V, simply route the output

back to the FB pin through R1, but do not populate R4.

V

(2.50V)

OUT

Overcurrent Protection

0V

The overcurrent function protects the converter from a shorted

T3

T0

T1

T2

output by using the upper MOSFET on-resistance, r

, to

DS(ON)

TIME

monitor the current. This method enhances the converter’s

efficiency and reduces cost by eliminating a current sensing

resistor.

FIGURE 1. SOFT-START INTERVAL

7

ISL6439

+3.3V

V

(2.5V)

OUT

VIN

VCC

CPVOUT

BOOT

D1

C4

Q1

UGATE

PHASE

L

OUT

0V

V

OUT

ISL6439

Q2

LGATE

+

Internal Soft-Start Function

Delay Interval

C

OUT

FB

C1

R1

C3

COMP

R3

C2

R2

R4

T0

T1

T2

TIME

FIGURE 3. OVER CURRENT PROTECTION RESPONSE

FIGURE 2. OUTPUT VOLTAGE SELECTION

where I

OCSET

is the internal OCSET current source (20µA

typical). The OC trip point varies mainly due to the MOSFET

variations. To avoid overcurrent tripping in the

The overcurrent function cycles the soft-start function in a

hiccup mode to provide fault protection. A resistor (R

programs the overcurrent trip level (see Typical Application

r

DS(ON)

)

OCSET

normal operating load range, find the R

the equation above with:

resistor from

OCSET

diagrams on pages 2 and 3). An internal 20µA (typical)

1. The maximum r

temperature.

at the highest junction

DS(ON)

current sink develops a voltage across R

that is

OCSET

referenced to V . When the voltage across the upper

IN

MOSFET (also referenced to V ) exceeds the voltage across

IN

2. The minimum I

from the specification table.

OCSET

(∆I)

R

, the overcurrent function initiates a soft-start

OCSET

I

> I

+ ----------

OUT(MAX)

3. Determine I

for

,

PEAK

2

sequence.

where ∆I is the output inductor ripple current.

Figure 3 illustrates the protection feature responding to an

overcurrent event. At time t0, an overcurrent condition is

sensed across the upper MOSFET. As a result, the regulator

is quickly shutdown and the internal soft-start function

begins producing soft-start ramps. The delay interval seen

by the output is equivalent to three soft-start cycles. The

fourth internal soft-start cycle initiates a normal soft-start

ramp of the output, at time t1. The output is brought back

into regulation by time t2, as long as the overcurrent event

has cleared.

For an equation for the ripple current see the section under

component guidelines titled ‘Output Inductor Selection’.

A small ceramic capacitor should be placed in parallel with

R

to smooth the voltage across

R

in the

OCSET

presence of switching noise on the input voltage.

Current Sinking

The ISL6439 incorporates a MOSFET shoot-through

protection method which allows a converter to sink current

as well as source current. Care should be exercised when

designing a converter with the ISL6439 when it is known that

the converter may sink current.

Had the cause of the over current still been present after the

delay interval, the over current condition would be sensed

and the regulator would be shut down again for another

delay interval of three soft-start cycles. The resulting hiccup

mode style of protection would continue to repeat

indefinitely.

When the converter is sinking current, it is behaving as a

boost converter that is regulating its input voltage. This

means that the converter is boosting current into the input

rail of the regulator. If there is nowhere for this current to go,

such as to other distributed loads on the rail or through a

voltage limiting protection device, the capacitance on this rail

will absorb the current. This situation will allow the voltage

level of the input rail to increase. If the voltage level of the rail

is boosted to a level that exceeds the maximum voltage

rating of any components attached to the input rail, then

The overcurrent function will trip at a peak inductor current

(I

PEAK)

determined by:

I

x R

OCSET

I

= ----------------------------------------------------

PEAK

r

DS(ON)

8

ISL6439

those components may experience an irreversible failure or

experience stress that may shorten their lifespan. Ensuring

that there is a path for the current to flow other than the

capacitance on the rail will prevent this failure mode.

+3.3V V

IN

ISL6439

VCC

C

VCC

Application Guidelines

Layout Considerations

Layout is very important in high frequency switching

converter design. With power devices switching efficiently at

CPVOUT

C

BP

C

IN

GND

D1

300kHz or 600kHz, the resulting current transitions from one

device to another cause voltage spikes across the

interconnecting impedances and parasitic circuit elements.

These voltage spikes can degrade efficiency, radiate noise

into the circuit, and lead to device overvoltage stress. Careful

component layout and printed circuit board design minimizes

the voltage spikes in the converters.

BOOT

C

BOOT

Q1

UGATE

PHASE

L

OUT

C

V

PHASE

OUT

Q2

As an example, consider the turn-off transition of the PWM

MOSFET. Prior to turn-off, the MOSFET is carrying the full load

current. During turn-off, current stops flowing in the MOSFET

and is picked up by the lower MOSFET. Any parasitic

inductance in the switched current path generates a large

voltage spike during the switching interval. Careful component

selection, tight layout of the critical components, and short,

wide traces minimizes the magnitude of voltage spikes.

LGATE

COMP

OUT

C

2

C

1

R

2

R

1

FB

C

R

3

R4

There are two sets of critical components in a DC-DC

converter using the ISL6439. The switching components are

the most critical because they switch large amounts of

energy, and therefore tend to generate large amounts of

noise. Next are the small signal components which connect

to sensitive nodes or supply critical bypass current and

signal coupling.

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

A multi-layer printed circuit board is recommended. Figure 4

shows the connections of the critical components in the

The critical small signal components include any bypass

capacitors, feedback components, and compensation

components. Position the bypass capacitor, C , close to the

VCC pin with a via directly to the ground plane. Place the

PWM converter compensation components close to the FB

and COMP pins. The feedback resistors for both regulators

should also be located as close as possible to the relevant

FB pin with vias tied straight to the ground plane as required.

converter. Note that capacitors C and C

could each

IN OUT

BP

represent numerous physical capacitors. Dedicate one solid

layer, usually a middle layer of the PC board, for a ground

plane and make all critical component ground connections

with vias to this layer. Dedicate another solid layer as a

power plane and break this plane into smaller islands of

common voltage levels. Keep the metal runs from the

PHASE terminals to the output inductor short. The power

plane should support the input power and output power

nodes. Use copper filled polygons on the top and bottom

circuit layers for the phase nodes. Use the remaining printed

circuit layers for small signal wiring. The wiring traces from

the GATE pins to the MOSFET gates should be kept short

and wide enough to easily handle the 1A of drive current.

Feedback Compensation

Figure 5 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

) is regulated to the Reference voltage level. The

error amplifier (Error Amp) output (V ) is compared with

the oscillator (OSC) triangular wave to provide a pulse-

width modulated (PWM) wave with an amplitude of V at

(V

OUT

E/A

IN

The switching components should be placed close to the

ISL6439 first. Minimize the length of the connections between

the PHASE node. The PWM wave is smoothed by the output

filter (L and C ).

O

the input capacitors, C , and the power switches by placing

IN

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

them nearby. Position both the ceramic and bulk input

capacitors as close to the upper MOSFET drain as possible.

Position the output inductor and output capacitors between the

upper MOSFET and lower MOSFET and the load.

OUT E/A

Gain and the output filter (L and C ), with a double pole

O

break frequency at F and a zero at F

. The DC Gain of

LC ESR

9

ISL6439

the modulator is simply the input voltage (V ) divided by the

IN

Compensation Break Frequency Equations

peak-to-peak oscillator voltage ∆V

.

OSC

1

F

= ----------------------------------

V

F

= --------------------------------------------------------

IN

DRIVER

Z1

P1

OSC

2π × R × C

C

x C

2













1

2

PWM

---------------------

2π x R

x

L

2

O

COMPARATOR

V

OUT

C

+ C

2

1

-

PHASE

+

∆V

C

O

OSC

1

= ------------------------------------------------------

2π x (R + R ) x C

F

= -----------------------------------

2π x R x C

Z2

P2

1

3

ESR

(PARASITIC)

Z

FB

V

E/A

Figure 6 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak due to the high Q factor of the output filter and is not

shown in Figure 6. Using the above guidelines should give a

Compensation Gain similar to the curve plotted. The open

loop error amplifier gain bounds the compensation gain.

Z

-

IN

+

REFERENCE

ERROR

AMP

DETAILED COMPENSATION COMPONENTS

Z

FB

V

Check the compensation gain at F with the capabilities of

OUT

P2

C

1

Z

IN

the error amplifier. The Closed Loop Gain is constructed on

the graph of Figure 6 by adding the Modulator Gain (in dB) to

the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

C

R

3

2

3

2

R

1

COMP

compensation transfer function and plotting the gain.

FB

-

+

The compensation gain uses external impedance networks

Z

and Z to provide a stable, high bandwidth (BW) overall

FB

IN

ISL6439

REFERENCE

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

Modulator Break Frequency Equations

OPEN LOOP

ERROR AMP GAIN

F

P1

F

Z1

Z2

P2

100

80

1

F

= -----------------------------------------

F

= ------------------------------------------

LC

ESR

V

2π x ESR x C













2π x

L

x C

O O

IN

O

---------------

20log

V

OSC

60

The compensation network consists of the error amplifier

(internal to the ISL6439) and the impedance networks Z

40

COMPENSATION

GAIN

IN

and Z . The goal of the compensation network is to provide

FB

20

a closed loop transfer function with the highest 0dB crossing

0

frequency (f

) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f and

R2

0dB







-------

20log



R1

0dB

-20

-40

-60

MODULATOR

GAIN

180 degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R , R ,

LOOP GAIN

10M

F

ESR

LC

1

2

R , C , C , and C ) in Figure 5. Use these guidelines for

3

1

2

3

10

100

1K

10K

100K

1M

locating the poles and zeros of the compensation network:

FREQUENCY (Hz)

1. Pick gain (R /R ) for desired converter bandwidth.

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

2

1

2. Place first zero below filter’s double pole (~75% F ).

LC

Component Selection Guidelines

3. Place second zero at filter’s double pole.

4. Place first pole at the ESR zero.

Charge Pump Capacitor Selection

A capacitor across pins CT1 and CT2 is required to create

the proper bias voltage for the ISL6439 when operating the

IC from 3.3V. Selecting the proper capacitance value is

important so that the bias current draw and the current

required by the MOSFET gates do not overburden the

5. Place second pole at half the switching frequency.

6. Check gain against error amplifier’s open-loop gain.

7. Estimate phase margin - repeat if necessary.

10

ISL6439

capacitor. A conservative approach is presented in the

following equation.

One of the parameters limiting the converter’s response to

a load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6439 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

I

BiasAndGate

------------------------------------

C

=

× 1.5

PUMP

V

× f

s

CC

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

Modern digital ICs can produce high transient load slew

rates. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (Effective Series Resistance) and voltage rating

requirements rather than actual capacitance requirements.

L x I

TRAN

OUT

t

=

t

=

FALL

RISE

V

- V

V

OUT

IN

where: I

is the transient load current step, t

is the

TRAN

RISE

is the

response time to the application of load, and t

FALL

response time to the removal of load. The worst case

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

response time can be either at the application or removal of

load. Be sure to check both of these equations at the

minimum and maximum output levels for the worst case

response time.

Input Capacitor Selection

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor’s ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the Equivalent Series Inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q turns on. Place the

small ceramic capacitors physically close to the MOSFETs

1

and between the drain of Q and the source of Q .

1

2

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC load current.

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

The maximum RMS current required by the regulator may be

closely approximated through the following equation:

2

 

V_OUT

-------------

V_IN

V

_IN– V_OUTV_OUT

2

1





 

------

---------------------------- -------------

I_RMS

=

× I_OUT

+

×



12

L × f_s

V_IN

MAX

V

- V

OUT

V

OUT

IN

f x L

∆V

OUT

= ∆I x ESR

∆I =

x

V

s

IN

For a through hole design, several electrolytic capacitors may

be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge current rating. These capacitors

must be capable of handling the surge-current at power-up.

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

11

ISL6439

Some capacitor series available from reputable manufacturers

are surge current tested.

Bootstrap Component Selection

External bootstrap components, a diode and capacitor, are

required to provide sufficient gate enhancement to the upper

MOSFET. The internal MOSFET gate driver is supplied by

the external bootstrap circuitry as shown in Figure 7. The

MOSFET Selection/Considerations

The ISL6439 requires two N-Channel power MOSFETs.

These should be selected based upon r

, gate supply

DS(ON)

boot capacitor, C

, develops a floating supply voltage

BOOT

requirements, and thermal management requirements.

referenced to the PHASE pin. This supply is refreshed each

cycle, when D conducts, to a voltage of CPVOUT less

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss components;

conduction loss and switching loss. The conduction losses are

the largest component of power dissipation for both the upper

and the lower MOSFETs. These losses are distributed between

the two MOSFETs according to duty factor. The switching

losses seen when sourcing current will be different from the

switching losses seen when sinking current. When sourcing

current, the upper MOSFET realizes most of the switching

losses. The lower switch realizes most of the switching losses

when the converter is sinking current (see equations on next

page). These equations assume linear voltage-current

transitions and do not adequately model power loss due the

reverse-recovery of the upper and lower MOSFET’s body

diode. The gate-charge losses are dissipated by the ISL6439

and don't heat the MOSFETs. However, large gate-charge

BOOT

the boot diode drop, V , plus the voltage rise across

D

Q

.

LOWER

CPVOUT

D

BOOT

+

V

-

V

IN

D

BOOT

C

ISL6439

BOOT

UGATE

PHASE

Q

UPPER

NOTE:

= V

V

-V

D

G-S

CC

LGATE

LOWER

-

+

NOTE:

= V

V

G-S

CC

GND

increases the switching interval, t

which increases the

SW

FIGURE 7. UPPER GATE DRIVE BOOTSTRAP

MOSFET switching losses. Ensure that both MOSFETs are

within their maximum junction temperature at high ambient

temperature by calculating the temperature rise according to

package thermal-resistance specifications. A separate heatsink

may be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

Just after the PWM switching cycle begins and the charge

transfer from the bootstrap capacitor to the gate capacitance

is complete, the voltage on the bootstrap capacitor is at its

lowest point during the switching cycle. The charge lost on

the bootstrap capacitor will be equal to the charge

transferred to the equivalent gate-source capacitance of the

upper MOSFET as shown:

Losses while Sourcing current

2

1

--

P

= Io × r

× D + ⋅ Io × V × t

× f

SW

UPPER

DS(ON)

IN

2

s

Q

= C

× (V

– V

BOOT2

)

GATE

BOOT

BOOT1

2

P

= Io x r

x (1 - D)

LOWER

DS(ON)

Losses while Sinking current

where Q

MOSFET, C

is the maximum total gate charge of the upper

GATE

2

P

= Io x r

x D

UPPER

DS(ON)

is the bootstrap capacitance, V is

BOOT

BOOT1

2

1

the bootstrap voltage immediately before turn-on, and

--

P

= Io × r

× (1 – D) + ⋅ Io × V × t

× f

SW s

LOWER

DS(ON)

IN

2

V

is the bootstrap voltage immediately after turn-on.

BOOT2

Where: D is the duty cycle = V

OUT

/ V ,

IN

is the combined switch ON and OFF time, and

t

The bootstrap capacitor begins its refresh cycle when the gate

drive begins to turn-off the upper MOSFET. A refresh cycle

ends when the upper MOSFET is turned on again, which

varies depending on the switching frequency and duty cycle.

SW

f is the switching frequency.

s

The minimum bootstrap capacitance can be calculated by

Given the reduced available gate bias voltage (5V), logic-

level or sub-logic-level transistors should be used for both N-

MOSFETs. Caution should be exercised with devices

rearranging the previous equation and solving for C

.

BOOT

Q

GATE

C

=

----------------------------------------------------

exhibiting very low V

characteristics. The shoot-

BOOT

GS(ON)

V

– V

BOOT1

BOOT2

through protection present aboard the ISL6439 may be

circumvented by these MOSFETs if they have large parasitic

impedences and/or capacitances that would inhibit the gate

of the MOSFET from being discharged below its threshold

level before the complementary MOSFET is turned on.

Typical gate charge values for MOSFETs considered in

these types of applications range from 20 to 100nC. Since

the voltage drop across Q is negligible, V is

LOWER BOOT1

simply V

CPVOUT

- V . A schottky diode is recommended to

D

12

ISL6439

minimize the voltage drop across the bootstrap capacitor

during the on-time of the upper MOSFET. Initial calculations

should also be considered when selecting the final bootstrap

capacitance value.

with V

no less than 4V will quickly help narrow the

BOOT2

A fast recovery diode is recommended when selecting a

bootstrap diode to reduce the impact of reverse recovery

bootstrap capacitor range.

For example, consider an upper MOSFET is chosen with a

charge loss. Otherwise, the recovery charge, Q , would

RR

maximum gate charge, Q , of 100nC. Limiting the voltage

drop across the bootstrap capacitor to 1V results in a value

of no less than 0.1µF. The tolerance of the ceramic capacitor

have to be added to the gate charge of the MOSFET and

taken into consideration when calculating the minimum

bootstrap capacitance.

g

ISL6439 DC-DC Converter Application Circuit

Figure 8 shows an application circuit of a DC-DC Converter.

Detailed information on the circuit, including a complete Bill-

of-Materials and circuit board description, can be found in

the ISL6439 Application Note.

3.3V

C

1

C

2

0.1µF

1000pF

GND

11

U

1

TP

C

1

3

VCC

6

3

4

5

OCSET

CPVOUT

BOOT

CT1

CT2

R

1

ISL6439

TP

3

9.76kΩ

C

4

0.22µF

C

5

D

C

1

10µF

C

Ceramic

6

13

1µF

10

1

CPGND

GND

0.1µF

7

14

12

UGATE

PHASE

L

1

2.5V @ 5A

9

ENABLE

2

C

LGATE

FB

8,9

Q

COMP

8

1

7

C

10

R

3

33pF

C

R

11

2

2.26kΩ

R

C

4

12

6.49kΩ 5600pF

GND

124Ω 8200pF

R

5

1.07kΩ

FIGURE 8. 3.3V to 2.5V 5A DC-DC CONVERTER

Component Selection Notes:

- Each 150µF, Panasonic EEF-UE0J151R or Equivalent.

C

3,8,9

D1 - 30mA Schottky Diode, MA732 or Equivalent

L - 1µH Inductor, Panasonic P/N ETQ-P6F1ROSFA or Equivalent.

1

Q - Fairchild MOSFET; ITF86110DK8.

1

13

ISL6439

Small Outline Plastic Packages (SOIC)

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

E

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

8.55

3.80

MAX

1.75

0.25

0.51

0.25

8.75

4.00

NOTES

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

-

SEATING PLANE

A

9

0.0075

0.3367

0.1497

0.0098

0.3444

0.1574

-

-A-

o

h x 45

D

3

4

-C-

α

µ

0.050 BSC

1.27 BSC

-

e

A1

C

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

B

0.10(0.004)

5

0.25(0.010) M

C A M B S

L

6

N

α

14

7

NOTES:

o

0

8

0

8

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

14

ISL6439

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L16.5x5B

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

0.80

0.90

-

A1

A2

A3

b

-

9

0.20 REF

9

0.28

2.95

0.33

0.40

3.25

5, 8

D

5.00 BSC

-

D1

D2

E

4.75 BSC

9

3.10

7, 8

5.00 BSC

-

E1

E2

e

4.75 BSC

9

3.10

7, 8

0.80 BSC

-

k

0.25

0.35

-

L

0.60

0.75

0.15

8

L1

N

-

16

4

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

15


型号：	ISL6439CR
厂家：	Intersil
描述：	Single Sync Buck PWM Controller for Broadband Gateway Applications 单同步降压PWM控制器，用于宽带网关应用栅控制器
文件：	总15页 (文件大小：378K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6439CR [INTERSIL]

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