ISL6522A [INTERSIL]
Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller; 降压和同步整流器脉宽调制( PWM )控制器型号: | ISL6522A |
厂家: | Intersil |
描述: | Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller |
文件: | 总13页 (文件大小:439K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6522A
®
Data Sheet
April 13, 2005
FN9122.2
Buck and Synchronous Rectifier
Features
• Drives two N-Channel MOSFETs
Pulse-Width Modulator (PWM) Controller
The ISL6522A provides complete control and protection for
a DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous rectified buck
topology. The ISL6522A integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.
• Operates from +5V or +12V input
• Simple single-loop control design
- Voltage-mode PWM control
• Fast transient response
- High-bandwidth error amplifier
- Full 0-100% duty ratio
The output voltage of the converter can be precisely
regulated to as low as 0.8V, with a maximum tolerance of
±0.5% over temperature and line voltage variations.
• Excellent output voltage regulation
- 0.8V internal reference
- ±0.5% over line voltage and temperature
The ISL6522A provides simple, single feedback loop,
voltage-mode control with fast transient response. It includes
a 200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0–100%.
• Overcurrent fault monitor
- Does not require extra current sensing element
- Uses MOSFETs r
DS(ON)
• Converter can source and sink current
• Small converter size
- Constant frequency operation
- 200kHz free-running oscillator programmable from
50kHz to over 1MHz
The ISL6522A protects against overcurrent conditions by
inhibiting PWM operation. The ISL6522A monitors the
• 14 Ld SOIC and 16 Lead 5x5mm QFN Packages
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline.
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
current by using the r
of the upper MOSFET which
DS(ON)
eliminates the need for a current sensing resistor.
Ordering Information
TEMP.
PKG.
PART NUMBER* RANGE (°C)
PACKAGE
14 Ld SOIC
DWG. #
• Pb-Free Available (RoHS Compliant)
ISL6522ACB
25 to 70
25 to 70
M14.15
M14.15
ISL6522ACBZ
(See Note)
14 Ld SOIC
(Pb-free)
Applications
• Power supply for Pentium , Pentium Pro, PowerPC and
AlphaPC™ microprocessors
®
®
ISL6522ACR
25 to 70
25 to 70
16 Ld 5x5 QFN
L16.5x5B
L16.5x5B
ISL6522ACRZ
(See Note)
16 Ld 5x5 QFN
(Pb-free)
• High-power 5V to 3.xV DC-DC regulators
• Low-voltage distributed power supplies
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add “-T” suffix for tape and reel.
CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2005. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL6522A
Pinouts
ISL6522ACR (16 LD QFN)
ISL6522A (14 LD SOIC)
TOP VIEW
TOP VIEW
14
13
12
11
10
9
1
2
3
4
5
6
7
RT
OCSET
SS
VCC
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
16 15 14 13
SS
COMP
FB
1
2
3
4
12 PVCC
COMP
FB
11 LGATE
10 PGND
EN
8
GND
EN
9
BOOT
5
6
7
8
Typical Application
12V
+5V OR +12V
V
CC
OCSET
EN
SS
RT
MONITOR AND
PROTECTION
BOOT
OSC
UGATE
PHASE
ISL6522A
+V
O
REF
+12V
PV
CC
LGATE
PGND
-
+
+
-
FB
GND
COMP
FN9122.2
2
April 13, 2005
ISL6522A
Block Diagram
VCC
POWER-ON
RESET (POR)
EN
SS
10µA
SOFT-
START
+
-
OCSET
OVER
CURRENT
BOOT
4V
UGATE
200µA
PHASE
PWM
0.8V
COMPARATOR
REF
GATE
CONTROL
LOGIC
REFERENCE
INHIBIT
PWM
+
-
+
-
PV
CC
ERROR
AMP
LGATE
PGND
GND
FB
COMP
RT
OSCILLATOR
FN9122.2
3
April 13, 2005
ISL6522A
Absolute Maximum Ratings
Thermal Information
Thermal Resistance
QFN Package (Notes 1, 2). . . . . . . . . .
SOIC Package (Note 1) . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V
θ
(°C/W)
36
65
θ
(°C/W)
5
CC
JA
JC
Boot Voltage, V
- V
. . . . . . . . . . . . . . . . . . . . . . +15.0V
BOOT
PHASE
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to V
+0.3V
CC
N/A
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Recommended Operating Conditions
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
CC
Ambient Temperature Range, ISL6522AC. . . . . . . . . . 25°C to 70°C
Junction Temperature Range, ISL6522AC . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. SeeTech
JA
Brief TB379.
2. For θ , the "case temp" location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
SUPPLY CURRENT
CC
Nominal Supply
I
EN = V ; UGATE and LGATE Open
CC
-
-
5
-
mA
CC
Shutdown Supply
POWER-ON RESET
EN = 0V
50
100
µA
Rising V
Threshold
Threshold
V
V
V
= 4.5VDC
= 4.5VDC
= 4.5VDC
-
-
10.4
V
V
V
V
CC
Falling V
OCSET
OCSET
OCSET
8.1
0.8
-
-
-
-
2.0
-
CC
Enable-Input Threshold Voltage
Rising V Threshold
1.27
OCSET
OSCILLATOR
Free Running Frequency
Total Variation
R
= OPEN, V
= 12
175
-20
-
200
-
230
+20
-
kHz
%
T
CC
6kΩ < R to GND < 200kΩ
T
Ramp Amplitude
REFERENCE
∆V
R
= OPEN
1.9
V
P-P
OSC
T
Reference Voltage Tolerance
Reference Voltage
ERROR AMPLIFIER
DC Gain
V
-0.5
-
-
0.5
-
%
V
REF
0.800
-
-
-
88
15
6
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/µs
COMP = 10pF
GATE DRIVERS
Upper Gate Source
Upper Gate Sink
Lower Gate Source
Lower Gate Sink
PROTECTION
I
V
- V
PHASE
= 12V, V = 6V
UGATE
350
500
5.5
450
3.5
-
10
-
mA
Ω
UGATE
BOOT
R
I
= 0.3A
-
300
-
UGATE
LGATE
I
V
= 12V, V
= 6V
mA
Ω
LGATE
CC
LGATE
= 0.3A
R
I
6.5
LGATE
LGATE
OCSET Current Source
Soft-Start Current
I
V
= 4.5VDC
170
-
200
10
230
-
µA
µA
OCSET
OCSET
I
SS
FN9122.2
4
April 13, 2005
ISL6522A
Typical Performance Curves
80
70
60
50
40
30
20
10
0
R
PULLUP
TO +12V
T
1000
100
10
C
= 3300pF
GATE
C = 1000pF
GATE
R
PULLDOWN
T
TO V
SS
C
= 10pF
GATE
100 200 300 400 500 600 700 800 900 1000
10
100
SWITCHING FREQUENCY (kHz)
1000
SWITCHING FREQUENCY (kHz)
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
FIGURE 1. R RESISTANCE vs FREQUENCY
T
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
Functional Pin Descriptions
RT
This pin provides oscillator switching frequency adjustment.
EN
By placing a resistor (R ) from this pin to GND, the nominal
T
This pin is the open-collector enable pin. Pull this pin below
1V to disable the converter. In shutdown, the soft-start pin is
discharged and the UGATE and LGATE pins are held low.
200kHz switching frequency is increased according to the
following equation:
6
5 • 10
Fs ≈ 200kHz + ------------------
(R to GND)
GND
R
T
T
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
Conversely, connecting a pull-up resistor (R ) from this pin
T
to V
reduces the switching frequency according to the
CC
PHASE
following equation:
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for overcurrent protection. This pin also provides the return
path for the upper gate drive.
7
4 • 10
Fs ≈ 200kHz – ------------------
(R to 12V)
T
R
T
OCSET
UGATE
Connect a resistor (R
) from this pin to the drain of the
OCSET
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET. This pin is also
monitored by the adaptive shoot through protection circuitry to
determine when the upper MOSFET has turned off.
upper MOSFET. R
, an internal 200µA current source
OCSET
(I
), and the upper MOSFET on-resistance (r
) set
OCS
DS(ON)
the converter overcurrent (OC) trip point according to the
following equation:
BOOT
I
• R
OCS
OCSET
I
= -------------------------------------------
PEAK
r
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
DS(ON)
An overcurrent trip cycles the soft-start function.
SS
PGND
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the
soft-start interval of the converter.
This is the power ground connection. Tie the lower MOSFET
source to this pin.
LGATE
COMP and FB
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
Connect LGATE to the lower MOSFET gate. This pin provides
the gate drive for the lower MOSFET. This pin is also
FN9122.2
5
April 13, 2005
ISL6522A
monitored by the adaptive shoot through protection circuitry to
determine when the lower MOSFET has turned off.
VOLTAGE
V
SOFT START
PVCC
Provide a bias supply for the lower gate drive to this pin.
VCC
V
OUT
Provide a 12V bias supply for the chip to this pin.
V
COMP
Functional Description
Initialization
V
OSC(MIN)
CLAMP ON V
COMP
The ISL6522A automatically initializes upon receipt of
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages and the enable (EN) pin.
The POR monitors the bias voltage at the VCC pin and the
RELEASED AT STEADY STATE
TIME
t
t
t
0
2
1
C
SS
-----------
t
t
=
⋅ V
input voltage (V ) on the OCSET pin. The level on OCSET
1
OSC(MIN)
IN
I
SS
is equal to V less a fixed voltage drop (see overcurrent
IN
V
OUT
C
protection). With the EN pin held to V , the POR function
CC
SS
SteadyState
V
IN
----------- ------------------------------------------------
⋅ ∆V
OSC
= t – t
=
⋅
SoftStart
2
1
I
initiates soft-start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
SS
C
= Soft Start Capacitor
Where:
SS
= Soft Start Current = 10µA
+12V power source, V and V
+12V power source must exceed the rising V
before POR initiates operation.
are equivalent and the
IN
CC
I
SS
threshold
CC
V
V
= Bottom of Oscillator = 1.35V
OSC(MIN)
= Input Voltage
IN
∆V
= Peak to Peak Oscillator Voltage = 1.9V
The POR function inhibits operation with the chip disabled
(EN pin low). With both input supplies above their POR
thresholds, transitioning the EN pin high initiates a soft-start
interval.
OSC
V
= Steady State Output Voltage
OUTSteadyState
FIGURE 3. SOFT-START INTERVAL
Soft-Start
4V
2V
0V
The POR function initiates the soft-start sequence. An internal
10µA current source charges an external capacitor (C ) on
SS
the SS pin to 4V. Soft-start clamps the error amplifier output
(COMP pin) to the SS pin voltage. Figure 3 shows the
soft-start interval. At t in Figure 3, the SS and COMP
1
15A
voltages reach the valley of the oscillator’s triangle wave. The
oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t2, at which
point the output is in regulation and the clamp on the COMP
pin is released. This method provides a rapid and controlled
output voltage rise.
10A
5A
0A
TIME (20ms/DIV)
FIGURE 4. OVERCURRENT OPERATION
Overcurrent Protection
The overcurrent function protects the converter from a
shorted output by using the upper MOSFETs on-resistance,
r
to monitor the current. This method enhances the
DS(ON)
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
)
OCSET
programs the overcurrent trip level. An internal 200µA
(typical) current sink develops a voltage across R
that
OCSET
FN9122.2
6
April 13, 2005
ISL6522A
is reference to V . When the voltage across the upper
IN
capacitors, damage may occur to these parts. If the bias
MOSFET (also referenced to V ) exceeds the voltage
IN
voltage for the ISL6522A comes from the V rail, then the
IN
across R
, the overcurrent function initiates a soft-start
maximum voltage rating of the ISL6522A may be exceeded
and the IC will experience a catastrophic failure and the
converter will no longer be operational. Ensuring that there is a
path for the current to follow other than the capacitance on the
rail will prevent these failure modes.
OCSET
sequence. The soft-start function discharges C with a
SS
10µA current sink and inhibits PWM operation. The soft-start
function recharges C , and PWM operation resumes with
SS
the error amplifier clamped to the SS voltage. Should an
overload occur while recharging C , the soft-start function
SS
Application Guidelines
Layout Considerations
inhibits PWM operation while fully charging C to 4V to
SS
complete its cycle. Figure 4 shows this operation with an
overload condition. Note that the inductor current increases
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
to over 15A during the C charging interval and causes an
SS
overcurrent trip. The converter dissipates very little power
with this method. The measured input power for the
conditions of Figure 4 is 2.5W.
The overcurrent function will trip at a peak inductor current
(I
determined by:
PEAK)
I
• R
OCSET
OCSET
I
= ---------------------------------------------------
PEAK
r
DS(ON)
Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C
and C each represent numerous physical capacitors.
O
Locate the ISL6522A within three inches of the MOSFETs,
Q1 and Q2. The circuit traces for the MOSFETs’ gate and
source connections from the ISL6522A must be sized to
handle up to 1A peak current.
where I
is the internal OCSET current source (200µA
OCSET
is typical). The OC trip point varies mainly due to the
MOSFETs r
in the normal operating load range, find the R
from the equation above with:
variations. To avoid overcurrent tripping
DS(ON)
resistor
OCSET
IN
The maximum r
DS(ON)
at the highest junction temperature.
from the specification table.
+ (∆I) ⁄ 2 ,
1. The minimum I
OCSET
2. Determine I
for I
> I
PEAK
OUT(MAX)
PEAK
where ∆I is the output inductor ripple current.
V
IN
For an equation for the ripple current see the section under
ISL6522A
UGATE
component guidelines titled Output Inductor Selection.
Q1
Q2
L
O
A small ceramic capacitor should be placed in parallel with
V
OUT
PHASE
R
to smooth the voltage across R
in the
OCSET
OCSET
presence of switching noise on the input voltage.
C
IN
C
D2
O
LGATE
PGND
Current Sinking
The ISL6522A incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6522A when it is known
that the converter may sink current.
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
When the converter is sinking current, it is behaving as a boost
converter that is regulating its input voltage. This means that
the converter is boosting current into the V rail, the voltage
IN
SS
that is being down-converted. If there is nowhere for this current
close to the SS pin because the internal current source is
to go, such as to other distributed loads on the V rail, through
only 10µA. Provide local V
decoupling between VCC and
IN
CC
a voltage limiting protection device, or other methods, the
GND pins. Locate the capacitor, C
to the BOOT and PHASE pins.
as close as practical
BOOT
capacitance on the V bus will absorb the current. This
IN
situation will cause the voltage level of the V rail to increase. If
IN
the voltage level of the rail is boosted to a level that exceeds the
maximum voltage rating of the MOSFETs or the input
FN9122.2
7
April 13, 2005
ISL6522A
V
IN
+V
Q1
IN
OSC
BOOT
DRIVER
DRIVER
D1
PWM
C
L
O
BOOT
PHASE
+12V
VCC
L
O
COMPARATOR
V
V
OUT
OUT
ISL6522A
-
PHASE
+
∆V
OSC
C
SS
O
C
Q2
O
ESR
(PARASITIC)
Z
C
FB
VCC
C
SS
V
E/A
Z
GND
-
IN
+
REFERENCE
ERROR
AMP
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
DETAILED COMPENSATION COMPONENTS
Figure 7 highlights the voltage-mode control loop for a
Z
FB
V
synchronous rectified buck converter. The output voltage
OUT
C2
Z
IN
(V
) is regulated to the reference voltage level. The error
OUT
C1
C3
R3
R2
amplifier (error amp) output (V ) is compared with the
E/A
oscillator (OSC) triangular wave to provide a pulse-width
R1
modulated (PWM) wave with an amplitude of V at the
COMP
IN
PHASE node. The PWM wave is smoothed by the output filter
FB
-
(L and C ).
O
O
+
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
ISL6522A
REF
OUT E/A
gain and the output filter (L and C ), with a double pole
O
O
break frequency at F and a zero at F
. The DC gain of
LC
ESR
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
the modulator is simply the input voltage (V ) divided by the
IN
peak-to-peak oscillator voltage ∆V
.
OSC
ND
3. Place 2
Zero at Filter’s Double Pole
4. Place 1 Pole at the ESR Zero
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Modulator Break Frequency Equations
ST
1
1
ND
F
= --------------------------------------
F
= --------------------------------------------
ESR
)
5. Place 2
LC
2π • (ESR • C
2π •
L • C
O
O O
The compensation network consists of the error amplifier
(internal to the ISL6522A) and the impedance networks Z
IN
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
and Z . The goal of the compensation network is to provide
FB
a closed loop transfer function with the highest 0dB crossing
frequency (f
) and adequate phase margin. Phase margin
0dB
is the difference between the closed loop phase at f
and
0dB
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
compensation gain at F with the capabilities of the error
P2
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 8 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
Compensation Break Frequency Equations
1
1
F
= ----------------------------------
F
= ------------------------------------------------------
Z1
P1
2π • R2 • C1
C1 • C2
----------------------
2π • R2 •
C1 + C2
The compensation gain uses external impedance networks
1
1
----------------------------------
F
= -----------------------------------------------------
F
=
Z2
P2
Z
and Z to provide a stable, high bandwidth (BW) overall
2π • R3 • C3
2π • (R1 + R3) • C3
FB
IN
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
1. Pick Gain (R2/R1) for desired converter bandwidth
ST
2. Place 1 Zero Below Filter’s Double Pole
(~75% F
)
LC
FN9122.2
April 13, 2005
8
ISL6522A
most cases, multiple electrolytic capacitors of small case size
100
80
F
F
P1
F
perform better than a single large case capacitor.
F
Z2
Z1
P2
Output Inductor Selection
OPEN LOOP
ERROR AMP GAIN
60
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
40
20LOG
(R2/R1)
20
20LOG
(V /∆V
)
OSC
IN
0
COMPENSATION
GAIN
MODULATOR
GAIN
-20
-40
-60
CLOSED LOOP
GAIN
V
- V
Fs x L
V
OUT
IN
OUT
------------------------------- ---------------
∆I =
•
∆V
= ∆I x ESR
F
OUT
LC
F
V
ESR
IN
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6522A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current value
to the transient current level. During this interval the difference
between the inductor current and the transient current level
must be supplied by the output capacitor. Minimizing the
response time can minimize the output capacitance required.
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L
V
× I
L
× I
O
TRAN
O
TRAN
t
= -------------------------------
t
= ------------------------------
RISE
FALL
– V
V
IN
OUT
OUT
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium-Pro be composed of at least forty (40) 1.0µF
ceramic capacitors in the 1206 surface-mount package.
where: I
is the transient load current step, t
is the
is the
TRAN
response time to the application of load, and t
RISE
FALL
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
impedance with frequency to select a suitable component. In
FN9122.2
9
April 13, 2005
ISL6522A
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
Standard-gate MOSFETs are normally recommended for
use with the ISL6522A. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V . The boot capacitor, C
CC
BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
CC
less the boot diode drop (V ) when the lower MOSFET, Q2
D
turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V . For Q2, a
CC
MOSFET Selection/Considerations
The ISL6522A requires two N-Channel power MOSFETs.
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to PVCC.
These should be selected based upon r
, gate supply
DS(ON)
requirements, and thermal management requirements.
D
BOOT
+12V
+5V OR +12V
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
-
+
V
D
VCC
BOOT
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses seen
when sinking current. When sourcing current, the upper
MOSFET realizes most of the switching losses. The lower
switch realizes most of the switching losses when the converter
is sinking current (see the equations below).
ISL6522A
C
BOOT
Q1
UGATE
PHASE
NOTE:
V
≈ V
- V
CC D
G-S
+5V
OR +12V
PVCC
D2
Q2
LGATE
PGND
-
NOTE:
≈ PVCC
+
V
G-S
GND
Losses while Sourcing Current
2
1
2
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
--
P
= Io × r
× D + ⋅ Io × V × t
× F
SW
UPPER
DS(ON)
IN
S
2
P
= Io x r
x (1 - D)
DS(ON)
LOWER
+12V
Losses while Sinking Current
+5V OR LESS
2
P
= Io x r
x D
VCC
UPPER
DS(ON)
2
1
2
--
× (1 – D) + ⋅ Io × V × t
P
= Io × r
× F
SW S
BOOT
LOWER
DS(ON)
IN
ISL6522A
Where: D is the duty cycle = V
/ V ,
IN
OUT
Q1
UGATE
t
F
is the switching interval, and
is the switching frequency.
SW
S
NOTE:
PHASE
V
≈ V
- 5V
CC
G-S
+5V
These equations assume linear voltage-current transitions and
do not adequately model power loss due the reverse-recovery
of the upper and lower MOSFET’s body diode. The
OR +12V
PVCC
D2
Q2
LGATE
PGND
-
NOTE:
≈ PVCC
gate-charge losses are dissipated by the ISL6522A and do not
heat the MOSFETs. However, large gate-charge increases the
+
V
G-S
switching interval, t
which increases the upper MOSFET
SW
GND
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature by
calculating the temperature rise according to package thermal-
resistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
FIGURE 10. UPPER GATE DRIVE - DIRECT V
CC
DRIVE OPTION
Figure 10 shows the upper gate drive supplied by a direct
connection to V . This option should only be used in
CC
converter systems where the main input voltage is +5V
or
DC
less. The peak upper gate-to-source voltage is approximately
FN9122.2
April 13, 2005
10
ISL6522A
V
less the input supply. For +5V main power and +12V
DC
ISL6522A DC-DC Converter Application
Circuit
CC
for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage rating
Figure 11 shows a DC-DC converter circuit for a
microprocessor application, originally designed to employ
the HIP6006 controller. Given the similarities between the
HIP6006 and ISL6522A controllers, the circuit can be
implemented using the ISL6522A controller without any
modifications. Detailed information on the circuit, including a
complete bill of materials and circuit board description, can
be found in Application Note AN9722. See Intersil’s home
page on the web: http://www.intersil.com.
exceeds the maximum voltage applied to PV
.
CC
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
12V
CC
V
IN
C17-18
C1-3
3x 680µF
2x 1µF
1206
RTN
C12
1µF
C19
R7
10K
1206
VCC
14
1000pF
R6
CR1
4148
OCSET
2
6
ENABLE
MONITOR AND
PROTECTION
SS
RT
3
3.01K
Q1
PHASE
TP2
10 BOOT
1
C20
0.1µF
9
UGATE
OSC
L1
R1
SPARE
C13
0.1µF
U1
PHASE
PVCC
8
ISL6522A
REF
V
OUT
13
CR2
Q2
LGATE
PGND
C6-9
4x 1000µF
12
11
-
+
-
MBR
340
+
5
FB
RTN
4
7
R2
1K
GND
JP1
COMP
C14
33pF
C15
R5
COMP
TP1
15K
0.01µF
C16
SPARE
R4
SPARE
R3
1K
Component Selection Notes:
C1-C3 - Three each 680µF 25W VDC, Sanyo MV-GX or equivalent.
C6-C9 - Four each 1000µF 6.3W VDC, Sanyo MV-GX or equivalent.
L1 - Core: micrometals T50-52B; winding: ten turns of 17AWG.
CR1 - 1N4148 or equivalent.
CR2 - 3A, 40V Schottky, Motorola MBR340 or equivalent.
Q1, Q2 - Fairchild MOSFET; RFP25N05
FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT
FN9122.2
April 13, 2005
11
ISL6522A
Small Outline Plas tic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
0.25(0.010)
M
B M
H
AREA
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Rev. 0 12/93
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN9122.2
12
April 13, 2005
ISL6522A
Quad Flat No-Lead Plas tic Package (QFN)
Micro Lead Frame Plas tic Package (MLFP)
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
A
MIN
0.80
NOMINAL
MAX
1.00
0.05
1.00
NOTES
0.90
-
A1
A2
A3
b
-
-
-
-
-
9
0.20 REF
9
0.28
2.95
2.95
0.33
0.40
3.25
3.25
5, 8
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
3.10
7, 8
5.00 BSC
-
E1
E2
e
4.75 BSC
9
3.10
7, 8
0.80 BSC
-
k
0.25
0.35
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9122.2
13
April 13, 2005
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