ISL6524ACBZA-T [INTERSIL]
VRM8.5 PWM and Triple Linear Power System Controller; VRM8.5 PWM和三路线性电源系统控制器型号: | ISL6524ACBZA-T |
厂家: | Intersil |
描述: | VRM8.5 PWM and Triple Linear Power System Controller |
文件: | 总16页 (文件大小:451K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6524A
®
Data Sheet
April 8, 2005
FN9064.1
VRM8.5 PWM and Triple Linear Power
System Controller
Features
• Provides 4 Regulated Voltages
- Microprocessor Core, AGTL+ Bus, AGP Bus Power,
and North/South Bridge Core
• Drives N-Channel MOSFETs
• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
The ISL6524A provides the power control and protection for
four output voltages in high-performance microprocessor and
computer applications. The IC integrates one PWM controller
and three linear controllers, as well as the monitoring and
protection functions into a 28-pin SOIC package. The PWM
controller regulates the microprocessor core voltage with a
synchronous-rectified buck converter. One linear controller
supplies the computer system’s AGTL+ 1.2V bus power. The
other two linear controllers regulate power for the 1.5V AGP
bus and the 1.8V power for the chipset core voltage and/or
cache memory circuits.
• Excellent Output Voltage Regulation
- Core PWM Output: ±1% Over Temperature
- All Other Outputs: ±3% Over Temperature
• VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core
Output Voltage Selection
- Wide Range - 1.050V to 1.825V
• Power-Good Output Voltage Monitors
- Separate delayed VTT Power Good
The ISL6524A includes an Intel VRM8.5 compatible, TTL
5-input digital-to-analog converter (DAC) that adjusts the
microprocessor core-targeted PWM output voltage from
1.050V to 1.825V in 25mV steps. The precision reference and
voltage-mode control provide ±1% static regulation. The linear
regulators use external N-channel MOSFETs or bipolar NPN
pass transistors to provide fixed output voltages of 1.2V ±3%
(V
), 1.5V ±3% (V
) and 1.8V ±3% (V ).
OUT2
OUT3
OUT4
The ISL6524A monitors all the output voltages. A delayed-
rising VTT (V output) Power Good signal is issued
• Over-Voltage and Over-Current Fault Monitors
- Switching Regulator Doesn’t Require Extra Current
OUT2
before the core PWM starts to ramp up. Another system
Power Good signal is issued when the core is within ±10% of
the DAC setting and all other outputs are above their under-
voltage levels. Additional built-in over-voltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM
Sensing Element, Uses MOSFET’s r
DS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Internal Oscillator
• Pb-Free Available (RoHS Compliant)
controllers’ over-current function monitors the output current
by using the voltage drop across the upper MOSFET’s
DS(ON)
Applications
r
, eliminating the need for a current sensing resistor.
•
Motherboard Power Regulation for Computers
Pinout
Ordering Information
ISL6524A (SOIC) TOP VIEW
TEMP.
PKG.
DWG.
#
DRIVE2
1
2
3
4
5
6
7
8
9
28 VCC
RANGE
PART NUMBER
ISL6524ACB*
ISL6524ACBZ* (Note)
ISL6524ACBZA-T (Note) 0 to 70 28 Ld SOIC (Pb-free) M28.3
ISL6524EVAL1 Evaluation Board
(°C)
PACKAGE
FIX
VID3
27 UGATE
26 PHASE
25 LGATE
24 PGND
23 OCSET
22 VSEN1
21 FB
0 to 70 28 Ld SOIC
M28.3
VID2
0 to 70 28 Ld SOIC (Pb-free) M28.3
VID1
VID0
VID25
PGOOD
VTTPG
*Add “-T” suffix for tape and reel.
20 COMP
19 VSEN3
18 DRIVE3
17 GND
FAULT/RT 10
VSEN2 11
SS24 12
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
SS13 13
16 VAUX
15 DRIVE4
VSEN4 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
OCSET
VCC
VSEN1
VSEN3
1.5V or 1.26V
VAUX
EA3
-
DRIVE3
POWER-ON
RESET (POR)
+
VAUX
x0.75
x0.75
UV3
UV4
-
+
200µA
x
x
1.10
0.90
+
-
+
+
DRIVE4
VSEN4
-
-
EA4
+
+
-
1.8V or 1.26V
PGOOD
-
+
FIX
-
x
1.15
INHIBIT
VCC
VCC
OV
DRIVE1
SOFT-
START
& FAULT
LOGIC
UGATE
PHASE
OC
+
DRIVE2
VSEN2
-
FAULT
-
GATE
CONTROL
+
+
EA2
+
-
VCC
-
EA1
PWM
PWM
COMP
-
UV2
>
+
LGATE
PGND
GND
x0.90
SYNCH
DRIVE
+
-
SET
1.2V
28µA
TTL D/A
CONVERTER
(DAC)
28µA
Q
Q
DACOUT
OSCILLATOR
FAULT/RT
CLK
D
CLR
4.5V
4.5V
FB
COMP
VID3 VID2
VID1 VID0 VID25
VTTPG
SS13
SS24
FIGURE 1. BLOCK DIAGRAM
+5V
IN
Q1
Q2
Q3
LINEAR
V
CONTROLLER
OUT1
V
OUT2
PWM1
CONTROLLER
ISL6524A
+3.3V
IN
Q4
LINEAR
LINEAR
Q5
V
CONTROLLER
CONTROLLER
OUT3
V
OUT4
FIGURE 2. SIMPLIFIED POWER SYSTEM DIAGRAM
+12V
IN
+5V
IN
L
IN
C
IN
VCC
OCSET
POWERGOOD
PGOOD
DRIVE2
Q3
V
OUT2
UGATE
Q1
FAULT/RT
PHASE
V
L
OUT1
1.2V
OUT1
1.3V to 3.5V
C
OUT2
FIX
Q2
LGATE
VSEN2
C
OUT1
PGND
VSEN1
VTT POWERGOOD
VTTPG
FB
ISL6524A
VAUX
+3.3V
IN
COMP
Q4
DRIVE3
V
OUT3
VSEN3
VID3
VID2
VID1
VID0
VID25
1.5V
C
C
OUT3
OUT4
DRIVE4
Q5
V
OUT4
VSEN4
SS24
SS13
1.8V
C
SS13
C
SS24
GND
FIGURE 3. TYPICAL APPLICATION
FN9064.1
April 8, 2005
3
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 1)
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
θ
JA
(°C/W)
70
CC
PGOOD, RT/FAULT, DRIVE, PHASE, and
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GATE Voltage. . . . . . . . . . . . . . . . . . . GND - 0.3V to V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
+ 0.3V
CC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
CC
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . 0°C to 125°C°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
UGATE, LGATE, DRIVE2, DRIVE3, and
DRIVE4 Open
-
9
-
mA
CC
POWER-ON RESET
Rising VCC Threshold
Falling VCC Threshold
Rising VAUX Threshold
VAUX Threshold Hysteresis
-
-
-
10.4
V
V
V
V
V
8.2
-
-
-
-
-
-
-
2.5
0.5
1.26
Rising V
Threshold
OCSET
OSCILLATOR
Free Running Frequency
Total Variation
F
185
-15
-
200
-
215
+15
-
kHz
%
OSC
6kΩ < RT to GND < 200kΩ; Note 2
Ramp Amplitude
∆V
1.9
V
P-P
OSC
DAC REFERENCE
DAC(VID25-VID3) Input Low Voltage
DAC(VID25-VID3) Input High Voltage
DACOUT Voltage Accuracy
-
-
-
-
0.8
-
V
V
2.0
-1.0
+1.0
%
LINEAR REGULATORS (V
Regulation Tolerance
, V
OUT2 OUT3
, AND V
)
OUT4
-
-
3
1.26
1.2
1.5
1.8
75
-
-
-
-
-
-
-
-
%
V
VSEN3 Regulation Voltage
VSEN2 Regulation Voltage
VSEN3 Regulation Voltage
VSEN4 Regulation Voltage
VREG
VREG
VREG
VREG
FIX = 0V
3
2
3
4
-
V
FIX = open
-
V
FIX = open
-
V
VSEN3,4 Under-Voltage Level
VSEN3,4 Under-Voltage Hysteresis
Output Drive Current
VSEN3,4
UV
VSEN3,4 Rising
VSEN3,4 Falling
-
%
-
7
%
VAUX-V
> 0.6V
20
40
mA
DRIVE2,3,4
SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Note 2
Note 2
-
-
-
88
15
6
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBWP
SR
MHz
V/µs
COMP = 10pF, Note 2
FN9064.1
4
April 8, 2005
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
PWM CONTROLLERS GATE DRIVERS
UGATE Source
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC = 12V, V
= 6V
= 1V
-
-
-
-
1
-
A
Ω
A
Ω
UGATE
UGATE
UGATE Sink
R
V
= 1V
GATE-PHASE
1.7
1
3.5
-
UGATE
LGATE
LGATE Source
I
VCC = 12V, V
LGATE
LGATE Sink
R
V
= 1V
LGATE
1.4
3.0
LGATE
PROTECTION
VSEN1 Over-Voltage (VSEN1/DACOUT)
FAULT Sourcing Current
OCSET Current Source
Soft-Start Current
VSEN1 Rising
-
120
8.5
200
28
-
%
mA
µA
µA
I
V
V
V
= 2.0V
-
170
-
-
230
-
OVP
FAULT/RT
OCSET
I
= 4.5V
OCSET
DC
= 2.0V
DC
I
SS13,24
SS13,24
POWER GOOD
VSEN1 Upper Threshold
(VSEN1/DACOUT)
VSEN1 Rising
VSEN1 Rising
VSEN1 Falling
108
92
-
-
110
94
%
%
VSEN1 Under-Voltage
(VSEN1/DACOUT)
VSEN1 Hysteresis (VSEN1/DACOUT)
PGOOD Voltage Low
-
-
-
-
-
2
-
-
0.8
-
%
V
V
I
= -4mA
PGOOD
PGOOD
VSEN2 Under-Voltage
VSEN2 Hysteresis
VSEN2 Rising
VSEN2 Falling
1.08
48
-
V
-
mV
V
VTTPG Voltage Low
V
I
= -4mA
VTTPG
0.8
VTTPG
NOTE:
2. Guaranteed by design.
Typical Performance Curves
100
C = 4800pF
C
= C = C
LGATE
UGATE
VIN = 5V
VCC = 12V
80
60
40
1000
R
PULLUP
T
TO +12V
C = 3600pF
C = 1500pF
100
10
R
PULLDOWN TO V
SS
20
0
T
C = 660pF
10
100
SWITCHING FREQUENCY (kHz)
1000
100
200
300
400
500
600
700
800
900 1000
SWITCHING FREQUENCY (kHz)
FIGURE 4. R RESISTANCE vs FREQUENCY
T
FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY
FN9064.1
April 8, 2005
5
OCSET (Pin 23)
Functional Pin Descriptions
VCC (Pin 28)
Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.
Connect a resistor (R
) from this pin to the drain of the
OCSET
upper MOSFET. R
, an internal 200µA current source
OCSET
(I
), and the upper MOSFET’s on-resistance (r
)
OCSET
DS(ON)
set the converter over-current (OC) trip point according to
the following equation:
I
× R
OCSET
OCSET
GND (Pin 17)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
---------------------------------------------------
I
=
PEAK
r
DS(ON)
An over-current trip cycles the soft-start function.
PGND (Pin 24)
This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.
The voltage at OCSET pin is monitored for power-on reset
(POR) purposes.
PHASE (Pin 26)
VAUX (Pin 16)
Connect the PHASE pin to the PWM converter’s upper
MOSFET source. This pin represents the gate drive return
current path and is used to monitor the voltage drop across
the upper MOSFET for over-current protection.
Connect this pin to the ATX 3.3V output. The voltage present
at this pin is monitored for sequencing purposes. This pin
provides the necessary base bias for the NPN pass
transistors, as well as the current sunk through the 5kΩ VID
pull-up resistors.
UGATE (Pin 27)
Connect UGATE pin to the PWM converter’s upper
MOSFET gate. This pin provides the gate drive for the upper
MOSFET.
SS13 (Pin 13)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the soft-start
LGATE (Pin 25)
Connect LGATE to the synchronous PWM converter’s lower
MOSFET gate. This pin provides the gate drive for the lower
MOSFET.
interval of the synchronous switching converter (V
) and
OUT1
the AGP regulator (V
). A VTTPG high signal is also
OUT3
delayed by the time interval required by the charging of this
capacitor from 0V to 1.25V (see Soft-Start details).
SS24 (Pin 12)
COMP and FB (Pins 20, 21)
Connect a capacitor from this pin to ground. This capacitor,
COMP and FB are the available external pins of the
synchronous PWM regulator error amplifier. The FB pin is
the inverting input of the error amplifier. Similarly, the COMP
pin is the error amplifier output. These pins are used to
compensate the voltage-mode control feedback loop of the
synchronous PWM converter.
along with an internal 28µA current source, sets the soft-start
interval of the V
regulator. Pulling this pin below 0.8V
OUT2
induces a chip reset (POR) and shutdown.
VTTPG (Pin 9)
VTTPG is an open collector output used to indicate the
VSEN1 (Pin 22)
status of the V
regulator output voltage. This pin is
OUT2
pulled low when the V
output is below the under-
This pin is connected to the synchronous PWM converters’
output voltage. The PGOOD and OVP comparator circuits
use this signal to report output voltage status and for over-
voltage protection.
OUT2
voltage threshold or when the SS13 pin is below 1.25V.
PGOOD (Pin 8)
PGOOD is an open collector output used to indicate the
status of the output voltages. This pin is pulled low when the
synchronous regulator output is not within ±10% of the
DACOUT reference voltage or when any of the other outputs
is below its under-voltage threshold.
DRIVE2 (Pin 1)
Connect this pin to the gate/base of a N-type external pass
transistor (MOSFET or bipolar). This pin provides the drive
for the 1.2V regulator’s pass transistor.
VID3, VID2, VID1, VID0, VID25 (Pins 3-7)
VSEN2 (Pin 11)
Connect this pin to the output of the standard buck PWM
regulator. The voltage at this pin is regulated to a 1.2V level.
This pin is also monitored for under-voltage events.
VID3-25 are the TTL-compatible input pins to the 5-bit DAC.
The logic states of these five pins program the internal
voltage reference (DACOUT). The level of DACOUT sets the
microprocessor core converter output voltage (V
), as
OUT1
FIX (Pin 2)
well as the corresponding PGOOD and OVP thresholds.
Each VID pin is connected to the VAUX pin through a 5kΩ
pull-up resistor.
Grounding this pin bypasses the internal resistor dividers that
set the output voltage of the 1.5V and 1.8V linear regulators.
FN9064.1
6
April 8, 2005
This way, the output voltage of the two regulators can be
adjusted from 1.26V up to the input voltage (+3.3V or +5V;
VOUT4 can only be set from 1.7V up) by way of an external
resistor divider connected at the corresponding VSEN pin.
The new output voltage set by the external resistor divider can
be determined using the following formula:
regulate the microprocessor core voltage (V ). The PWM
OUT1
controller drives 2 MOSFETs (Q1 and Q2) in a synchronous-
rectified buck converter configuration and regulates the core
voltage to a level programmed by the 5-bit digital-to-analog
converter (DAC). The first linear controller (EA2) is designed to
provide the AGTL+ bus voltage (V
) by driving a MOSFET
OUT2
(Q3) pass element to regulate the output voltage to a level of
1.2V. The remaining two linear controllers (EA3 and EA4)
supply the 1.5V advanced graphics port (AGP) bus power
R
OUT
----------------
V
= 1.265V × 1 +
OUT
R
GND
(V
) and the 1.8V chipset core power (V ).
where R
is the resistor connected from VSEN to the
OUT3
OUT4
OUT
output of the regulator, and R
is the resistor connected
GND
Initialization
from VSEN to ground. Left open, the FIX pin is pulled high,
enabling fixed output voltage operation.
The ISL6524A automatically initializes in ATX-based systems
upon receipt of input power. The Power-On Reset (POR)
function continually monitors the input supply voltages. The
DRIVE3 (Pin 18)
Connect this pin to the gate/base of a N-type external pass
transistor (MOSFET or bipolar). This pin provides the drive
for the 1.5V regulator’s pass transistor.
POR monitors the bias voltage (+12V ) at the VCC pin, the
IN
5V input voltage (+5V ) at the OCSET pin, and the 3.3V input
IN
voltage (+3.3V ) at the VAUX pin. The normal level on
IN
OCSET is equal to +5V less a fixed voltage drop (see over-
IN
VSEN3 (Pin 19)
Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for undervoltage events.
current protection). The POR function initiates soft-start
operation after all supply voltages exceed their POR
thresholds.
DRIVE4 (Pin 15)
Connect this pin to the base of an external bipolar transistor.
This pin provides the drive for the 1.8V regulator’s pass
transistor.
Soft-Start
The 1.8V supply designed to power the chipset (OUT4),
cannot lag the ATX 3.3V by more than 2V, at any time. To
meet this special requirement, the linear block controlling this
output operates independently of the chip’s power-on reset.
Thus, DRIVE4 is driven to raise the OUT4 voltage before the
input supplies reach their POR levels. As seen in Figure 6, at
time T0 the power is turned on and the input supplies ramp
up. Immediately following, OUT4 is also ramped up, lagging
the ATX 3.3V by about 1.8V. At time T1, the POR function
initiates the SS24 soft-start sequence. Initially, the voltage on
the SS24 pin rapidly increases to approximately 1V (this
minimizes the soft-start interval). Then, an internal 28µA
VSEN4 (Pin 14)
Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for undervoltage events.
FAULT/RT (Pin 10)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R ) from this pin to GND, the nominal
T
200kHz switching frequency is increased according to the
following equation:
current source charges an external capacitor (C
) on the
6
SS24
5 × 10
T
--------------------
Fs ≈ 200kHz +
SS24 pin to about 4.5V. As the SS24 voltage increases, the
EA2 error amplifier drives Q3 to provide a smooth transition to
the final set voltage. The OUT4 reference (clamped to SS24)
increasing past the intermediary level, established based on
the ATX 3.3V presence at the VAUX pin, brings the output in
regulation soon after T2.
(R to GND)
R (kΩ)
T
Conversely, connecting a resistor from this pin to VCC
reduces the switching frequency according to the following
equation:
7
4 × 10
T
--------------------
Fs ≈ 200kHz –
(R to 12V)
T
R (kΩ)
As OUT2 increases past the 90% power-good level, the second
soft-start (SS13) is released. Between T2 and T3, the SS13 pin
voltage ramps from 0V to the valley of the oscillator’s triangle
wave (at 1.25V). Contingent upon OUT2 remaining above
1.08V, the first PWM pulse on PHASE1 triggers the VTTPG pin
to go high. The oscillator’s triangular wave form is compared to
the clamped error amplifier output voltage. As the SS13 pin
voltage increases, the pulse-width on the PHASE1 pin
increases, bringing the OUT1 output within regulation limits.
Similarly, the SS13 voltage clamps the reference voltage for
OUT3, enabling a controlled output voltage ramp-up. At time
T4, all output voltages are within power-good limits, situation
reported by the PGOOD pin going high.
Nominally, the voltage at this pin is 1.26V. In the event of an
over-voltage or over-current condition, this pin is internally
pulled to VCC.
Description
Operation
The ISL6524A monitors and precisely controls 4 output voltage
levels (Refer to Figures 1, 2, 3). It is designed for
microprocessor computer applications with 3.3V, 5V, and 12V
bias input from an ATX power supply. The IC has one PWM
and three linear controllers. The PWM controller is designed to
FN9064.1
7
April 8, 2005
signals). An under-voltage on either linear output (VSEN2,
VSEN3, or VSEN4) is ignored until the respective UP signal
goes high. This allows V
and V
to increase
OUT3
OUT4
ATX 12V
ATX 5V
without fault at start-up. Following an over-current event
(OC1, UV2, or UV3 event), bringing the SS24 pin below 0.8V
resets the over-current latch and generates a soft-started
ramp-up of the outputs 1, 2, and 3.
10V
VTTPG
SS13
SS13UP
UV3
SS24
PGOOD
OC
0V
LATCH
INHIBIT1,2,3
S
R
Q
3.0V
ATX 3.3V
OC1
SSDOWN
V
(1.65V)
OUT1
COUNTER
4V
SS13
V
(1.8V)
OUT4
R
0.8V
SS24
FAULT
LATCH
V
(1.2V)
OUT2
S
Q
SS24UP
V
(1.5V)
OUT3
POR
4V
Q
R
0V
OV
UV4
FAULT
R
COUNTER
T0
T1
T2
T3
T4T5
TIME
R
FIGURE 6. SOFT-START INTERVAL
S
Q
UV2
OC
LATCH
The T2 to T3 time interval is dependent upon the value of
. The same capacitor is also responsible for the ramp-
up time of the OUT1 and OUT3 voltages. If selecting a
different capacitor then recommended in the circuit application
literature, consider the effects the different value will have on
the ramp-up time and inrush currents of the OUT1 and OUT3
outputs.
C
SS13
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
OUT1 Over-Voltage Protection
During operation, a short across the PWM upper MOSFET
(Q1) causes V
to increase. When the output exceeds
OUT1
the over-voltage threshold of 120% of DACOUT, the over-
voltage comparator trips to set the fault latch and turns the
lower MOSFET (Q2) on as needed to regulate the output
voltage to the 120% threshold. This operation typically
results in the blow of the input fuse, subsequent discharge of
Fault Protection
All four outputs are monitored and protected against extreme
overload. The chip’s response to an output overload is
selective, depending on the faulting output.
V
.
OUT1
An over-voltage on V
output (VSEN1) disables outputs
OUT1
1, 2, and 3, and latches the IC off. An under-voltage on
output latches the IC off. A single over-current event
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2, is driven on.
V
OUT4
on output 1, or an under-voltage event on output 2 or 3,
increments the respective fault counters and triggers a
shutdown of outputs 1, 2, and 3, followed by a soft-start re-
start. After three consecutive fault events on either counter,
the chip is latched off. Removal of bias power resets both the
fault latch and the counters. Both counters are also reset by
a successful start-up of all the outputs.
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s on-
resistance, r
to monitor the current for protection
DS(ON)
Figure 7 shows a simplified schematic of the fault logic. The
over-current latches are set dependent upon the states of
the over-current (OC1), output 2 and 3 under-voltage (UV2,
UV3) and the soft-start signals (SS13, SS24). Window
comparators monitor the SS pins and indicate when the
against a shorted output. All linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive currents.
Figure 8 illustrates the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
respective C pins are fully charged to above 4.0V (UP
SS
FN9064.1
April 8, 2005
8
current increases through the inductor (L
). At time T1,
the OC1 comparator trips when the voltage across Q1 (i
across R
OCSET
helps V
OCSET
track the variations of V due
IN
OUT1
•
to MOSFET switching. The over-current function will trip at a
peak inductor current (I determined by:
D
r
) exceeds the level programmed by R . This
OCSET
DS(ON)
PEAK)
inhibits outputs 1, 2, and 3, discharges the soft-start capacitor
with 28µA current sink, and increments the counter.
I
× R
OCSET
OCSET
C
SS24
Soft-start capacitor C
---------------------------------------------------
I
=
PEAK
r
is quickly discharged. C
starts
DS(ON)
SS13
SS13
ramping up at T2 and initiates a new soft-start cycle. With
OUT2 still overloaded, the inductor current increases to trip
the over-current comparator. Again, this inhibits the outputs,
The OC trip point varies with MOSFET’s rDS(ON)
temperature variations. To avoid over-current tripping in the
normal operating load range, determine the ROCSET
resistor value from the equation above with:
but the C
soft-start voltage continues increasing to above
is, again,
SS24
4.0V before discharging. Soft-start capacitor C
SS13
quickly discharged. The counter increments to 2. The soft-
start cycle repeats at T3 and trips the over-current
comparator. The SS24 pin voltage increases to above 4.0V at
T4 and the counter increments to 3. This sets the fault latch to
disable the converter.
1. The maximum r
2. The minimum I
at the highest junction temperature
from the specification table
DS(ON)
OCSET
3. Determine I
for I
> I
+ (∆I)/2,
PEAK
PEAK
OUT(MAX)
where ∆I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
FAULT
REPORTED
10V
0V
OVER-CURRENT TRIP:
V
= +5V
IN
V
> V
DS
SET
i
× r
> I
× R
D
DS(ON) OCSET
OCSET
COUNT
= 3
COUNT
= 1
COUNT
= 2
R
OCSET
OCSET
4V
2V
0V
I
i
OCSET
D
V
+
SET
200µA
VCC
UGATE
+
DRIVE
V
OVERLOAD
APPLIED
DS
+
-
OC
PHASE
GATE
CONTROL
PWM
V
= V – V
PHASE
IN
DS
0A
V
= V – V
OCSET
IN
SET
T0T1
T2
T3 T4
TIME
FIGURE 9. OVER-CURRENT DETECTION
FIGURE 8. OVER-CURRENT OPERATION
OUT1 Voltage Program
The three linear controllers monitor their respective VSEN
pins for under-voltage. Should excessive currents cause
VSEN3 or VSEN4 to fall below the linear under-voltage
threshold, the respective UV signals set the OC latch or the
The output voltage of the PWM converter is programmed to
discrete levels between 1.050V and 1.825V. This output
(OUT1) is designed to supply the core voltage of Intel’s
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter (DAC). The
level of DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, since they are internally
pulled to the VAUX pin through 5kΩ resistors. Changing the
VID inputs during operation is not recommended and could
toggle the PGOOD signal and exercise the over-voltage
protection. The output voltage program is Intel VRM8.5
compatible.
FAULT latch, providing respective C capacitors are fully
SS
charged. Blanking the UV signals during the C charge
SS
interval allows the linear outputs to build above the under-
voltage threshold during normal operation. Cycling the bias
input power off then on resets the counter and the fault latch.
An external resistor (R
) programs the over-current trip
OCSET
level for the PWM converter. As shown in Figure 9, the internal
200µA current sink (I ) develops a voltage across
OCSET
R
(V
) that is referenced to V . The DRIVE signal
OCSET SET IN
enables the over-current comparator (OC). When the voltage
across the upper MOSFET (V ) exceeds V , the over-
DS(ON) SET
current comparator trips to set the over-current latch. Both
V
and V are referenced to V and a small capacitor
SET
DS IN
FN9064.1
9
April 8, 2005
up to their set values in a quick and controlled fashion, while
meeting the system timing requirements.
TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM
PIN NAME
NOMINAL
DACOUT
VOLTAGE
Shutdown
VID3
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID2
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID25
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
The PWM output does not switch until the soft-start voltage
1.050
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
(V
) exceeds the oscillator’s valley voltage. Additionally,
SS13
the reference on each linear’s amplifier is clamped to the
soft-start voltage. Holding the SS24 pin low (with an open
drain or open collector signal) turns off regulators 1, 2 and 3.
Regulator 4 (MCH) will simply drop its output to the
intermediate soft-start level. This output is not allowed to
violate the 2V maximum potential gap to the ATX 3.3V
output.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn-off
transition of the upper MOSFET. Prior to turn-off, the upper
MOSFET was carrying the full load current. During the turn-
off, current stops flowing in the upper MOSFET and is picked
up by the lower MOSFET or Schottky diode. Any inductance
in the switched current path generates a large voltage spike
during the switching interval. Careful component selection,
tight layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using an ISL6524A controller. The switching
power components are the most critical because they switch
large amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high-
frequency ceramic de-coupling capacitors, close to the
power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.
1
NOTE: 0 = connected to GND, 1 = open or connected to 3.3V
through pull-up resistors
Application Guidelines
Soft-Start Interval
Initially, the soft-start function clamps the error amplifier’s output
of the PWM converter. This generates PHASE pulses of
increasing width that charge the output capacitor(s). The
resulting output voltages start-up as shown in Figure 6.
The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, C . Locate
SS
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from any SS
node, since the internal current source is only 28µA.
The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval
and the surge current are programmed by the soft-start
A multi-layer printed circuit board is recommended. Figure
10 shows the connections of the critical components in the
converter. Note that the capacitors C and C
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
each
IN
OUT
capacitor, C . Programming a faster soft-start interval
SS
increases the peak surge current. Using the recommended
0.1µF soft start capacitors ensure all output voltages ramp
FN9064.1
10
April 8, 2005
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE node, but do not
unnecessarily oversize this particular island. Since the
PHASE node is subject to very high dV/dt voltages, the stray
capacitor formed between these island and the surrounding
circuitry will tend to couple switching noise. Use the
remaining printed circuit layers for small signal wiring. The
wiring traces from the control IC to the MOSFET gate and
source should be sized to carry 2A peak currents.
V
IN
OSC
DRIVER
DRIVER
PWM
L
O
V
OUT
COMP
∆V
OSC
-
PHASE
+
C
O
ESR
(PARASITIC)
Z
FB
V
E/A
Z
IN
-
+
REFERENCE
ERROR
AMP
L
DETAILED COMPENSATION COMPONENTS
IN
+5V
IN
Z
FB
V
OUT
C
C2
IN
+12V
Z
IN
C
VCC
VCC GND
OCSET
C
C1
C3
R3
R2
OCSET
+3.3V
IN
R1
R
OCSET
COMP
Q3
DRIVE2
Q1
L
V
OUT2
FB
UGATE
PHASE
-
OUT
V
OUT1
+
C
OUT2
ISL6524A
C
OUT1
DACOUT
LGATE
CR1
SS24
SS13
Q2
C
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
SS24,13
V
OUT3
ISL6524A
V
OUT4
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
C
OUT3
DRIVE4
DRIVE3
C
OUT4
OUT E/A
Gain, given by V /V
PGND
Q5
Q4
, and shaped by the output filter, with
IN OSC
a double pole break frequency at F and a zero at F
LC
.
ESR
+3.3V
IN
Modulator Break Frequency Equations
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
1
1
---------------------------------------
-----------------------------------------
F
=
F
=
ESR
LC
2π × ESR × C
2π ×
L × C
O
O O
VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE
The compensation network consists of the error amplifier
(internal to the ISL6524A) and the impedance networks Z
IN
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
and Z . The goal of the compensation network is to provide a
FB
closed loop transfer function with high 0dB crossing frequency
(f
) and adequate phase margin. Phase margin is the
0dB
difference between the closed loop phase at f
and 180o.
PWM1 Controller Feedback Compensation
0dB
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller requiring external
compensation.
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 11. Use these guidelines for locating the poles
and zeros of the compensation network:
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
1. Pick Gain (R2/R1) for desired converter bandwidth
ST
2. Place 1 Zero Below Filter’s Double Pole (~75% F
ND
)
LC
(V
) is regulated to the Reference voltage level. The
OUT
3. Place 2
4. Place 1 Pole at the ESR Zero
5. Place 2
Zero at Filter’s Double Pole
reference voltage level is the DAC output voltage (DACOUT)
ST
for the PWM. The error amplifier output (V ) is compared with
E/A
ND
Pole at Half the Switching Frequency
the oscillator (OSC) triangular wave to provide a pulse-width
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
modulated wave with an amplitude of V at the PHASE node.
IN
The PWM wave is smoothed by the output filter (L and C ).
O
O
FN9064.1
April 8, 2005
11
Compensation Break Frequency Equations
PWM Output Capacitors
Modern microprocessors produce transient load rates
above 1A/ns. High frequency capacitors initially supply the
transient current and slow the load rate-of-change seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
resistance) and voltage rating requirements rather than
actual capacitance requirements.
1
1
-----------------------------------
------------------------------------------------------
F
=
F
=
P1
Z1
2π × R2 × C1
C1 × C2
----------------------
×
2π × R
2
C1 + C2
1
1
------------------------------------------------------
-----------------------------------
F
=
F
=
Z2
P2
2π × (R1 + R3) × C3
2π × R3 × C3
Figure 12 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 12. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
gain. Check the compensation gain at F with the capabilities
P2
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 12 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop following a high slew-rate transient’s
edge. An aluminum electrolytic capacitor’s ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter. Work
with your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
OPEN LOOP
F
F
F
P1
F
Z1
Z2
P2
ERROR AMP GAIN
100
80
60
40
20
0
V
IN
-----------------
20log
V
P – P
COMPENSATION
GAIN
R2
R1
-------
20log
-20
-40
-60
CLOSED LOOP
GAIN
MODULATOR
GAIN
F
F
ESR
Linear Output Capacitors
LC
The output capacitors for the linear regulators provide
10
100
1K
10K
100K
1M
10M
dynamic load current. Thus capacitors C
, C , and
OUT2 OUT3
FREQUENCY (Hz)
C
should be selected for transient load regulation.
OUT4
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
PWM Output Inductor Selection
The compensation gain uses external impedance networks
The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:
Z
and Z to provide a stable, high bandwidth (BW) overall
FB
IN
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
V
– V
V
OUT
IN
OUT
∆V
= ∆I × ESR
------------------------------- ---------------
∆I =
×
OUT
F
× L
V
S
IN
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converter requires an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
Increasing the value of inductance reduces the ripple current
and voltage. However, large inductance values increase the
converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6524A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
FN9064.1
12
April 8, 2005
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required.
gain, saturation voltages, gate supply requirements, and
thermal management considerations.
PWM MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the dominant
design factors. The power dissipation includes two main loss
components: conduction losses and switching losses. These
losses are distributed between the upper and lower MOSFET
according to the duty factor. The conduction losses are the
main component of power dissipation for the lower MOSFETs.
Only the upper MOSFET has significant switching losses, since
the lower device turns on and off into near zero voltage.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L
V
× I
TRAN
L
× I
TRAN
O
O
-------------------------------
=
------------------------------
t
t
=
RISE
FALL
– V
V
IN
OUT
OUT
The equations presented assume linear voltage-current
transitions and do not model power losses due to the lower
MOSFET’s body diode or the output capacitances
associated with either MOSFET. The gate charge losses are
dissipated by the controller IC (ISL6524A) and do not
contribute to the MOSFETs’ heat rise. Ensure that both
MOSFETs are within their maximum junction temperature at
high ambient temperature by calculating the temperature
rise according to package thermal resistance specifications.
A separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
where: I
is the transient load current step, t
is the
TRAN
response time to the application of load, and t
RISE
is the
FALL
response time to the removal of load. Be sure to check both
of these equations at the minimum and maximum output
levels for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage. The maximum RMS current rating
requirement for the input capacitors of a buck regulator is
approximately 1/2 of the DC output load current. Worst-case
RMS current draw in a circuit employing the ISL6524A
amounts to the largest RMS current draw of the switching
regulator.
2
I
× r
× V
I
× V × t
× F
SW S
O
DS(ON)
OUT
O
IN
------------------------------------------------------------ ----------------------------------------------------
P
P
=
+
UPPER
LOWER
V
2
IN
2
I
× r
× (V – V
OUT
)
O
DS(ON)
IN
--------------------------------------------------------------------------------
=
V
IN
The r
is different for the two equations above even if
DS(ON)
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
the same device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 13 shows the gate drive where the
upper MOSFET’s gate-to-source voltage is approximately
V
less the input supply. For +5V main power and +12VDC
CC
for the bias, the approximate gate-to-source voltage of Q1 is
7V. The lower gate drive voltage is 12V. A logic-level
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V
.
CC
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. For best
results, the diode must be a surface-mount Schottky type to
prevent the parasitic MOSFET body diode from conducting. It
is acceptable to omit the diode and let the body diode of the
lower MOSFET clamp the negative inductor swing, but one
must ensure the PHASE node negative voltage swing does
not exceed -3V to -5V peak. The diode's rated reverse
breakdown voltage must be equal or greater to 1.5 times the
maximum input voltage.
MOSFET Selection/Considerations
The ISL6524A requires 5 external transistors. Two
N-channel MOSFETs are employed by the PWM converter.
The GTL, AGP, and memory linear controllers can each drive
a MOSFET or a NPN bipolar as a pass transistor. All these
transistors should be selected based upon r
, current
DS(ON)
FN9064.1
13
April 8, 2005
Linear Controllers Transistor Selection
+5V OR LESS
+12V
The ISL6524A linear controllers are compatible with both
NPN bipolar as well as N-channel MOSFET transistors. The
main criteria for selection of pass transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is
VCC
ISL6524A
Q1
UGATE
PHASE
NOTE:
≈ V -5V
P
= I × (V – V
OUT
)
LINEAR
O
IN
V
GS
CC
CR1
LGATE
PGND
Q2
Select a package and heatsink that maintains the junction
temperature below the maximum desired temperature with
the maximum expected ambient temperature.
-
+
NOTE:
V
≈ V
CC
GS
GND
When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating V
is sufficiently large to provide the desired
FIGURE 13. UPPER GATE DRIVE - DIRECT V
DRIVE
CE
CC
output load current when the base is fed with the minimum
driver output current.
In order to ensure the strict timing/level requirement of
OUT4, an NPN transistor is recommended for use as a pass
element on this output (Q5). An low gate threshold NMOS
could be used, but meeting the requirements would then
depend on the VCC bias being sufficiently high to allow
control of the MOSFET.
FN9064.1
14
April 8, 2005
ISL6524A DC-DC Converter Application Circuit
Figure 14 shows an application circuit of a power supply for
a microprocessor computer system. The power supply
and +12VDC. For detailed information on the circuit,
including a Bill-of-Materials and circuit board description, see
Application Note AN9925. Also see the Intersil web site at
www.intersil.com
provides the microprocessor core voltage (V
), the GTL
), and the
OUT1
bus voltage (V
), the AGP bus voltage (V
OUT3
OUT2
memory controller hub voltage (V
) from +3.3V, +5VDC,
OUT4
+5V
+12V
L1
1µH
+
C1
680µF
+3.3V
GND
GND
C2
C3
GND
1µF
C4
1µF
1nF
VCC
28
R2
R3
10kΩ
FIX
2
23
8
OCSET1
PGOOD
1.5kΩ
POWER GOOD
V
Q3
DRIVE2
1
HUF76107
V
(VTT)
Q1
OUT2
VSEN2
11
UGATE1
HUF76139
27
26
(CORE)
OUT1
(1.050V to 1.825V)
+1.2V
L2
+
FAULT/RT
PHASE1
LGATE1
PGND
C6
10
1000µF
1.8µH
Q2
+
25
24
HUF76143
C7-9
3x1000µF
R7
4.99kΩ
R10
10kΩ
VSEN1
FB1
C11
22
21
0.30µF
R11
VTT
POWER GOOD
VTTPG
VAUX
U1
9
3.32kΩ
C12
ISL6524A
R12
270pF
C13
22nF
R13
12.1k
COMP1
20
16
33Ω
+
C15
R14
C14
10µF
R15
267kΩ
2.2nF
43kΩ
Q4
HUF76107
DRIVE3
VSEN3
18
19
VID25
VID0
VID1
7
6
5
4
V
(AGP)
OUT3
+1.5V
+
C17
560µF
VID2
VID3
3
Q5
2SD1802
DRIVE4
VSEN4
15
14
SS24
SS13
12
V
(MCH)
OUT4
C18
0.1µF
13
+1.8V
17
GND
+
C20
C21
560µF
0.1µF
FIGURE 14.
FN9064.1
15
April 8, 2005
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
0.7125 17.70
3
-A-
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
µ
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9064.1
16
April 8, 2005
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