ISL6526ACRZ [INTERSIL]
Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; 单同步降压脉宽调制( PWM )控制器型号: | ISL6526ACRZ |
厂家: | Intersil |
描述: | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
文件: | 总15页 (文件大小:330K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6526, ISL6526A
®
Data Sheet
March 20, 2007
FN9055.8
Single Synchronous Buck Pulse-Width
Modulation (PWM) Controller
Features
• Operates from 3.3V to 5V Input
The ISL6526, ISL6526A make simple work out of
• 0.8V to V Output Range
IN
- 0.8V Internal Reference
implementing a complete control and protection scheme for
a DC/DC stepdown converter. Designed to drive N-Channel
MOSFETs in a synchronous buck topology, the ISL6526,
ISL6526A integrate the control, output adjustment,
monitoring and protection functions into a single package.
- ±1.5% Over Load, Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
The ISL6526, ISL6526A provide simple, single feedback
loop, voltage-mode control with fast transient response. The
output voltage can be precisely regulated to as low as 0.8V,
with a maximum tolerance of ±1.5% over temperature and
line voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s r
DS(on)
The error amplifier features a 15MHz gain-bandwidth
product and 6V/μs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
• Converter can Source and Sink Current
• Small Converter Size
- Internal Fixed Frequency Oscillator
-
-
ISL6526: 300kHz
ISL6526A: 600kHz
Protection from overcurrent conditions is provided by
monitoring the r
of the upper MOSFET to inhibit PWM
DS(ON)
• Internal Soft-Start
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
• 14 Lead SOIC or 16 Lead 5x5 QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supplies for Microprocessors
- PCs
- Embedded Controllers
• Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
- DDR SDRAM Bus Termination Supply
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• 3.3V-Input DC/DC Regulators
• Low-Voltage Distributed Power Supplies
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001-2005, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6526, ISL6526A
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP
RANGE (°C)
PKG
DWG. #
PACKAGE
14 Ld SOIC
ISL6526CB*
ISL6526CB
0 to +70
M14.15
ISL6526CBZ*
ISL6526ACB*
ISL6526ACBZ*
ISL6526CR*
6526CBZ
0 to +70
14 Ld SOIC (Pb-free)
14 Ld SOIC
M14.15
ISL6526ACB
0 to +70
M14.15
6526ACBZ
0 to +70
14 Ld SOIC (Pb-free)
16 Ld 5x5 QFN
M14.15
ISL 6526CR
0 to +70
L16.5x5B
L16.5x5B
L16.5x5B
L16.5x5B
M14.15
ISL6526CRZ*
ISL6526ACR*
ISL6526ACRZ*
ISL6526IB*
ISL6526 CRZ
0 to +70
16 Ld 5x5 QFN (Pb-free)
16 Ld 5x5 QFN
ISL 6526ACR
0 to +70
ISL6526 ACRZ
ISL6526IB
0 to +70
16 Ld 5x5 QFN (Pb-free)
14 Ld SOIC
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
ISL6526IBZ*
6526IBZ
14 Ld SOIC (Pb-free)
14 Ld SOIC
M14.15
ISL6526AIB*
ISL6526AIB
M14.15
ISL6526AIBZ*
ISL6526IR*
6526AIBZ
14 Ld SOIC (Pb-free)
16 Ld 5x5 QFN
M14.15
ISL 6526IR
L16.5x5B
L16.5x5B
L16.5x5B
L16.5x5B
ISL6526IRZ*
ISL 6526IRZ
16 Ld 5x5 QFN (Pb-free)
16 Ld 5x5 QFN
ISL6526AIR*
ISL 6526AIR
ISL6526AIRZ*
ISL6526EVAL1
ISL6526EVAL2
ISL6526AEVAL1
ISL6526AEVAL2
*Add “-T” suffix for tape and reel.
ISL65 26AIRZ
16 Ld 5x5 QFN (Pb-free)
ISL6526 SOIC Evaluation Board
ISL6526 QFN Evaluation Board
ISL6526A SOIC Evaluation Board
ISL6526A QFN Evaluation Board
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
ISL6526, ISL6526A
(14 LD SOIC)
TOP VIEW
ISL6526, ISL6526A
(16 LD QFN)
TOP VIEW
GND
1
2
3
4
5
6
7
14 UGATE
BOOT
13
12
11
10
9
LGATE
CPVOUT
CT1
16 15 14 13
PHASE
VCC
CPVOUT
CT1
1
2
3
4
12 PHASE
11 VCC
CPGND
ENABLE
COMP
CT2
OCSET
FB
10
9
CT2
CPGND
NC
8
OCSET
5
6
7
8
FN9055.8
March 20, 2007
2
ISL6526, ISL6526A
Typical Application - 3.3V Input
3.3V
V
IN
C
IN
C
BULK
VCC
OCSET
CT1
CT2
R
OCSET
C
PUMP
CPVOUT
ISL6526, ISL6526A
D
C
BOOT
C
DCPL
C
HF
BOOT
CPGND
GND
BOOT
UGATE
PHASE
Q
Q
1
L
OUT
C
V
OUT
ENABLE
COMP
LGATE
OUT
2
FB
DISABLE
C
I
R
FB
R
C
F
F
R
OFFSET
FN9055.8
March 20, 2007
3
ISL6526, ISL6526A
Typical Application - 5V Input
+5V
V
IN
C
BULK
VCC
OCSET
CT1
CT2
R
OCSET
CPVOUT
ISL6526, ISL6526A
D
C
BOOT
BOOT
N/C
C
IN
C
HF
BOOT
CPGND
GND
UGATE
PHASE
Q
Q
1
L
OUT
C
V
OUT
ENABLE
COMP
LGATE
OUT
2
FB
DISABLE
C
I
R
FB
R
C
F
F
R
OFFSET
Block Diagram
VCC
CPVOUT
CT1
CT2
CHARGE
PUMP
POWER-ON
ENABLE
RESET (POR)
CPGND
OCSET
BOOT
+
-
SOFT-START
OC
UGATE
COMPARATOR
20μA
PHASE
PWM
COMPARATOR
ERROR
AMP
GATE
CONTROL
LOGIC
+
-
+
-
+
-
PWM
0.8V
LGATE
FB
OSCILLATOR
COMP
FIXED 300kHz or 600kHz
GND
FN9055.8
March 20, 2007
4
ISL6526, ISL6526A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Absolute Boot Voltage, V . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Thermal Resistance
θ
(°C/W)
θ
(°C/W)
JC
JA
BOOT
Upper Driver Supply Voltage, V
SOIC Package (Note 1) . . . . . . . . . . . .
QFN Package (Note 2). . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
67
35
N/A
5
- V
. . . . . . . . . . . +7.0V
BOOT
PHASE
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
For Recommended soldering conditions see Tech Brief TB389.
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ
the
JC,
JA
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Recommended Operating Conditions, unless otherwise noted V
= 3.3V ±5% and T = +25°C
A
CC
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
6.1
6.9
7.7
mA
BIAS
POWER-ON RESET
Rising CPVOUT POR Threshold
POR
Commercial
Industrial
4.25
4.10
0.3
4.30
4.30
0.6
4.42
4.50
0.9
V
V
V
CPVOUT POR Threshold Hysteresis
OSCILLATOR
Frequency
f
IC = ISL6526C, Commercial
IC = ISL6526I, Industrial
275
250
530
510
-
300
300
600
600
1.5
325
340
645
650
-
kHz
kHz
kHz
kHz
OSC
IC = ISL6526AC, Commercial
IC = ISL6526AI, Industrial
Ramp Amplitude
ΔV
V
P-P
OSC
REFERENCE
Reference Voltage Tolerance
Nominal Reference Voltage
CHARGE PUMP
-
-
-
1.5
-
%
V
V
0.800
REF
Nominal Charge Pump Output
Charge Pump Output Regulation
ERROR AMPLIFIER
DC Gain
V
V
= 3.3V, No Load
VCC
-
-
5.1
2
-
-
V
CPVOUT
%
Guaranteed by Design
-
-
-
88
15
6
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBWP
SR
MHz
V/μs
SOFT-START
Soft-Start Slew Rate
Commercial
Industrial
6.2
6.2
-
-
7.3
7.6
ms
ms
FN9055.8
March 20, 2007
5
ISL6526, ISL6526A
Electrical Specifications Recommended Operating Conditions, unless otherwise noted V
= 3.3V ±5% and T = +25°C (Continued)
A
CC
PARAMETER
GATE DRIVERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
PROTECTION/DISABLE
OCSET Current Source
I
V
V
- V
PHASE
= 5V, V = 4V
UGATE
-
-
-
-
-1
1
-
-
-
-
A
A
A
A
UGATE-SRC
BOOT
I
UGATE-SNK
I
= 3.3V, V = 4V
LGATE
-1
2
LGATE-SRC
VCC
I
LGATE-SNK
I
Commercial
Industrial
18
16
-
20
20
-
22
22
μA
μA
V
OCSET
Disable Threshold
V
0.8
DISABLE
GND
Functional Pin Description
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
14 LEAD (SOIC)
TOP VIEW
GND
1
2
3
4
5
6
7
14 UGATE
PHASE
BOOT
PHASE
VCC
13
12
11
LGATE
CPVOUT
CT1
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
10 CPGND
CT2
9
8
ENABLE
COMP
OCSET
FB
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off.
16 LEAD 5X5 (QFN)
TOP VIEW
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-Channel MOSFET.
16 15 14 13
CPVOUT
1
2
3
4
12 PHASE
11 VCC
CT1
CT2
LGATE
10
9
CPGND
NC
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off.
OCSET
5
6
7
8
OCSET
Connect a resistor (R
OCSET
) from this pin to the drain of the
, an internal 20μA current
VCC
upper MOSFET (V ). R
IN
OCSET
This pin provides the bias supply for the ISL6526, ISL6526A.
Connect a well-decoupled 3.3V supply to this pin.
source (I
), and the upper MOSFET on-resistance
OCSET
(r ) set the converter overcurrent (OC) trip point
DS(ON)
according to the following equation:
COMP and FB
I
xR
OCSET
OCSET
-------------------------------------------------
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the internal
error amplifier and the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-
control feedback loop of the converter.
I
=
PEAK
r
DS(ON)
(EQ. 1)
An overcurrent trip cycles the soft-start function.
FN9055.8
March 20, 2007
6
ISL6526, ISL6526A
width on the UGATE pin increases to reach the steady-state
ENABLE
duty cycle at time t3.
This pin is the open-collector enable pin. Pulling this pin to a
level below 0.8V will disable the controller. Disabling the
ISL6526, ISL6526A cause the oscillator to stop, the LGATE
and UGATE outputs to be held low, and the soft-start circuitry
to re-arm.
(1V/DIV)
CPVOUT (5V)
VCC (3.3V)
CT1 and CT2
These pins are the connections for the external charge
pump capacitor. A minimum of a 0.1μF ceramic capacitor is
recommended for proper operation of the IC.
V
(2.50V)
OUT
CPVOUT
This pin represents the output of the charge pump. The
voltage at this pin is the bias voltage for the IC. Connect a
decoupling capacitor from this pin to ground. The value of
the decoupling capacitor should be at least 10x the value of
the charge pump capacitor. This pin may be tied to the
bootstrap circuit as the source for creating the BOOT
voltage.
0V
T3
T0
T1
T2
TIME
FIGURE 1. SOFT-START INTERVAL
Shoot-Through Protection
A shoot-through condition occurs when both the upper
MOSFET and lower MOSFET are turned on simultaneously,
effectively shorting the input voltage to ground. To protect
the regulator from a shoot-through condition, the ISL6526,
ISL6526A incorporate specialized circuitry which insures
that the complementary MOSFETs are not ON
simultaneously.
CPGND
This pin represents the signal and power ground for the
charge pump. Tie this pin to the ground island/plane through
the lowest impedance connection available.
Functional Description
Initialization
The adaptive shoot-through protection utilized by the
ISL6526, ISL6526A look at the lower gate drive pin, LGATE,
and the upper gate drive pin, UGATE, to determine whether
a MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the complementary
MOSFET is turned ON. This method of shoot-through
protection allows the regulator to sink or source current.
The ISL6526, ISL6526A automatically initialize upon receipt
of power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the output voltage of the charge pump. During
POR, the charge pump operates on a free running oscillator.
Once the POR level is reached, the charge pump oscillator
is synched to the PWM oscillator. The POR function also
initiates the soft-start operation after the charge pump output
voltage exceeds its POR threshold.
Since the voltage of the lower MOSFET gate and the upper
MOSFET gate are being measured to determine the state of
the MOSFET, the designer is encouraged to consider the
repercussions of introducing external components between
the gate drivers and their respective MOSFET gates before
actually implementing such measures. Doing so may
interfere with the shoot-through protection.
Soft-Start
The POR function initiates the digital soft-start sequence.
The PWM error amplifier reference is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s). This
method provides a rapid and controlled output voltage rise.
The soft-start sequence typically takes about 6.5ms.
Output Voltage Selection
The output voltage can be programmed to any level between
V
and the internal reference, 0.8V. An external resistor
IN
Figure 1 shows the soft-start sequence for a typical application.
At t0, the +3.3V VCC voltage starts to ramp. At time t1, the
Charge Pump begins operation and the +5V CPVOUT IC bias
voltage starts to ramp up. Once the voltage on CPVOUT
crosses the POR threshold at time t2, the output begins the
soft-start sequence. The triangle waveform from the PWM
oscillator is compared to the rising error amplifier output
voltage. As the error amplifier voltage increases, the pulse-
divider is used to scale the output voltage relative to the
reference voltage and feed it back to the inverting input of
the error amplifier, see Figure 2. However, since the value of
R1 affects the values of the rest of the compensation
components, it is advisable to keep its value less than 5kΩ.
R4 can be calculated based on the following equation:
R1 × 0.8V
-------------------------------------
R4 =
V
– 0.8V
OUT1
(EQ. 2)
FN9055.8
March 20, 2007
7
ISL6526, ISL6526A
If the output voltage desired is 0.8V, simply route the output
back to the FB pin through R1, but do not populate R4.
delay interval of three soft-start cycles. The resulting hiccup
mode style of protection would continue to repeat
indefinitely.
+3.3V
V
(2.5V)
OUT
VIN
VCC
CPVOUT
D1
BOOT
C4
Q1
UGATE
ISL6526,
ISL6526A
L
OUT
0V
V
OUT
PHASE
LGATE
Q2
+
INTERNAL SOFT-START FUNCTION
DELAY INTERVAL
C
OUT
FB
C1
R1
C3
COMP
R3
C2
R2
R4
T0
T1
T2
TIME
FIGURE 3. OVERCURRENT PROTECTION RESPONSE
FIGURE 2. OUTPUT VOLTAGE SELECTION
The overcurrent function will trip at a peak inductor current
(I
determined by:
PEAK)
Overcurrent Protection
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET on-resistance, r , to
I
x R
OCSET
OCSET
----------------------------------------------------
I
=
PEAK
r
DS(ON)
(EQ. 3)
DS(ON)
monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
where I
OCSET
is the internal OCSET current source (20μA
typical). The OC trip point varies mainly due to the MOSFET
r
variations. To avoid overcurrent tripping in the
DS(ON)
The overcurrent function cycles the soft-start function in a
normal operating load range, find the R
the equation above with:
resistor from
OCSET
hiccup mode to provide fault protection. A resistor (R
)
OCSET
programs the overcurrent trip level (see Typical Application
diagrams on pages 3 and 4). An internal 20μA (typical) current
sink develops a voltage across R that is referenced to
1. The maximum r
temperature.
at the highest junction
DS(ON)
OCSET
2. The minimum I
3. Determine I
from the specification table.
OCSET
V . When the voltage across the upper MOSFET (also
IN
(ΔI)
2
----------
+
OUT(MAX)
I
> I
referenced to V ) exceeds the voltage across R
, the
for
,
IN
OCSET
PEAK
PEAK
overcurrent function initiates a soft-start sequence.
where ΔI is the output inductor ripple current.
Figure 3 illustrates the protection feature responding to an
overcurrent event. At time t0, an overcurrent condition is
sensed across the upper MOSFET. As a result, the regulator
is quickly shutdown and the internal soft-start function begins
producing soft-start ramps. The delay interval seen by the
output is equivalent to three soft-start cycles. The fourth
internal soft-start cycle initiates a normal soft-start ramp of
the output, at time T1. The output is brought back into
regulation by time T2, as long as the overcurrent event has
cleared.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R
to smooth the voltage across
R
in the
OCSET
OCSET
presence of switching noise on the input voltage.
Current Sinking
The ISL6526, ISL6526A incorporate a MOSFET shoot-
through protection method which allows a converter to sink
current as well as source current. Care should be exercised
when designing a converter with the ISL6526, ISL6526A
when it is known that the converter may sink current.
Had the cause of the overcurrent still been present after the
delay interval, the overcurrent condition would be sensed
and the regulator would be shut down again for another
FN9055.8
March 20, 2007
8
ISL6526, ISL6526A
When the converter is sinking current, it is behaving as a
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
boost converter that is regulating its input voltage. This
means that the converter is boosting current into the input
rail of the regulator. If there is nowhere for this current to go,
such as to other distributed loads on the rail or through a
voltage limiting protection device, the capacitance on this rail
will absorb the current. This situation will allow the voltage
level of the input rail to increase. If the voltage level of the rail
is boosted to a level that exceeds the maximum voltage
rating of any components attached to the input rail, then
those components may experience an irreversible failure or
experience stress that may shorten their lifespan. Ensuring
that there is a path for the current to flow other than the
capacitance on the rail will prevent this failure mode.
+3.3V V
IN
ISL6526, ISL6526A
VCC
C
VCC
CPVOUT
C
BP
C
IN
GND
D1
BOOT
C
BOOT
Application Guidelines
Q1
Q2
UGATE
PHASE
Layout Considerations
L
OUT
V
PHASE
OUT
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
300kHz or 600kHz, the resulting current transitions from one
device to another causing voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, radiate noise
into the circuit, and lead to device overvoltage stress.
Careful component layout and printed circuit board design
minimizes the voltage spikes in the converters.
C
LGATE
COMP
OUT
C
2
C
1
R
2
R
1
FB
C
R
3
3
R4
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET
and is picked up by the lower MOSFET. Any parasitic
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful component
selection, tight layout of the critical components, and short, wide
traces minimizes the magnitude of voltage spikes.
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
There are two sets of critical components in a DC/DC
converter using the ISL6526, ISL6526A. The switching
components are the most critical because they switch large
amounts of energy, and therefore tend to generate large
amounts of noise. Next are the small signal components
which connect to sensitive nodes or supply critical bypass
current and signal coupling.
The switching components should be placed close to the
ISL6526, ISL6526A first. Minimize the length of the connections
between the input capacitors, C , and the power switches by
IN
placing them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between the
upper MOSFET and lower MOSFET and the load.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
The critical small signal components include any bypass
capacitors, feedback components, and compensation
converter. Note that capacitors C and C
could each
IN OUT
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
components. Position the bypass capacitor, C , close to
BP
the VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.
FN9055.8
March 20, 2007
9
ISL6526, ISL6526A
relate the compensation network’s poles, zeros and gain to
the components (R , R , R , C , C , and C ) in Figure 5.
Use these guidelines for locating the poles and zeros of the
Feedback Compensation
1
2
3
1
2
3
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
compensation network:
(V
) is regulated to the Reference voltage level. The
OUT
error amplifier (Error Amp) output (V ) is compared with
the oscillator (OSC) triangular wave to provide a pulse-
E/A
1. Pick gain (R /R ) for desired converter bandwidth.
2
1
2. Place first zero below filter’s double pole (~75% F ).
LC
width modulated (PWM) wave with an amplitude of V at
IN
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
the PHASE node. The PWM wave is smoothed by the output
filter (L and C ).
O
O
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
OUT E/A
Gain and the output filter (L and C ), with a double pole
O
O
break frequency at F and a zero at F
the modulator is simply the input voltage (V ) divided by the
peak-to-peak oscillator voltage ΔV
OSC
. The DC Gain of
LC ESR
Compensation Break Frequency Equations
IN
1
1
.
----------------------------------
F
F
=
=
--------------------------------------------------------
F
=
Z1
Z2
P1
2π × R × C
C
x C
2
2
⎛
⎜
⎝
⎞
⎟
⎠
1
2
---------------------
2π x R
x
2
C
+ C
2
1
V
IN
DRIVER
OSC
1
1
------------------------------------------------------
2π x (R + R ) x C
-----------------------------------
2π x R x C
F
=
PWM
COMPARATOR
P2
L
O
V
1
3
3
3
3
OUT
(EQ. 4)
-
DRIVER
PHASE
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
+
ΔV
C
O
OSC
ESR
(PARASITIC)
Z
FB
V
E/A
Z
-
IN
+
Check the compensation gain at F with the capabilities of
REFERENCE
P2
ERROR
AMP
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
DETAILED COMPENSATION COMPONENTS
Z
FB
V
OUT
C
1
Z
IN
compensation transfer function and plotting the gain.
C
C
R
R
3
2
3
2
The compensation gain uses external impedance networks
Z
and Z to provide a stable, high bandwidth (BW) overall
FB
IN
R
1
COMP
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
FB
-
+
ISL6526, ISL6526A
REFERENCE
OPEN LOOP
ERROR AMP GAIN
F
F
F
P1
F
Z1
Z2
P2
100
80
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
⎛
⎜
⎝
⎞
⎟
⎠
IN
-----------------
20log
V
OSC
60
Modulator Break Frequency Equations
40
COMPENSATION
GAIN
1
1
-----------------------------------------
------------------------------------------
F
=
F
=
ESR
20
LC
2π x ESR x C
2π x
L
x C
O O
O
0
R2
R1
⎛
⎝
⎞
⎠
-------
20log
The compensation network consists of the error amplifier
(internal to the ISL6526, ISL6526A) and the impedance
networks Z and Z . The goal of the compensation
-20
-40
-60
MODULATOR
GAIN
LOOP GAIN
10M
F
F
ESR
LC
IN
FB
network is to provide a closed loop transfer function with the
10
100
1K
10K
100K
1M
highest 0dB crossing frequency (f ) and adequate phase
0dB
margin. Phase margin is the difference between the closed
FREQUENCY (Hz)
loop phase at f
0dB
and 180 degrees. The equations below
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FN9055.8
March 20, 2007
10
ISL6526, ISL6526A
of the ripple current. The ripple voltage and current are
approximated by the following equations:
Component Selection Guidelines
Charge Pump Capacitor Selection
V
- V
V
OUT
IN
OUT
ΔV
= ΔI x ESR
A capacitor across pins CT1 and CT2 is required to create
the proper bias voltage for the ISL6526, ISL6526A when
operating the IC from 3.3V. Selecting the proper capacitance
value is important so that the bias current draw and the
current required by the MOSFET gates do not overburden
the capacitor. A conservative approach is presented in the
following equation.
ΔI =
x
OUT
f x L
V
s
IN
(EQ. 6)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6526, ISL6526A will provide either 0% or 100% duty
cycle in response to a load transient. The response time is
the time required to slew the inductor current from an initial
current value to the transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor. Minimizing the response time can minimize the
output capacitance required.
I
BiasAndGate
------------------------------------
C
=
× 1.5
PUMP
V
× f
s
CC
(EQ. 5)
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
Modern digital ICs can produce high transient load slew
rates. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
L x I
L x I
V
TRAN
- V
OUT
TRAN
t
=
t
=
FALL
RISE
V
IN
OUT
(EQ. 7)
is the
where: I
is the transient load current step, t
RISE
TRAN
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
response time to the application of load, and t
is the
FALL
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q turns on. Place the
small ceramic capacitors physically close to the MOSFETs
1
and between the drain of Q and the source of Q .
1
2
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
FN9055.8
March 20, 2007
11
ISL6526, ISL6526A
The maximum RMS current required by the regulator may be
closely approximated through the following equation:
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors should be used for both
N-MOSFETs. Caution should be exercised with devices
2
VOUT
-------------
VIN
VIN – VOUT VOUT
2
1
12
⎛
⎛
⎞ ⎞
exhibiting very low V characteristics. The shoot-
------ ---------------------------- -------------
IRMS
=
× IOUT
+
×
×
GS(ON)
⎝
⎝
⎠ ⎠
VIN
L × fs
MAX
MAX
through protection present aboard the ISL6526, ISL6526A
may be circumvented by these MOSFETs if they have large
parasitic impedances and/or capacitances that would inhibit
the gate of the MOSFET from being discharged below its
threshold level before the complementary MOSFET is turned
on.
(EQ. 8)
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 7. The
MOSFET Selection/Considerations
The ISL6526, ISL6526A require two N-Channel power
boot capacitor, C
, develops a floating supply voltage
BOOT
MOSFETs. These should be selected based upon r
,
DS(ON)
referenced to the PHASE pin. This supply is refreshed each
cycle, when D conducts, to a voltage of CPVOUT less
gate supply requirements, and thermal management
requirements.
BOOT
the boot diode drop, V , plus the voltage rise across
D
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
Q
.
LOWER
CPVOUT
ISL6526,
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching losses
when the converter is sinking current (see equations on next
page). These equations assume linear voltage-current
ISL6526A
D
BOOT
+
V
-
V
IN
D
BOOT
C
BOOT
UGATE
PHASE
Q
Q
UPPER
NOTE:
= V -V
D
V
G-S
CC
LGATE
LOWER
-
+
NOTE:
= V
transitions and do not adequately model power loss due the
reverse-recovery of the upper and lower MOSFET’s body
diode. The gate-charge losses are dissipated by the ISL6526,
ISL6526A and don't heat the MOSFETs. However, large gate-
V
G-S
CC
GND
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
charge increases the switching interval, t which increases
SW
the MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
Losses while Sourcing current
2
1
2
--
× D + ⋅ Io × V × t
P
= Io × r
× f
Q
= C
× (V
– V
)
BOOT2
UPPER
LOWER
DS(ON)
IN SW s
GATE
BOOT
BOOT1
(EQ. 10)
2
P
= Io x r
x (1 - D)
DS(ON)
where Q
MOSFET, C
is the maximum total gate charge of the upper
GATE
Losses while Sinking current
is the bootstrap capacitance, V is
BOOT
BOOT1
2
P
= Io x r
x D
DS(ON)
UPPER
the bootstrap voltage immediately before turn-on, and
is the bootstrap voltage immediately after turn-on.
2
1
2
--
× (1 – D) + ⋅ Io × V × t
P
= Io × r
× f
s
V
BOOT2
LOWER
DS(ON)
IN SW
Where: D is the duty cycle = V
/ V ,
OUT IN
The bootstrap capacitor begins its refresh cycle when the gate
drive begins to turn-off the upper MOSFET. A refresh cycle
t
is the combined switch ON and OFF time, and
SW
f is the switching frequency.
s
(EQ. 9)
FN9055.8
March 20, 2007
12
ISL6526, ISL6526A
ends when the upper MOSFET is turned on again, which
varies depending on the switching frequency and duty cycle.
drop across the bootstrap capacitor to 1V results in a value
of no less than 0.1μF. The tolerance of the ceramic capacitor
should also be considered when selecting the final bootstrap
capacitance value.
The minimum bootstrap capacitance can be calculated by
rearranging the previous equation and solving for C
.
BOOT
A fast recovery diode is recommended when selecting a
bootstrap diode to reduce the impact of reverse recovery
Q
GATE
----------------------------------------------------
C
=
BOOT
V
– V
BOOT1
BOOT2
charge loss. Otherwise, the recovery charge, Q , would
(EQ. 11)
RR
have to be added to the gate charge of the MOSFET and
taken into consideration when calculating the minimum
bootstrap capacitance.
Typical gate charge values for MOSFETs considered in
these types of applications range from 20 to 100nC. Since
the voltage drop across Q
is negligible, V
is
LOWER
BOOT1
simply V
- V . A schottky diode is recommended to
CPVOUT
D
ISL6526, ISL6526A DC/DC Converter
Application Circuit
Figure 8 shows an application circuit of a DC/DC Converter.
Detailed information on the circuit, including a complete Bill-
of-Materials and circuit board description, can be found in
Application Note AN9994.
minimize the voltage drop across the bootstrap capacitor
during the on-time of the upper MOSFET. Initial calculations
with V
no less than 4V will quickly help narrow the
BOOT2
bootstrap capacitor range.
For example, consider an upper MOSFET is chosen with a
maximum gate charge, Q , of 100nC. Limiting the voltage
g
3.3V
C
0.1μF
1
C
2
1000pF
GND
11
U
1
TP
C
1
3
VCC
6
3
4
5
OCSET
ISL6526, ISL6526A
CPVOUT
CT1
CT2
R
1
TP
3
9.76kΩ
C
4
0.22μF
C
10μF
CERAMIC
5
D
C
1
C
6
13
1μF
BOOT
10
1
CPGND
GND
0.1μF
7
14
12
UGATE
PHASE
L
1
2.5V @ 5A
9
ENABLE
ENABLE
2
C
LGATE
8,9
Q
1
COMP
8
FB
7
C
10
R
3
33pF
C
R
11
2
2.26kΩ
R
C
4
12
6.49kΩ 5600pF
GND
124Ω 8200pF
R
5
1.07kΩ
FIGURE 8. 3.3V TO 2.5V 5A DC/DC CONVERTER
Component Selection Notes:
- Each 150μF, Panasonic EEF-UE0J151R or Equivalent.
C
3,8,9
D1 - 30mA Schottky Diode, MA732 or Equivalent
L - 1μH Inductor, Panasonic P/N ETQ-P6F1ROSFA or Equivalent.
1
Q - Fairchild MOSFET; ITF86110DK8.
1
FN9055.8
March 20, 2007
13
ISL6526, ISL6526A
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN9055.8
March 20, 2007
14
ISL6526, ISL6526A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
0.80
0.90
-
A1
A2
A3
b
-
-
-
-
-
9
0.20 REF
9
0.28
2.95
2.95
0.33
0.40
3.25
3.25
5, 8
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
3.10
7, 8
5.00 BSC
-
E1
E2
e
4.75 BSC
9
3.10
7, 8
0.80 BSC
-
k
0.25
0.35
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9055.8
March 20, 2007
15
相关型号:
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RENESAS
ISL6526AIBZ-T
2A SWITCHING CONTROLLER, 640kHz SWITCHING FREQ-MAX, PDSO14, ROHS COMPLIANT, PLASTIC, MS-012-AB, SOIC-14
RENESAS
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