ISL6528_技术文档

ISL6528

®

Data Sheet

December 28, 2004

FN9038.3

Dual Regulator - Standard Buck PWM

and Linear Power Controller

Features

• Pb-Free Available (RoHS Compliant)

• Provides two regulated voltages

- One standard buck PWM

The ISL6528 provides the power control and protection for

two output voltages in high-performance graphics cards and

other embedded processor applications. The dual-output

controller drives an N-Channel MOSFET in a standard buck

topology and a NPN pass transistor in a linear configuration.

The ISL6528 provides both a regulated high current, low

voltage supply and an independent, lower current supply

integrated in an 8-lead SOIC package. The controller is ideal

for graphics card applications where both graphics

- One linear controller

• Small converter size

- 600kHz constant frequency operation

- Small external component count

• Excellent output voltage regulation

- Both outputs: ±2% over temperature

• Single 5V bias and bootstrap supply

processing unit (GPU) and memory supplies are required.

The standard buck converter is a simple, single feedback

loop, voltage-mode control with fast transient response. Both

the switching regulator and linear regulator provide a

maximum static regulation tolerance of ±2% over line, load,

and temperature ranges. Each output is user-adjustable by

means of external resistors.

• Output voltage range: 0.8V to 3.3V

• Simple single-loop voltage-mode PWM control design

• Fast PWM converter transient response

- High-bandwidth error amplifier

- Full 0–100% duty ratio

• Linear controller drives bipolar linear pass transistor

• Fully-adjustable outputs

An integrated soft-start feature brings both supplies into

regulation in a controlled manner. Each output is monitored

via the FB pins for undervoltage events. If either output

drops below 52.5% of the internal reference voltage, both

regulators are shutdown.

• Undervoltage fault monitoring on both outputs

Applications

Ordering Information

•

Graphics–GPU and memory supplies

PKG.

DWG. #

• ASIC power supplies

o

PART NUMBER TEMP. RANGE ( C) PACKAGE

• Embedded processor and I/O supplies

• DSP supplies

ISL6528CB

0 to 70

8Ld SOIC Tape and Reel

0 to 70 8 Ld SOIC

8 Ld SOIC

M8.15

ISL6528CB-T

Related Literature

ISL6528CBZ

(See Note)

M8.15

(Pb-free)

• Technical Brief TB363 Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)

ISL6528CBZ-T

(See Note)

8Ld SOIC Tape and Reel (Pb-free)

ISL6528EVAL1

Evaluation Board

Pinout

NOTE: Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with

both SnPb and Pb-free soldering operations. Intersil Pb-free products

are MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ISL6528

(SOIC)

TOP VIEW

GND

VCC

DRIVE2

FB2

1

2

3

4

8

7

6

5

UGATE

BOOT

COMP

FB

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6528

Simplified Power System Diagram

+5V

+3.3V

Q1

V

OUT1

PWM

Q2

LINEAR

CONTROLLER

V

OUT2

CONTROLLER

+

D1

+

ISL6528

Typical Application

+5V

+3.3V

+

D2

C

IN

C

BP

VCC

BOOT

DRIVE2

FB2

V

Q2

OUT2

2.5V

C

BOOT

UGATE

Q1

V

OUT1

1.5V

L

+

OUT

C

OUT2

PHASE

ISL6528

+

D1

C

OUT1

FB

COMP

GND

FN9038.3

3

December 28, 2004

ISL6528

Absolute Maximum Ratings

Thermal Information

Thermal Resistance (Typical, Note 1)

o

UGATE, BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +10V

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +7V

FB, DRIVE2, FB2, COMP, . . . . . . . . . . . GND -0.3V to VCC +0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

θ

( C/W)

JA

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

110

o

Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C

o

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

(SOIC - Lead Tips Only)

Operating Conditions

Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%

Supply Voltage to drain of upper MOSFET . . . . . . . . . +3.3V ±10%

o

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0 C to 70 C

o

Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0 C to 125 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY CURRENT

Nominal Supply Current

POWER-ON RESET

Rising VCC Threshold

Falling VCC Threshold

OSCILLATOR AND SOFT-START

Free Running Frequency

Ramp Amplitude

I

UGATE and DRIVE2 Open

2

3.7

6.5

mA

CC

4.25

3.75

4.4

3.8

4.50

4.00

V

F

550

-

600

1.5

650

-

kHz

OSC

∆V

V

P-P

OSC

SS

Soft-Start Interval

T

3.10

3.42

3.75

ms

REFERENCE VOLTAGE

Reference Voltage

V

.784 0.800 .816

V

REF

System Accuracy

-2.00

-

+2.00

%

PWM CONTROLLER ERROR AMPLIFIER

DC Gain

-

15

-

80

-

dB

MHz

V/µs

%

Gain-Bandwidth Product

Slew Rate

GBWP

SR

6

Undervoltage Level (V /V

)

V

48.13 52.5 56.88

FB REF

UV

PWM CONTROLLER GATE DRIVER

UGATE Source Impedance

R

VCC = 5V, V

= 2.5V

-

2.75

3.0

5.0

Ω

UGATE

UGATE Sink Impedance

V

UGATE-PHASE

= 2.5V

UGATE

LINEAR REGULATOR ERROR AMPLIFIER

Output Drive Current

VCC > 4.5V

100

120

-

mA

%

Overvoltage Level (V

/V

)

V

150.0 160.0 175.0

48.13 52.5 56.88

FB2 REF

OV

Undervoltage Level (V /V

)

%

FB2 REF

UV

FN9038.3

4

December 28, 2004

ISL6528

Description

Functional Pin Descriptions

Operation Overview

The ISL6528 monitors and precisely controls two output

voltage levels. Refer to the Block Diagram, Simplified

Power System Diagram, and Typical Application Schematic

on pp. 2–3. The controller is intended for use in graphics

card or embedded processor applications with 3.3V and 5V

bias input available. The IC integrates both a standard buck

PWM controller and a linear controller. The PWM controller

is designed to regulate the high current GPU voltage

GND

VCC

DRIVE2

FB2

1

2

3

4

8

7

6

5

UGATE

BOOT

COMP

FB

GND (Pin 1)

(V

). The PWM controller drives a single N-Channel

OUT1

Signal ground for the IC. All voltage levels are measured

with respect to this pin. Place via close to pin to minimize

impedance path to ground plane.

MOSFET (Q1) in a standard buck converter configuration

and regulates the output voltage to a level programmed by

a resistor divider. The linear controller is designed to

regulate the lower current local memory voltage (V

through an external NPN pass transistor.

)

VCC (Pin 2)

OUT2

Provide a well decoupled 5V bias supply for the IC to this

pin. The voltage at this pin is monitored for Power-On Reset

(POR) purposes.

Initialization

The ISL6528 automatically initializes upon application of

input power. Special sequencing of the input supplies is not

necessary. The POR function continually monitors the input

bias supply voltage at the VCC pin. The POR function

initiates soft-start operation after the 5V bias supply voltage

exceeds its POR threshold.

DRIVE2 (Pin 3)

Connect this pin to the base terminal of an external bipolar

NPN transistor. This pin provides the base current drive for

the linear regulator pass transistor.

FB2 (Pin 4)

Soft-Start

Connect the output of the linear regulator to this pin through

a properly sized resistor divider. The voltage at this pin is

regulated to 0.8V. This pin is also monitored for undervoltage

events.

The POR function initiates the digital soft-start sequence.

Both the linear regulator error amplifier and PWM error

amplifier reference inputs are forced to track a voltage level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator regulates the output relative

to the tracked soft-start voltage slowly charging the output

capacitor(s). Simultaneously, the linear output follows the

smooth ramp of the soft-start function into normal regulation.

Pulling and holding FB2 above 1.25V shuts down both

regulators. Releasing FB2 initiates soft-start on both

regulators.

FB (Pin 5) and COMP (Pin 6)

Figure 1 shows the soft-start sequence for a typical application.

At T0, the +5V VCC bias voltage starts to ramp followed by the

3.3V input supply. Once the voltage on VCC crosses the 4.4V

POR threshold at time T1, both outputs begin their soft-start

sequence. The triangle waveform from the PWM oscillator is

compared to the rising error amplifier output voltage. As the

error amplifier voltage increases, the pulse-width on the

UGATE pin increases to reach its steady-state duty cycle at

time T2. The error amplifier reference of the linear controller

also rises relative to the soft-start reference. The resulting soft

FB and COMP are the available external pins of the error

amplifier. The FB pin is the inverting input of the error amplifier

and the COMP pin is the error amplifier output. These pins are

used to compensate the voltage-mode control feedback loop of

the standard buck converter.

BOOT (Pin 7)

Connect a suitable capacitor (0.47µF recommended) from

this pin to the source terminal of the upper MOSFET

(PHASE node). This bootstrap capacitor supplies the

UGATE driver the energy necessary to turn and hold the

upper MOSFET on. The absolute maximum voltage on

BOOT must be kept below 10V. This can be met with a 5V

VCC and 3.3V drain supply to the upper MOSFET.

ramp on DRIVE2 brings V

T2.

within regulation limits by time

OUT2

Undervoltage Protection

The FB and FB2 pins are monitored during converter

operation by two separate undervoltage (UV) comparators. If

the FB voltage drops below 52.5% of the reference voltage

(0.42V), a fault signal is generated. The internal fault logic

UGATE (Pin 8)

Connect UGATE to the upper MOSFET gate. This pin

provides the gate drive for the MOSFET.

FN9038.3

5

December 28, 2004

ISL6528

+5V (VCC)

V

(2.5V)

OUT2

V

(1.5V)

OUT1

+3.3V (UPPER FET DRAIN)

Delay Interval

V

0V

(0.5V/DIV)

(1V/DIV)

(2.5V)

V

(2.5V)

(1.5V)

OUT2

Internal Soft-Start Function

Delay Interval

V

OUT1

0V

(0.5V/DIV)

T2

TIME

T0

T1

T2

TIME

T0

T3

T4

FIGURE 2. UNDERVOLTAGE PROTECTION RESPONSE

FIGURE 1. SOFT-START INTERVAL

value chosen for R1, R4 can be calculated based on the

following equation:

shuts down both regulators simultaneously when the fault

signal triggers a restart.

R1 × 0.8V

OUT1

Figure 2 illustrates the protection feature responding to an

R4 = -------------------------------------

(EQ. 1)

V

– 0.8V

UV event on V

. At time T0, VOUT1 has dropped below

OUT1

52.5% of the nominal output voltage. Both outputs are

quickly shut down and the internal soft-start function begins

producing soft-start ramps. The delay interval, T0 to T3,

seen by the output is equivalent to three soft-start cycles.

After a short delay interval of 10.5ms, the fourth internal soft-

start cycle initiates a normal soft-start ramp of the output, at

time T3. Both outputs are brought back into regulation by

time T4, as long as the UV event has cleared.

If the output voltage desired is 0.8V, simply route VOUT1

back to the FB pin through R1, but do not populate R4.

+5V

D2

VCC

BOOT

+3.3V

Had the cause of the UV still been present after the delay

interval, the UV protection circuitry becomes active

approximately 875µs into the soft-start interval. A fault signal

could then be generated and the outputs once again

shutdown. The resulting hiccup mode style of protection

would continue to repeat indefinitely.

C4

UGATE

Q1

L

OUT

V

OUT1

ISL6528

Output Voltage Selection

+

D1

C

OUT1

The output voltage of the PWM converter can be

programmed to any level between V (i.e. +3.3V) and the

IN

FB

internal reference, 0.8V. An external resistor divider is used

to scale the output voltage relative to the reference voltage

and feed it back to the inverting input of the error amplifier,

see Figure 3. However, since the value of R1 affects the

values of the rest of the compensation components, it is

advisable to keep its value less than 5kΩ. Depending on the

C2

R1

C3

COMP

R3

C1

R2

R4

FIGURE 3. OUTPUT VOLTAGE SELECTION OF THE PWM

FN9038.3

December 28, 2004

6

ISL6528

PHASE voltage is then smoothed by the output filter, L

OUT

+3.3V

IN

and C

, to produce a DC voltage level.

OUT

The modulator transfer function is defined as V

/V .

OUT E/A

DRIVE2

FB2

Q2

The internal PWM comparator and driver circuits equate to a

V

OUT2

DC gain block dominated by the supply voltage, V , divided

IN

by the peak-to-peak magnitude of the triangle wave, ∆V

ISL6528

R5

.

OSC

+

C

R6

OUT2

The output filter components, L

and C

, shape the

OUT

overall modulator small-signal transfer function by

contributing a double pole break frequency at F and a

LC

zero at F

.

ESR

R5





R6

V

= 0.8 × 1 + -------

OUT2





Modulator Break Frequency Equations

1

F

= ---------------------------------------

FIGURE 4. OUTPUT VOLTAGE SELECTION OF THE LINEAR

LC

(EQ. 5)

2π ×

L

× C

O

The linear regulator output voltage is also set by means of

an external resistor divider as shown in Figure 4. The two

resistors used to set the output voltage should not exceed a

1

F

= -----------------------------------------

(EQ. 6)

ESR

2π × ESR × C

O

The compensation network consists of the error amplifier

and the impedance networks Z and Z . They provide the

link between the modulator transfer function and a

controllable closed loop transfer function of V /V

goal of component selection for the compensation network is

to provide a loop gain with high 0dB crossing frequency

) and adequate phase margin. Phase margin is the

difference between the closed loop phase at f

degrees.

parallel equivalent value, referred to as R , of 5kΩ. This

FB

IN FB

restriction is due to the manner of implementation of the soft-

start function. The following relationship must be met:

. The

OUT REF

R5 × R6

---------------------

< 5kΩ

(EQ. 2)

R

=

FB

R5 + R6

(f

0dB

To ensure the parallel combination of the feedback resistors

and 180

0dB

meets this criteria, choose a target value for R of less than

FB

5kΩ and then apply the following equations:

V

IN

OUT2

------------------

R5 =

× R

(EQ. 3)

FB

DRIVER

REF

OSC

PWM

R5 × V

L

OUT

REF

COMP

(EQ. 4)

R6 = ----------------------------------------

– V

V

OUT

V

OUT2

REF

-

PHASE

+

∆V

C

OSC

O

where V

OUT2

is the desired linear regulator output voltage

ESR

(PARASITIC)

and V

is the internal reference voltage, 0.8V. For an

REF

Z

output voltage of 0.8V, simply populate R5 with a value less

FB

than 5kΩ and do not populate R6.

Z

IN

V

E/A

+

V

Converter Shutdown

REF

ERROR

AMP

Pulling and holding the FB2 pin above a typical threshold of

1.28V will shutdown both regulators. Upon release of the

FB2 pin, the regulators enter into a soft-start cycle which

brings both outputs back into regulation.

DETAILED COMPENSATION COMPONENTS

Z

FB

V

OUT

C2

Z

IN

PWM Controller Feedback Compensation

C1

C3

R3

R2

A simplified representation of the voltage-mode control loop

used for output regulation by the standard buck converter is

R1

COMP

shown in Figure 5. The output voltage, V

the negative input of the error amplifier which is regulated to

the reference voltage level, V . The error amplifier output,

, is fed back to

OUT

FB

-

REF

+

V

, is compared with the triangle wave produced by the

E/A

oscillator, V

ISL6528

0.8V

, to provide a pulse-width modulated (PWM)

OSC

signal from the PWM comparator. This signal is then used to

switch the MOSFET and produce a PWM waveform with an

amplitude of V at the PHASE node. The square-wave

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

IN

FN9038.3

December 28, 2004

7

ISL6528

The compensation gain uses external impedance networks

and Z to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin.

Compensation Break Frequency Equations

Z

FB

IN

Poles:

1

F

= -------------------------------------------------------

(EQ. 8)

(EQ. 9)

P1

C1 × C2



×



----------------------

2π × R

2





C1 + C2

1

F

= -----------------------------------

P2

2π × R3 × C3

Application Guidelines

Zeros:

1

F

= -----------------------------------

Z1

Layout Considerations

(EQ. 10)

(EQ. 11)

2π × R2 × C1

Layout is very important in high frequency switching

converter design. With power devices switching efficiently at

600kHz, the resulting current transitions from one device to

another cause voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device overvoltage stress. Careful component

layout and printed circuit board design minimizes the voltage

spikes in the converters.

1

F

= ------------------------------------------------------

Z2

2π × (R1 + R3) × C3

Follow this procedure for selecting compensation

components by locating the poles and zeros of the

compensation network:

1. Set the loop gain (R2/R1) to provide a converter

bandwidth of one quarter of the switching frequency.

2. Place the first compensation zero, F , below the output

Z1

filter double pole (~75% F ).

LC

As an example, consider the turn-off transition of the PWM

MOSFET. Prior to turn-off, the MOSFET is carrying the full

load current. During turn-off, current stops flowing in the

MOSFET and is picked up by the lower Schottky diode. Any

parasitic inductance in the switched current path generates a

large voltage spike during the switching interval. Careful

component selection, tight layout of the critical components,

and short, wide traces minimizes the magnitude of voltage

spikes.

3. Position the second compensation zero, F , at the

Z2

output filter double pole, F

.

LC

4. Locate the first compensation pole, F , attheoutputfilter

P1

ESR zero, F

.

ESR

5. Position the second compensation pole at half the

converter switching frequency, F

.

SW

6. Check gain against error amplifier’s open-loop gain.

7. Estimate phase margin; repeat if necessary.

8.

There are two sets of critical components in a DC-DC

converter using the ISL6528. The switching components are

the most critical because they switch large amounts of

energy, and therefore tend to generate large amounts of

noise. Next are the small signal components which connect

to sensitive nodes or supply critical bypass current and

signal coupling.

OPEN LOOP

F

P1

F

Z1

Z2

P2

ERROR AMP GAIN

100

80

60

40

20

0

V













IN

-----------------

20log

V

OSC

COMPENSATION

GAIN

A multi-layer printed circuit board is recommended. Figure 7

shows the connections of the critical components in the

R2

--------









converter. Note that capacitors C and C

could each

20log

IN OUT

R1

-20

-40

-60

represent numerous physical capacitors. Dedicate one solid

layer, usually a middle layer of the PC board, for a ground

plane and make all critical component ground connections

through vias to this layer. Dedicate another solid layer as a

power plane and break this plane into smaller islands of

common voltage levels. Keep the metal runs from the

PHASE terminal to the output inductor short. The power

plane should support the input and output power nodes. Use

copper filled polygons on the top and bottom circuit layers for

the phase node. Use the remaining printed circuit layers for

small signal wiring. The wiring traces from the UGATE pin to

the MOSFET gate should be kept short and wide enough to

easily handle the 1A of drive current.

MODULATOR

LOOP GAIN

10M

GAIN

F

ESR

LC

10

100

1K

10K

100K

1M

FREQUENCY (Hz)

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

Figure 6 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual modulator gain has a high

gain peak dependent on the quality factor (Q) of the output

filter, which is not shown in Figure 6. Using the above

procedure should yield a compensation gain similar to the

curve plotted. The open loop error amplifier gain bounds the

compensation gain. Check the compensation gain at F

with the capabilities of the error amplifier.

P2

The switching components should be placed close to the

ISL6528 first. Minimize the length of the connections

between the input capacitors, C , and the power switches

IN

FN9038.3

December 28, 2004

8

ISL6528

PWM REGULATOR OUTPUT CAPACITORS

+3.3 V

IN

Modern digital ICs can produce high transient load slew

rates. High frequency capacitors initially supply the transient

current and slow the load rate-of-change seen by the bulk

capacitors. The bulk filter capacitor selection is generally

determined by the effective series resistance (ESR) and

voltage rating requirements rather than actual capacitance

requirements.

+5 VCC

BP

VCC

C

IN

C

D2

GND

BOOT

C

BOOT

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

Q1

UGATE

L

OUT

C

V

PHASE

OUT1

ISL6528

D1

COMP

OUT1

C

2

C

1

R

2

R1

Specialized low-ESR capacitors intended for switching-

regulator applications are recommended for the bulk

capacitors. The bulk capacitor’s ESR determines the output

ripple voltage and the initial voltage drop following a high

slew-rate transient edge. Aluminum electrolytic, tantalum,

and special polymer capacitor ESR values are related to the

case size with lower ESR available in larger case sizes.

However, the equivalent series inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient

loading. Unfortunately, ESL is not a specified parameter.

Work with your capacitor supplier and measure the

capacitor’s impedance with frequency to select a suitable

component. In most cases, multiple electrolytic capacitors of

small case size perform better than a single large case

capacitor.

FB

C

R

3

R4

+3.3 V

IN

DRIVE2

FB2

Q2

V

R5

OUT2

R6

C

OUT2

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

LINEAR REGULATOR OUTPUT CAPACITORS

by placing them nearby. Position both the ceramic and bulk

input capacitors as close to the upper MOSFET drain as

possible. Position the output inductor and output capacitors

between the upper MOSFET and lower diode and the load.

The output capacitors for the linear regulator provide

dynamic load current. The linear controller uses dominant

pole compensation integrated into the error amplifier and is

relatively insensitive to output capacitor selection. Output

capacitors should be selected for transient load regulation.

The critical small signal components include any bypass

capacitors, feedback components, and compensation

PWM Output Inductor Selection

components. Position the bypass capacitor, C , close to

BP

The PWM converter requires an output inductor. The output

inductor is selected to meet the output voltage ripple

requirements and sets the converter response time to a load

transient. The inductor value determines the converter’s

ripple current and the ripple voltage is also a function of the

ripple current. The ripple voltage and current are

the VCC pin with a via directly to the ground plane. Place the

PWM converter compensation components close to the FB

and COMP pins. The feedback resistors for both regulators

should also be located as close as possible to the relevant

FB pin with vias tied straight to the ground plane as required.

approximated by the following equations:

Component Selection Guidelines

V

– V

V

OUT

IN

OUT

(EQ. 11)

(EQ. 12)

------------------------------- ---------------

∆I =

×

Output Capacitor Selection

F

× L

V

S

IN

Output capacitors are required to filter the output and supply

the load transient current. The filtering requirements are a

function of switching frequency and output current ripple.

The load transient requirements are a function of the

transient load current slew rate (di/dt) and magnitude. These

requirements are generally met with a mix of capacitors and

careful layout.

∆V

= ∆I × ESR

OUT

Increasing the value of inductance reduces the output ripple

current and voltage ripple. However, increasing the

FN9038.3

9

December 28, 2004

ISL6528

inductance value will slow the converter response time to a

load transient.

For a through-hole design, several aluminum electrolytic

capacitors may be needed. For surface mount designs,

tantalum or special polymer capacitors can be used, but

caution must be exercised with regard to the capacitor surge

current rating. These capacitors must be capable of handling

the surge-current at power-up.

One of the parameters limiting the converter’s response to a

load transient is the time required to slew the inductor

current. Given a sufficiently fast control loop design, the

ISL6528 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

interval required to slew the inductor current from an initial

current value to the final current level. During this interval the

difference between the inductor current and the load current

must be supplied by the output capacitor(s). Minimizing the

response time can minimize the output capacitance

required.

Transistor Selection/Considerations

The ISL6528 requires two external transistors. One N-

channel MOSFET is used as the upper switch in a standard

buck topology PWM converter. The linear controller drives

an NPN bipolar transistor as a pass element. The transistors

should be selected based upon r

saturation voltages, gate/base supply requirements, and

thermal management considerations.

, current gain,

DS(ON)

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

UPPER MOSFET SWITCH SELECTION

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

components; conduction loss and switching loss. The

conduction losses account for a large portion of the power

dissipation of the MOSFET. Switching losses also contribute

to the overall MOSFET power loss.

L

V

× I

TRAN

O

t

= -------------------------------

(EQ. 13)

RISE

– V

IN

OUT

L

× I

O

TRAN

(EQ. 14)

t

= ------------------------------

FALL

V

OUT

2

P

≅ I × r

× D

(EQ. 15)

Conduction

o

DS(on)

where I

is the transient load current step, t

is the

TRAN

RISE

is the

response time to the application of load, and t

response time to the removal of load.

FALL

1

(EQ. 16)

P

≅ --I × V × t

o IN SW

× F

Switching

SW

2

With a +3.3V input source, the worst case response time can

be either at the application or removal of load and dependent

upon the output voltage setting. Be sure to check both of

these equations at the minimum and maximum output levels

for the worst case response time.

where I is the maximum load current, D is the duty cycle of

o

the converter (defined as V /V ), t

is the switching

is the PWM switching frequency.

O

IN SW

interval, and F

SW

These equations assume linear voltage-current transitions

and are approximations. The gate-charge losses are

dissipated by the ISL6528 and do not heat the MOSFET.

However, large gate-charge increases the switching interval,

Input Capacitor Selection

The important parameters for the bulk input capacitors are

the voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and

current ratings above the maximum input voltage and largest

RMS current required by the circuit. The capacitor voltage

rating should be at least 1.25 times greater than the

maximum input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 of the summation of the DC load current.

t

, which increases the upper MOSFET switching losses.

SW

Ensure that the MOSFET is within its maximum junction

temperature at high ambient temperature by calculating the

temperature rise according to package thermal-resistance

specifications. A separate heatsink may be necessary

depending upon MOSFET power, package type, ambient

temperature, air flow, and load current requirements.

Given the reduced available gate bias voltage (5V) a logic-

level transistor is recommended for the upper switch. Close

attention to layout guidelines should be exercised with

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitance

for the high frequency decoupling and bulk capacitors to

supply the RMS current. Small ceramic capacitors can be

placed very close to the upper MOSFET to suppress the

voltage induced in the parasitic circuit impedances. Connect

them directly to ground with a via placed very close to the

ceramic capacitor footprint.

devices exhibiting very low V

low gate threshold could lead to some shoot-through despite

counteracting circuitry present aboard the ISL6528.

characteristics, as the

GS(on)

NPN PASS TRANSISTOR SELECTION

A bipolar NPN transistor must be used with the linear

controller. Insure the current gain at the given operating V

CE

is sufficiently large to provide the desired maximum output

FN9038.3

December 28, 2004

10

ISL6528

load current when the base is fed with the minimum driver

output current.

+5V

+3.3V

D2

The main criteria for selection of the linear regulator pass

transistor is package selection for efficient removal of heat.

Select a package and heatsink that maintains the junction

temperature below the rating with a maximum expected

ambient temperature.

C

BOOT

VCC

BOOT

Q1

UGATE

The power dissipated in a linear regulator is:

PHASE

D1

P

≅ I × (V – V

OUT

)

(EQ. 17)

LINEAR

O

IN

ISL6528

where I is the maximum output current and V

O

nominal output voltage of the linear regulator.

is the

OUT

FIGURE 8. UPPER GATE DRIVE

where Q

is the maximum total gate charge of the

GATE

Diode Selection (D1)

Rectifier D1 conducts when MOSFET Q1 is off. The diode

should be a Schottky type for low power losses. The power

dissipation in the Schottky rectifier is approximated by:

MOSFET, C

BOOT

is the bootstrap capacitance, V

is

BOOT1

the bootstrap voltage immediately before turn-on, and

is the bootstrap voltage immediately after turn-on.

V

BOOT2

The bootstrap capacitor begins its refresh cycle when the

gate drive begins to turn off the MOSFET. A refresh cycle

ends when the MOSFET is turned on again, which varies

depending on the switching frequency and duty cycle.

P

≅ I × V × (1 – D)

O f

(EQ. 18)

CONDUCTION

where I is the maximum output current of the PWM

O

converter, V is the Schottky forward voltage drop, and D is

f

The minimum bootstrap capacitance can be calculated by

the duty cycle of the converter (defined as V /V ).

IN

O

rearranging Equation 19 and solving for C

.

BOOT

In addition to power dissipation, package selection and

heatsink requirements are the main design trade-offs in

choosing a Schottky rectifier. Since the three factors are

interrelated, the selection process is an iterative procedure.

The maximum junction temperature of the rectifier must

remain below the manufacturer’s specified value, typically

125°C. By using the package thermal resistance

specification and the Schottky power dissipation equation,

the junction temperature of the rectifier can be estimated. Be

sure to use the available airflow and ambient temperature to

determine the junction temperature rise.

Q

GATE

(EQ. 20)

----------------------------------------------------

C

≥

BOOT

V

– V

BOOT1

BOOT2

Typical gate charge values for MOSFETs considered in

these types of applications range from 20–100nC. Since the

voltage drop across D2 is offset by the voltage drop across

is simply VCC (+5V). A good rule is to keep the

voltage drop across the bootstrap capacitor no greater than

1V during the on-time of the MOSFET. Initial calculations

D1, V

BOOT1

with V

no less than 4V will quickly help narrow the

bootstrap capacitor range.

BOOT2

Bootstrap Component Selection

For example, consider a MOSFET is chosen with a

External bootstrap components, a diode and capacitor, are

required to provide sufficient gate enhancement to the

MOSFET. The internal MOSFET gate driver is supplied by

the external bootstrap circuitry as shown in Figure 8. The

maximum gate charge, Q , of 100nC. Limiting the voltage

g

drop across the bootstrap capacitor to 1V results in a value

of no less than 0.1µF. The tolerance of the ceramic capacitor

should also be considered when selecting the final bootstrap

capacitance value.

boot capacitor, C

, develops a floating supply voltage

BOOT

referenced to the PHASE pin. This supply is refreshed each

cycle, when D1 conducts, to a voltage of VCC less the boot

A fast recovery diode is recommended when selecting a

bootstrap diode to reduce the impact of reverse recovery

diode drop, V , plus the voltage rise across D1.

D2

charge loss. Otherwise, the recovery charge, Q , would

RR

Just after the PWM switching cycle begins and the charge

transfer from the bootstrap capacitor to the gate capacitance

is complete, the voltage on the bootstrap capacitor is at its

lowest point during the switching cycle. The charge lost on

the bootstrap capacitor will be equal to the charge

transferred to the equivalent gate-source capacitance of the

MOSFET as shown in Equation 19.

have to be added to the gate charge of the MOSFET and

taken into consideration when calculating the minimum

bootstrap capacitance. Employing a Schottky diode over a

standard diode will also increase the gate drive voltage

available to enhance the MOSFET.

Q

= C

× (V

– V

BOOT2

)

(EQ. 19)

GATE

BOOT

BOOT1

FN9038.3

December 28, 2004

11

ISL6528

ISL6528 Converter Application Circuit

Figure 9 shows a typical DC-DC converter circuit for a graphics card application. Additional information on this circuit

can be obtained by referencing application note AN9982.

+3.3V

C8

C7

C6

1µF

330µF

D2

+5V

BAT54

C5

1µF

C4

0.1µF

VOUT1

(6A)

L1

Q1

C1

UGATE

BOOT

COMP

FB

GND

1.71µH

VCC

ISL6528

D1

C9,C10

C11

1µF

Q2

DRIVE2

2x470µF

FB2

VOUT2

(1A)

R5

11.3kΩ

150pF

C2

1500pF

R2

R6

5.36kΩ

C14

C12

39.2kΩ

470µF

1µF

R1

2.32kΩ

R4

C1

0.018µF

R2

2.67kΩ

30.9Ω

Q1 FDS6690A

Fairchild

FZT649

Fairchild

Q2

L1

Panasonic

Diode Inc.

ETQ-P6F1R8BFA

B520C-13

D1

FIGURE 9. POWER SUPPLY APPLICATION CIRCUIT FOR A GRAPHICS CONTROLLER

FN9038.3

December 28, 2004

12

ISL6528

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

E

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

-

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

o

h x 45

D

3

4

-C-

α

µ

0.050 BSC

1.27 BSC

-

e

A1

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

C

B

0.10(0.004)

5

0.25(0.010) M

C A M B S

L

6

N

α

8

7

NOTES:

o

0

8

0

8

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9038.3

13

December 28, 2004


型号：	ISL6528
厂家：	Intersil
描述：	Dual Regulator - Standard Buck PWM and Linear Power Controller 双稳压器 - 标准降压PWM和线性电源控制器稳压器控制器
文件：	总13页 (文件大小：384K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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