ISL6532BCR_技术文档

ISL6532B

®

Data Sheet

July 2004

FN9120.3

ACPI Regulator/Controller for

Features

Dual Channel DDR Memory Systems

• Generates 2 Regulated Voltages

The ISL6532B provides a complete ACPI compliant power

solution for up to 4 DIMM dual channel DDR/DDR2 memory

systems. Included are both a synchronous buck controller

- Synchronous Buck PWM Controller with Standby LDO

- 3A Integrated Sink/Source Linear Regulator with

Accurate V

/2 Divider Reference

DDQ

and integrated LDO to supply V

S0/S1 states and standby current during S3 state. During

Run mode, a fully integrated sink-source regulator generates

with high current during

- Glitch-free Transitions During State Changes

• ACPI Compliant Sleep State Control

DDQ

• Integrated V

REF

Buffer

an accurate (V

/2) high current V voltage without the

DDQ

TT

• PWM Controller Drives Low Cost N-Channel MOSFETs

• 250kHz Constant Frequency Operation

need for a negative supply. A buffered version of the V

/2

DDQ

reference is provided as V

.

REF

• Tight Output Voltage Regulation

The switching PWM controller drives two N-Channel

MOSFETs in a synchronous-rectified buck converter

- Both Outputs: ±2% Over Temperature

topology. The synchronous buck converter uses voltage-

• 5V or 3.3V Down Conversion

mode control with fast transient response. Both the switching

regulator and integrated standby LDO provide a maximum

static regulation tolerance of ±2% over line, load, and

temperature ranges. The output is user-adjustable by means

of external resistors down to 0.8V.

• Fully-Adjustable Outputs with Wide Voltage Range: Down

to 0.8V supports DDR and DDR2 Specifications

• Simple Single-Loop Voltage-Mode PWM Control Design

• Fast PWM Converter Transient Response

• Over Current Protection on V and Under/Over-Voltage

TT

Switching the memory core output between the PWM

regulator and the standby LDO during state transitions is

accomplished smoothly via the internal ACPI control

circuitry. The NCH signal provides synchronized switching of

a backfeed blocking switch during the transitions eliminating

the need to route 5V Dual to the memory supply.

Monitoring of Both Outputs

• Integrated Thermal Shutdown Protection

• QFN Package Option

- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad

Flat No Leads - Product Outline

- QFN Near Chip Scale Package Footprint; Improves

PCB Efficiency, Thinner in Profile

An integrated soft-start feature brings V

DDQ

into regulation

in a controlled manner when returning to S0/S1 state from

S4/S5 or mechanical off states. During S0 the PGOOD

signal indicates that all supplies are within spec and

operational.

• Pb-free available

Applications

•

Single and Dual Channel DDR Memory Power Systems in

ACPI compliant PCs

Each output is monitored for under and over-voltage events.

Current limiting is included on the V and V

standby

TT

DDQ

regulators. Thermal shutdown is integrated.

•

Graphics cards - GPU and memory supplies

• ASIC power supplies

Pinout

ISL6532B (QFN)

TOP VIEW

• Embedded processor and I/O supplies

• DSP supplies

Ordering Information

20 19 18 17 16

5VSBY

GND

VTT

NCH

TEMP. RANGE

o

1

2

3

4

5

15

14

13

12

11

PART NUMBER

( C)

PACKAGE

PKG. DWG. #

PGOOD

GND

ISL6532BCR

0 to 70

20 Ld 6x6 QFN L20.6x6

ISL6532BCRZ

(See Note)

20 Ld 6x6 QFN L20.6x6

(Pb-free)

VTT

COMP

FB

VDDQ

*Add “-T” suffix to part number for tape and reel packaging.

6

7

8

9

10

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding

compounds/die attach materials and 100% matte tin plate termination finish, which

is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J Std-020B.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL6532B

Simplified Power System Diagram

12V

5VSBY

5V

SLP_S3

SLP_S5

SLEEP

STATE

LOGIC

Q1

Q2

V

DDQ

PWM

CONTROLLER

+

5VSBY/3V3SBY

STANDBY

LDO

ISL6532B

V

REF

TT

VTT

REGULATOR

+

Typical Application - 5V or 3.3V Input

5VSBY

+12V

+3.3V

C

BP

+5V OR +3.3V

R

NCH

PGOOD

S3#

S5#

V

DDQ

SLP_S3

SLP_S5

NCH

V

REF

+

VREF_OUT

C

IN

VREF_IN

+

UGATE

Q1

Q2

V

DDQ

2.5V

C

SS

L

OUT

+

ISL6532B

LGATE

C

VDDQ

VTT

VDDQ

V

TT

+

C

VTT

VTTSNS

FB

COMP

GND

3

ISL6532B

Typical Application - Input From 5V Dual

5VSBY

+12V

+3.3V

C

BP

5V DUAL

R

NCH

PGOOD

S3#

S5#

V

DDQ

SLP_S3

SLP_S5

NCH

V

REF

+

VREF_OUT

VREF_IN

C

IN

UGATE

LGATE

Q1

Q2

V

DDQ

2.5V

C

SS

L

OUT

+

ISL6532B

C

VDDQ

VTT

VDDQ

V

TT

+

C

VTT

VTTSNS

FB

COMP

GND

4

ISL6532B

Absolute Maximum Ratings

Thermal Information

o

5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V

P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +14V

UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V

All other Pins . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VSBY + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2

Thermal Resistance (Typical, Notes 1, 2) θ_JA( C/W) θ_JC( C/W)

QFN Package . . . . . . . . . . . . . . . . . . . 32

Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C

5

o

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

o

Recommended Operating Conditions

Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%

Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Supply Voltage on 3V3SBY . . . . . . . . . . . . . . . . . . . . . +3.3V ±10%

o

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0 C to 70 C

o

Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0 C to 125 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams and Typical Application Schematics

PARAMETER

5VSBY SUPPLY CURRENT

Nominal Supply Current

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

S3# & S5# HIGH, UGATE/LGATE Open

3.00

3.50

5.25

-

7.25

4.75

mA

CC_S0

CC_S3

S3# LOW, S5# HIGH, UGATE/LGATE

Open

I

S5# LOW, S3# Don’t Care,

UGATE/LGATE Open

300

-

800

µA

CC_S5

POWER-ON RESET

Rising 5VSBY POR Threshold

Falling 5VSBY POR Threshold

Rising P12V POR Threshold

Falling P12V POR Threshold

OSCILLATOR AND SOFT-START

PWM Frequency

4.00

3.60

10.0

8.80

-

4.35

3.95

10.5

9.75

V

f

220

-

250

280

-

kHz

V

OSC

Ramp Amplitude

∆V

1.5

OSC

Error Amp Reset Time

VDDQ Soft-Start Interval

REFERENCE VOLTAGE

Reference Voltage

t

S5# LOW to S5# HIGH

6.5

-

9.5

ms

RESET

t

SS

V

-

0.800

-

V

REF

System Accuracy

-2.0

+2.0

%

PWM CONTROLLER ERROR AMPLIFIER

DC Gain

Guaranteed By Design

-

15

-

80

-

dB

Gain-Bandwidth Product

Slew Rate

GBWP

SR

MHz

V/µs

6

STATE LOGIC

S3# Transition Level

V

-

1.5

-

V

S3

S5

S5# Transition Level

5

ISL6532B

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams and Typical Application Schematics (Continued)

PARAMETER

PWM CONTROLLER GATE DRIVERS

UGATE and LGATE Source

UGATE and LGATE Sink

NCH BACKFEED CONTROL

NCH Current Sink

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

-

-0.8

0.8

-

A

GATE

I

NCH = 0.8V

-

6

mA

V

NCH

NCH Trip Level

V

9.0

9.5

10

NCH

VDDQ STANDBY LDO

Output Drive Current

P5VSBY = 5.0V

P5VSBY = 3.3V

-

650

550

mA

VTT REGULATOR

Upper Divider Impedance

Lower Divider Impedance

VREF_OUT Buffer Source Current

R

-

2.5

-

kΩ

mA

A

U

R

L

I

-

2

3

VREF_OUT

Maximum V Load Current

TT

I

Periodic load applied with 30% duty cycle

and 10ms period using ISL6532EVAL1

evaluation board (see Application Note

AN1055)

-3

-

VTT_MAX

VTT Over Current Trip

PGOOD

I

By Design

-3.3

-

3.3

A

TRIP_VTT

PGOOD Rising Threshold

PGOOD Falling Threshold

PROTECTION

V

S3# & S5# HIGH

-

57.5

45.0

-

%

VTTSNS/ VDDQ

V

VTTSNS/ VDDQ

VDDQ OV Level

V

/V

FB REF

S3# & S5# HIGH

By Design

-

115

85

-

%

VDDQ UV Level

/V

FB REF

Thermal Shutdown Limit

T

140

°C

SD

P5VSBY (Pin 8)

This pin provides the V

Functional Pin Description

5VSBY (Pin 1)

5VSBY is the bias supply of the ISL6532B. It is typically

connected to the 5V standby rail of an ATX power supply.

During S4/S5 sleep states the ISL6532B enters a reduced

power mode and draws less than 1mA (I

5VSBY supply. This pin should be locally bypassed using a

0.1µF capacitor.

output power during the S3

DDQ

sleep state. The regulator is capable of providing standby

power from either a 5V or 3.3V source.

V

DDQ

GND (Pin 2, 13, 21)

) from the

CC5

The GND terminals of the ISL6532B provide the return path

for the V LDO, Standby LDO and switching MOSFET gate

TT

drivers. High ground currents are conducted directly through

the exposed paddle of the QFN package which must be

electrically connected to the ground plane through a path as

low in inductance as possible.

P12V (Pin 18)

P12V provides the gate drive current to the switching

MOSFETs of the PWM power stage. The V regulation

TT

circuit is also powered by P12V. P12V is only required during

S0/S1/S2 operation. P12V is typically connected to the +12V

rail of an ATX power supply.

UGATE (Pin 20)

UGATE drives the upper (control) FET of the V

DDQ

synchronous buck switching regulator. UGATE is driven

between GND and P12V.

6

ISL6532B

The calculated capacitance, C , will charge the output

SS

LGATE (Pin 19)

capacitor bank on the V rail in a controlled manner without

reaching the current limit of the V LDO.

TT

LGATE drives the lower (synchronous) FET of the V

synchronous buck switching regulator. LGATE is driven

between GND and P12V.

DDQ

NCH (Pin 15)

NCH is an open-drain output that controls the MOSFET

FB (Pin 11) and COMP (Pin 12)

blocking backfeed from V

to the input rail during sleep

DDQ

The V

DDQ

switching regulator employs a single voltage

states. A 2kΩ or larger resistor is to be tied between the 12V

rail and the NCH pin. Until the voltage on the NCH pin

reaches the NCH trip level, the PWM is disabled.

control loop. FB is the negative input to the voltage loop error

amplifier. The positive input of the error amplifier is

connected to a precision 0.8V reference and the output of

the error amplifier is connected to the COMP pin. The V

output voltage is set by an external resistor divider

DDQ

If NCH is not actively utilized, it still must be tied to the 12V

rail through a resistor. For systems using 5V dual as the

input to the switching regulator, a time constant, in the form

of a capacitor, can be added to the NCH pad to delay start of

the PWM switcher until the 5V dual has switched from

5VSBY to 5VATX.

connected to FB. With a properly selected divider, V

can

DDQ

be set to any voltage between the power rail (reduced by

converter losses) and the 0.8V reference. Loop

compensation is achieved by connecting an AC network

across COMP and FB.

PGOOD (Power Good) (Pin 14)

The FB pin is also monitored for under and over-voltage

events.

Power Good is an open-drain logic output that changes to a

logic low if the V regulator is out of regulation in S0/S1/S2

TT

state. PGOOD will always be low in any state other than

S0/S1/S2.

VDDQ (Pins 5, 6)

The V

pins should be connected externally together to

the regulated V output. During S0/S1 states, the V

DDQ

TT

S5# (Pin 17)

pins serve as inputs to the V regulator and to the V

TT

Reference precision divider. During S3 (Suspend to RAM)

state, the V pins serve as an output from the integrated

This pin accepts the SLP_S5# sleep state signal.

S3# (Pin 16)

DDQ

standby LDO.

This pin accepts the SLP_S3# sleep state signal.

VTT (Pins 3, 4)

Functional Description

The VTT pins should be connected together. During S0/S1

Overview

states, the VTT pins serve as the outputs of the V linear

TT

regulator. During any sleep state, the V regulator is

TT

disabled.

The ISL6532B provides complete control, drive, protection

and ACPI compliance for a regulator powering DDR memory

systems. It is primarily designed for computer applications

powered from an ATX power supply. A 250kHz Synchronous

Buck Regulator with a precision 0.8V reference provides the

proper Core voltage to the system memory of the computer.

An internal LDO regulator with the ability to both sink and

source current and an externally available buffered reference

VTTSNS (Pin 7)

VTTSNS is used as the feedback for control of the V linear

TT

regulator. Connect this pin to the V output at the physical

TT

point of desired regulation.

VREF_OUT (Pin 9)

that tracks the V

output by 50% provides the V

TT

DDQ

termination voltage.

VREF_OUT is a buffered version of V and also acts as the

TT

reference voltage for the V linear regulator. It is

TT

recommended that a minimum capacitance of 0.1µF be

ACPI compliance is realized through the SLP_S3 and

SLP_S5 sleep signals and through monitoring of the 12V

ATX bus.

connected between V

and VREF_OUT and also

DDQ

between VREF_OUT and GND for proper operation.

VREF_IN (Pin 10)

Initialization

A capacitor, C , connected between VREF_IN and ground

SS

is required. This capacitor and the parallel combination of

The ISL6532B automatically initializes upon receipt of input

power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input bias supply voltages. The POR monitors

the bias voltage at the 5VSBY and P12V pins. The POR

function initiates soft-start operation after the bias supply

voltages exceed their POR thresholds.

the Upper and Lower Divider Impedance (R ||R ), sets the

U

L

time constant for the start up ramp when transitioning from

S3 to S0/S1/S2.

The minimum value for C can be found through the

SS

following equation:

C

⋅ V

VTTOUT

DDQ

R

L

------------------------------------------------

>

C

SS

||

10 ⋅ 2A ⋅ R

U

7

ISL6532B

By directly monitoring 12VATX and the SLP_S3 and SLP_S5

ACPI State Transitions

signals, the ISL6532B can achieve PGOOD status

significantly faster than other devices that depend on the

Latched_Backfeed_Cut signal for timing.

Cold Start (S5/S4 to S0 Transition)

At the onset of a mechanical start, the ISL6532B receives it’s

bias voltage from the 5V Standby bus (5VSBY). As soon as

the SLP_S3 and SLP_S5 signals have transitioned HIGH,

the ISL6532B starts an internal counter. Following a cold

start or any subsequent S5 state, state transitions are

ignored until the system enters S0/S1. None of the

Active to Sleep (S0 to S3 Transition)

When SLP_S3 goes LOW with SLP_S5 still HIGH, the

ISL6532B will disable the V linear regulator. The V

TT

DDQ

standby regulator will be enabled and the V

switching

DDQ

regulator will be disabled. NCH is pulled low to disable the

backfeed blocking MOSFET. PGOOD will also transition

regulators will begin the soft start procedure until the 5V

Standby bus has exceeded POR, the 12V bus has exceeded

LOW. When V is disabled, the internal reference for the

POR and V

NCH

has exceeded the trip level.

TT

V

regulator is internally shorted to the V rail. This allows

TT

Once all of these conditions are met, the PWM error

amplifier will first be reset by internally shorting the COMP

pin to the FB pin. This reset lasts for 2048 clock cycles which

the V rail to float. When floating, the voltage on the V

rail will depend on the leakage characteristics of the memory

and MCH I/O pins. It is important to note that the V rail

may not bleed down to 0V.

TT TT

TT

is typically 8.2ms (one clock cycle = 1/f

start sequence will then begin.

). The digital soft

OSC

The V

rail will be supported in the S3 state through the

DDQ

standby V

The PWM error amplifier reference input is clamped to a level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator generates PHASE pulses of

increasing width that charge the output capacitor(s). The

LDO. When S3 transitions LOW, the Standby

DDQ

regulator is immediately enabled. The switching regulator is

disabled synchronous to the switching waveform. The shut

off time will range between 4 and 8µs. The standby LDO is

capable of supporting up to 650mA of load with P5VSBY tied

to the 5V Standby Rail. The standby LDO may receive input

from either the 3.3V Standby rail or the 5V Standby rail

through the P5VSBY pin. It is recommended that the 5V

Standby rail be used as the current delivery capability of the

LDO is greater.

internal V LDO will also soft start through the reference

TT

that tracks the output of the PWM regulator. The soft start

lasts for 2048 clock cycles, which is typically 8.2ms. This

method provides a rapid and controlled output voltage rise.

Figure 1 shows the soft start sequence for a typical cold

start. Due to the soft start capacitance, C , on the

SS

VREF_IN pin, the S5 to S0 transition profile of the V rail

TT

will have a more rounded features at the start and end of the

Sleep to Active (S3 to S0 Transition)

When SLP_S3 transitions from LOW to HIGH with SLP_S5

held HIGH and after the 12V rail exceeds POR, the

soft start whereas the V

profile has distinct starting and

DDQ

ending points to the ramp up.

ISL6532B will enable the V

switching regulator, disable

DDQ

the V

standby regulator, enable the V LDO and force

DDQ

TT

the NCH pin to a high impedance state turning on the

blocking MOSFET. The internal short between the V

S3

S5

TT

reference and the V rail is released. Upon release of the

TT

short, the capacitor on VREF_IN is then charged up through

12VATX 2V/DIV

5VSBY

the internal resistor divider network. The V output will

TT

V

DDQ

500mV/DIV

follow this capacitor charge-up, acting as the S3 to S0

1V/DIV

transition soft start for the V rail. The PGOOD comparator

TT

is enabled only after 2048 clock cycles, or typically 8.2ms,

have passed following the S3 transition to a HIGH state.

V

TT

500mV/DIV

Figure 2 illustrates a typical state transition from S3 to S0. It

should be noted that the soft start profile of the V LDO

TT

PGOOD

5V/DIV

output will vary according to the value of the capacitor on the

VREF_IN pin.

2048 CLOCK

CYCLES

2048 CLOCK

CYCLES

Active to Shutdown (S0 to S4/S5 Transition)

When the system transitions from active, S0, state to

shutdown, S4/S5, state, the ISL6532B IC disables all

regulators and forces the PGOOD pin and the NCH pin

LOW.

12V POR

SOFT START

SOFT START ENDS

PGOOD COMPARATOR

ENABLED

INITIATES

FIGURE 1. TYPICAL COLD START

8

ISL6532B

V

DDQ

S3

S5

12VATX 2V/DIV

V

DDQ

500mV/DIV

V

TT

500mV/DIV

V

TT

500mV/DIV

INTERNAL DELAY

DELAY INTERVAL

PGOOD

5V/DIV

2048 CLOCK

CYCLES

PGOOD COMPARATOR

12V POR

ENABLED

FIGURE 2. TYPICAL S3 TO S0 STATE TRANSITION

T0

T1

T2

TIME

V

Over Current Protection

TT

FIGURE 3. V /V

LDO UNDER VOLTAGE PROTECTION

RESPONSES

TT DDQ

The internal V LDO is protected from fault conditions

TT

through a 3.3A current limit. This current limit protects the

ISL6532B if the LDO is sinking or sourcing current. During

Shoot-Through Protection

an overcurrent event on the V LDO, only the V LDO is

TT TT

A shoot-through condition occurs when both the upper and

lower MOSFETs are turned on simultaneously, effectively

shorting the input voltage to ground. To protect from a shoot-

through condition, the ISL6532B incorporates specialized

circuitry which insures that complementary MOSFETs are

not ON simultaneously.

disabled. Once the over current condition on the V rail is

TT

removed, V will recover.

TT

Over/Under Voltage Protection.

Both the internal V LDO and the V

regulator are

TT

DDQ

protected from faults through internal Over/Under voltage

detection circuitry. If either rail falls below 85% of the targeted

voltage, then an undervoltage event is tripped. An under

voltage will disable all regulators for a period of 3 soft-start

cycles, after which a normal soft-start is initiated. If the output

remains under 85% of target, the regulators will continue to be

disabled and soft-started in a hiccup mode until the fault is

cleared. See Figure 3.

The adaptive shoot-through protection utilized by the V

DDQ

regulator looks at the lower gate drive pin, LGATE, and the

upper gate drive pin, UGATE, to determine whether a

MOSFET is ON or OFF. If the voltage from UGATE or from

LGATE to GND is less than 0.8V, then the respective

MOSFET is defined as being OFF and the other MOSFET is

allowed to be turned ON. This method allows the V

regulator to both source and sink current.

DDQ

If either rail exceeds 115% of the targeted voltage, then all

outputs are immediately disabled. The ISL6532B will not re-

enable the outputs until either the bias voltage is toggled in

order to initiate a POR or the SLP_S5 signal is forced LOW

and then back to HIGH.

Since the voltage of the MOSFET gates are being measured

to determine the state of the MOSFET, the designer is

encouraged to consider the repercussions of introducing

external components between the gate drivers and their

respective MOSFET gates before actually implementing

such measures. Doing so may interfere with the shoot-

through protection.

Thermal Protection (S0/S3 State)

If the ISL6532B IC junction temperature reaches a nominal

o

temperature of 140 C, all regulators will be disabled. The

ISL6532B will not re-enable the outputs until the junction

temperature drops below 110 C and either the bias voltage

o

Application Guidelines

is toggled in order to initiate a POR or the SLP_S5 signal is

forced LOW and then back to HIGH.

Layout Considerations

Layout is very important in high frequency switching

converter design. With power devices switching efficiently at

250kHz, the resulting current transitions from one device to

another cause voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

9

ISL6532B

12V

ATX

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device over-voltage stress. Careful component

layout and printed circuit board design minimizes these

voltage spikes.

P12V

C

BP

GND

NCH

V

IN_DDR

ISL6532B

As an example, consider the turn-off transition of the upper

MOSFET. Prior to turn-off, the MOSFET is carrying the full

load current. During turn-off, current stops flowing in the

MOSFET and is picked up by the lower MOSFET. Any

parasitic inductance in the switched current path generates a

large voltage spike during the switching interval. Careful

component selection, tight layout of the critical components,

and short, wide traces minimizes the magnitude of voltage

spikes.

5VSBY

P5VSBY

5VSBY

C

IN

C

BP

GND

L

UGATE

OUT

Q

1

V

DDQ

C

OUT1

LGATE

COMP

Q

2

There are two sets of critical components in the ISL6532B

switching converter. The switching components are the most

critical because they switch large amounts of energy, and

therefore tend to generate large amounts of noise. Next are

the small signal components which connect to sensitive

nodes or supply critical bypass current and signal coupling.

C

2

C

1

R

2

R

1

FB

C

R

3

R

4

A multi-layer printed circuit board is recommended. Figure 4

shows the connections of the critical components in the

VDDQ(2)

VTT(2)

V

DDQ

converter. Note that capacitors C and C

could each

IN OUT

V

TT

represent numerous physical capacitors. Dedicate one solid

layer, usually a middle layer of the PC board, for a ground

plane and make all critical component ground connections

with vias to this layer. Dedicate another solid layer as a

power plane and break this plane into smaller islands of

common voltage levels. Keep the metal runs from the

PHASE terminals to the output inductor short. The power

plane should support the input power and output power

nodes. Use copper filled polygons on the top and bottom

circuit layers for the phase nodes. Use the remaining printed

circuit layers for small signal wiring. The wiring traces from

the GATE pins to the MOSFET gates should be kept short

and wide enough to easily handle the 1A of drive current.

C

OUT2

GND PAD

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

Feedback Compensation - PWM Buck Converter

Figure 5 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

In order to dissipate heat generated by the internal V LDO,

TT

the ground pad, pin 21, should be connected to the internal

ground plane through at least four vias. This allows the heat

to move away from the IC and also ties the pad to the ground

plane through a low impedance path.

(V

) is regulated to the Reference voltage level. The

OUT

error amplifier output (V ) is compared with the oscillator

E/A

(OSC) triangular wave to provide a pulse-width modulated

(PWM) wave with an amplitude of V at the PHASE node.

IN

The switching components should be placed close to the

ISL6532B first. Minimize the length of the connections

The PWM wave is smoothed by the output filter (L and C ).

O

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

between the input capacitors, C , and the power switches

IN

by placing them nearby. Position both the ceramic and bulk

input capacitors as close to the upper MOSFET drain as

possible. Position the output inductor and output capacitors

between the upper and lower MOSFETs and the load.

OUT E/A

Gain and the output filter (L and C ), with a double pole

O

break frequency at F and a zero at F

. The DC Gain of

LC ESR

the modulator is simply the input voltage (V ) divided by the

IN

peak-to-peak oscillator voltage ∆V

OSC

.

The critical small signal components include any bypass

capacitors, feedback components, and compensation

components. Place the PWM converter compensation

components close to the FB and COMP pins. The feedback

resistors should be located as close as possible to the FB

pin with vias tied straight to the ground plane as required.

Modulator Break Frequency Equations

1

F

= ------------------------------------------

F

= -------------------------------------------

LC

ESR

2π x ESR x C

2π x

L

x C

O O

O

10

ISL6532B

V

Compensation Break Frequency Equations

IN

DRIVER

OSC

PWM

L

1

O

COMPARATOR

V

DDQ

F

= -----------------------------------

F

= --------------------------------------------------------

Z1

P1

2π x R x C

C

x C

2













1

-

---------------------

2π x R

x

PHASE

2

+

∆V

C

O

C

+ C

OSC

1

2

1

F

= ------------------------------------------------------

F

= -----------------------------------

ESR

(PARASITIC)

Z2

P2

2π x (R + R ) x C

2π x R x C

1

3

Z

FB

V

Figure 6 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual Modulator Gain has a high

gain peak due to the high Q factor of the output filter and is

not shown in Figure 6. Using the above guidelines should

give a Compensation Gain similar to the curve plotted. The

open loop error amplifier gain bounds the compensation

gain. Check the compensation gain at FP2 with the

capabilities of the error amplifier. The Closed Loop Gain is

constructed on the graph of Figure 6 by adding the

Modulator Gain (in dB) to the Compensation Gain (in dB).

This is equivalent to multiplying the modulator transfer

function to the compensation transfer function and plotting

the gain.

E/A

Z

-

IN

+

REFERENCE

ERROR

AMP

DETAILED COMPENSATION COMPONENTS

Z

FB

V

DDQ

C

1

Z

IN

C

R

3

2

3

2

R

1

COMP

FB

-

+

R

4

The compensation gain uses external impedance networks

ISL6532B

Z

and Z to provide a stable, high bandwidth (BW) overall

REFERENCE

FB IN

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

R









1

V

= 0.8 × 1 + ------



DDQ

R



4

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN AND OUTPUT

VOLTAGE SELECTION

100

F

P1

F

Z2

Z1

P2

80

60

40

20

0

The compensation network consists of the error amplifier

(internal to the ISL6532B) and the impedance networks Z

OPEN LOOP

ERROR AMP GAIN

IN

and Z . The goal of the compensation network is to provide

FB

a closed loop transfer function with the highest 0dB crossing

20LOG

(R /R )

frequency (f

) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f and

2

1

0dB

20LOG

(V /∆V

)

0dB

IN OSC

180 degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R , R ,

COMPENSATION

GAIN

MODULATOR

GAIN

-20

-40

-60

1

2

CLOSED LOOP

GAIN

R , C , C , and C ) in Figure 5. Use these guidelines for

3

1

2

3

locating the poles and zeros of the compensation network:

F

LC

F

ESR

100K

FREQUENCY (Hz)

10

100

1K

10K

1M

10M

1. Pick Gain (R /R ) for desired converter bandwidth.

2

1

ST

2. Place 1 Zero Below Filter’s Double Pole (~75% F ).

LC

ND

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

3. Place 2

Zero at Filter’s Double Pole.

ST

4. Place 1 Pole at the ESR Zero.

ND

5. Place 2

Pole at Half the Switching Frequency.

Output Voltage Selection

The output voltage of the VDDQ PWM converter can be

programmed to any level between VIN and the internal

reference, 0.8V. An external resistor divider is used to scale

the output voltage relative to the reference voltage and feed

it back to the inverting input of the error amplifier, see

Figure 6.

6. Check Gain against Error Amplifier’s Open-Loop Gain.

7. Estimate Phase Margin - Repeat if Necessary.

11

ISL6532B

However, since the value of R1 affects the values of the rest of

Output Capacitor Selection - LDO Regulator

The output capacitors used in LDO regulators are used to

provide dynamic load current. The amount of capacitance

and type of capacitor should be chosen with this criteria in

mind.

the compensation components, it is advisable to keep its

value less than 5kΩ. Depending on the value chosen for R1,

R4 can be calculated based on the following equation:

R1 × 0.8V

R4 = ----------------------------------

V

– 0.8V

DDQ

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

If the output voltage desired is 0.8V, simply route V

to the FB pin through R1, but do not populate R4.

back

DDQ

The output voltage for the internal V linear regulator is set

TT

internal to the ISL6532B to track the V

voltage by 50%.

DDQ

There is no need for external programming resistors.

V

- V

OUT

V

OUT

IN

Fs x L

∆V

OUT

= ∆I x ESR

∆I =

x

Component Selection Guidelines

V

IN

Output Capacitor Selection - PWM Buck Converter

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

An output capacitor is required to filter the inductor current

and supply the load transient current. The filtering

requirements are a function of the switching frequency and

the ripple current. The load transient requirements are a

function of the slew rate (di/dt) and the magnitude of the

transient load current. These requirements are generally met

with a mix of capacitors and careful layout.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6532B will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

DDR memory systems are capable of producing transient

load rates above 1A/ns. High frequency capacitors initially

supply the transient and slow the current load rate seen by the

bulk capacitors. The bulk filter capacitor values are generally

determined by the ESR (Effective Series Resistance) and

voltage rating requirements rather than actual capacitance

requirements.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

L x I

TRAN

OUT

t

=

t

=

FALL

RISE

V

- V

V

OUT

IN

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor’s ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the Equivalent Series Inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

where: I

is the transient load current step, t

is the

TRAN

RISE

is the

response time to the application of load, and t

FALL

response time to the removal of load. The worst case

response time can be either at the application or removal of

load. Be sure to check both of these equations at the

minimum and maximum output levels for the worst case

response time.

Input Capacitor Selection - PWM Buck Converter

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time the upper MOSFET

turns on. Place the small ceramic capacitors physically close

to the MOSFETs, between the drain of upper MOSFET and

the source of lower MOSFET.

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

12

ISL6532B

The important parameters for the bulk input capacitance are

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

the voltage rating and the RMS current rating. For reliable

operation, select bulk capacitors with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. Their voltage rating should be

at least 1.25 times greater than the maximum input voltage,

while a voltage rating of 1.5 times is a conservative

guideline. For worst cases, the RMS current rating

requirement for the input capacitor of a buck regulator is

approximately 1/2 the DC output load current.

components; conduction loss and switching loss. The

conduction losses are the largest component of power

dissipation for both the upper and the lower MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor. The switching losses seen when

sourcing current will be different from the switching losses

seen when sinking current. When sourcing current, the

upper MOSFET realizes most of the switching losses. The

lower switch realizes most of the switching losses when the

converter is sinking current (see the equations below).

These equations assume linear voltage-current transitions

and do not adequately model power loss due the reverse-

recovery of the upper and lower MOSFET’s body diode. The

gate-charge losses are dissipated in part by the ISL6532B

and do not significantly heat the MOSFETs. However, large

gate-charge increases the switching interval, tSW which

increases the MOSFET switching losses. Ensure that both

MOSFETs are within their maximum junction temperature at

high ambient temperature by calculating the temperature

rise according to package thermal-resistance specifications.

A separate heatsink may be necessary depending upon

MOSFET power, package type, ambient temperature and air

flow.

The maximum RMS current required by the regulator may be

closely approximated through the following equation:

2

V

– V

V

OUT

V

IN







 

 

 

2

1

12

OUT

IN

OUT

---------------

------

------------------------------- ---------------

I

=

× I

+

×



RMS

OUT

V

L × f

MAX



IN

sw

For a through hole design, several electrolytic capacitors

may be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge current rating. These

capacitors must be capable of handling the surge-current at

power-up. Some capacitor series available from reputable

manufacturers are surge current tested.

MOSFET Selection - PWM Buck Converter

The ISL6532B requires 2 N-Channel power MOSFETs for

switching power and a third MOSFET to block backfeed from

V

to the Input in S3 Mode. These should be selected

Approximate Losses while Sourcing current

DDQ

2

1

based upon r

, gate supply requirements, and thermal

DS(ON)

management requirements.

--

P

= Io × r

× D + ⋅ Io × V × t

× f

SW

UPPER

LOWER

DS(ON)

IN

2

x (1 - D)

s

2

P

= Io x r

DS(ON)

Approximate Losses while Sinking current

2

P

= Io x r

x D

UPPER

DS(ON)

2

1

--

P

= Io × r

× (1 – D) + ⋅ Io × V × t

× f

SW s

LOWER

DS(ON)

IN

2

Where: D is the duty cycle = V

OUT

/ V ,

IN

is the combined switch ON and OFF time, and

t

SW

f is the switching frequency.

s

13

ISL6532B

of-Materials and circuit board description, can be found in

Application Note AN1055.

ISL6532B Application Circuit

Figure 7 shows an application circuit utilizing the ISL6532B.

Detailed information on the circuit, including a complete Bill-

5VSBY

VCC12

VCC5

R

1

+3.3V

4.99kΩ

C

17,18

1µF

Q

5

R

C

2

16

1µF

10.0kΩ

L

PGOOD

1

NCH

2.1µH

S5

S3

SLP_S5#

SLP_S3#

V

DDQ

+

C

1-3

2200µF

4,5

1µF

C

26

0.1µF

V

REF

VREF_OUT

VREF_IN

V

UGATE

LGATE

Q

DDQ

1,3

C

27

0.1µF

2.5V

C

19

0.47µF

L

2

C

+

6-8

1800µF

ISL6532B

2.1µH

C

9-12

Q

2,4

V

DDQ

22µF

VDDQ

+

C

20

220µF

V

TT

VTT

R

4

1.25V

+

1.74kΩ

C

21

220µF

FB

C

R

22.6Ω

COMP

13

56nF

5

VTTSNS

C

15

1000pF

C

R

3

19.1kΩ

14

6.8nF

R

6

825Ω

FIGURE 7. DDR SDRAM AND AGP VOLTAGE REGULATOR USING THE ISL6532B

14

ISL6532B

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L20.6x6

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VJJB ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.28

3.55

0.33

0.40

3.85

5, 8

D

6.00 BSC

-

D1

D2

E

5.75 BSC

9

3.70

7, 8

6.00 BSC

-

E1

E2

e

5.75 BSC

9

3.70

7, 8

0.80 BSC

-

k

0.25

0.35

-

L

0.60

0.75

0.15

8

L1

N

-

20

5

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

15


型号：	ISL6532BCR
厂家：	Intersil
描述：	ACPI Regulator/Controller for Dual Channel DDR Memory Systems ACPI稳压器/控制器双通道DDR内存系统稳压器双倍数据速率控制器
文件：	总15页 (文件大小：361K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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