ISL6568CRZ-TR5184_技术文档

ISL6568

®

Data Sheet

March 9, 2006

FN9187.4

Two-Phase Buck PWM Controller with

Integrated MOSFET Drivers for VRM9,

VRM10, and AMD Hammer Applications

Features

• Integrated Multi-Phase Power Conversion

- 1 or 2-Phase Operation

The ISL6568 two-phase PWM control IC provides a

precision voltage regulation system for advanced

microprocessors. The integration of power MOSFET drivers

into the controller IC marks a departure from the separate

PWM controller and driver configuration of previous multi-

phase product families. By reducing the number of external

parts, this integration is optimized for a cost and space

saving power management solution.

• Precision Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over Temperature

- Adjustable Reference-Voltage Offset

• Precision Channel Current Sharing

- Uses Loss-Less r

Current Sampling

DS(ON)

• Accurate Load Line Programming

Outstanding features of this controller IC include

programmable VID codes compatible with Intel

VRM9,VRM10, as well as AMD Hammer microprocessors. A

unity gain, differential amplifier is provided for remote voltage

sensing, compensating for any potential difference between

remote and local grounds. The output voltage can also be

positively or negatively offset through the use of a single

external resistor.

- Uses Loss-Less Inductor DCR Current Sampling

• Variable Gate Drive Bias: 5V to 12V

• Microprocessor Voltage Identification Inputs

- Up to a 6-Bit DAC

- Selectable between Intel’s VRM9, VRM10, or AMD

Hammer DAC codes

- Dynamic VID-on-the-fly Technology

• Overcurrent Protection

A unique feature of the ISL6568 is the combined use of both

DCR and r

current sensing. Load line voltage

DS(ON)

• Multi-tiered Overvoltage Protection

• Digital Soft-Start

positioning (droop) and overcurrent protection are

accomplished through continuous inductor DCR current

sensing, while r

channel-current balance. Using both methods of current

sampling utilizes the best advantages of each technique.

current sensing is used for accurate

DS(ON)

• Selectable Operation Frequency up to 1.5MHz Per Phase

• Pb-Free Plus Anneal Available (RoHS Compliant)

Protection features of this controller IC include a set of

sophisticated overvoltage, undervoltage, and overcurrent

protection. Overvoltage results in the converter turning the

lower MOSFETs ON to clamp the rising output voltage and

protect the microprocessor. The overcurrent protection level

is set through a single external resistor. Furthermore, the

ISL6568 includes protection against an open circuit on the

remote sensing inputs. Combined, these features provide

advanced protection for the microprocessor and power

system.

Pinout

ISL6568 (QFN)

TOP VIEW

32 31 30 29 28 27 26 25

VID12.5

REF

1

2

3

4

5

6

7

8

24 BOOT1

23

22

PHASE1

VID4

OFS

VCC

21 VID3

33

GND

20

19

18

COMP

FB

ENLL

PHASE2

BOOT2

VDIFF

RGND

17 UGATE2

9

10 11 12 13 14 15 16

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6568

Ordering Information

PART

TEMP.

PKG.

PART NUMBER*

MARKING

(°C)

PACKAGE

DWG. #

ISL6568CRR5184

ISL6568CR-TR5184

ISL6568CRZR5184

ISL6568CRZ-TR5184

ISL6568CRZAR5184

ISL6568CRZA-TR5184

ISL6568IR

ISL6568CR

0 to 70

32 Ld 5x5 QFN

L32.5x5

0 to 70

32 Ld 5x5 QFN (Pb-free) Tape and Reel

32 Ld 5x5 QFN (Pb-free)

L32.5x5

ISL6568CRZ

ISL6568IR

0 to 70

32 Ld 5x5 QFN (Pb-free) Tape and Reel

32 Ld 5x5 QFN (Pb-free)

0 to 70

32 Ld 5x5 QFN (Pb-free) Tape and Reel

32 Ld 5x5 QFN

-40 to 85

ISL6568IR-T

ISL6568IR

32 Ld 5x5 QFN Tape and Reel

32 Ld 5x5 QFN (Pb-free)

ISL6568IRZ

ISL6568IRZ-T

32 Ld 5x5 QFN (Pb-free) Tape and Reel

32 Ld 5x5 QFN (Pb-free)

ISL6568IRZA

ISL6568IRZA-T

32 Ld 5x5 QFN (Pb-free) Tape and Reel

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified

at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN9187.4

2

March 9, 2006

ISL6568

Block Diagram

ENLL

OCSET

PGOOD

ICOMP

100µA

OC

ISEN AMP

0.66V

ISUM

IREF

VCC

POWER-ON

RESET

PVCC

+1V

RGND

VSEN

BOOT1

SOFT START

AND

x1

FAULT LOGIC

UGATE1

SHOOT-

THROUGH

PROTECTION

GATE

VDIFF

PHASE1

LGATE1

FS

CONTROL

LOGIC

UVP

0.2V

OVP

CLOCK AND

SAWTOOTH

GENERATOR

OVP

V

PWM1

∑

BOOT2

+150mV

x 0.82

UGATE2

SHOOT-

THROUGH

PROTECTION

GATE

CONTROL

LOGIC

PHASE2

LGATE2

PWM2

∑

VID4

VID3

DYNAMIC

VID

VID2

VID1

D/A

VID0

PHASE 2

DETECT

VID12.5

CHANNEL

CURRENT

BALANCE

1

N

REF

FB

E/A

COMP

OFS

∑

OFFSET

CHANNEL

CURRENT

SENSE

GND

ISEN1 ISEN2

FN9187.4

March 9, 2006

3

ISL6568

Typical Application - ISL6568

FB

COMP

VDIFF

VSEN

RGND

+12V

+5V

PVCC1

VCC

BOOT1

UGATE1

OFS

PHASE1

ISEN1

FS

REF

LGATE1

VID4

VID3

ISL6568

+12V

VID2

PVCC2

VID1

LOAD

VID0

VID12.5

BOOT2

UGATE2

PGOOD

GND

PHASE2

ISEN2

+12V

LGATE2

ENLL

IREF

OCSET

ICOMP

ISUM

FN9187.4

March 9, 2006

4

ISL6568

Typical Application - ISL6568 with NTC Thermal Compensation

FB

COMP

VDIFF

VSEN

RGND

+12V

+5V

PVCC1

VCC

BOOT1

UGATE1

OFS

PHASE1

ISEN1

FS

REF

LGATE1

VID4

VID3

ISL6568

+12V

VID2

PVCC2

VID1

LOAD

VID0

VID12.5

PLACE IN CLOSE

PROXIMITY

BOOT2

UGATE2

PGOOD

GND

PHASE2

ISEN2

NTC

+12V

LGATE2

ENLL

IREF

OCSET

ICOMP

ISUM

FN9187.4

March 9, 2006

5

ISL6568

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

Thermal Resistance

θ

(°C/W)

35

θ

(°C/W)

5

JA

JC

QFN Package (Notes 1, 2) . . . . . . . . . .

Absolute Boot Voltage, V

. . . . . . . .GND - 0.3V to GND + 36V

BOOT

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

Phase Voltage, V

PHASE

. . . . . . . . GND - 0.3V to 15V (PVCC = 12)

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

= 12V)

+ 0.3V

BOOT-PHASE

Upper Gate Voltage, V

. . . . V

- 0.3V to V

PHASE

UGATE

BOOT

V

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

Lower Gate Voltage, V

. . . . . . . . GND - 0.3V to PVCC + 0.3V

LGATE

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD

Recommended Operating Conditions

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5%

Ambient Temperature

(ISL6568CRR5184, ISL6568CRZR5184) . . . . . . . . . 0°C to 70°C

Ambient Temperature (ISL6568IR, ISL6568IRZ). . . . .-40°C to 85°C

CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational section of this specification is not implied.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.

PARAMETER

BIAS SUPPLY AND INTERNAL OSCILLATOR

Input Bias Supply Current

TEST CONDITIONS

MIN

TYP

MAX UNITS

I

; ENLL = high

-

15

20

-

mA

V

VCC

Gate Drive Bias Current

; ENLL = high

-

1.5

PVCC

VCC POR (Power-On Reset) Threshold

VCC Rising

VCC Falling

PVCC Rising

PVCC Falling

4.25

3.75

4.25

3.60

-

4.38

3.88

4.38

3.88

1.50

66.6

250

4.50

4.00

4.50

4.00

-

V

PVCC POR (Power-On Reset) Threshold

V

Oscillator Ramp Amplitude (Note 3)

Maximum Duty Cycle (Note 3)

V

PP

-

%

Oscillator Frequency, F

R

= 100kΩ (± 0.1%)

225

275

kHz

SW

T

CONTROL THRESHOLDS

ENLL Rising Threshold

-

0.66

100

0.3

-

V

mV

V

ENLL Hysteresis

COMP Shutdown Threshold

COMP Falling

0.2

0.4

REFERENCE AND DAC

System Accuracy (VID = 1.0V - 1.850V)

System Accuracy (VID = 0.8V - 1.0V)

DAC Input Low Voltage (VR9, VR10)

DAC Input High Voltage (VR9, VR10)

DAC Input Low Voltage (AMD)

DAC Input High Voltage (AMD)

OFS Sink Current Accuracy (Negative Offset)

OFS Source Current Accuracy (Positive Offset)

-0.5

-0.8

-

0.5

0.8

0.4

-

%

V

-

0.8

-

V

0.6

-

V

1.0

47.5

-

V

R

= 30kΩ from OFS to VCC

= 10kΩ from OFS to GND

50.0

52.5

µA

OFS

FN9187.4

6

March 9, 2006

ISL6568

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

ERROR AMPLIFIER

DC Gain (Note 3)

R

C

= 10K to ground

-

96

20

-

dB

MHz

V/µs

V

L

Gain-Bandwidth Product (Note 3)

Slew Rate (Note 3)

= 100pF, R = 10K to ground

L

-

= 100pF, Load = ±400µA

-

3.90

-

8

Maximum Output Voltage

Minimum Output Voltage

OVERCURRENT PROTECTION

OCSET trip current

Load = 1mA

Load = -1mA

4.20

0.85

-

1.0

V

93

-5

100

0

107

5

µA

mV

OCSET Accuracy

OCSET and ISUM Difference

ICOMP Offset

0

5

PROTECTION

Undervoltage Threshold

Undervoltage Hysteresis

Overvoltage Threshold while IC Disabled

VSEN falling

VSEN Rising

80

-

82

3

84

-

%VID

V

, VRM9.0 Configuration

OVP

1.92

1.62

1.97

1.67

2.02

1.72

V

, Hammer and VRM10.0 Configurations

OVP

Overvoltage Threshold

VSEN Rising

VID +

125mV

VID +

150mV

VID +

175mV

Overvoltage Hysteresis

VSEN Falling

-

50

-

mV

V

Open Sense-Line Protection Threshold

IREF Rising and Falling

VDIFF VDIFF + VDIFF

+ 0.9V

1V

+ 1.1V

SWITCHING TIME (Note 3)

UGATE Rise Time

t

V

= 12V, 3nF Load, 10% to 90%

= 12V, 3nF Load, 90% to 10%

-

26

18

12

10

-

ns

RUGATE; PVCC

LGATE Rise Time

V

RLGATE; PVCC

UGATE Fall Time

V

FUGATE; PVCC

LGATE Fall Time

V

FLGATE; PVCC

UGATE Turn-On Non-overlap

LGATE Turn-On Non-overlap

GATE DRIVE RESISTANCE (Note 3)

Upper Drive Source Resistance

Upper Drive Sink Resistance

Lower Drive Source Resistance

Lower Drive Sink Resistance

OVER TEMPERATURE SHUTDOWN

Thermal Shutdown Setpoint (Note 3)

Thermal Recovery Setpoint (Note 3)

NOTE:

; V

= 12V, 3nF Load, Adaptive

PDHUGATE PVCC

; V

PDHLGATE PVCC

V

= 12V, 15mA Source Current

1.25

0.9

2.0

3.0

Ω

PVCC

= 12V, 15mA Sink Current

= 12V, 15mA Source Current

= 12V, 15mA Sink Current

1.65

1.25

0.80

0.85

0.60

2.2

1.35

-

160

100

-

°C

3. Parameter magnitude guaranteed by design. Not 100% tested.

FN9187.4

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March 9, 2006

ISL6568

Timing Diagram

t

PDHUGATE

t

RUGATE

FUGATE

UGATE

LGATE

t

FLGATE

RLGATE

t

PDHLGATE

Simplified Power System Diagram

+12V

IN

+5V

IN

Q1

CHANNEL1

Q2

5-6

VID

DAC

V

OUT

Q3

Q4

CHANNEL2

ISL6568

FS

Functional Pin Description

A resistor, placed from FS to ground, will set the switching

frequency. Refer to Equation 34 for proper resistor

calculation.

VCC

VCC is the bias supply for the ICs small-signal circuitry.

Connect this pin to a +5V supply and locally decouple using

a quality 1.0µF ceramic capacitor.

VID4, VID3, VID2, VID1, VID0, and VID12.5

These are the inputs for the internal DAC that provides the

reference voltage for output regulation. These pins respond

to TTL logic thresholds. The ISL6568 decodes the VID

inputs to establish the output voltage; see VID Tables for

correspondence between DAC codes and output voltage

settings. These pins are internally pulled high, to

approximately 1.2V, by 40µA (typically) internal current

sources; the internal pull-up current decreases to 0 as the

VID voltage approaches the internal pull-up voltage. All VID

pins are compatible with external pull-up voltages not

exceeding the IC’s bias voltage (VCC).

PVCC

This pin is the power supply pin for the MOSFET drivers.

This pin can be connected to any voltage from +5V to +12V,

depending on the desired MOSFET gate drive level.

GND

GND is the bias and reference ground for the IC.

ENLL

This pin is a threshold-sensitive (approximately 0.66V) enable

input for the controller. Held low, this pin disables controller

operation. Pulled high, the pin enables the controller for

operation. ENLL has a internal 1.0µA pull-up to 5V.

The VID12.5 pin also serves as the internal DAC compliance

selector. The way this pin is connected selects which of the

three internal DAC codes will be used. For VRM10 codes

this pin must be less that 3V. To encode the DAC with Intel

FN9187.4

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March 9, 2006

ISL6568

VRM9.0 codes, connect the VID12.5 pin to a +5V source

through a 50kΩ resistor. To encode the DAC with AMD

Hammer VID codes, connect this pin to a +5V source

through a 5kΩ resistor.

ISEN1 and ISEN2

These pins are used for balancing the channel currents by

sensing the current through each channel’s lower MOSFET

when it is conducting. Connect a resistor between the ISEN1

and ISEN2 pins and their respective phase node. This

resistor sets a current proportional to the current in the lower

MOSFET during its conduction interval.

VSEN and RGND

VSEN and RGND are inputs to the precision differential

remote-sense amplifier and should be connected to the sense

pins of the remote load.

UGATE1 and UGATE2

Connect these pins to the corresponding upper MOSFET

gates. These pins are used to control the upper MOSFETs

and are monitored for shoot-through prevention purposes.

Maximum individual channel duty cycle is limited to 66%.

ICOMP, ISUM, and IREF

ISUM, IREF, and ICOMP are the DCR current sense

amplifier’s negative input, positive input, and output

respectively. For accurate DCR current sensing, connect a

resistor from each channel’s phase node to ISUM and

connect IREF to the summing point of the output inductors,

roughly Vout. A parallel R-C feedback circuit connected

between ISUM and ICOMP will then create a voltage from

IREF to ICOMP proportional to the voltage drop across the

inductor DCR. This voltage is referred to as the droop voltage

and is added to the differential remote-sense amplifier output.

BOOT1 and BOOT2

These pins provide the bias voltage for the corresponding

upper MOSFET drives. Connect these pins to appropriately-

chosen external bootstrap capacitors. Internal bootstrap

diodes connected to the PVCC pins provide the necessary

bootstrap charge.

PHASE1 and PHASE2

Connect these pins to the sources of the upper MOSFETs.

These pins are the return path for the upper MOSFET

drives.

NOTE: An optional 0.01µF ceramic capacitor can be placed from the

IREF pin to the ISUM pin to help reduce any noise affects that may

occur due to layout.

VDIFF

LGATE1 and LGATE2

These pins are used to control the lower MOSFETs. Connect

these pins to the corresponding lower MOSFETs’ gates.

VDIFF is the output of the differential remote-sense amplifier.

The voltage on this pin is equal to the difference between

VSEN and RGND added to the difference between IREF and

ICOMP. VDIFF therefore represents the output voltage plus

the droop voltage.

PGOOD

During normal operation PGOOD indicates whether the

output voltage is within specified overvoltage and

undervoltage limits. If the output voltage exceeds these limits

or a reset event occurs (such as an overcurrent event),

PGOOD is pulled low. PGOOD is always low prior to the end

of soft-start.

FB and COMP

These pins are the internal error amplifier inverting input and

output respectively. FB, VDIFF, and COMP are tied together

through external R-C networks to compensate the regulator.

REF

The REF input pin is the positive input of the error amplifier. It

is internally connected to the DAC output through a 1kΩ

resistor. A capacitor is used between the REF pin and ground

to smooth the voltage transition during Dynamic VID

operations.

Operation

Multi-Phase Power Conversion

Microprocessor load current profiles have changed to the

point that the advantages of multi-phase power conversion

are impossible to ignore. The technical challenges

associated with producing a single-phase converter that is

both cost-effective and thermally viable have forced a

change to the cost-saving approach of multi-phase. The

ISL6568 controller helps simplify implementation by

integrating vital functions and requiring minimal external

components. The block diagram on page 2 provides a top

level view of multi-phase power conversion using the

ISL6568 controller.

OFS

The OFS pin provides a means to program a dc current for

generating an offset voltage across the resistor between FB

and VDIFF. The offset current is generated via an external

resistor and precision internal voltage references. The polarity

of the offset is selected by connecting the resistor to GND or

VCC. For no offset, the OFS pin should be left unconnected.

OCSET

This is the overcurrent set pin. Placing a resistor from OCSET

to ICOMP allows a 100µA current to flow out this pin,

producing a voltage reference. Internal circuitry compares the

voltage at OCSET to the voltage at ISUM, and if ISUM ever

exceeds OCSET, the overcurrent protection activates.

FN9187.4

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March 9, 2006

ISL6568

of N symmetrically phase-shifted inductor currents in

Equation 2. Peak-to-peak ripple current decreases by an

amount proportional to the number of channels. Output-

voltage ripple is a function of capacitance, capacitor

equivalent series resistance (ESR), and inductor ripple

current. Reducing the inductor ripple current allows the

designer to use fewer or less costly output capacitors.

IL1 + IL2 + IL3, 7A/DIV

IL3, 7A/DIV

PWM3, 5V/DIV

(V – N V

) V

OUT

IL2, 7A/DIV

PWM2, 5V/DIV

IN

OUT

(EQ. 2)

I

= -----------------------------------------------------------

C, PP

Lf

V

S

IN

Another benefit of interleaving is to reduce input ripple

current. Input capacitance is determined in part by the

maximum input ripple current. Multi-phase topologies can

improve overall system cost and size by lowering input ripple

current and allowing the designer to reduce the cost of input

capacitance. The example in Figure 2 illustrates input

currents from a three-phase converter combining to reduce

the total input ripple current.

IL1, 7A/DIV

PWM1, 5V/DIV

1µs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

Interleaving

The converter depicted in Figure 2 delivers 1.5V to a 36A load

from a 12V input. The RMS input capacitor current is 5.9A.

Compare this to a single-phase converter also stepping down

12V to 1.5V at 36A. The single-phase converter has 11.9A

RMS input capacitor current. The single-phase converter

must use an input capacitor bank with twice the RMS current

capacity as the equivalent three-phase converter.

The switching of each channel in a multi-phase converter is

timed to be symmetrically out of phase with each of the other

channels. In a 3-phase converter, each channel switches 1/3

cycle after the previous channel and 1/3 cycle before the

following channel. As a result, the three-phase converter has

a combined ripple frequency three times greater than the

ripple frequency of any one phase. In addition, the peak-to-

peak amplitude of the combined inductor currents is reduced

in proportion to the number of phases (Equations 1 and 2).

Increased ripple frequency and lower ripple amplitude mean

that the designer can use less per-channel inductance and

lower total output capacitance for any performance

specification.

INPUT-CAPACITOR CURRENT, 10A/DIV

CHANNEL 3

INPUT CURRENT

10A/DIV

Figure 1 illustrates the multiplicative effect on output ripple

frequency. The three channel currents (IL1, IL2, and IL3)

combine to form the AC ripple current and the DC load

current. The ripple component has three times the ripple

frequency of each individual channel current. Each PWM

pulse is terminated 1/3 of a cycle after the PWM pulse of the

previous phase. The peak-to-peak current for each phase is

about 7A, and the dc components of the inductor currents

combine to feed the load.

CHANNEL 2

INPUT CURRENT

10A/DIV

CHANNEL 1

INPUT CURRENT

10A/DIV

1µs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 3-PHASE

CONVERTER

To understand the reduction of ripple current amplitude in the

multi-phase circuit, examine the equation representing an

individual channel peak-to-peak inductor current.

Figures 22 and 23 in the section entitled Input Capacitor

Selection can be used to determine the input-capacitor RMS

current based on load current, duty cycle, and the number of

channels. They are provided as aids in determining the

optimal input capacitor solution.

(V – V

) V

IN

OUT

(EQ. 1)

I

= -----------------------------------------------------

PP

Lf

V

S

IN

In Equation 1, V and V

IN

are the input and output

OUT

voltages respectively, L is the single-channel inductor value,

PWM Operation

and f is the switching frequency.

S

The timing of each converter leg is set by the number of

active channels. The default channel setting for the ISL6568

is two. One switching cycle is defined as the time between

the internal PWM1 pulse termination signals. The pulse

termination signal is the internally generated clock signal

that triggers the falling edge of PWM1. The cycle time of the

The output capacitors conduct the ripple component of the

inductor current. In the case of multi-phase converters, the

capacitor current is the sum of the ripple currents from each

of the individual channels. Compare Equation 1 to the

expression for the peak-to-peak current after the summation

FN9187.4

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March 9, 2006

ISL6568

pulse termination signal is the inverse of the switching

frequency set by the resistor between the FS pin and

+

I

PWM1

V

COMP

TO GATE

CONTROL

LOGIC

+

-

ground. Each cycle begins when the clock signal commands

PWM1 to go low. The PWM1 transition signals the internal

channel-1 MOSFET driver to turn off the channel-1 upper

MOSFET and turn on the channel-1 synchronous MOSFET.

In the default channel configuration, the PWM2 pulse

terminates 1/2 of a cycle after the PWM1 pulse.

SAWTOOTH SIGNAL

f(s)

FILTER

ER

+

I

AVG

Σ

÷ N

I

2

-

If the BOOT2 and PHASE2 pins are both connected to +12V

single channel operation is selected.

I

1

NOTE: Channel 2 is optional.

Once a PWM pulse transitions low, it is held low for a

minimum of 1/3 cycle. This forced off time is required to

ensure an accurate current sample. Current sensing is

described in the next section. After the forced off time

expires, the PWM output is enabled. The PWM output state

is driven by the position of the error amplifier output signal,

FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-

BALANCE ADJUSTMENT

Current Sampling

In order to realize proper current-balance, the currents in

each channel must be sampled every switching cycle. This

sampling occurs during the forced off-time, following a PWM

transition low. During this time the current-sense amplifier

uses the ISEN inputs to reproduce a signal proportional to

V

, minus the current correction signal relative to the

COMP

sawtooth ramp as illustrated in Figure 3. When the modified

voltage crosses the sawtooth ramp, the PWM output

V

COMP

transitions high. The internal MOSFET driver detects the

change in state of the PWM signal and turns off the

synchronous MOSFET and turns on the upper MOSFET.

The PWM signal will remain high until the pulse termination

signal marks the beginning of the next cycle by triggering the

PWM signal low.

the inductor current, I . This sensed current, I

, is simply

L

SEN

a scaled version of the inductor current. The sample window

opens exactly 1/6 of the switching period, t , after the

SW

PWM transitions low. The sample window then stays open

the rest of the switching cycle until PWM transitions high

again, as illustrated in Figure 4.

Channel-Current Balance

The sampled current, at the end of the t

, is

SAMPLE

One important benefit of multi-phase operation is the thermal

advantage gained by distributing the dissipated heat over

multiple devices and greater area. By doing this the designer

avoids the complexity of driving parallel MOSFETs and the

expense of using expensive heat sinks and exotic magnetic

materials.

proportional to the inductor current and is held until the next

switching period sample. The sampled current is used only

for channel-current balance.

I

L

In order to realize the thermal advantage, it is important that

each channel in a multi-phase converter be controlled to

carry about the same amount of current at any load level. To

achieve this, the currents through each channel must be

PWM

SWITCHING PERIOD

sampled every switching cycle. The sampled currents, I ,

n

from each active channel are summed together and divided

by the number of active channels. The resulting cycle

I

SEN

average current, I

, provides a measure of the total load-

AVG

current demand on the converter during each switching

cycle. Channel-current balance is achieved by comparing

the sampled current of each channel to the cycle average

current, and making the proper adjustment to each channel

pulse width based on the error. Intersil’s patented current-

balance method is illustrated in Figure 3, with error

SAMPLING PERIOD

NEW SAMPLE

CURRENT

OLD SAMPLE

CURRENT

TIME

correction for channel 1 represented. In the figure, the cycle

FIGURE 4. SAMPLE AND HOLD TIMING

average current, I

, is compared with the channel 1

AVG

sample, I , to create an error signal I

.

1

ER

The filtered error signal modifies the pulse width

commanded by V to correct any unbalance and force

The ISL6568 supports MOSFET r

current sensing to

DS(ON)

sample each channel’s current for channel-current balance.

The internal circuitry, shown in Figure 5 represents channel

n of an N-channel converter. This circuitry is repeated for

each channel in the converter, but may not be active

COMP

I

toward zero. The same method for error signal

ER

correction is applied to each active channel.

FN9187.4

11

March 9, 2006

ISL6568

depending on the status of the BOOT2 and PHASE2 pins,

TABLE 2. AMD HAMMER VOLTAGE IDENTIFICATION CODES

as described in the PWM Operation section.

VID4

1

0

VID3

1

0

1

0

VID2

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VDAC

Off

V

IN

r

CHANNEL N

DS(ON)

ISEN

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

I

= I -------------------------

SEN

UPPER MOSFET

L

R

I

n

I

L

SAMPLE

&

ISEN(n)

HOLD

-

R

ISEN

-

+

I

r

L

DS(ON)

+

CHANNEL N

LOWER MOSFET

ISL6565A INTERNAL CIRCUIT

EXTERNAL CIRCUIT

FIGURE 5. ISL6568 INTERNAL AND EXTERNAL CURRENT-

SENSING CIRCUITRY FOR CURRENT BALANCE

The ISL6568 senses the channel load current by sampling

the voltage across the lower MOSFET r

Figure 5. A ground-referenced operational amplifier, internal

to the ISL6568, is connected to the PHASE node through a

, as shown in

DS(ON)

resistor, R

. The voltage across R

is equivalent to

ISEN

the voltage drop across the r

ISEN

of the lower MOSFET

DS(ON)

while it is conducting. The resulting current into the ISEN pin

is proportional to the channel current, I . The ISEN current is

L

sampled and held as described in the Current Sampling

section. From Figure 5, the following equation for I is

n

derived where I is the channel current.

L

r

DS(ON)

I

= I ----------------------

(EQ. 3)

n

L

R

ISEN

Output Voltage Setting

The ISL6568 uses a digital to analog converter (DAC) to

generate a reference voltage based on the logic signals at the

VID pins. The DAC decodes the 5 or 6-bit logic signals into

one of the discrete voltages shown in Tables 2, 3, and 4.

Each VID pin is pulled up to an internal 1.2V voltage by a

weak current source (40µA current), which decreases to 0 as

the voltage at the VID pin varies from 0 to the internal 1.2V

pull-up voltage. External pull-up resistors or active-high

output stages can augment the pull-up current sources, up to

a voltage of 5V.

.

The ISL6568 accommodates three different DAC ranges:

Intel VRM9.0, AMD Hammer, or Intel VRM10.0. The state of

the VID12.5 pin decides which DAC version is active. Refer

to Table 1 for a description of how to select the desired DAC

version.

TABLE 1. ISL6568 DAC SELECT TABLE

DAC VERSION

VRM10.0

VID12.5 PIN CONDITION

Less then 3V

VRM9.0

50kΩ resistor to +5V

5kΩ resistor to +5V

AMD HAMMER

FN9187.4

12

March 9, 2006

ISL6568

TABLE 3. VRM9 VOLTAGE IDENTIFICATION CODES

TABLE 4. VRM10 VOLTAGE IDENTIFICATION CODES

VID0 VID12.5 VDAC

VID4

1

0

1

VID3

1

0

1

VID2

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

VID4

1

0

VID3

1

0

1

0

VID2

1

0

1

0

1

0

1

0

VID1

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VDAC

Off

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Off

1

Off

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

0

1

0

1

0

1

0

1

0

1

0

1

0

12.75

1

0

FN9187.4

13

March 9, 2006

ISL6568

TABLE 4. VRM10 VOLTAGE IDENTIFICATION CODES (Continued)

EXTERNAL CIRCUIT

ISL6568 INTERNAL CIRCUIT

VID4

1

VID3

0

VID2

1

VID1

1

VID0 VID12.5 VDAC

R

C

COMP

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.2750

1.2875

1.300

VID DAC

1k

1

0

1

REF

1

0

1

C

+

1

0

1

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

-

V

FB

COMP

1

0

1

0

ERROR AMPLIFIER

+

1

0

1

0

R

V

FB

OFS

I

OFS

-

1

0

1

0

VDIFF

VSEN

1

0

1

0

1

0

1

+

OUT

-

+

V

1

0

1

RGND

IREF

1

0

1

-

1

0

1

+

V

DROOP

-

1

0

ICOMP

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

1

0

1

0

1

0

FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

0

1

0

1

The ISL6568 incorporates an internal differential remote-

sense amplifier in the feedback path. The amplifier removes

the voltage error encountered when measuring the output

voltage relative to the controller ground reference point,

resulting in a more accurate means of sensing output

voltage. Connect the microprocessor sense pins to the non-

inverting input, VSEN, and inverting input, RGND, of the

0

1

0

1

0

1

0

1

0

1

0

remote-sense amplifier. The droop voltage, V

, also

DROOP

feeds into the remote-sense amplifier. The remote-sense

output, V , is therefore equal to the sum of the output

0

1

0

DIFF

voltage, V

0

1

0

1

, and the droop voltage. V

is connected to

OUT

DIFF

0

1

0

1

the inverting input of the error amplifier through an external

resistor.

0

1

0

1

The output of the error amplifier, V

, is compared to the

COMP

Voltage Regulation

sawtooth waveform to generate the PWM signals. The PWM

signals control the timing of the Internal MOSFET drivers

and regulate the converter output so that the voltage at FB is

equal to the voltage at REF. This will regulate the output

voltage to be equal to Equation 4. The internal and external

circuitry that controls voltage regulation is illustrated in

Figure 6.

In order to regulate the output voltage to a specified level,

the ISL6568 uses the integrating compensation network

shown in Figure 6. This compensation network insures that

the steady-state error in the output voltage is limited only to

the error in the reference voltage (output of the DAC) and

offset errors in the OFS current source, remote-sense and

error amplifiers. Intersil specifies the guaranteed tolerance of

the ISL6568 to include the combined tolerances of each of

these elements.

(EQ. 4)

V

= V

– V

OFS DROOP

OUT

REF

FN9187.4

14

March 9, 2006

ISL6568

-

Load-Line (Droop) Regulation

V (s)

L

I

OUT

V

L

Some microprocessor manufacturers require a precisely-

controlled output impedance. This dependence of output

voltage on load current is often termed “droop” or “load line”

regulation.

DCR

PHASE1

PHASE2

INDUCTOR

OUT

I

L1

R

C

S

OUT

L

As shown in Figure 6, a voltage, V

, proportional to the

DROOP

OUT

DCR

total current in all active channels, I , feeds into the

INDUCTOR

L2

differential remote-sense amplifier. The resulting voltage at

the output of the remote-sense amplifier is the sum of the

output voltage and the droop voltage. As Equation 4 shows,

feeding this voltage into the compensation network causes

the regulator to adjust the output voltage so that it’s equal to

the reference voltage minus the droop voltage.

R

S

ISUM

R

C

COMP

The droop voltage, V

current through the output inductors. This is accomplished

by using a continuous DCR current sensing method.

, is created by sensing the

DROOP

ICOMP

-

V

DROOP

+

(optional)

IREF

Inductor windings have a characteristic distributed

resistance or DCR (Direct Current Resistance). For

simplicity, the inductor DCR is considered as a separate

lumped quantity, as shown in Figure 7. The channel current,

ISL6568

FIGURE 7. DCR SENSING CONFIGURATION

I , flowing through the inductor, passes through the DCR.

L

Equation 5 shows the s-domain equivalent voltage, V ,

L

By simply adjusting the value of R , the load line can be set

S

across the inductor.

to any level, giving the converter the right amount of droop at

all load currents. It may also be necessary to compensate for

any changes in DCR due to temperature. These changes

cause the load line to be skewed, and cause the R-C time

constant to not match the L/DCR time constant. If this

becomes a problem a simple negative temperature

(EQ. 5)

V (s) = I ⋅ (s ⋅ L + DCR)

L

The inductor DCR is important because the voltage dropped

across it is proportional to the channel current. By using a

simple R-C network and a current sense amplifier, as shown

in Figure 7, the voltage drop across all of the inductors’

DCRs can be extracted. The output of the current sense

coefficient resistor network can be used in the place of

R

to compensate for the rise in DCR due to

COMP

temperature.

amplifier, V

, can be shown to be proportional to the

DROOP

Note: An optional 10nF ceramic capacitor from the ISUM pin

to the IREF pin is recommended to help reduce any noise

affects on the current sense amplifier due to layout.

channel currents I and I , shown in Equation 6.

L1 L2

(EQ. 6)

s ⋅ L







------------- + 1

R



DCR

COMP

------------------------------------------------------------------------- -----------------------

V

(s) =

⋅

⋅ (I + I ) ⋅ DCR

L1 L2

DROOP

(s ⋅ R

⋅ C

+ 1)

R

Output-Voltage Offset Programming

COMP

S

The ISL6568 allows the designer to accurately adjust the

If the R-C network components are selected such that the

R-C time constant matches the inductor L/DCR time

offset voltage by connecting a resistor, R

, from the OFS

OFS

pin to VCC or GND. When R

is connected between OFS

OFS

and VCC, the voltage across it is regulated to 1.5V. This

causes a proportional current (I ) to flow into the OFS pin

constant, then V

is equal to the sum of the voltage

DROOP

drops across the individual DCRs, multiplied by a gain. As

OFS

is connected to ground, the

Equation 7 shows, V

total output current, I

is therefore proportional to the

(EQ. 7)

⋅ DCR

OUT

DROOP

OUT

and out of the FB pin. If R

voltage across it is regulated to 0.5V, and I

OFS

.

flows into the

OFS

FB pin and out of the OFS pin. The offset current flowing

through the resistor between VDIFF and FB will generate the

R

COMP

--------------------

V

=

⋅ I

DROOP

R

S

desired offset voltage which is equal to the product (I

x

OFS

R

). These functions are shown in Figures 8 and 9.

FB

FN9187.4

March 9, 2006

15

ISL6568

For Negative Offset (connect R

OFS

to VCC):

VDIFF

1.5 × R

FB

R

= --------------------------

(EQ. 9)

OFS

+

OFS

-

V

OFFSET

V

R

FB

VREF

E/A

Dynamic VID

FB

Modern microprocessors need to make changes to their core

voltage as part of normal operation. They direct the core-

voltage regulator to do this by making changes to the VID

inputs. The core-voltage regulator is required to monitor the

DAC inputs and respond to on-the-fly VID changes in a

controlled manner, supervising a safe output voltage transition

without discontinuity or disruption.

I

OFS

-

The DAC mode the ISL6568 is operating in determines how

the controller responds to a dynamic VID change. When in

VRM10 mode the ISL6568 checks the VID inputs six times

every switching cycle. If a new code is established and it

stays the same for 3 consecutive readings, the ISL6568

recognizes the change and increments the reference.

Specific to VRM10, the processor controls the VID

1.5V

+

-

0.5V

OFS

ISL6568

R

OFS

GND

VCC

GND

FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

transitions and is responsible for incrementing or

decrementing one VID step at a time. In VRM10 setting, the

ISL6568 will immediately change the reference to the new

requested value as soon as the request is validated; in

cases where the reference step is too large, the sudden

change can trigger overcurrent or overvoltage events.

VDIFF

-

V

R

OFS

+

FB

In order to ensure the smooth transition of output voltage

during a VRM10 VID change, a VID step change smoothing

network is required for an ISL6568 based voltage regulator.

This network is composed of a 1kΩ internal resistor between

VREF

E/A

FB

I

OFS

the output of DAC and the capacitor C

, between the REF

REF

pin and ground. The selection of C

is based on the time

REF

duration for 1 bit VID change and the allowable delay time.

Assuming the microprocessor controls the VID change at 1

VCC

bit every T , the relationship between C

VID

and T

is

REF

VID

given by Equation 10.

-

R

OFS

1.5V

C

= 0.004X T

VID

+

(EQ. 10)

REF

+

-

0.5V

OFS

As an example, for a VID step change rate of 5µs per bit, the

value of C is 22nF based on Equation 10.

ISL6568

REF

GND

VCC

When running in VRM9 or AMD Hammer operation, the

ISL6568 responds slightly differently to a dynamic VID change

than when in VRM10 mode. In these modes the VID code can

be changed by more than a 1-bit step at a time. Once the

controller receives the new VID code it waits half of a phase

cycle and then begins slewing the DAC 12.5mV every phase

cycle, until the VID and DAC are equal. Thus, the total time

FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

Once the desired output offset voltage has been determined,

use the following formulas to set R

:

OFS

to GND):

For Positive Offset (connect R

OFS

required for a VID change, t

, is dependent on the

DVID

0.5 × R

FB

switching frequency (f ), the size of the change (∆V ), and

VID

(EQ. 8)

S

R

= --------------------------

OFS

V

OFFSET

the time required to register the VID change. The one-cycle

addition in the t equation is due to the possibility that the

DVID

VID code change may occur up to one full switching cycle

before being recognized. The approximate time required for a

ISL6568-based converter in AMD Hammer configuration

FN9187.4

16

March 9, 2006

ISL6568

running at f = 335kHz to make a 1.1V to 1.5V reference

S

1.6

1.4

1.2

1.

voltage change is about 100µs, as calculated using the

following equation.

∆V

1

VID





(EQ. 11)

----

t

=

----------------- + 1.5

 

DVID

f

0.0125

S

Advanced Adaptive Zero Shoot-Through Deadtime

Control (Patent Pending)

0.8

0.6

0.4

The integrated drivers incorporate a unique adaptive deadtime

control technique to minimize deadtime, resulting in high

efficiency from the reduced freewheeling time of the lower

MOSFET body-diode conduction, and to prevent the upper and

lower MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other has

turned off.

Q

= 100nC

GATE

50nC

0.2

0.0

20nC

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

∆V (V)

BOOT_CAP

FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

During turn-off of the lower MOSFET, the PHASE voltage is

monitored until it reaches a -0.3V/+0.8V trip point for a

forward/reverse current, at which time the UGATE is released

Gate Drive Voltage Versatility

to rise. An auto-zero comparator is used to correct the r

DS(ON)

The ISL6568 provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. The controller

ties the upper and lower drive rails together. Simply applying

a voltage from 5V up to 12V on PVCC sets both gate drive

rail voltages simultaneously.

drop in the phase voltage preventing false detection of the

-0.3V phase level during r conduction period. In the

DS(ON)

case of zero current, the UGATE is released after 35ns delay of

the LGATE dropping below 0.5V. During the phase detection,

the disturbance of LGATE falling transition on the PHASE node

is blanked out to prevent falsely tripping. Once the PHASE is

high, the advanced adaptive shoot-through circuitry monitors

the PHASE and UGATE voltages during a PWM falling edge

and the subsequent UGATE turn-off. If either the UGATE falls

to less than 1.75V above the PHASE or the PHASE falls to less

than +0.8V, the LGATE is released to turn on.

Initialization

Prior to initialization, proper conditions must exist on the

ENLL, VCC, PVCC and the VID pins. When the conditions are

met, the controller begins soft-start. Once the output voltage is

within the proper window of operation, the controller asserts

PGOOD.

Internal Bootstrap Device

Enable and Disable

Both integrated drivers feature an internal bootstrap schottky

diode. Simply adding an external capacitor across the BOOT

and PHASE pins completes the bootstrap circuit. The

bootstrap function is also designed to prevent the bootstrap

capacitor from overcharging due to the large negative swing

at the PHASE node. This reduces voltage stress on the boot

to phase pins.

While in shutdown mode, the PWM outputs are held in a

high-impedance state. This forces the drivers to short gate-

to-source of the upper and lower MOSFET’s to assure the

MOSFETs remain off. The following input conditions must be

met before the ISL6566 is released from this shutdown

mode.

The bootstrap capacitor must have a maximum voltage

rating above PVCC + 5V and its capacitance value can be

chosen from the following equation:

1. The bias voltage applied at VCC must reach the internal

power-on reset (POR) rising threshold. Once this

threshold is reached, proper operation of all aspects of

the ISL6568 is guaranteed. Hysteresis between the rising

and falling thresholds assure that once enabled, the

ISL6568 will not inadvertently turn off unless the bias

voltage drops substantially (see Electrical

Q

GATE

-------------------------------------

C

≥

BOOT_CAP

∆V

BOOT_CAP

(EQ. 12)

Specifications).

Q

• PVCC

G1

-----------------------------------

Q

=

• N

Q1

GATE

V

GS1

where Q is the amount of gate charge per upper MOSFET

G1

at V

gate-source voltage and N is the number of

Q1

GS1

control MOSFETs. The ∆V

allowable droop in the rail of the upper gate drive.

term is defined as the

BOOT_CAP

FN9187.4

17

March 9, 2006

ISL6568

Thus, the soft-start period (not including the 16 PHASE clock

cycle delay) up to a given voltage, V , can be

ISL6568 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

VCC

DAC

approximated by the following equation

V

⋅ 1280

DAC

(EQ. 13)

T

= ---------------------------------

SS

f

S

PVCC1

+12V

where V

is the DAC-set VID voltage, and f is the

S

DAC

POR

switching frequency.

CIRCUIT

ENABLE

10.7kΩ

COMPARATOR

The ISL6568 also has the ability to start up into a pre-

charged output, without causing any unnecessary

disturbance. The FB pin is monitored during soft-start, and

should it be higher than the equivalent internal ramping

reference voltage, the output drives hold both MOSFETs off.

Once the internal ramping reference exceeds the FB pin

potential, the output drives are enabled, allowing the output

to ramp from the pre-charged level to the final level dictated

by the DAC setting. Should the output be pre-charged to a

level exceeding the DAC setting, the output drives are

enabled at the end of the soft-start period, leading to an

abrupt correction in the output voltage down to the DAC-set

level.

ENLL

+

-

1.40kΩ

0.66V

SOFT-START

AND

FAULT LOGIC

FIGURE 11. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (ENLL) FUNCTION

2. The voltage on ENLL must be above 0.66V. The EN input

allows for power sequencing between the controller bias

voltage and another voltage rail. The enable comparator

holds the ISL6568 in shutdown until the voltage at ENLL

rises above 0.66V. The enable comparator has 60mV of

hysteresis to prevent bounce.

OUTPUT PRECHARGED

ABOVE DAC LEVEL

OUTPUT PRECHARGED

BELOW DAC LEVEL

3. The driver bias voltage applied at the PVCC pin must

reach the internal power-on reset (POR) rising threshold.

Hysteresis between the rising and falling thresholds

assure that once enabled, the ISL6568 will not

V

(0.5V/DIV)

GND>

OUT

inadvertently turn off unless the PVCC bias voltage drops

substantially (see Electrical Specifications).

ENLL (5V/DIV)

4. The VID code must not be 111111 or 111110 in VRM10

mode or 11111 in AMD Hammer or VRM9 modes. These

codes signal the controller that no load is present. The

controller will enter shut-down mode after receiving either

of these codes and will execute soft-start upon receiving

any other code. These codes can be used to enable or

disable the controller but it is not recommended. After

receiving one of these codes, the controller executes a

2-cycle delay before changing the overvoltage trip level to

the shut-down level and disabling PWM. Overvoltage

shutdown cannot be reset using one of these codes.

T1 T2

T3

FIGURE 12. SOFT-START WAVEFORMS FOR ISL6568-BASED

MULTI-PHASE CONVERTER

Fault Monitoring and Protection

The ISL6568 actively monitors output voltage and current to

detect fault conditions. Fault monitors trigger protective

measures to prevent damage to a microprocessor load. One

common power good indicator is provided for linking to

external system monitors. The schematic in Figure 13

outlines the interaction between the fault monitors and the

power good signal.

When each of these conditions is true, the controller

immediately begins the soft-start sequence.

SOFT-START

The soft-start function allows the converter to bring up the

output voltage in a controlled fashion, resulting in a linear

ramp-up. Following a delay of 16 PHASE clock cycles

between enabling the chip and the start of the ramp, the

output voltage progresses at a fixed rate of 12.5mV per each

16 PHASE clock cycles.

FN9187.4

18

March 9, 2006

ISL6568

overvoltage trip level is the higher of DAC plus 150mV or a

fixed voltage, V . The fixed voltage, V , is 1.67V when

running in AMD Hammer, or VRM10 modes, and 1.97V for

VRM9 mode. Upon successful soft-start, the overvoltage trip

level is only DAC plus 150mV. OVP releases 50mV below its

trip point if it was “DAC plus 150mV” that tripped it, and

releases 100mV below its trip point if it was the fixed voltage,

R

V

OCSET

OVP OVP

OCSET

ICOMP

-

OCSET

+

IREF

ISUM

+

ISEN

-

V

100uA

DROOP

+

V

, that tripped it. Actions are taken by the ISL6568 to

OVP

protect the microprocessor load when an overvoltage

condition occurs, until the output voltage falls back within set

limits.

OC

+

-

VDIFF

+1V

At the inception of an overvoltage event, all LGATE signals

are commanded high, and the PGOOD signal is driven low.

This causes the controller to turn on the lower MOSFETs

and pull the output voltage below a level that might cause

damage to the load. The LGATE outputs remain high until

VDIFF falls to within the overvoltage limits explained above.

The ISL6568 will continue to protect the load in this fashion

as long as the overvoltage condition recurs.

VID + 150mV

SOFT-START, FAULT

AND CONTROL LOGIC

V

OVP

Once an overvoltage condition ends the ISL6568 continues

normal operation and PGOOD returns high.

-

OV

UV

VSEN

RGND

Pre-POR Overvoltage Protection

+

-

PGOOD

x1

Prior to PVCC and VCC exceeding their POR levels, the

ISL6568 is designed to protect the load from any overvoltage

events that may occur. This is accomplished by means of an

internal 10kΩ resistor tied from PHASE to LGATE, which

turns on the lower MOSFET to control the output voltage

until the overvoltage event ceases or the input power supply

cuts off. For complete protection, the low side MOSFET

should have a gate threshold well below the maximum

voltage rating of the load/microprocessor.

-

+

0.82 x DAC

ISL6568 INTERNAL CIRCUITRY

FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY

In the event that during normal operation the PVCC or VCC

voltage falls back below the POR threshold, the pre-POR

overvoltage protection circuitry reactivates to protect from

any more pre-POR overvoltage events.

Power Good Signal

The power good pin (PGOOD) is an open-drain logic output

that transitions high when the converter is operating after

soft-start. PGOOD pulls low during shutdown and releases

high after a successful soft-start. PGOOD transitions low

when an undervoltage, overvoltage, or overcurrent condition

is detected or when the controller is disabled by a reset from

ENLL, POR, or one of the no-CPU VID codes. If after an

undervoltage or overvoltage event occurs the output returns

to within under and overvoltage limits, PGOOD will return

high.

Open Sense Line Protection

In the case that either of the remote sense lines, VSEN or

GND, become open, the ISL6568 is designed to detect this

and shut down the controller. This event is detected by

monitoring the voltage on the IREF pin, which is a local

version of V

OUT

sensed at the outputs of the inductors.

If VSEN or RGND become opened, VDIFF falls, causing the

duty cycle to increase and the output voltage on IREF to

increase. If the voltage on IREF exceeds “VDIFF+1V”, the

controller will shut down. Once the voltage on IREF falls

below “VDIFF+1V”, the ISL6568 will restart at the beginning

of soft-start.

Undervoltage Detection

The undervoltage threshold is set at 82% of the VID code.

When the output voltage (VSEN-RGND) is below the

undervoltage threshold, PGOOD gets pulled low. No other

action is taken by the controller. PGOOD will return high if

the output voltage rises above 85% of the VID code.

Overcurrent Protection

The ISL6568 detects overcurrent events by comparing the

Overvoltage Protection

The ISL6568 constantly monitors the difference between the

VSEN and RGND voltages to detect if an overvoltage event

occurs. During soft-start, while the DAC is ramping up, the

droop voltage, V

shown in Figure 13. The droop voltage, set by the external

current sensing circuitry, is proportional to the output current

, to the OCSET voltage, V , as

DROOP OCSET

FN9187.4

19

March 9, 2006

ISL6568

as shown in Equation 7. A constant 100µA flows through

, creating the OCSET voltage. When the droop

voltage exceeds the OCSET voltage, the overcurrent

protection circuitry activates. Since the droop voltage is

proportional to the output current, the overcurrent trip level,

Principally, the designer will be concerned with whether

R

components can be mounted on both sides of the circuit

board, whether through-hole components are permitted, the

total board space available for power-supply circuitry, and

the maximum amount of load current. Generally speaking,

the most economical solutions are those in which each

phase handles between 25 and 30A. All surface-mount

designs will tend toward the lower end of this current range.

If through-hole MOSFETs and inductors can be used, higher

per-phase currents are possible. In cases where board

space is the limiting constraint, current can be pushed as

high as 40A per phase, but these designs require heat sinks

and forced air to cool the MOSFETs, inductors and heat-

dissipating surfaces.

OCSET

I

, can be set by selecting the proper value for R

,

MAX

OCSET

as shown in Equation 14.

I

⋅ R

100µ ⋅ R

⋅ DCR

COMP

MAX

(EQ. 14)

R

= ---------------------------------------------------------

OCSET

S

Once the output current exceeds the overcurrent trip level,

will exceed V , and a comparator will trigger

V

DROOP

OCSET

the converter to begin overcurrent protection procedures. At

the beginning of overcurrent shutdown, the controller turns

off both upper and lower MOSFETs. The system remains in

this state for a period of 4096 switching cycles. If the

controller is still enabled at the end of this wait period, it will

attempt a soft-start (as shown in Figure 14). If the fault

remains, the trip-retry cycles will continue indefinitely until

either the controller is disabled or the fault is cleared. Note

that the energy delivered during trip-retry cycling is much

less than during full-load operation, so there is no thermal

hazard.

MOSFETS

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct, the switching frequency,

the capability of the MOSFETs to dissipate heat, and the

availability and nature of heat sinking and air flow.

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is

simple, since virtually all of the loss in the lower MOSFET is

due to current conducted through the channel resistance

(r

). In Equation 15, I is the maximum continuous

DS(ON)

M

output current, I is the peak-to-peak inductor current (see

PP

OUTPUT CURRENT, 50A/DIV

Equation 1), and d is the duty cycle (V

/V ).

OUT IN

2

I

(1 – d)

12













I

L, PP

(EQ. 15)

M

P

= r

(1 – d) + --------------------------------

-----

N

LOW, 1

DS(ON)

0A

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

OUTPUT VOLTAGE,

500mV/DIV

diode forward voltage at I , V

, the switching

frequency, f , and the length of dead times, t and t , at

M

D(ON)

S

d1

d2

0V

the beginning and the end of the lower-MOSFET conduction

interval respectively.

2ms/DIV

FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE

F

= 500kHz

SW







I

N

I

M

I

(EQ. 16)





M

PP

P

= V

f

D(ON) S



t

d1



t

d2



+

----- + --------

----- – --------

LOW, 2

2

 N

2 

General Design Guide

The total maximum power dissipated in each lower MOSFET

is approximated by the summation of P and P

This design guide is intended to provide a high-level

.

LOW,2

explanation of the steps necessary to create a multi-phase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced below. In

addition to this guide, Intersil provides complete reference

designs that include schematics, bills of materials, and example

board layouts for all common microprocessor applications.

LOW,1

UPPER MOSFET POWER CALCULATION

In addition to r losses, a large portion of the upper-

DS(ON)

MOSFET losses are due to currents conducted across the

input voltage (V ) during switching. Since a substantially

IN

higher portion of the upper-MOSFET losses are dependent

on switching frequency, the power calculation is more

complex. Upper MOSFET losses can be divided into

separate components involving the upper-MOSFET

switching times, the lower-MOSFET body-diode reverse-

Power Stages

The first step in designing a multi-phase converter is to

determine the number of phases. This determination

depends heavily on the cost analysis which in turn depends

on system constraints that differ from one design to the next.

FN9187.4

20

March 9, 2006

ISL6568

recovery charge, Q , and the upper MOSFET r

rr

Calculating the power dissipation in the drivers for a desired

DS(ON)

conduction loss.

application is critical to ensure safe operation. Exceeding the

maximum allowable power dissipation level will push the IC

beyond the maximum recommended operating junction

temperature of 125°C. The maximum allowable IC power

dissipation for the 5x5 QFN package is approximately 4W at

room temperature. See Layout Considerations paragraph for

thermal transfer improvement suggestions.

When the upper MOSFET turns off, the lower MOSFET does

not conduct any portion of the inductor current until the

voltage at the phase node falls below ground. Once the

lower MOSFET begins conducting, the current in the upper

MOSFET falls to zero as the current in the lower MOSFET

ramps up to assume the full inductor current. In Equation 17,

the required time for this commutation is t and the

When designing the ISL6568 into an application, it is

recommended that the following calculation is used to

ensure safe operation at the desired frequency for the

selected MOSFETs. The total gate drive power losses,

1

UP,1

approximated associated power loss is P

.

t

I

N

I













1

M

PP



2





(EQ. 17)

P

≈ V

f

S

----

2

----- + --------

UP,1

IN



P

, due to the gate charge of MOSFETs and the

Qg_TOT

integrated driver’s internal circuitry and their corresponding

average driver current can be estimated with Equations 21

and 22, respectively.

At turn-on, the upper MOSFET begins to conduct and this

transition occurs over a time t . In Equation 18, the

2

UP,2

approximate power loss is P

.

P

= P

+ P

+ I • VCC

Qg_Q2 Q

(EQ. 21)

t

I

N

I













Qg_TOT

Qg_Q1

2

M

PP









(EQ. 18)

P

≈ V

f

S

----

2

----- –

--------

2

UP,2

IN

3

--

P

=

• Q

• PVCC • F

• N

Q2



• N

Q1 PHASE

A third component involves the lower MOSFET reverse-

Qg_Q1

Qg_Q2

G1

SW

2

recovery charge, Q . Since the inductor current has fully

rr

commutated to the upper MOSFET before the lower-

P

I

= Q

• PVCC • F

• N

PHASE

G2

SW

MOSFET body diode can recover all of Q , it is conducted

rr

through the upper MOSFET across VIN. The power

(EQ. 22)

+ I

dissipated as a result is P

.

UP,3

3



--

=

• Q

• N

+ Q

• N

• F

PHASE SW

(EQ. 19)

DR

G1

G2

Q2

Q





P

= V

Q f

Q1

2

UP,3

IN rr S

In Equations 21 and 22, P

is the total upper gate drive

Finally, the resistive part of the upper MOSFET is given in

Qg_Q1

power loss and P

is the total lower gate drive power loss;

Equation 20 as P

.

Qg_Q2

UP,4

the gate charge (Q and Q ) is defined at the particular gate

G1

G2

2

---------

12

to source drive voltage PVCC in the corresponding MOSFET









I

PP

M

(EQ. 20)

P

≈ r

d +



-----

N

data sheet; I is the driver total quiescent current with no load

UP,4

DS(ON)

Q



at both drive outputs; N and N are the number of upper

Q1

Q2

and lower MOSFETs per phase, respectively; N

is the

PHASE

The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results

from Equations 17, 18, 19 and 20. Since the power

equations depend on MOSFET parameters, choosing the

correct MOSFETs can be an iterative process involving

repetitive solutions to the loss equations for different

MOSFETs and different switching frequencies.

number of active phases. The I VCC product is the quiescent

Q*

power of the controller without capacitive load and is typically

75mW at 300kHz.

PVCC

BOOT

D

C

GD

Package Power Dissipation

R

HI1

G

UGATE

C

DS

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers

located in the controller. Since there are a total of two drivers

in the controller package, the total power dissipated by both

drivers must be less than the maximum allowable power

dissipation for the QFN package.

R

LO1

R

GI1

C

G1

GS

Q1

S

PHASE

FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FN9187.4

March 9, 2006

21

ISL6568

PVCC

V

IN

D

CHANNEL N

UPPER MOSFET

C

GD

I

L

R

HI2

G

LGATE

C

DS

ISEN(n)

R

LO2

R

GI2

C

G2

GS

R

ISEN

Q2

S

-

ISL6568

I

r

L

DS(ON)

+

CHANNEL N

FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

LOWER MOSFET

The total gate drive power losses are dissipated among the

resistive components along the transition path and in the

bootstrap diode. The portion of the total power dissipated in the

controller itself is the power dissipated in the upper drive path

FIGURE 17. ISL6568 INTERNAL AND EXTERNAL CURRENT-

SENSING CIRCUITRY

Select values for these resistors based on the room

temperature r

of the lower MOSFETs; the full-load

DS(ON)

operating current, I ; and the number of phases, N using

FL

resistance, P

, the lower drive path resistance, P ,

DR_UP

Equation 24.

and in the boot strap diode, P

. The rest of the power will

BOOT

r

I

be dissipated by the external gate resistors (R and R ) and

G1 G2

DS(ON) FL

(EQ. 24)

R

= ----------------------- -------

–

ISEN

6

N

the internal gate resistors (R

and R ) of the MOSFETs.

GI2

50 ×10

GI1

Figures 15 and 16 show the typical upper and lower gate

In certain circumstances, it may be necessary to adjust the

value of one or more ISEN resistors. When the components of

one or more channels are inhibited from effectively dissipating

their heat so that the affected channels run hotter than

drives’ turn-on transition path. The total power dissipation in the

controller itself, P , can be roughly estimated as:

DR

P

= P

+ P

+ (I • VCC)

(EQ. 23)

DR

DR_UP

DR_LOW

BOOT

Q

desired, choose new, smaller values of R

for the affected

ISEN

P

phases (see the section entitled Channel-Current Balance).

Choose R in proportion to the desired decrease in

Qg_Q1

3

P

= ---------------------

BOOT

ISEN,2

temperature rise in order to cause proportionally less current

to flow in the hotter phase.

P

R





Qg_Q1

HI1

LO1

---------------------

P

=

-------------------------------------- + --------------------------------------- •





DR_UP

3

R

+ R

R

+ R





HI1

EXT1

LO1

EXT1

∆T

2

(EQ. 25)

R

= R

----------

ISEN,2

ISEN

1

P

R









Qg_Q2

HI2

LO2

---------------------

P

R

=

-------------------------------------- + --------------------------------------- •



DR_LOW

2

R

+ R

R

+ R



HI2

EXT2

LO2 EXT2

In Equation 25, make sure that ∆T is the desired temperature

2

rise above the ambient temperature, and ∆T is the measured

1

R

N

GI1

GI2

temperature rise above the ambient temperature. While a

single adjustment according to Equation 25 is usually

= R

+ -------------

R

= R

+ -------------

EXT1

G1

EXT2

G2

N

Q1

Q2

sufficient, it may occasionally be necessary to adjust R

two or more times to achieve optimal thermal balance

between all channels.

ISEN

Current Balancing Component Selection

The ISL6568 senses the channel load current by sampling

the voltage across the lower MOSFET r

, as shown in

DS(ON)

Load Line Regulation Component Selection (DCR

Current Sensing)

Figure 17. The ISEN pins are denoted ISEN1 and ISEN2.

The resistors connected between these pins and the

respective phase nodes determine the gains in the channel-

current balance loop.

For accurate load line regulation, the ISL6568 senses the

total output current by detecting the voltage across the

output inductor DCR of each channel (As described in the

Load Line Regulation section). As Figure 18 illustrates, an

R-C network is required to accurately sense the inductor

DCR voltage and convert this information into a “droop”

voltage, which is proportional to the total output current.

FN9187.4

22

March 9, 2006

ISL6568

Choosing the components for this current sense network is a

two step process. First, R and C must be

Due to errors in the inductance or DCR it may be necessary

to adjust the value of R to match the time constants

correctly. The effects of time constant mismatch can be seen

in the form of droop overshoot or undershoot during the

initial load transient spike, as shown in Figure 19. Follow the

steps below to ensure the R-C and inductor L/DCR time

constants are matched accurately.

COMP

chosen so that the time constant of this R

-C

COMP COMP

network matches the time constant of the inductor L/DCR.

Then the resistor R must be chosen to set the current

S

sense network gain, obtaining the desired full load droop

voltage. Follow the steps below to choose the component

values for this R-C network.

1. Capture a transient event with the oscilloscope set to

about L/DCR/2 (sec/div). For example, with L = 1µH and

DCR = 1mΩ, set the oscilloscope to 500µs/div.

1. Choose an arbitrary value for C

. The recommended

COMP

value is 0.01µF.

2. Record ∆V1 and ∆V2 as shown in Figure 19.

2. Plug the inductor L and DCR component values, and the

values for C

chosen in steps 1, into Equation 26 to

3. Select a new value, R

, for the time constant

COMP

COMP,2

calculate the value for R

.

resistor based on the original value, R

, using the

COMP

COMP,1

following equation.

L

(EQ. 26)

R

= ---------------------------------------

COMP

DCR ⋅ C

∆V

1

COMP

(EQ. 28)

----------

R

= R

⋅

COMP, 2

COMP, 1

2

3. Use the new value for R

obtained from Equation

COMP

26, as well as the desired full load current, I , full load

4. Replace R

with the new value and check to see that

FL

COMP

droop voltage, V

, and inductor DCR in Equation

the error is corrected. Repeat the procedure if necessary.

DROOP

27 to calculate the value for R .

S

After choosing a new value for R

, it will most likely be

COMP

I

FL

necessary to adjust the value of R to obtain the desired full

S

(EQ. 27)

------------------------

R

=

⋅ R

⋅ DCR

COMP

S

V

load droop voltage. Use Equation 27 to obtain the new value

DROOP

for R .

S

-

V (s)

L

I

OUT

L

DCR

PHASE1

PHASE2

V

INDUCTOR

L1

OUT

I

∆V

2

R

C

S

OUT

∆V

1

L

DCR

V

OUT

INDUCTOR

L2

R

S

I

TRAN

ISUM

∆I

R

C

COMP

ICOMP

-

FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR

V

DROOP

+

(optional)

IREF

Compensation

The two opposing goals of compensating the voltage

regulator are stability and speed.

ISL6568

FIGURE 18. DCR SENSING CONFIGURATION

The load-line regulated converter behaves in a similar

manner to a peak current mode controller because the two

poles at the output filter L-C resonant frequency split with the

introduction of current information into the control loop. The

final location of these poles is determined by the system

function, the gain of the current signal, and the value of the

compensation components, R and C .

C

FN9187.4

23

March 9, 2006

ISL6568

In Equations 29, L is the per-channel filter inductance

C

(OPTIONAL)

2

divided by the number of active channels; C is the sum total

of all output capacitors; ESR is the equivalent series

C

resistance of the bulk output filter capacitance; and V is

PP

R

C

COMP

the peak-to-peak sawtooth signal amplitude as described in

the Electrical Specifications.

FB

Once selected, the compensation values in Equations 29

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

ISL6568

R

FB

improved by making adjustments to R . Slowly increase the

C

VDIFF

value of R while observing the transient performance on an

C

oscilloscope until no further improvement is noted. Normally,

C

will not need adjustment. Keep the value of C from

C

FIGURE 20. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL6568 CIRCUIT

Equations 29 unless some performance issue is noted.

The optional capacitor C , is sometimes needed to bypass

2

Since the system poles and zero are affected by the values

of the components that are meant to compensate them, the

solution to the system equation becomes fairly complicated.

Fortunately, there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator, by compensating the L-C

poles and the ESR zero of the voltage mode approximation,

yields a solution that is always stable with very close to ideal

transient performance.

noise away from the PWM comparator (See Figure 20).

Keep a position available for C , and be prepared to install a

2

high-frequency capacitor of between 22pF and 150pF in

case any leading edge jitter problem is noted.

Output Filter Design

The output inductors and the output capacitor bank together

to form a low-pass filter responsible for smoothing the

pulsating voltage at the phase nodes. The output filter also

must provide the transient energy until the regulator can

respond. Because it has a low bandwidth compared to the

switching frequency, the output filter limits the system

transient response. The output capacitors must supply or

sink load current while the current in the output inductors

increases or decreases to meet the demand.

Select a target bandwidth for the compensated system, f .

0

The target bandwidth must be large enough to assure

adequate transient performance, but smaller than 1/3 of the

per-channel switching frequency. The values of the

compensation components depend on the relationships of f

0

to the L-C pole frequency and the ESR zero frequency. For

each of the following three, there is a separate set of

equations for the compensation components.

In high-speed converters, the output capacitor bank is usually

the most costly (and often the largest) part of the circuit.

Output filter design begins with minimizing the cost of this part

of the circuit. The critical load parameters in choosing the

output capacitors are the maximum size of the load step, ∆I,

the load-current slew rate, di/dt, and the maximum allowable

1

------------------- > f

Case 1:

0

2π LC

2πf V

0.66V

LC

pp

0

R

C

= R -----------------------------------

C

FB

IN

output-voltage deviation under transient loading, ∆V

Capacitors are characterized according to their capacitance,

ESR, and ESL (equivalent series inductance).

.

MAX

0.66V

IN

= ------------------------------------

2πV

R

f

PP FB 0

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

initially deviate by an amount approximated by the voltage

drop across the ESL. As the load current increases, the

voltage drop across the ESR increases linearly until the load

current reaches its final value. The capacitors selected must

have sufficiently low ESL and ESR so that the total output-

voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

response, the output voltage initially deviates by an amount

1

-------------------

≤ f < -----------------------------

0

2πC(ESR)

Case 2:

Case 3:

2π LC

2

V

(2π)

f

LC

0

PP

R

C

= R --------------------------------------------

(EQ. 29)

C

FB

0.66 V

IN

0.66V

IN

= ------------------------------------------------------------

2

(2π)

f

V

R

LC

0

PP FB

1

f > -----------------------------

0

2πC(ESR)

2π f V

L

pp

di

(EQ. 30)

0

∆V ≈ (ESL) ---- + (ESR) ∆I

R

C

= R

-----------------------------------------

dt

C

FB

0.66 V (ESR)

IN

0.66V (ESR)

C

IN

The filter capacitor must have sufficiently low ESL and ESR

so that ∆V < ∆V

= -------------------------------------------------

2πV

R

f

L

.

MAX

PP FB 0

FN9187.4

24

March 9, 2006

ISL6568

Most capacitor solutions rely on a mixture of high frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

Switching frequency is determined by the selection of the

frequency-setting resistor, R . Figure 21 and Equation 34

T

are provided to assist in selecting the correct value for R .

T

(EQ. 34)

[

]

)

10.61 – 1.035log(f

S

R

= 10

T

1000

100

10

The ESR of the bulk capacitors also creates the majority of

the output-voltage ripple. As the bulk capacitors sink and

source the inductor ac ripple current (See Interleaving and

Equation 2), a voltage develops across the bulk capacitor

ESR equal to I

(ESR). Thus, once the output capacitors

are selected, the maximum allowable ripple voltage,

C,PP

V

, determines the lower limit on the inductance.

PP(MAX)





V

– N V

V

OUT OUT



IN



(EQ. 31)

L

(ESR)

≥

-----------------------------------------------------------

f V

V

IN PP(MAX)

S

10

100

1000

10000

SWITCHING FREQUENCY (kHz)

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

FIGURE 21. R vs SWITCHING FREQUENCY

T

Input Capacitor Selection

The input capacitors are responsible for sourcing the ac

component of the input current flowing into the upper

MOSFETs. Their RMS current capacity must be sufficient to

handle the ac component of the current drawn by the upper

MOSFETs which is related to duty cycle and the number of

active phases.

∆V

. This places an upper limit on inductance.

MAX

Equation 32 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 33

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually

less than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of

the two results. In each equation, L is the per-channel

inductance, C is the total output capacitance, and N is the

number of active channels.

0.3

0.2

0.1

2 ⋅ N ⋅ C ⋅ V

O

(EQ. 32)

L ≤ --------------------------------- ∆V

– (∆I ⋅ ESR)

MAX

2

(

)

∆I

(

)

1.25 ⋅ N ⋅ C

(EQ. 33)







I

= 0

= 0.5 I

= 0.75 I

L ≤ --------------------------------- ∆V

– (∆I ⋅ ESR)

V

– V

IN O



L,PP

MAX

2

)

(

∆I

O

Switching Frequency

0

0.2

0.4

0.6

0.8

1.0

There are a number of variables to consider when choosing

the switching frequency, as there are considerable effects on

the upper MOSFET loss calculation. These effects are

outlined in MOSFETs, and they establish the upper limit for

the switching frequency. The lower limit is established by the

requirement for fast transient response and small output-

voltage ripple as outlined in Output Filter Design. Choose the

lowest switching frequency that allows the regulator to meet

the transient-response requirements.

DUTY CYCLE (V

V

)

O

IN/

FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 2-PHASE CONVERTER

For a two-phase design, use Figure 22 to determine the

input-capacitor RMS current requirement set by the duty

cycle, maximum sustained output current (I ), and the ratio

O

of the peak-to-peak inductor current (I

) to I . Select a

O

L,PP

bulk capacitor with a ripple current rating which will minimize

FN9187.4

25

March 9, 2006

ISL6568

the total number of input capacitors required to support the

RMS current calculated. The voltage rating of the capacitors

should also be at least 1.25 times greater than the maximum

input voltage. Figure 23 provides the same input RMS

current information for single-phase designs. Use the same

approach for selecting the bulk capacitor type and number.

connect to sensitive nodes or supply critical bypassing

current and signal coupling.

The power components should be placed first, which include

the MOSFETs, input and output capacitors, and the inductors. It

is important to have a symmetrical layout for each power train,

preferably with the controller located equidistant from each.

Symmetrical layout allows heat to be dissipated equally

across all three power trains. Equidistant placement of the

controller to the three power trains also helps keep the gate

drive traces equally short, resulting in equal trace impedances

and similar drive capability of all sets of MOSFETs.

0.6

0.4

0.2

When placing the MOSFETs try to keep the source of the

upper FETs and the drain of the lower FETs as close as

thermally possible. Input Bulk capacitors should be placed

close to the drain of the upper FETs and the source of the lower

FETs. Locate the output inductors and output capacitors

between the MOSFETs and the load. The high-frequency input

and output decoupling capacitors (ceramic) should be placed

as close as practicable to the decoupling target, making use of

the shortest connection paths to any internal planes, such as

vias to GND next or on the capacitor solder pad.

I

= 0

= 0.5 I

= 0.75 I

L,PP

O

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V /V

)

IN

O

The critical small components include the bypass capacitors

for VCC and PVCC, and many of the components

FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR SINGLE-PHASE CONVERTER

surrounding the controller including the feedback network

and current sense components. Locate the VCC/PVCC

bypass capacitors as close to the ISL6566 as possible. It is

especially important to locate the components associated

with the feedback circuit close to their respective controller

pins, since they belong to a high-impedance circuit loop,

sensitive to EMI pick-up. It is also important to place the

current sense components close to their respective pins on

Low capacitance, high-frequency ceramic capacitors are

needed in addition to the input bulk capacitors to suppress

leading and falling edge voltage spikes. The spikes result from

the high current slew rate produced by the upper MOSFET

turn on and off. Select low ESL ceramic capacitors and place

one as close as possible to each upper MOSFET drain to

minimize board parasitics and maximize suppression.

the ISL6566, including R

, R , R

, and C .

ISEN

S

COMP

Layout Considerations

A multi-layer printed circuit board is recommended. Figure 25

shows the connections of the critical components for the

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

converter. Note that capacitors C

and C could each

xxIN

xxOUT

represent numerous physical capacitors. Dedicate one solid

layer, usually the one underneath the component side of the

board, for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into smaller

islands of common voltage levels. Keep the metal runs from the

PHASE terminal to output inductors short. The power plane

should support the input power and output power nodes. Use

copper filled polygons on the top and bottom circuit layers for

the phase nodes. Use the remaining printed circuit layers for

small signal wiring.

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit

and lead to device overvoltage stress. Careful component

selection, layout, and placement minimizes these voltage

spikes. Consider, as an example, the turnoff transition of the

upper PWM MOSFET. Prior to turnoff, the upper MOSFET

was carrying channel current. During the turnoff, current

stops flowing in the upper MOSFET and is picked up by the

lower MOSFET. Any inductance in the switched current path

generates a large voltage spike during the switching interval.

Careful component selection, tight layout of the critical

components, and short, wide circuit traces minimize the

magnitude of voltage spikes.

Routing UGATE, LGATE, and PHASE traces

Great attention should be paid to routing the UGATE, LGATE,

and PHASE traces since they drive the power train MOSFETs

using short, high current pulses. It is important to size them as

large and as short as possible to reduce their overall

impedance and inductance. They should be sized to carry at

least one ampere of current (0.02” to 0.05”). Going between

There are two sets of critical components in a DC-DC

converter using a ISL6566 controller. The power

components are the most critical because they switch large

amounts of energy. Next are small signal components that

FN9187.4

26

March 9, 2006

ISL6568

layers with vias should also be avoided, but if so, use two vias

for interconnection when possible.

Extra care should be given to the LGATE traces in particular

since keeping their impedance and inductance low helps to

significantly reduce the possibility of shoot-through. It is also

important to route each channels UGATE and PHASE traces

in as close proximity as possible to reduce their inductances.

Thermal Management

For maximum thermal performance in high current, high

switching frequency applications, connecting the thermal

GND pad of the ISL6566 to the ground plane with multiple

vias is recommended. This heat spreading allows the part to

achieve its full thermal potential. It is also recommended

that the controller be placed in a direct path of airflow if

possible to help thermally manage the part.

Suppressing MOSFET Gate Leakage

With VCC at ground potential, UGATE is high impedance. In

this state, any stray leakage has the potential to deliver

charge to the gate of the upper MOSFET. If UGATE receives

sufficient charge to bias the device on, a low impedance path

will be connected between the upper MOSFET drain and

PHASE. If this occurs and the input power supply is present

and active, the system could see potentially damaging

current. Worst-case leakage currents are on the order of

pico-amps; therefore, a 10kΩ resistor, connected from

UGATE to PHASE, is more than sufficient to bleed off any

stray leakage current. This resistor will not affect the normal

performance of the driver or reduce its efficiency.

FN9187.4

27

March 9, 2006

ISL6568

LOCATE CLOSE TO IC

(MINIMIZE CONNECTION PATH)

KEY

C

2

HEAVY TRACE ON CIRCUIT PLANE LAYER

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

R

FB

R

C

1

FB

COMP

VDIFF

+12V

VSEN

RGND

LOCATE NEAR SWITCHING TRANSISTORS;

(MINIMIZE CONNECTION PATH)

+5V

PVCC

BOOT1

UGATE1

C

BIN1

(CF2)

VCC

(CF1)

C

BOOT1

R

OFS

PHASE1

ISEN1

OFS

R

ISEN1

FS

LGATE1

REF

R

T

C

REF

ISL6568

VID4

VID3

C

(C

)

HFOUT

+12V

BOUT

VID2

C

BIN2

VID1

LOAD

VID0

BOOT2

VID12.5

C

BOOT2

UGATE2

PGOOD

GND

LOCATE NEAR LOAD;

(MINIMIZE CONNECTION PATH)

PHASE2

ISEN2

+12V

R

ISEN2

LGATE2

ENLL

IREF

OCSET

ICOMP

ISUM

R

C

COMP

R

S

R

OCSET

R

COMP

FIGURE 24. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

FN9187.4

28

March 9, 2006

ISL6568

Quad Flat No-Lead Plas tic Package (QFN)

Micro Lead Frame Plas tic Package (MLFP)

L32.5x5

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.18

2.95

0.23

0.30

3.25

5,8

D

5.00 BSC

-

D1

D2

E

4.75 BSC

9

3.10

7,8

5.00 BSC

-

E1

E2

e

4.75 BSC

9

3.10

7,8

0.50 BSC

-

k

0.25

0.30

-

L

0.40

0.50

0.15

8

L1

N

-

32

8

-

10

2

Nd

Ne

P

3

8

-

3

0.60

12

9

θ

-

9

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9187.4

29

March 9, 2006


型号：	ISL6568CRZ-TR5184
厂家：	Intersil
描述：	Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications 两相降压PWM控制器与VRM9 ， VRM10 ，和AMD锤应用集成MOSFET驱动器驱动器控制器
文件：	总29页 (文件大小：717K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6568CRZ-TR5184 [INTERSIL]

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