ISL6610ACBZ [INTERSIL]
Dual Synchronous Rectified MOSFET Drivers; 双同步整流MOSFET驱动器
| 型号： | ISL6610ACBZ |
| 厂家： | 
Intersil |
| 描述： | Dual Synchronous Rectified MOSFET Drivers |
| 文件： | 总11页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6610, ISL6610A
®
Data Sheet
November 22, 2006
FN6395.0
Dual Synchronous Rectified MOSFET
Drivers
Features
• 5V Quad N-Channel MOSFET Drives for Two
Synchronous Rectified Bridges
The ISL6610, ISL6610A integrates two ISL6609, ISL6609A
drivers with enable function removed and is optimized to
drive two independent power channels in a synchronous-
rectified buck converter topology. These drivers, combined
with an Intersil ISL63xx or ISL65xx multiphase PWM
controller, form a complete high efficiency voltage regulator
at high switching frequency.
• Pin-to-pin Compatible with ISL6614 (12V Drive)
• Adaptive Shoot-Through Protection
• 0.4Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast Output Rise and Fall
The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Each driver is capable of driving a 3nF load with less than
10ns rise/fall time. Bootstrapping of the upper gate driver is
implemented via an internal low forward drop diode,
reducing implementation cost, complexity, and allowing the
use of higher performance, cost effective N-Channel
MOSFETs. Adaptive shoot-through protection is integrated
to prevent both MOSFETs from conducting simultaneously.
- Low Tri-State Hold-Off Time
• BOOT Capacitor Overcharge Prevention (ISL6610A)
• Low V Internal Bootstrap Diode
F
• Power-On Reset
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Utilization, Thinner Profile
The ISL6610, ISL6610A features 4A typical sink current for
the lower gate driver, enhancing the lower MOSFET gate
hold-down capability during PHASE node rising edge,
preventing power loss caused by the self turn-on of the lower
MOSFET due to the high dV/dt of the switching node.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
The ISL6610, ISL6610A also features an input that
recognizes a high-impedance state, working together with
Intersil multiphase PWM controllers to prevent negative
transients on the controlled output voltage when operation is
suspended. This feature eliminates the need for the schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Ordering Information
PART
NUMBER
(Note)
TEMP.
RANGE
(°C)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
In addition, the ISL6610As bootstrap function is designed to
prevent the BOOT capacitor from overcharging, should
excessively large negative swings occur at the transitions of
the PHASE node.
ISL6610CBZ
ISL6610CRZ
ISL6610IBZ
ISL6610IRZ
6610CBZ
66 10CRZ
6610IBZ
0 to +70 14 Ld SOIC
M14.15
0 to +70 16 Ld 4x4 QFN L16.4x4
-40 to +85 14 Ld SOIC M14.15
-40 to +85 16 Ld 4x4 QFN L16.4x4
0 to +70 14 Ld SOIC M14.15
ISL6610ACRZ 66 10ACRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
ISL6610AIBZ 6610AIBZ -40 to +85 14 Ld SOIC M14.15
66 10IRZ
Applications
ISL6610ACBZ 6610ACBZ
• Core Voltage Supplies for Intel® and AMD®
Microprocessors
• High Frequency Low Profile High Efficiency DC/DC
Converters
ISL6610AIRZ 66 10AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
• High Current Low Voltage DC/DC Converters
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Synchronous Rectification for Isolated Power Supplies
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.
ISL6610, ISL6610A
Pinouts
ISL6610, ISL6610A
(14 LD SOIC)
TOP VIEW
ISL6610, ISL6610A
(16 LD QFN)
TOP VIEW
14
13
12
11
10
9
PWM1
PWM2
GND
1
2
3
4
VCC
PHASE1
UGATE1
BOOT1
16 15 14 13
GND
LGATE1
PVCC
1
2
3
4
12 UGATE1
11 BOOT1
LGATE1
PVCC
17
GND
BOOT2
5
6
10
9
BOOT2
PGND
UGATE2
PHASE2
PGND
UGATE2
LGATE2
7
8
5
6
7
8
Block Diagram
ISL6610, ISL6610A
R
BOOT
PVCC
VCC
BOOT1
UGATE1
PHASE1
4.9K
4.6K
CHANNEL 1
SHOOT-
THROUGH
PROTECTION
PVCC
PWM1
LGATE1
PGND
PGND
CONTROL
LOGIC
R
VCC
4.9K
BOOT
PVCC
BOOT2
UGATE2
PWM2
GND
PHASE2
SHOOT-
THROUGH
PROTECTION
CHANNEL 2
4.6K
PVCC
LGATE2
PGND
PAD
FOR ISL6610CR/10ACR, THE PAD ON THE BOTTOM SIDE OF
THE QFN PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
INTEGRATED 3Ω RESISTOR (R ) AVAILABLE ONLY IN ISL6610A
BOOT
FN6395.0
November 22, 2006
2
ISL6610, ISL6610A
Typical Application - Multiphase Converter Using ISL6610 Gate Drivers
BOOT1
+5V
+12V
UGATE1
PHASE1
VCC
LGATE1
PVCC
+5V
DUAL
DRIVER
ISL6610
+5V
BOOT2
+12V
COMP
V
FB
CC
VSEN
UGATE2
ISEN1
PWM1
PWM1
PWM2
PHASE2
NC2
PGOOD
EN
PWM2
ISEN2
LGATE2
NC1
MAIN
CONTROL
ISL65xx
GND
PGND
VID
+V
CORE
ISEN3
PWM3
PWM4
FS/DIS
BOOT1
+5V
+12V
GND
ISEN4
UGATE1
PHASE1
VCC
LGATE1
PVCC
DUAL
DRIVER
ISL6610
+5V
BOOT2
+12V
UGATE2
PHASE2
PWM1
PWM2
LGATE2
PGND
GND
FN6395.0
November 22, 2006
3
ISL6610, ISL6610A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (V , V ) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°C/W)
JA
JC
EN PWM
BOOT Voltage (V
SOIC Package (Note 1) . . . . . . . . . . . .
QFN Package (Notes 2 and 3). . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
90
46
N/A
8.5
). . . -0.3V to 25V (DC) or 36V (<200ns)
BOOT-GND
BOOT To PHASE Voltage (V
). . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
BOOT-PHASE
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC)
GND -8V (<20ns Pulse Width, 10μJ) to 30V (<100ns)
UGATE Voltage . . . . . . . . . . . . . . . . V
- 0.3V (DC) to V
PHASE
BOOT
- 5V (<20ns Pulse Width, 10μJ) to V
BOOT
V
PHASE
Recommended Operating Conditions
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
+150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Constantly operated at 150°C may shorten the life of the part.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
JA
3. θ , “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
JC
Electrical Specifications These specifications apply for TA = -40°C to +85°C, unless otherwise noted
PARAMETER
SUPPLY CURRENT
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Bias Supply Current
I
PWM pin floating, V
= V
= 5V
= 5V
-
-
240
1.6
-
-
μA
VCC+PVCC
VCC
PVCC
F
= 300kHz, V
= V
mA
PWM
VCC
PVCC
BOOTSTRAP DIODE
Forward Voltage
VF
Forward bias current = 2mA
TA = 0°C to +70°C
0.30
0.30
0.60
0.60
0.70
0.75
V
V
Forward bias current = 2mA
TA = -40°C to +85°C
POWER-ON RESET
POR Rising
-
2.6
-
3.4
3.0
400
4.2
V
V
POR Falling
-
-
Hysteresis
mV
PWM INPUT
Sinking Impedance
R
R
-
-
4.6
4.9
-
-
kΩ
kΩ
V
PWM_SNK
Source Impedance
PWM_SRC
Tri-State Rising Threshold
Tri-State Falling Threshold
Tri-State Shutdown Holdoff Time
SWITCHING TIME (Note 4, See Figure 1)
UGATE Rise Time
V
V
= V
= V
= 5V (250mV Hysteresis)
= 5V(300mV Hysteresis)
1.00
3.10
-
1.20
3.41
80
1.40
3.70
-
VCC
VCC
PVCC
PVCC
V
t
ns
TSSHD
t
3nF Load
3nF Load
3nF Load
3nF Load
-
-
-
-
-
-
8.0
8.0
8.0
4.0
18
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
RU
LGATE Rise Time
t
RL
FU
UGATE Fall Time
t
LGATE Fall Time
t
FL
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
t
Outputs Unloaded
Outputs Unloaded
PDLU
t
25
PDLL
FN6395.0
November 22, 2006
4
ISL6610, ISL6610A
Electrical Specifications These specifications apply for TA = -40°C to +85°C, unless otherwise noted (Continued)
PARAMETER
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
OUTPUT (Note 4)
SYMBOL
TEST CONDITIONS
Outputs Unloaded
MIN
TYP
18
MAX
UNITS
ns
t
-
-
-
-
-
-
PDHU
t
Outputs Unloaded
Outputs Unloaded
23
ns
PDHL
t
20
ns
PTS
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
NOTE:
R
R
250mA Source Current
250mA Sink Current
250mA Source Current
250mA Sink Current
-
-
-
-
1.0
1.0
1.0
0.4
2.5
2.5
2.5
1.0
Ω
Ω
Ω
Ω
UG_SRC
UG_SNK
R
LG_SRC
LG_SNK
R
4. Guaranteed by Characterization. Not 100% tested in production.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
DFN
SYMBOL
FUNCTION
1
15
PWM1
The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
2
16
PWM2
GND
The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
3
4
5
1
2
3
Bias and reference ground. All signals are referenced to this node.
LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
PVCC
This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor
from this pin to PGND.
6
-
4
5,8
6
PGND
NC1,2
Power ground return of both low gate drivers.
No connection.
7
8
LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
7
PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This
pin provides a return path for the upper gate drive.
9
9
UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
10
10
BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this
pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
11
11
BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this
pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
12
13
12
13
UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This
pin provides a return path for the upper gate drive.
14
-
14
17
VCC
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR
ceramic capacitor from this pin to GND.
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
FN6395.0
November 22, 2006
5
ISL6610, ISL6610A
Timing Diagram
2.5V
t
PWM
PDHU
t
t
PDLU
TSSHD
t
FU
t
t
RU
RU
t
PTS
1V
UGATE
LGATE
t
PTS
1V
t
RL
t
TSSHD
t
PDHL
t
t
PDLL
FL
FIGURE 1. TIMING DIAGRAM
absorb the current injected into the lower gate through the
Operation and Adaptive Shoot-Through Protection
drain-to-gate capacitor (C ) of the lower MOSFET and
help prevent shoot through caused by the self turn-on of the
lower MOSFET due to high dV/dt of the switching node.
GD
Designed for high speed switching, the ISL6610, ISL6610A
MOSFET driver controls both high-side and low-side N-
Channel FETs from one externally provided PWM signal.
Tri-State PWM Input
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Figure 1). After a short propagation delay
A unique feature of the ISL6610, ISL6610A is the adaptable
tri-state PWM input. Once the PWM signal enters the
shutdown window, either MOSFET previously conducting is
turned off. If the PWM signal remains within the shutdown
window for longer than 80ns of the previously conducting
MOSFET, the output drivers are disabled and both MOSFET
gates are pulled and held low. The shutdown state is
removed when the PWM signal moves outside the shutdown
window. The PWM rising and falling thresholds outlined in
the Electrical Specifications determine when the lower and
upper gates are enabled. During normal operation in a
typical application, the PWM rise and fall times through the
shutdown window should not exceed either output’s turn-off
propagation delay plus the MOSFET gate discharge time to
~1V. Abnormally long PWM signal transition times through
the shutdown window will simply introduce additional dead
time between turn off and turn on of the synchronous
bridge’s MOSFETs. For optimal performance, no more than
100pF parasitic capacitive load should be present on the
PWM line of ISL6610, ISL6610A (assuming an Intersil PWM
controller is used).
[t
], the lower gate begins to fall. Typical fall times [t
]
PDLL
FL
are provided in the Electrical Specifications. Adaptive shoot-
through circuitry monitors the LGATE voltage and turns on
the upper gate following a short delay time [t
] after the
PDHU
LGATE voltage drops below ~1V. The upper gate drive then
begins to rise [t ] and the upper MOSFET turns on.
RU
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t ]. The adaptive shoot-through circuitry
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time, t , after the upper
MOSFET’s gate voltage drops below 1V. The lower gate then
rises [t ], turning on the lower MOSFET. These methods
prevent both the lower and upper MOSFETs from conducting
simultaneously (shoot-through), while adapting the dead
time to the gate charge characteristics of the MOSFETs
being used.
] is encountered before the upper
PDLU
FU
PDHL
RL
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower
Bootstrap Considerations
This driver features an internal bootstrap diode. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit. The ISL6610A’s internal
bootstrap resistor is designed to reduce the overcharging of
MOSFET conducts for a longer time during a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement. The 0.4Ω on-resistance
and 4A sink current capability enable the lower gate driver to
FN6395.0
November 22, 2006
6
ISL6610, ISL6610A
the bootstrap capacitor when exposed to excessively large
the SO14 package is approximately 1W at room
temperature, while the power dissipation capacity in the
QFN packages, with an exposed heat escape pad, is around
2W. See Layout Considerations paragraph for thermal
transfer improvement suggestions. When designing the
driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively,
negative voltage swing at the PHASE node. Typically, such
large negative excursions occur in high current applications
2
that use D -PAK and D-PAK MOSFETs or excessive layout
parasitic inductance. The following equation helps select a
proper bootstrap capacitor size:
Q
GATE
-------------------------------------
C
≥
BOOT_CAP
ΔV
BOOT_CAP
(EQ. 1)
Q
• PVCC
G1
-----------------------------------
Q
=
• N
Q1
GATE
V
GS1
where Q is the amount of gate charge per upper MOSFET
G1
P
= 2 • (P
+ P
) + I • VCC
(EQ. 2)
Qg_TOT
Qg_Q1
Qg_Q2
Q
at V
gate-source voltage and N is the number of
GS1
control MOSFETs. The ΔV
Q1
term is defined as the
2
BOOT_CAP
Q
• PVCC
G1
--------------------------------------
allowable droop in the rail of the upper gate drive.
P
=
• F
• N
Qg_Q1
SW
Q1
Q2
V
GS1
As an example, suppose two HAT2168 FETs are chosen as
2
Q
• PVCC
G2
the upper MOSFETs. The gate charge, Q , from the data
G
--------------------------------------
P
=
• F
• N
• N
• F
Qg_Q2
SW
V
sheet is 12nC at 5V (V ) gate-source voltage. Then the
GS
GS2
Q
is calculated to be 26.4nC at 5.5V PVCC level. We
GATE
will assume a 100mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.264μF is required. The next larger standard value
capacitance is 0.33µF. A good quality ceramic capacitor is
recommended.
Q
• N
Q
G2
V
GS2
⎛
⎜
⎝
⎞
⎟
⎠
G1
V
Q1
Q2
(EQ. 3)
----------------------------- -----------------------------
I
= 2 •
+
+ I
SW Q
DR
GS1
where the gate charge (Q and Q ) is defined at a
particular gate to source voltage (V
corresponding MOSFET datasheet; I is the driver’s total
G1
G2
and V
) in the
GS1
GS2
2.0
Q
1.8
1.6
1.4
1.2
1.0
0.8
0.6
quiescent current with no load at both drive outputs and can
be negligible; N and N are number of upper and lower
Q1 Q2
MOSFETs, respectively. The factor 2 is the number of active
channels. The I product is the quiescent power of the
V
Q
CC
driver without capacitive load and is typically negligible.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
Q
= 100nC
GATE
resistors (R and R , should be a short to avoid
G1 G2
0.4
50nC
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R and R ) of
MOSFETs. Figures 3 and 4 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as:
0.2
0.0
20nC
GI1
GI2
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV (V)
BOOT
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
P
P
= 2 • (P
+ P
) + I • VCC
DR_LOW Q
(EQ. 4)
DR
DR_UP
R
Power Dissipation
R
P
Qg_Q1
⎛
⎞
HI1
LO1
-------------------------------------- --------------------------------------- ---------------------
=
+
•
⎜
⎝
⎟
DR_UP
Package power dissipation is mainly a function of the
R
+ R
R
+ R
EXT1
2
⎠
HI1
EXT1
LO1
switching frequency (F ), the output drive impedance, the
SW
R
R
P
Qg_Q2
⎛
⎜
⎝
⎞
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
HI2
LO2
-------------------------------------- --------------------------------------- ---------------------
P
R
=
+
•
⎟
DR_LOW
R
+ R
R
+ R
⎠
EXT2
2
HI2
EXT2
LO2
R
R
GI1
GI2
-------------
-------------
= R
+
R
= R +
G2
EXT2
G1
EXT2
N
N
Q1
Q2
FN6395.0
November 22, 2006
7
ISL6610, ISL6610A
profile MOSFETs, such as Direct FETs and multi-SOURCE
PVCC
BOOT
leads devices (SO-8, LFPAK, PowerPAK), have low parasitic
lead inductances and can be driven by either ISL6610 or
ISL6610A (assuming proper layout design). The ISL6610,
missing the 3Ω integrated BOOT resistor, typically yields
slightly higher efficiency than the ISL6610A.
D
C
GD
R
HI1
G
C
DS
R
R
LO1
R
GI1
C
G1
UGATE
PHASE
Layout Considerations
GS
Q1
S
A good layout helps reduce the ringing on the switching
node (PHASE) and significantly lower the stress applied to
the output drives. The following advice is meant to lead to an
optimized layout and performance:
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
• Keep decoupling loops (VCC-GND, PVCC-PGND and
BOOT-PHASE) short and wide, at least 25 mils. Avoid
using vias on decoupling components other than their
ground terminals, which should be on a copper plane with
at least two vias.
PVCC
D
C
GD
LGATE
R
HI2
G
C
DS
• Minimize trace inductance, especially on low-impedance
lines. All power traces (UGATE, PHASE, LGATE, PGND,
PVCC, VCC, GND) should be short and wide, at least 25
mils. Try to place power traces on a single layer,
otherwise, two vias on interconnection are preferred
where possible. For no connection (NC) pins on the QFN
part, connect it to the adjacent net (LGATE2/PHASE2) can
reduce trace inductance.
R
R
LO2
R
GI2
C
G2
GS
Q2
S
GND
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
• Shorten all gate drive loops (UGATE-PHASE and LGATE-
PGND) and route them closely spaced.
Application Information
• Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
MOSFET and Driver Selection
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding absolute maximum rating
of the devices. The negative ringing at the edges of the
PHASE node could increase the bootstrap capacitor voltage
through the internal bootstrap diode, and in some cases, it
may overstress the upper MOSFET driver. Careful layout,
proper selection of MOSFETs and packaging, as well as the
proper driver can go a long way toward minimizing such
unwanted stress.
• Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
• Avoid routing relatively high impedance nodes (such as
PWM and ENABLE lines) close to high dV/dt UGATE and
PHASE nodes.
PVCC
BOOT
In addition, connecting the thermal pad of the QFN package
to the power ground through multiple vias, or placing a low
noise copper plane (such as power ground) underneath the
SOIC part is recommended. This is to improve heat
dissipation and allow the part to achieve its full thermal
potential.
D
R
HI1
G
Q1
R
LO1
UGATE
PHASE
Upper MOSFET Self Turn-On Effects At Startup
S
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to the
R
=1-2Ω
PH
FIGURE 5. PHASE RESISTOR TO MINIMIZE SERIOUS
NEGATIVE PHASE SPIKE
self-coupling via the internal C
of the MOSFET, the
GD
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging inrush energy.
2
The selection of D -PAK, or D-PAK packaged MOSFETs, is
a much better match (for the reasons discussed) for the
ISL6610A with a phase resistor, as shown in Figure 5. Low-
FN6395.0
November 22, 2006
8
ISL6610, ISL6610A
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (R
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
) across the gate and source of the
–V
UGPH
DS
---------------------------------
⎛
⎜
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎟
⎟
⎠
dV
-------
⋅ R ⋅ C
dV
dt
iss
dt
-------
V
=
⋅ R ⋅ C
1 – e
(EQ. 5)
GS_MILLER
rss
rate of rise, the C /C
ratio, as well as the gate-source
GD GS
threshold of the upper MOSFET. A higher dV/dt, a lower
/C ratio, and a lower gate-source threshold upper
C
= C
+ C
C
= C
C
R = R
+ R
DS GS
iss
GD
GS
rss
GD
UGPH
GI
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ typically sufficient, not affecting normal
performance and efficiency.
VCC
VIN
BOOT
The coupling effect can be roughly estimated with the
following equations, which assume a fixed linear input ramp
and neglect the clamping effect of the body diode of the
upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10MΩ or greater) probe to
ensure a safe design margin.
D
C
BOOT
C
GD
DU
DL
G
UGATE
C
DS
R
GI
C
Q
GS
UPPER
S
PHASE
FIGURE 6. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
FN6395.0
November 22, 2006
9
ISL6610, ISL6610A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.23
1.95
1.95
0.28
0.35
2.25
2.25
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.10
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.10
7, 8
0.65 BSC
-
k
0.25
0.50
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN6395.0
November 22, 2006
10
ISL6610, ISL6610A
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6395.0
November 22, 2006
11
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