ISL6612ACBZA-T [INTERSIL]
Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; 与预POR过压保护先进的同步整流降压MOSFET驱动器
| 型号： | ISL6612ACBZA-T |
| 厂家： | 
Intersil |
| 描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP |
| 文件： | 总12页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6612A, ISL6613A
®
Data Sheet
July 25, 2005
FN9159.4
Advanced Synchronous Rectified Buck
MOSFET Drivers with Pre-POR OVP
Features
• Pin-to-pin Compatible with HIP6601 SOIC family
The ISL6612A and ISL6613A are high frequency MOSFET
drivers specifically designed to drive upper and lower power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with HIP63xx or
ISL65xx Multi-Phase Buck PWM controllers and N-Channel
MOSFETs form complete core-voltage regulator solutions for
advanced microprocessors.
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of r
Conduction Offset Effect
DS(ON)
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
The ISL6612A drives the upper gate to 12V, while the lower
gate can be independently driven over a range from 5V to
12V. The ISL6613A drives both upper and lower gates over
a range of 5V to 12V. This drive-voltage provides the
flexibility necessary to optimize applications involving trade-
offs between gate charge and conduction losses.
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial startup.
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC-DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Briefs TB400 and TB417 for Power Train
Design, Layout Guidelines, and Feedback Compensation
Design
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6612A, ISL6613A
Ordering Information
Ordering Information (Continued)
TEMP.
PKG.
TEMP.
PKG.
PART NUMBER** RANGE (°C)
PACKAGE
8 Ld SOIC
8 Ld SOIC Tape and Reel
0 to 85 8 Ld SOIC (Pb-Free)
DWG. #
PART NUMBER** RANGE (°C)
PACKAGE
DWG. #
M8.15
M8.15
M8.15
M8.15
ISL6612ACB
0 to 85
ISL6613ACBZ*
0 to 85
8 Ld SOIC (Pb-Free)
ISL6612ACB-T
ISL6612ACBZ*
ISL6613ACBZ-T* 8 Ld SOIC Tape and Reel (Pb-Free)
ISL6613AECB 0 to 85 8 Ld EPSOIC
ISL6613AECB-T 8 Ld EPSOIC Tape and Reel
ISL6613AECBZ* 0 to 85 8 Ld EPSOIC (Pb-Free)
ISL6613AECBZ-T* 8 Ld EPSOIC Tape and Reel (Pb-Free)
M8.15
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
L10.3x3
L10.3x3
L10.3x3
L10.3x3
M8.15
M8.15
ISL6612ACBZ-T* 8 Ld SOIC Tape and Reel (Pb-Free)
ISL6612ACBZA* 0 to 85 8 Ld SOIC (Pb-Free)
ISL6612ACBZA-T* 8 Ld SOIC Tape and Reel (Pb-Free)
M8.15
M8.15
L10.3x3
L10.3x3
L10.3x3
L10.3x3
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15B
M8.15
ISL6612ACR
0 to 85
10 Ld 3x3 DFN Tape and Reel
0 to 85 10 Ld 3x3 DFN (Pb-Free)
10 Ld 3x3 DFN
ISL6613AEIB
-40 to +85 8 Ld EPSOIC
ISL6612ACR-T
ISL6612ACRZ*
ISL6613AEIB-T
ISL6613AEIBZ*
8 Ld EPSOIC Tape and Reel
-40 to +85 8 Ld EPSOIC (Pb-Free)
ISL6612ACRZ-T* 10 Ld 3x3 DFN Tape and Reel (Pb-Free)
ISL6612AECB 0 to 85 8 Ld EPSOIC
ISL6612AECB-T 8 Ld EPSOIC Tape and Reel
ISL6612AECBZ* 0 to 85 8 Ld EPSOIC (Pb-Free)
ISL6612AECBZ-T* 8 Ld EPSOIC Tape and Reel (Pb-Free)
ISL6613AEIBZ-T* 8 Ld EPSOIC Tape and Reel (Pb-Free)
ISL6613ACR
0 to 85
10 Ld 3x3 DFN Tape and Reel
0 to 85 10 Ld 3x3 DFN (Pb-Free)
10 Ld 3x3 DFN
ISL6613ACR-T
ISL6613ACRZ*
ISL6613ACRZ-T* 10 Ld 3x3 DFN Tape and Reel (Pb-Free)
ISL6612AEIB
-40 to +85 8 Ld EPSOIC
ISL6613AIB
-40 to +85 8 Ld SOIC
M8.15
ISL6612AEIB-T
ISL6612AEIBZ*
8 Ld EPSOIC Tape and Reel
-40 to +85 8 Ld EPSOIC (Pb-Free)
ISL6613AIB-T
ISL6613AIBZ*
ISL6613AIBZ*-T
ISL6613AIR
8 Ld SOIC Tape and Reel
M8.15
-40 to +85 8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel (Pb-free)
-40 to +85 10 Ld 3x3 DFN
M8.15
ISL6612AEIBZ-T* 8 Ld EPSOIC Tape and Reel (Pb-Free)
L10.3x3
L10.3x3
L10.3x3
L10.3x3
ISL6612AIB
-40 to +85 8 Ld SOIC
M8.15
ISL6612AIB-T
ISL6612AIBZ*
8 Ld SOIC Tape and Reel
-40 to +85 8 Ld SOIC (Pb-free)
ISL6613AIR-T
ISL6613AIRZ*
10 Ld 3x3 DFN Tape and Reel
-40 to +85 10 Ld 3x3 DFN (Pb-Free)
M8.15
M8.15
ISL6612AIBZ*-T 8 Ld SOIC Tape and Reel (Pb-free)
ISL6613AIRZ-T* 10 Ld 3x3 DFN Tape and Reel (Pb-Free)
L10.3x3
L10.3x3
L10.3x3
L10.3x3
M8.15
ISL6612AIR
-40 to +85 10 Ld 3x3 DFN
*Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL6612AIR-T
ISL6612AIRZ*
10 Ld 3x3 DFN Tape and Reel
-40 to +85 10 Ld 3x3 DFN (Pb-Free)
ISL6612AIRZ-T* 10 Ld 3x3 DFN Tape and Reel (Pb-Free)
ISL6613ACB
0 to 85
8 Ld SOIC
Check website for availability.
M8.15
ISL6613ACB-T
8 Ld SOIC Tape and Reel
Pinouts
ISL6612ACB, ISL6612AIB, ISL6613ACB, ISL6613AIB (SOIC)
ISL6612ACR, ISL6612AIR, ISL6613ACR, ISL6613AIR
ISL6612AECB, ISL6612AEIB, ISL6613AECB, ISL6613AEIB
(10L 3X3 DFN)
(EPSOIC)
TOP VIEW
TOP VIEW
1
2
3
4
5
10
9
8
7
6
UGATE
BOOT
PHASE
UGATE
BOOT
PWM
1
2
3
4
8
7
6
5
PHASE
PVCC
VCC
PVCC
N/C
GND
N/C
PWM
GND
GND
VCC
LGATE
GND
LGATE
FN9159.4
2
July 25, 2005
ISL6612A, ISL6613A
Block Diagram
ISL6612A AND ISL6613A
UVCC
BOOT
VCC
UGATE
OTP AND
Pre-POR OVP
FEATURES
+5V
10K
PHASE
PVCC
SHOOT-
THROUGH
PROTECTION
(LVCC)
UVCC = VCC FOR ISL6612A
UVCC = PVCC FOR ISL6613A
PWM
POR/
CONTROL
LOGIC
LGATE
GND
8K
FOR DFN AND EPSOIC-DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
PAD
FN9159.4
July 25, 2005
3
ISL6612A, ISL6613A
Typical Application - 3 Channel Converter Using ISL65xx and ISL6612A Gate Drivers
+12V
+5V TO 12V
BOOT
UGATE
VCC
PVCC
PWM
PHASE
LGATE
ISL6612A
GND
+12V
+5V TO 12V
VCC
+5V
+V
CORE
BOOT
VCC
VFB
COMP
PWM1
PWM2
PWM3
UGATE
PHASE
PVCC
PWM
VSEN
ISL6612A
PGOOD
LGATE
MAIN
GND
CONTROL
ISL65xx
VID
ISEN1
ISEN2
ISEN3
FS
+12V
+5V TO 12V
GND
BOOT
VCC
UGATE
PHASE
PVCC
PWM
ISL6612A
LGATE
GND
FN9159.4
July 25, 2005
4
ISL6612A, ISL6613A
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
Thermal Information
Thermal Resistance
θ
(°C/W)
θ
(°C/W)
JA
JC
SOIC Package (Note 1). . . . . . . . . . . .
EPSOIC Package (Notes 2, 3) . . . . . .
DFN Package (Notes 2, 3). . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
100
N/A
7
7
BOOT Voltage (V
). . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
BOOT-GND
50
Input Voltage (V
). . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V
PWM
48
UGATE . . . . . . . . . . . . . . . . . . . V
- 0.3V
to V
BOOT
to V
PVCC
PVCC
DC
BOOT-GND
+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V
PHASE
DC
BOOT
V
- 3.5V (<100ns Pulse Width, 2µJ) to V
PHASE
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
DC
GND - 5V (<100ns Pulse Width, 2µJ) to V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
to 15V
DC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, V
<36V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . .Class I JEDEC STD
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . .5V to 12V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air.
JA
2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Bias Supply Current
I
I
ISL6612A, f
ISL6613A, f
ISL6612A, f
ISL6613A, f
ISL6612A, f
ISL6613A, f
ISL6612A, f
ISL6613A, f
= 300kHz, V
= 300kHz, V
=12V
=12V
-
-
-
-
-
-
-
-
7.2
4.5
11
5
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
VCC
VCC
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
VCC
VCC
= 1MHz, V
= 1MHz, V
= 12V
= 12V
VCC
VCC
Gate Drive Bias Current
I
I
= 300kHz, V
= 300kHz, V
= 12V
2.5
5.2
7
PVCC
PVCC
PVCC
PVCC
= 12V
= 1MHz, V
= 1MHz, V
= 12V
PVCC
PVCC
= 12V
13
POWER-ON RESET AND ENABLE
VCC Rising Threshold
T
= 0°C to 85°C
9.35
8.35
7.35
6.35
9.80
9.80
7.60
7.60
10.00
10.00
8.00
V
V
V
V
A
VCC Rising Threshold
T
= -40°C to 85°C
= 0°C to 85°C
= -40°C to 85°C
A
VCC Falling Threshold
T
A
VCC Falling Threshold
T
8.00
A
PWM INPUT (See Timing Diagram on Page 7)
Input Current
I
V
V
= 5V
= 0V
-
450
-400
3.00
2.00
-
-
µA
µA
V
PWM
PWM
PWM
-
-
PWM Rising Threshold
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
-
-
PWM Falling Threshold
-
-
V
Typical Three-State Shutdown Window
Three-State Lower Gate Falling Threshold
Three-State Lower Gate Rising Threshold
1.80
2.40
V
-
-
1.50
1.00
-
-
V
V
FN9159.4
5
July 25, 2005
ISL6612A, ISL6613A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
Three-State Upper Gate Rising Threshold
Three-State Upper Gate Falling Threshold
Shutdown Holdoff Time
SYMBOL
TEST CONDITIONS
VCC = 12V
VCC = 12V
MIN
TYP
3.20
2.60
245
26
MAX
UNITS
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSSHD
UGATE Rise Time
t
V
V
V
V
V
V
V
V
V
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
RU
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
LGATE Rise Time
t
18
RL
UGATE Fall Time
t
18
FU
LGATE Fall Time
t
12
FL
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT (Note 4)
t
10
PDHU
t
10
PDHL
t
10
PDLU
t
= 12V, 3nF Load
10
PDLL
t
= 12V, 3nF Load
10
PDTS
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
I
V
= 12V, 3nF Load
-
1.25
2.0
2
-
3.0
-
A
Ω
A
Ω
Ω
A
Ω
A
Ω
U_SOURCE
PVCC
R
150mA Source Current
1.25
U_SOURCE
I
V
= 12V, 3nF Load
PVCC
-
-
U_SINK
Upper Drive Transition Sink Impedance
Upper Drive DC Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
R
70ns With Respect To PWM Falling
150mA Source Current
1.3
1.65
2
2.2
3.0
-
U_SINK_TR
U_SINK_DC
L_SOURCE
R
0.9
-
I
V
= 12V, 3nF Load
PVCC
150mA Source Current
R
0.85
-
1.25
3
2.2
-
L_SOURCE
I
V
= 12V, 3nF Load
L_SINK
PVCC
150mA Sink Current
Lower Drive Sink Impedance
R
0.60
0.80
1.35
L_SINK
NOTE:
4. Guaranteed by design. Not 100% tested in production.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
DFN
SYMBOL
FUNCTION
1
2
1
2
UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in choosing the capacitor value.
-
3, 8
4
N/C
No Connection.
3
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.
4
5
6
7
5
6
7
9
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
VCC
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
PVCC
This pin supplies power to both upper and lower gate drives in ISL6613A; only the lower gate drive in ISL6612A.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
8
9
10
11
PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
FN9159.4
6
July 25, 2005
ISL6612A, ISL6613A
Description
1.5V<PWM<3.2V
1.0V<PWM<2.6V
PWM
t
t
PDLU
PDHU
t
TSSHD
t
PDTS
t
PDTS
t
FU
UGATE
LGATE
t
RU
t
t
FL
RL
t
t
TSSHD
PDLL
t
PDHL
FIGURE 1. TIMING DIAGRAM
Operation
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
Designed for versatility and speed, the ISL6612A and
ISL6613A MOSFET drivers control both high-side and low-
side N-Channel FETs of a half-bridge power train from one
externally provided PWM signal.
These drivers incorporate a unique adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFETs’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated during initial startup;
the upper gate (UGATE) is held low and the lower gate
(LGATE), controlled by the Pre-POR overvoltage protection
circuits, is connected to the PHASE. Once the VCC voltage
surpasses the VCC Rising Threshold (See Electrical
Specifications), the PWM signal takes control of gate
transitions. A rising edge on PWM initiates the turn-off of the
lower MOSFET (see Timing Diagram). After a short
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.2V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the r
DS(ON)
drop in the phase voltage preventing from false detection of the
-0.2V phase level during r conduction period. In the case
propagation delay [t
], the lower gate begins to fall. Typical
PDLL
fall times [t ] are provided in the Electrical Specifications
FL
DS(ON
section. Adaptive shoot-through circuitry monitors the PHASE
of zero current, the UGATE is released after 35ns delay of the
LGATE dropping below 0.5V. During the phase detection, the
disturbance of LGATE’s falling transition on the PHASE node is
blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
voltage and determines the upper gate delay time [t
]. This
PDHU
prevents both the lower and upper MOSFETs from conducting
simultaneously. Once this delay period is complete, the upper
gate drive begins to rise [t ] and the upper MOSFET turns on.
RU
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
] is encountered before the upper
PDLU
gate begins to fall [t ]. Again, the adaptive shoot-through
FU
circuitry determines the lower gate delay time, t
. The
Three-State PWM Input
PDHL
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next section for
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
details). The lower gate then rises [t ], turning on the lower
MOSFET.
RL
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
FN9159.4
7
July 25, 2005
ISL6612A, ISL6613A
This feature helps prevent a negative transient on the output
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q , from the data
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
G
sheet is 10nC at 4.5V (V ) gate-source voltage. Then the
GS
Q
is calculated to be 53nC for UVCC (i.e. PVCC in
GATE
ISL6613A, VCC in ISL6612A) = 12V. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.267µF is required.
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
1.6
1.4
1.2
1.
Power-On Reset (POR) Function
During initial startup, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 9.8V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 7.6V (typically), operation of the driver is
disabled.
0.8
0.6
Q
= 100nC
GATE
0.4
Pre-POR Overvoltage Protection
50nC
0.2
0.0
Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
protection circuits during initial startup. The PHASE is
connected to the gate of the low side MOSFET (LGATE),
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial startup. For
complete protection, the low side MOSFET should have a
gate threshold well below the maximum voltage rating of the
load/microprocessor.
20nC
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
∆V (V)
BOOT_CAP
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6612A and ISL6613A provide the user flexibility in
choosing the gate drive voltage for efficiency optimization.
The ISL6612A upper gate drive is fixed to VCC [+12V], but
the lower drive rail can range from 12V down to 5V
depending on what voltage is applied to PVCC. The
ISL6613A ties the upper and lower drive rails together.
Simply applying a voltage from 5V up to 12V on PVCC sets
both gate drive rail voltages simultaneously.
When VCC drops below its POR level, both gates pull low
and the Pre-POR overvoltage protection circuits are not
activated until VCC resets.
Internal Bootstrap Device
Both drivers feature an internal bootstrap schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F ), the output drive impedance, the
SW
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
125°C. The maximum allowable IC power dissipation for the
SO8 package is approximately 800mW at room temperature,
while the power dissipation capacity in the EPSOIC and DFN
packages, with an exposed heat escape pad, is more than
2W and 1.5W, respectively. Both EPSOIC and DFN
The bootstrap capacitor must have a maximum voltage
rating above UVCC + 5V and its capacitance value can be
chosen from the following equation:
Q
GATE
-------------------------------------
C
≥
BOOT_CAP
∆V
BOOT_CAP
(EQ. 1)
Q
• UVCC
G1
-----------------------------------
Q
=
• N
Q1
GATE
V
GS1
packages are more suitable for high frequency applications.
See Layout Considerations paragraph for thermal transfer
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation
is used to ensure safe operation at the desired frequency for
where Q is the amount of gate charge per upper MOSFET
G1
at V
gate-source voltage and N is the number of
Q1
GS1
control MOSFETs. The ∆V
term is defined as the
BOOT_CAP
allowable droop in the rail of the upper gate drive.
FN9159.4
8
July 25, 2005
ISL6612A, ISL6613A
the selected MOSFETs. The total gate drive power losses
UVCC
BOOT
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively,
D
C
GD
R
HI1
G
C
DS
(EQ. 2)
P
= P
+ P
+ I • VCC
Q
Qg_TOT
P
Qg_Q1
Qg_Q2
2
R
R
LO1
R
GI1
C
G1
Q
• UVCC
GS
G1
Q1
---------------------------------------
=
• F
• N
Qg_Q1
SW
Q1
V
GS1
S
2
PHASE
Q
• LVCC
G2
--------------------------------------
P
=
• F
• N
Qg_Q2
SW
Q2
V
GS2
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
Q
• UVCC • N
Q
• LVCC • N
G2 Q2
G1
Q1
I
=
----------------------------------------------------- + ---------------------------------------------------- • F
+ I
DR
SW
Q
V
V
LVCC
GS1
GS2
D
(EQ. 3)
C
GD
where the gate charge (Q and Q ) is defined at a
G1
G2
R
HI2
G
particular gate to source voltage (V
and V
) in the
GS1
GS2
C
DS
corresponding MOSFET datasheet; I is the driver’s total
Q
R
R
LO2
R
GI2
C
G2
quiescent current with no load at both drive outputs; N
Q1
GS
Q2
and N are number of upper and lower MOSFETs,
Q2
S
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I VCC
Q*
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
resistors (R and R ) and the internal gate resistors
G1 G2
(R
GI1
and R ) of MOSFETs. Figures 3 and 4 show the
GI2
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
P
P
= P
+ P
+ I • VCC
(EQ. 4)
DR
DR_UP
DR_LOW
Q
P
R
R
Qg_Q1
HI1
LO1
---------------------
=
-------------------------------------- + ---------------------------------------
•
DR_UP
2
R
+ R
R
+ R
HI1
EXT1
LO1
EXT1
P
R
R
Qg_Q2
HI2
LO2
---------------------
P
R
=
-------------------------------------- + ---------------------------------------
•
DR_LOW
2
R
+ R
R
+ R
HI2
EXT2
LO2 EXT2
R
N
R
GI1
GI2
= R
+ -------------
R
= R
+ -------------
EXT1
G1
EXT2
G2
N
Q1
Q2
FN9159.4
9
July 25, 2005
ISL6612A, ISL6613A
Dual Flat No-Lead Plastic Package (DFN)
2X
L10.3x3
0.15
C A
2X
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
A
MILLIMETERS
0.15 C
B
SYMBOL
MIN
0.80
NOMINAL
0.90
MAX
1.00
NOTES
A
A1
A3
b
-
-
0.18
1.95
1.55
-
0.05
-
E
0.20 REF
0.23
-
6
0.28
2.05
1.65
5,8
INDEX
AREA
D
3.00 BSC
2.00
-
D2
E
7,8
TOP VIEW
SIDE VIEW
B
A
3.00 BSC
1.60
-
E2
e
7,8
0.10 C
0.08 C
0.50 BSC
-
-
k
0.25
0.30
-
-
L
0.35
0.40
8
C
A3
SEATING
PLANE
N
10
2
Nd
5
3
7
8
Rev. 3 6/04
D2
NOTES:
(DATUM B)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
D2/2
1
2
6
3. Nd refers to the number of terminals on D.
INDEX
AREA
k
NX
E2
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM A)
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
8
N
N-1
e
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
5
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
(Nd-1)Xe
0.10 M C A B
REF.
BOTTOM VIEW
C
L
0.415
NX (b)
(A1)
L
0.200
NX b
NX L
5
e
SECTION "C-C"
TERMINAL TIP
C C
C
FOR ODD TERMINAL/SIDE
FN9159.4
10
July 25, 2005
ISL6612A, ISL6613A
Small Outline Expos ed Pad Plas tic Packages (EPSOIC)
M8.15B
N
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.43
0.03
0.35
0.19
4.80
3.31
MAX
1.68
0.13
0.49
0.25
4.98
3.39
NOTES
A
A1
B
C
D
E
e
0.056
0.001
0.0138
0.0075
0.189
0.150
0.066
0.005
0.0192
0.0098
0.196
0.157
-
1
2
3
-
TOP VIEW
9
-
L
3
SEATING PLANE
A
4
-A-
D
o
0.050 BSC
1.27 BSC
-
h x 45
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.64
-
-C-
5
α
µ
L
6
e
B
A1
C
N
8
8
7
0.10(0.004)
o
o
o
o
0
8
0
8
-
α
P
0.25(0.010) M
SIDE VIEW
C A M B S
-
-
0.094
0.094
-
-
2.387
2.387
11
11
P1
Rev. 2 11/03
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
FN9159.4
11
July 25, 2005
ISL6612A, ISL6613A
Small Outline Plas tic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9159.4
12
July 25, 2005
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