ISL6614ACR-T [INTERSIL]
Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; 与预POR过压保护的双高级同步整流降压MOSFET驱动器
| 型号： | ISL6614ACR-T |
| 厂家： | 
Intersil |
| 描述： | Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP |
| 文件： | 总12页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6614A
®
Data Sheet
July 25, 2005
FN9160.2
Dual Advanced Synchronous Rectified
Buck MOSFET Drivers with Pre-POR OVP
Features
• Pin-to-pin Compatible with HIP6602 SOIC family
The ISL6614A integrates two ISL6613A MOSFET drivers and
is specifically designed to drive two Channel MOSFETs in a
synchronous rectified buck converter topology. These drivers
combined with HIP63xx or ISL65xx Multi-Phase Buck PWM
controllers and N-Channel MOSFETs form complete core-
voltage regulator solutions for advanced microprocessors.
• Quad N-Channel MOSFET Drives for Two Synchronous
Rectified Bridges
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of r
Conduction Offset Effect
DS(ON)
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 3A Sinking Current Capability
The ISL6614A drives both the upper and lower gates
simultaneously over a range from 5V to 12V. This drive-
voltage provides the flexibility necessary to optimize
applications involving trade-offs between gate charge and
conduction losses.
- Fast Rise/Fall Times and Low Propagation Delays
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during startup.
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
The ISL6614A also features a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief 400 and 417 for Power Train Design,
Layout Guidelines, and Feedback Compensation Design
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6614A
Pinouts
Ordering Information
14 LD SOIC
TOP VIEW
TEMP.
PKG.
PART NUMBER RANGE (°C)
PACKAGE
14 Ld SOIC
DWG. #
M14.15
M14.15
ISL6614ACB*
0 to 85
0 to 85
14
13
12
11
10
9
PWM1
PWM2
GND
1
2
3
4
VCC
ISL6614ACBZ*
(See Note)
14 Ld SOIC (Pb-free)
PHASE1
UGATE1
BOOT1
M14.15
ISL6614ACBZA*
(See Note)
0 to 85
14 Ld SOIC (Pb-free)
LGATE1
PVCC
L16.4x4
L16.4x4
ISL6614ACR*
0 to 85
0 to 85
16 Ld 4x4 QFN
BOOT2
5
6
ISL6614ACRZ*
(See Note)
16 Ld 4x4 QFN (Pb-free)
PGND
UGATE2
PHASE2
LGATE2
7
8
M14.15
M14.15
ISL6614AIB*
-40 to 85
-40 to 85
14 Ld SOIC
ISL6614AIBZ*
(See Note)
14 Ld SOIC (Pb-free)
16 LD 4X4 QFN
TOP VIEW
L16.4x4
L16.4x4
ISL6614AIR*
-40 to 85
-40 to 85
16 Ld 4x4 QFN
ISL6614AIRZ*
(See Note)
16 Ld 4x4 QFN (Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
16 15 14 13
GND
1
2
3
4
12 UGATE1
11 BOOT1
LGATE1
PVCC
GND
10
9
BOOT2
PGND
UGATE2
5
6
7
8
FN9160.2
2
July 25, 2005
ISL6614A
ti
Block Diagram
BOOT1
PVCC
VCC
UGATE1
OTP &
PRE-POR OVP
FEATURES
+5V
PHASE1
CHANNEL 1
SHOOT-
THROUGH
PROTECTION
10K
PVCC
PWM1
LGATE1
PGND
8K
PGND
CONTROL
LOGIC
+5V
PVCC
BOOT2
10K
8K
UGATE2
PWM2
GND
PHASE2
SHOOT-
THROUGH
PROTECTION
CHANNEL 2
PVCC
LGATE2
PGND
PAD
FOR ISL6614ACR, THE PAD ON THE BOTTOM SIDE OF
THE QFN PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
FN9160.2
July 25, 2005
3
ISL6614A
Typical Application - 4 Channel Converter Using ISL65xx and ISL6614A Gate Drivers
BOOT1
+12V
VCC
+12V
UGATE1
PHASE1
LGATE1
PVCC
+5V
DUAL
DRIVER
ISL6614A
5V TO 12V
BOOT2
COMP
V
FB
+12V
CC
VSEN
UGATE2
PHASE2
ISEN1
PWM1
PWM1
PWM2
PGOOD
EN
PWM2
ISEN2
LGATE2
PGND
MAIN
CONTROL
ISL65xx
GND
VID
+V
CORE
ISEN3
PWM3
PWM4
FS/DIS
BOOT1
+12V
VCC
+12V
GND
ISEN4
UGATE1
PHASE1
LGATE1
PVCC
DUAL
DRIVER
ISL6614A
5V TO 12V
BOOT2
+12V
UGATE2
PHASE2
PWM1
PWM2
LGATE2
PGND
GND
FN9160.2
4
July 25, 2005
ISL6614A
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
Thermal Information
Thermal Resistance (Typ. Notes 1, 2, 3)
SOIC Package (Note 1) . . . . . . . . . . . .
QFN Package (Notes 2, 3). . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
θ
(°C/W)
90
46
θ
(°C/W)
N/A
9
JA
JC
BOOT Voltage (V
BOOT-GND
). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (V
) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V
PWM
UGATE. . . . . . . . . . . . . . . . . . . V
- 0.3V
to V
+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V
PHASE
DC
BOOT
BOOT
V
- 3.5V (<100ns Pulse Width, 2µJ) to V
PHASE
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
to V
PVCC
DC
GND - 5V (<100ns Pulse Width, 2µJ) to V
PVCC
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
to 15V
DC
BOOT-GND
DC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, V
<36V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air.
JA
2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Bias Supply Current
I
f
f
= 300kHz, V
= 300kHz, V
= 12V
= 12V
-
-
7.1
9.7
-
-
mA
mA
VCC
PWM
PWM
PVCC
PVCC
Gate Drive Bias Current
POWER-ON RESET AND ENABLE
VCC Rising Threshold
I
PVCC
0°C to 85°C
-40°C to 85°C
0°C to 85°C
-40°C to 85°C
9.35
8.35
7.35
6.35
9.80
10.05
10.05
8.00
V
V
V
V
-
7.60
-
VCC Falling Threshold
8.00
PWM INPUT (See Timing Diagram on Page 8)
Input Current
I
V
V
= 5V
= 0V
-
500
-460
3.00
2.00
-
-
µA
µA
V
PWM
PWM
PWM
-
-
PWM Rising Threshold
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
-
-
PWM Falling Threshold
-
-
V
Typical Three-State Shutdown Window
Three-State Lower Gate Falling Threshold
Three-State Lower Gate Rising Threshold
Three-State Upper Gate Rising Threshold
Three-State Upper Gate Falling Threshold
Shutdown Holdoff Time
1.80
2.40
V
-
-
-
-
-
1.50
1.00
3.20
2.60
245
-
-
-
-
-
V
V
V
V
t
ns
TSSHD
FN9160.2
5
July 25, 2005
ISL6614A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
MIN
TYP
26
18
18
12
10
10
10
10
10
MAX
UNITS
ns
UGATE Rise Time
t
V
V
V
V
V
V
V
V
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RU
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
LGATE Rise Time
t
ns
RL
FU
UGATE Fall Time
t
ns
LGATE Fall Time
t
ns
FL
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT (Note 4)
t
t
t
ns
PDHU
t
ns
PDHL
PDLU
ns
t
= 12V, 3nF Load
ns
PDLL
PDTS
= 12V, 3nF Load
ns
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
I
V
= 12V, 3nF Load
-
1.25
2.0
2
-
3.0
-
A
Ω
A
Ω
Ω
A
Ω
A
Ω
U_SOURCE
PVCC
R
150mA Source Current
1.25
U_SOURCE
I
V
= 12V, 3nF Load
PVCC
-
-
U_SINK
Upper Drive Transition Sink Impedance
Upper Drive DC Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
R
70ns With Respect To PWM Falling
150mA Source Current
1.3
1.65
2
2.2
3.0
-
U_SINK_TR
U_SINK_DC
L_SOURCE
R
0.9
-
I
V
= 12V, 3nF Load
PVCC
R
150mA Source Current
0.85
-
1.25
3
2.2
-
L_SOURCE
I
V
= 12V, 3nF Load
L_SINK
PVCC
Lower Drive Sink Impedance
NOTE:
R
150mA Sink Current
0.60
0.80
1.35
L_SINK
4. Guaranteed by design. Not 100% tested in production.
FN9160.2
6
July 25, 2005
ISL6614A
Functional Pin Description
PKG. PIN #
PIN
SOIC QFN
SYMBOL
FUNCTION
1
2
15
16
PWM1
The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during
operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
PWM2
The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during
operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
3
4
5
1
2
3
GND
LGATE1
PVCC
Bias and reference ground. All signals are referenced to this node.
Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
This pin supplies power to both the lower and higher gate drives in ISL6614A. Its operating range is +5V to 12V.
Place a high quality low ESR ceramic capacitor from this pin to GND.
6
-
4
5, 8
6
PGND
N/C
It is the power ground return of both low gate drivers.
No Connection.
7
8
LGATE2
PHASE2
Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
7
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This
pin provides a return path for the upper gate drive.
9
9
UGATE2
BOOT2
Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
10
10
Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this
pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
11
11
BOOT1
Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this
pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
12
13
12
13
UGATE1
PHASE1
Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This
pin provides a return path for the upper gate drive.
14
14
VCC
Connect this pin to a +12V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR
ceramic capacitor from this pin to GND.
-
17
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
FN9160.2
7
July 25, 2005
ISL6614A
Description
1.5V<PWM<3.2V
1.0V<PWM<2.6V
PWM
t
t
PDLU
PDHU
t
TSSHD
t
PDTS
t
PDTS
t
FU
UGATE
LGATE
t
RU
t
t
FL
RL
t
t
TSSHD
PDLL
t
PDHL
FIGURE 1. TIMING DIAGRAM
Operation
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
Designed for versatility and speed, the ISL6614A MOSFET
driver controls both high-side and low-side N-Channel FETs of
two half-bridge power trains from two externally provided PWM
signals.
These drivers incorporate a unique adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFETs’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated during initial startup;
the upper gate (UGATE) is held low and the lower gate
(LGATE), controlled by the Pre-POR overvoltage protection
circuits, is connected to the PHASE. Once the VCC voltage
surpasses the VCC Rising Threshold (See Electrical
Specifications), the PWM signal takes control of gate
transitions. A rising edge on PWM initiates the turn-off of the
lower MOSFET (see Timing Diagram). After a short
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.2V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the r
DS(ON)
drop in the phase voltage preventing from false detection of the
-0.2V phase level during r conduction period. In the
propagation delay [t
], the lower gate begins to fall. Typical
PDLL
fall times [t ] are provided in the Electrical Specifications
FL
DS(ON)
section. Adaptive shoot-through circuitry monitors the PHASE
case of zero current, the UGATE is released after 35ns delay of
the LGATE dropping below 0.5V. During the phase detection,
the disturbance of LGATE’s falling transition on the PHASE
node is blanked out to prevent falsely tripping. Once the
PHASE is high, the advanced adaptive shoot-through circuitry
monitors the PHASE and UGATE voltages during a PWM
falling edge and the subsequent UGATE turn-off. If either the
UGATE falls to less than 1.75V above the PHASE or the
PHASE falls to less than +0.8V, the LGATE is released to turn
on.
voltage and determines the upper gate delay time [t
]. This
PDHU
prevents both the lower and upper MOSFETs from conducting
simultaneously. Once this delay period is complete, the upper
gate drive begins to rise [t ] and the upper MOSFET turns on.
RU
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
] is encountered before the upper
PDLU
gate begins to fall [t ]. Again, the adaptive shoot-through
FU
circuitry determines the lower gate delay time, t
. The
PDHL
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next section for
Three-State PWM Input
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
details). The lower gate then rises [t ], turning on the lower
MOSFET.
RL
FN9160.2
8
July 25, 2005
ISL6614A
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
MOSFETs per channel. The ∆V
term is defined as
BOOT_CAP
the allowable droop in the rail of the upper gate drive.
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q , from the data
G
sheet is 10nC at 4.5V (V ) gate-source voltage. Then the
GS
Q
is calculated to be 53nC for PVCC = 12V. We will
GATE
assume a 200mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.267µF is required.
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
1.6
1.4
1.2
1.
Power-On Reset (POR) Function
During initial startup, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 9.8V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 7.6V (typically), operation of the driver is
disabled.
0.8
0.6
Q
= 100nC
GATE
0.4
Pre-POR Overvoltage Protection
50nC
0.2
0.0
Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
protection circuits during initial startup. The PHASE is
connected to the gate of the low side MOSFET (LGATE),
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial startup. For
complete protection, the low side MOSFET should have a
gate threshold well below the maximum voltage rating of the
load/microprocessor.
20nC
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
∆V (V)
BOOT_CAP
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6614A provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The ISL6614A
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously. Connecting a SOT-23 package
type of dual schottky diodes from the VCC to BOOT1 and
BOOT2 can bypass the internal bootstrap devices of both
upper gates so that the part can operate as a dual ISL6612
driver, which has a fixed VCC (12V typically) on the upper
gate and a programmable lower gate drive voltage.
When VCC drops below its POR level, both gates pull low
and the Pre-POR overvoltage protection circuits are not
activated until VCC resets.
Internal Bootstrap Device
Both drivers feature an internal bootstrap schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F ), the output drive impedance, the
SW
The bootstrap capacitor must have a maximum voltage
rating above UVCC + 5V and its capacitance value can be
chosen from the following equation:
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
125°C. The maximum allowable IC power dissipation for the
SO14 package is approximately 1W at room temperature,
while the power dissipation capacity in the QFN packages,
with an exposed heat escape pad, is around 2W. See Layout
Considerations paragraph for thermal transfer improvement
Q
GATE
-------------------------------------
C
≥
BOOT_CAP
∆V
BOOT_CAP
(EQ. 1)
Q
• PVCC
G1
-----------------------------------
Q
=
• N
Q1
GATE
V
GS1
where Q is the amount of gate charge per upper MOSFET
G1
at V
gate-source voltage and N is the number of control
Q1
GS1
FN9160.2
9
July 25, 2005
ISL6614A
suggestions. When designing the driver into an application, it
PVCC
BOOT
is recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses due to
the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively,
D
C
GD
R
HI1
G
C
DS
R
R
LO1
R
GI1
C
G1
GS
Q1
(EQ. 2)
P
= 2 • P
+ 2 • P
+ I • VCC
Qg_Q2 Q
Qg_TOT
P
Qg_Q1
S
2
PHASE
Q
• PVCC
G1
--------------------------------------
=
=
• F
• N
Qg_Q1
SW
Q1
V
GS1
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
2
Q
• PVCC
G2
--------------------------------------
P
• F
• N
Qg_Q2
SW
Q2
V
GS2
PVCC
D
Q
• N
Q
• N
G1
Q1
G2
Q2
----------------------------- -----------------------------
I
=
+
• F
• 2 + I
SW Q
DR
C
V
V
GD
GS1
GS2
R
HI2
G
(EQ. 3)
C
DS
R
R
LO2
R
GI2
C
G2
where the gate charge (Q and Q ) is defined at a
G1
G2
GS
particular gate to source voltage (V
and V
) in the
Q2
GS1
GS2
corresponding MOSFET datasheet; I is the driver’s total
S
Q
quiescent current with no load at both drive outputs; N
Q1
and N are number of upper and lower MOSFETs,
Q2
respectively; PVCC is the drive voltages for both upper and
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
lower FETs, respectively. The I VCC product is the
Q*
quiescent power of the driver without capacitive load and is
typically 200mW at 300kHz.
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R and R ) and the internal gate resistors
G1
G2
(R
and R ) of MOSFETs. Figures 3 and 4 show the
GI2
GI1
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
P
= 2 • P
+ 2 • P
+ I • VCC
(EQ. 4)
DR
DR_UP
R
DR_LOW
R
Q
P
HI1
LO1
Qg_Q1
-------------------------------------- --------------------------------------- ---------------------
P
=
+
•
DR_UP
R
+ R
R
+ R
EXT1
2
HI1
EXT1
LO1
R
R
P
HI2
LO2
Qg_Q2
-------------------------------------- --------------------------------------- ---------------------
P
R
=
+
•
DR_LOW
R
+ R
R
+ R
EXT2
2
HI2
EXT2
LO2
R
R
N
GI1
GI2
-------------
-------------
= R
+
R
= R +
G2
EXT1
G1
EXT2
N
Q1
Q2
FN9160.2
10
July 25, 2005
ISL6614A
Quad Flat No-Lead Plas tic Package (QFN)
Micro Lead Frame Plas tic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.23
1.95
1.95
0.28
0.35
2.25
2.25
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.10
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.10
7, 8
0.65 BSC
-
k
0.25
0.50
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN9160.2
11
July 25, 2005
ISL6614A
Small Outline Plas tic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9160.2
12
July 25, 2005
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