ISL6615CRZ_技术文档

ISL6615

®

Data Sheet

April 24, 2008

FN6481.0

High-Frequency 6A Sink Synchronous

MOSFET Drivers with Protection Features

Features

• Dual MOSFET Drives for Synchronous Rectified Bridge

The ISL6615 is a high-speed MOSFET driver optimized to

drive upper and lower power N-Channel MOSFETs in a

synchronous rectified buck converter topology. This driver,

combined with an Intersil Digital or Analog multiphase PWM

controller, forms a complete high frequency and high

efficiency voltage regulator.

• Advanced Adaptive Zero Shoot-Through Protection

- Body Diode Detection

- LGATE Detection

- Auto-zero of r

DS(ON)

Conduction Offset Effect

• Adjustable Gate Voltage for Optimal Efficiency

• 36V Internal Bootstrap Schottky Diode

The ISL6615 drives both upper and lower gates over a range

of 4.5V to 13.2V. This drive-voltage provides the flexibility

necessary to optimize applications involving trade-offs

between gate charge and conduction losses.

• Bootstrap Capacitor Overcharging Prevention

• Supports High Switching Frequency (up to 1MHz)

- 6A LGATE Sinking Current Capability

The ISL6615 features 6A typical sink current for the low-side

gate driver, enhancing the lower MOSFET gate hold-down

capability during PHASE node rising edge, preventing power

loss caused by the self turn-on of the lower MOSFET due to

the high dV/dt of the switching node.

- Fast Rise/Fall Times and Low Propagation Delays

• Support 3.3V PWM Input logic

• Tri-State PWM Input for Safe Output Stage Shutdown

• Tri-State PWM Input Hysteresis for Applications with

Power Sequencing Requirement

An advanced adaptive zero shoot-through protection is

integrated to prevent both the upper and lower MOSFETs

from conducting simultaneously and to minimize the dead

time. The ISL6615 includes an overvoltage protection

feature operational before VCC exceeds its turn-on

threshold, at which the PHASE node is connected to the

gate of the low side MOSFET (LGATE). The output voltage

of the converter is then limited by the threshold of the low

side MOSFET, which provides some protection to the load if

the upper MOSFET(s) is shorted.

• Pre-POR Overvoltage Protection

• VCC Undervoltage Protection

• Expandable Bottom Copper PAD for Better Heat

Spreading

• Dual Flat No-Lead (DFN) Package

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile

The ISL6615 also features an input that recognizes a

high-impedance state, working together with Intersil

multiphase PWM controllers to prevent negative transients

on the controlled output voltage when operation is

suspended. This feature eliminates the need for the Schottky

diode that may be utilized in a power system to protect the

load from negative output voltage damage.

• Pb-Free (RoHS Compliant)

Applications

• Optimized for POL DC/DC Converters for IBA Systems

• Core Regulators for Intel® and AMD® Microprocessors

• High Current Low-Profile DC/DC Converters

• High Frequency and High Efficiency VRM and VRD

• Synchronous Rectification for Isolated Power Supplies

Related Literature

Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

Technical Brief TB389 “PCB Land Pattern Design and

Surface Mount Guidelines for QFN Packages”

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6615

Ordering Information

PART NUMBER

(Note)

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

PART MARKING

6615 CBZ

ISL6615CBZ*

ISL6615CRZ*

ISL6615IBZ*

ISL6615IRZ*

0 to +70

8 Ld SOIC

M8.15

6615

10 Ld 3x3 DFN

8 Ld SOIC

L10.3x3

M8.15

6615 IBZ

615I

-40 to +70

10 Ld 3x3 DFN

L10.3x3

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

Pinouts

ISL6615

(8 LD SOIC)

TOP VIEW

ISL6615

(10 LD 3x3 DFN)

TOP VIEW

UGATE

BOOT

PWM

1

2

3

4

8

7

6

5

PHASE

PVCC

VCC

1

2

3

4

5

10

9

PHASE

BOOT

N/C

PVCC

N/C

GND

8

7

GND

LGATE

PWM

VCC

6

LGATE

GND

RECOMMEND TO CONNECT PIN 3 TO GND AND PIN 8 TO PVCC

Block Diagram

ISL6615

(UVCC)

BOOT

VCC

UGATE

PRE-POR OVP

FEATURES

+5V

PHASE

(LVCC)

SHOOT-

THROUGH

13.6k

PVCC

PROTECTION

UVCC = PVCC

PWM

POR/

CONTROL

LOGIC

LGATE

GND

6.4k

SUBSTRATE RESISTANCE

FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF

PAD

THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.

FN6481.0

April 24, 2008

2

ISL6615

Absolute Maximum Ratings

Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

Thermal Resistance

θ

(°C/W)

θ

(°C/W)

JC

JA

SOIC Package (Note 1) . . . . . . . . . . . .

DFN Package (Notes 2, 3). . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

100

48

N/A

7

BOOT Voltage (V

). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V

) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V

BOOT-GND

Input Voltage (V

PWM

UGATE. . . . . . . . . . . . . . . . . . . V

- 0.3V

to V

+ 0.3V

PHASE

DC

BOOT

V

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V

to V

DC

PVCC

GND - 5V (<100ns Pulse Width, 2µJ) to V

PVCC

PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V

to 15V

< 36V))

DC

Recommended Operating Conditions

GND - 8V (<400ns, 20µJ) to 30V (<200ns, V

BOOT-GND

Ambient Temperature Range

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD

ISL6615CRZ, ISL6615CBZ . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6615IRZ, ISL6615IBZ. . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . . +125°C

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V ±10%

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air.

JA

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,

unless otherwise specified. Temperature limits established by characterization and are not production

tested.

PARAMETER

VCC SUPPLY CURRENT

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Bias Supply Current

I

f

= 300kHz, V

= 12V

-

4.5

8

-

mA

VCC

PWM

VCC

Gate Drive Bias Current

I

= 12V

PVCC

POWER-ON RESET AND ENABLE

VCC Rising Threshold

6.1

4.7

6.4

5.0

6.7

5.3

V

VCC Falling Threshold

PWM INPUT (See “TIMING DIAGRAM” on page 6)

Input Current

I

V

= 3.3V

= 0V

-

365

-350

1.70

1.30

-

µA

V

PWM

-

PWM Rising Threshold (Note 4)

PWM Falling Threshold (Note 4)

Typical Tri-State Shutdown Window

Tri-State Lower Gate Falling Threshold

Tri-State Lower Gate Rising Threshold

Tri-State Upper Gate Rising Threshold

Tri-State Upper Gate Falling Threshold

Shutdown Holdoff Time

VCC = 12V

-

V

1.32

1.82

V

-

1.18

0.76

2.36

1.96

65

-

V

t

ns

TSSHD

UGATE Rise Time (Note 4)

t

V

= 12V, 3nF Load, 10% to 90%

= 12V, 3nF Load, 90% to 10%

13

RU

PVCC

LGATE Rise Time (Note 4)

t

10

RL

FU

UGATE Fall Time (Note 4)

t

10

LGATE Fall Time (Note 4)

t

10

FL

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April 24, 2008

4

ISL6615

Electrical Specifications Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,

unless otherwise specified. Temperature limits established by characterization and are not production

tested. (Continued)

PARAMETER

UGATE Turn-On Propagation Delay (Note 4)

LGATE Turn-On Propagation Delay (Note 4)

UGATE Turn-Off Propagation Delay (Note 4)

LGATE Turn-Off Propagation Delay (Note 4)

LG/UG Tri-State Propagation Delay (Note 4)

OUTPUT (Note 4)

SYMBOL

TEST CONDITIONS

= 12V, 3nF Load, Adaptive

= 12V, 3nF Load

MIN

TYP

10

MAX

UNITS

ns

t

V

-

PDHU

PVCC

t

10

ns

PDHL

PDLU

t

10

ns

t

= 12V, 3nF Load

10

ns

PDLL

PDTS

t

= 12V, 3nF Load

10

ns

Upper Drive Source Current

I

V

= 12V, 3nF Load

-

2.5

1

-

A

Ω

A

Ω

A

Ω

A

Ω

U_SOURCE

PVCC

Upper Drive Source Impedance

Upper Drive Sink Current

R

150mA Source Current

U_SOURCE

I

V

= 12V, 3nF Load

4

U_SINK

PVCC

150mA Sink Current

V = 12V, 3nF Load

Upper Drive Sink Impedance

Lower Drive Source Current

R

0.8

4

U_SINK

L_SOURCE

I

PVCC

150mA Source Current

Lower Drive Source Impedance

Lower Drive Sink Current

R

0.7

6

L_SOURCE

I

V

= 12V, 3nF Load

L_SINK

PVCC

Lower Drive Sink Impedance

NOTE:

R

150mA Sink Current

0.45

L_SINK

4. Limits established by characterization and are not production tested.

Functional Pin Description

PACKAGE PIN #

SOIC

DFN

SYMBOL

FUNCTION

1

2

1

2

UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.

BOOT

Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the “TIMING

DIAGRAM” on page 6 under Description for guidance in choosing the capacitor value.

-

3, 8

4

N/C

No Connection. Recommend to connect pin 3 to GND and pin 8 to PVCC.

3

PWM

The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see

the “TIMING DIAGRAM” on page 6 section under Description for further details. Connect this pin to the PWM output of

the controller.

4

5

6

7

5

6

7

9

GND

Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.

LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.

VCC

Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.

PVCC

This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high

quality low ESR ceramic capacitor from this pin to GND.

8

9

10

11

PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides

a return path for the upper gate drive.

PAD

Connect this pad to the power ground plane (GND) via thermally enhanced connection.

FN6481.0

April 24, 2008

5

ISL6615

Description

1.18V < PWM < 2.36V

0.76V < PWM < 1.96V

PWM

t

PDLU

PDHU

t

TSSHD

t

PDTS

t

PDTS

t

FU

UGATE

LGATE

t

RU

t

FL

RL

t

TSSHD

PDLL

t

PDHL

FIGURE 1. TIMING DIAGRAM

Operation

Advanced Adaptive Zero Shoot-through Dead-time

Control

Designed for versatility and speed, the ISL6615 MOSFET

driver controls both high-side and low-side N-Channel FETs

of a half-bridge power train from one externally provided

PWM signal.

The ISL6615 driver incorporates a unique adaptive

dead-time control technique to minimize dead-time, resulting

in high efficiency from the reduced freewheeling time of the

lower MOSFETs’ body-diode conduction, and to prevent the

upper and lower MOSFETs from conducting simultaneously.

This is accomplished by ensuring the rising gate turns on its

MOSFET with minimum and sufficient delay after the other

has turned off.

Prior to VCC exceeding its POR level, the Pre-POR

overvoltage protection function is activated during initial

start-up; the upper gate (UGATE) is held low and the lower

gate (LGATE), controlled by the Pre-POR overvoltage

protection circuits, is connected to the PHASE. Once the

VCC voltage surpasses the VCC Rising Threshold (see

“Electrical Specifications” on page 4), the PWM signal takes

control of gate transitions. A rising edge on PWM initiates

the turn-off of the lower MOSFET (see Figure 1). After a

short propagation delay [t

Typical fall times [t ] are provided in the “Electrical

Specifications” on page 4. Adaptive shoot-through circuitry

monitors the LGATE voltage and determines the upper gate

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it drops below 1.75V. Prior to reaching this

level, there is a 25ns blanking period to protect against

sudden dips in the LGATE voltage. Once 1.75V is reached

the UGATE is released to rise after 20ns of propagation

delay. Once the PHASE is high, the adaptive shoot-through

circuitry monitors the PHASE and UGATE voltages during

PWM falling edge and subsequent UGATE turn-off. If

PHASE falls to less than +0.8V, the LGATE is released to

turn on after 10ns of propagation delay. If the

], the lower gate begins to fall.

PDLL

FL

delay time [t ]. This prevents both the lower and upper

MOSFETs from conducting simultaneously. Once this delay

PDHU

period is complete, the upper gate drive begins to rise [t

and the upper MOSFET turns on.

]

UGATE-PHASE falls to less than 1.75V and after 40ns of

propagation delay, LGATE is released to rise.

RU

A falling transition on PWM results in the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

Tri-state PWM Input

A unique feature of these drivers and other Intersil drivers is

the addition of a shutdown window to the PWM input. If the

PWM signal enters and remains within the shutdown window

for a set holdoff time, the driver outputs are disabled and

both MOSFET gates are pulled and held low. The shutdown

state is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the “Electrical Specifications” on

page 4 determine when the lower and upper gates are

enabled.

propagation delay [t

] is encountered before the upper

PDLU

gate begins to fall [t ]. Again, the adaptive shoot-through

FU

circuitry determines the lower gate delay time, t

. The

PDHL

PHASE voltage and the UGATE voltage are monitored, and

the lower gate is allowed to rise after PHASE drops below a

level or the voltage of UGATE to PHASE reaches a level

depending upon the current direction (see the following

section titled “Advanced Adaptive Zero Shoot-through

Dead-time Control” for details). The lower gate then rises

[t ], turning on the lower MOSFET.

RL

This feature helps prevent a negative transient on the output

voltage when the output is shut down, eliminating the

FN6481.0

April 24, 2008

6

ISL6615

Schottky diode that is used in some systems for protecting

the load from reversed output voltage events.

Q

is calculated to be 53nC for PVCC = 12V. We will

GATE

assume a 200mV droop in drive voltage over the PWM

cycle. We find that a bootstrap capacitance of at least

0.267µF is required. The next larger standard value

capacitance is 0.33µF. A good quality ceramic capacitor is

recommended.

In addition, more than 400mV hysteresis also incorporates

into the Tri-state shutdown window to eliminate PWM input

oscillations due to the capacitive load seen by the PWM

input through the body diode of the controller’s PWM output

when the power-up and/or power-down sequence of bias

supplies of the driver and PWM controller are required.

1.6

1.4

1.2

1.0

0.8

0.6

Power-On Reset (POR) Function

During initial start-up, the VCC voltage rise is monitored.

Once the rising VCC voltage exceeds 6.4V (typically),

operation of the driver is enabled and the PWM input signal

takes control of the gate drives. If VCC drops below the

falling threshold of 5.0V (typically), operation of the driver is

disabled.

Q

= 100nC

GATE

0.4

Pre-POR Overvoltage Protection

50nC

0.2

0.0

Prior to VCC exceeding its POR level, the upper gate is held

low and the lower gate is controlled by the overvoltage

protection circuits. The upper gate driver is powered from

PVCC and will be held low when a voltage of 2.75V or higher

is present on PVCC as VCC surpasses its POR threshold.

The PHASE is connected to the gate of the low side

MOSFET (LGATE), which provides some protection to the

microprocessor if the upper MOSFET(s) is shorted during

start-up, normal, or shutdown conditions. For complete

protection, the low side MOSFET should have a gate

threshold well below the maximum voltage rating of the

load/microprocessor.

20nC

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

ΔV (V)

BOOT_CAP

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

Gate Drive Voltage Versatility

The ISL6615 provides the user with flexibility in choosing the

gate drive voltage for efficiency optimization. The ISL6615

ties the upper and lower drive rails together. Simply applying

a voltage from +4.5V up to 13.2V on PVCC sets both gate

drive rail voltages simultaneously, while VCC’s operating

range is from +6.8V up to 13.2V.

Internal Bootstrap Device

Both drivers feature an internal bootstrap Schottky diode.

Simply adding an external capacitor across the BOOT and

PHASE pins completes the bootstrap circuit. The bootstrap

function is also designed to prevent the bootstrap capacitor

from overcharging due to the large negative swing at the

trailing-edge of the PHASE node. This reduces voltage

stress on the boot to phase pins.

Power Dissipation

Package power dissipation is mainly a function of the

switching frequency (F ), the output drive impedance, the

SW

external gate resistance, and the selected MOSFET’s

internal gate resistance and total gate charge. Calculating

the power dissipation in the driver for a desired application is

critical to ensure safe operation. Exceeding the maximum

allowable power dissipation level will push the IC beyond the

maximum recommended operating junction temperature of

+125°C. The maximum allowable IC power dissipation for

the SO8 package is approximately 800mW at room

temperature, while the power dissipation capacity in the DFN

package, with an exposed heat escape pad, is more than

1.5W. The DFN package is more suitable for high frequency

applications. See “Layout Considerations” on page 8 for

thermal transfer improvement suggestions. When designing

the driver into an application, it is recommended that the

following calculation is used to ensure safe operation at the

desired frequency for the selected MOSFETs. The total gate

drive power losses due to the gate charge of MOSFETs and

the driver’s internal circuitry and their corresponding average

driver current can be estimated with Equations 2 and 3,

respectively.

The bootstrap capacitor must have a maximum voltage

rating above PVCC + 5V and its capacitance value can be

chosen from Equation 1:

Q

GATE

-------------------------------------

C

≥

BOOT_CAP

ΔV

BOOT_CAP

(EQ. 1)

Q

• PVCC

G1

-----------------------------------

Q

=

• N

Q1

GATE

V

GS1

where Q is the amount of gate charge per upper MOSFET at

G1

V

gate-source voltage and N is the number of control

GS1

MOSFETs. The ΔV

Q1

term is defined as the allowable

BOOT_CAP

droop in the rail of the upper gate drive.

As an example, suppose two IRLR7821 FETs are chosen as

the upper MOSFETs. The gate charge, Q , from the data

G

sheet is 10nC at 4.5V (V ) gate-source voltage. Then the

GS

FN6481.0

April 24, 2008

7

ISL6615

PVCC

BOOT

D

(EQ. 2)

P

= P

+ P

+ I • VCC

Q

Qg_TOT

P

Qg_Q1

Qg_Q2

2

C

GD

Q

• PVCC

G1

R

--------------------------------------

=

• F

• N

G

HI1

Qg_Q1

SW

Q1

V

C

DS

GS1

R

LO1

R

GI1

C

G1

2

Q

• PVCC

G2

GS

--------------------------------------

P

=

• F

• N

Q1

Qg_Q2

Q2

V

GS2

S

PHASE

Q

• PVCC • N

Q

• PVCC • N

G2 Q2

⎛

⎜

⎝

⎞

⎟

⎠

G1

Q1

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

----------------------------------------------------- -----------------------------------------------------

I

=

+

• F

+ I

SW Q

DR

V

GS2

GS1

(EQ. 3)

where the gate charge (Q and Q ) is defined at a

G1

G2

PVCC

particular gate to source voltage (V

and V

) in the

GS1

GS2

corresponding MOSFET datasheet; I is the driver’s total

D

Q

quiescent current with no load at both drive outputs; N

and N are the number of upper and lower MOSFETs,

Q2

respectively; PVCC is the drive voltage for both upper and

Q1

C

R

GD

R

HI2

G

C

DS

lower FETs. The I *VCC product is the quiescent power of

R

Q

LO2

R

GI2

C

G2

the driver without capacitive load and is typically 200mW at

300kHz and VCC = PVCC = 12V.

GS

Q2

S

The total gate drive power losses are dissipated among the

resistive components along the transition path. The drive

resistance dissipates a portion of the total gate drive power

losses, the rest will be dissipated by the external gate

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

resistors (R and R ) and the internal gate resistors

G1 G2

Application Information

(R

GI1

and R ) of MOSFETs. Figures 3 and 4 show the

GI2

typical upper and lower gate drives turn-on transition path.

The power dissipation on the driver can be roughly

estimated, as shown in Equation 4.

Layout Considerations

The parasitic inductances of the PCB and of the power

devices’ packaging (both upper and lower MOSFETs) can

cause serious ringing, exceeding the device’s absolute

maximum ratings. A good layout helps reduce the ringing on

the switching node (PHASE) and significantly lowers the

stress applied to the output drives. The following advice is

meant to lead to an optimized layout and performance:

P

= P

+ P

+ I • VCC

(EQ. 4)

DR

DR_UP

DR_LOW

Q

P

R

⎛

⎞

Qg_Q1

HI1

LO1

-------------------------------------- --------------------------------------- ---------------------

P

=

+

•

⎜

⎝

⎟

⎠

DR_UP

R

+ R

R

+ R

EXT1

2

HI1

EXT1

LO1

P

R

⎛

⎜

⎝

⎞

Qg_Q2

HI2

LO2

• Keep decoupling loops (VCC-GND, PVCC-GND and

BOOT-PHASE) short and wide (at least 25 mils). Avoid

using vias on decoupling components other than their

ground terminals, which should be on a copper plane with

at least two vias.

-------------------------------------- --------------------------------------- ---------------------

P

R

=

+

•

⎟

DR_LOW

R

+ R

R

+ R

EXT2

2

⎠

HI2

EXT2

LO2

R

GI1

GI2

-------------

= R

+

R

= R +

G2

EXT1

G1

EXT2

N

Q1

Q2

• Minimize trace inductance, especially on low-impedance

lines. All power traces (UGATE, PHASE, LGATE, GND,

PVCC, VCC, GND) should be short and wide (at least

25 mils). Try to place power traces on a single layer,

otherwise, two vias on interconnection are preferred

where possible. For no connection (NC) pins on the QFN

part, connect it to the adjacent net (LGATE2/PHASE2) can

reduce trace inductance.

FN6481.0

April 24, 2008

8

ISL6615

• Shorten all gate drive loops (UGATE-PHASE and

LGATE-GND) and route them closely spaced.

C

/C ratio, and a lower gate-source threshold upper

DS GS

FET will require a smaller resistor to diminish the effect of

the internal capacitive coupling. For most applications, the

integrated 20kΩ typically sufficient, not affecting normal

performance and efficiency.

• Minimize the inductance of the PHASE node. Ideally, the

source of the upper and the drain of the lower MOSFET

should be as close as thermally allowable.

The coupling effect can be roughly estimated with the

formulas in Equation 5, which assume a fixed linear input

ramp and neglect the clamping effect of the body diode of

the upper drive and the bootstrap capacitor. Other parasitic

components such as lead inductances and PCB

capacitances are also not taken into account. These

equations are provided for guidance purpose only.

Therefore, the actual coupling effect should be examined

using a very high impedance (10MΩ or greater) probe to

ensure a safe design margin.

• Minimize the current loop of the output and input power

trains. Short the source connection of the lower MOSFET

to ground as close to the transistor pin as feasible. Input

capacitors (especially ceramic decoupling) should be

placed as close to the drain of upper and source of lower

MOSFETs as possible.

• Avoid routing relatively high impedance nodes (such as

PWM and ENABLE lines) close to high dV/dt UGATE and

PHASE nodes.

In addition, for heat spreading, place copper underneath the

IC whether it has an exposed pad or not. The copper area

can be extended beyond the bottom area of the IC and/or

connected to buried power ground plane(s) with thermal

vias. This combination of vias for vertical heat escape,

extended copper plane, and buried planes for heat

–V

DS

⎛

⎜

⎝

⎞

---------------------------------

dV

⎟

⎠

-------

⋅ R ⋅ C

dV

dt

iss

dt

-------

V

=

⋅ R ⋅ C

1 – e

(EQ. 5)

GS_MILLER

rss

C

= C

+ C

C

= C

spreading allows the IC to achieve its full thermal potential.

R = R

+ R

iss

GD

GS

rss

GD

UGPH

GI

Upper MOSFET Self Turn-On Effects at Start-up

Should the driver have insufficient bias voltage applied, its

outputs are floating. If the input bus is energized at a high

dV/dt rate while the driver outputs are floating, due to the

PVCC

VIN

BOOT

C

D

BOOT

C

GD

self-coupling via the internal C

of the MOSFET, the

GD

UGATE could momentarily rise up to a level greater than the

threshold voltage of the MOSFET. This could potentially turn

on the upper switch and result in damaging inrush energy.

Therefore, if such a situation (when input bus powered up

before the bias of the controller and driver is ready) could

conceivably be encountered, it is a common practice to

DU

DL

G

UGATE

C

DS

R

GI

C

Q

GS

UPPER

S

PHASE

place a resistor (R

) across the gate and source of the

UGPH

upper MOSFET to suppress the Miller coupling effect. The

value of the resistor depends mainly on the input voltage’s

FIGURE 5. GATE-TO-SOURCE RESISTOR TO REDUCE

UPPER MOSFET MILLER COUPLING

rate of rise, the C /C

ratio, as well as the gate-source

GD GS

threshold of the upper MOSFET. A higher dV/dt, a lower

FN6481.0

April 24, 2008

9

ISL6615

Dual Flat No-Lead Plastic Package (DFN)

2X

L10.3x3

0.15

C A

2X

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

D

A

MILLIMETERS

0.15 C

B

SYMBOL

MIN

0.80

NOMINAL

0.90

MAX

1.00

NOTES

A

A1

A3

b

-

0.18

1.95

1.55

-

0.05

-

E

0.20 REF

0.23

-

6

0.28

2.05

1.65

5,8

INDEX

AREA

D

3.00 BSC

2.00

-

D2

E

7,8

TOP VIEW

B

A

3.00 BSC

1.60

-

E2

e

7,8

0.10 C

0.08 C

0.50 BSC

-

k

0.25

0.30

-

L

0.35

0.40

8

SIDE VIEW

C

A3

SEATING

PLANE

N

10

2

Nd

5

3

7

8

Rev. 3 6/04

D2

NOTES:

(DATUM B)

1. Dimensioning and trancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

D2/2

1

2

6

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

INDEX

AREA

k

NX

E2

(DATUM A)

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

E2/2

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

NX L

8

N

N-1

e

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

NX b

5

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

(Nd-1)Xe

0.10 M C A B

REF.

BOTTOM VIEW

C

L

0.415

NX (b)

(A1)

L

0.200

NX b

NX L

5

e

SECTION "C-C"

TERMINAL TIP

FOR ODD TERMINAL/SIDE

C C

C

FN6481.0

April 24, 2008

10

ISL6615

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerances per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6481.0

April 24, 2008

11


型号：	ISL6615CRZ
厂家：	Intersil
描述：	High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features 驱动光电二极管接口集成电路驱动器
文件：	总11页 (文件大小：233K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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