ISL6721AB [INTERSIL]
Flexible Single Ended Current Mode PWM Controller; 灵活的单端电流模式PWM控制器
| 型号： | ISL6721AB |
| 厂家： | 
Intersil |
| 描述： | Flexible Single Ended Current Mode PWM Controller |
| 文件： | 总20页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6721
®
Data Sheet
July 2004
FN9110.2
Flexible Single Ended Current Mode PWM
Controller
Features
• 1A MOSFET Gate Driver
The ISL6721 is a low power, single-ended pulse width
modulating (PWM) current mode controller designed for a
wide range of DC-DC conversion applications including
boost, flyback, and isolated output configurations. Peak
current mode control effectively handles power transients
and provides inherent over-current protection. Other features
include a low power mode where the supply current drops to
less than 200µA during over voltage and over current
shutdown faults.
• 100µA Startup Current
• Fast Transient Response with Peak Current Mode Control
• Adjustable Switching Frequency up to 1MHz
• Bi-Directional Synchronization
• Low Power Disable Mode
• Delayed Restart from OV and OC Shutdown Faults
• Adjustable Slope Compensation
• Adjustable Soft Start
This advanced BiCMOS design features low operating
current, adjustable operating frequency up to 1MHz,
adjustable soft-start, and a bi-directional SYNC signal that
allows the oscillator to be locked to an external clock for
noise sensitive applications.
• Adjustable Over Current Shutdown Delay
• Adjustable UV and OV Monitors
• Leading Edge Blanking
Ordering Information
• Integrated Thermal Shutdown
TEMP. RANGE
PKG.
DWG. #
o
• 1% Tolerance voltage Reference
• Pb-free available
PART NUMBER
( C)
PACKAGE
ISL6721AB
-40 to 105
-40 to 105
16 Ld SOIC
M16.15
M16.15
ISL6721ABZ
(See Note)
16 Ld SOIC
(Pb-free)
Applications
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
ISL6721AV
-40 to 105
-40 to 105
16 Ld TSSOP M16.173
ISL6721AVZ
(See Note)
16 Ld TSSOP M16.173
(Pb-free)
Add “-T” suffix to part number for tape and reel packaging.
• Industrial Power Systems
• Isolated Buck and Flyback Regulators
• Boost Regulators
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
ISL6721 (SOIC, TSSOP)
TOP VIEW
GATE
ISENSE
SYNC
SLOPE
UV
1
2
3
4
5
6
7
8
16 VC
15 PGND
14 VCC
13 VREF
12 LGND
11 SS
OV
10 COMP
RTCT
ISET
9
FB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2004. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6721
Functional Block Diagram
VREF
5.00 V
1 %
VCC
VREF
START/STOP
SOFTSTART
CHARGE 70 µA
CURRENT
UV COMPARATOR
+
-
ENABLE
ON
+
-
BG
SS CHARGE
SS
15 µA
LGND
VOLTAGE CLAMP
THERMAL
OVERCURRENT
SHUTDOWN
DELAY
PROTECTION
25 µA
SS CHARGED
+
-
RESTART
DELAY
4.375V
ISET
ON
0.8
ISENSE
S
R
Q
Q
5K
-
+
OC DETECT
+
+
VREF
Σ
53 µA
0.1
OVERCURRENT
COMPARATOR
Q
Q
100mV
OC LATCH
SLOPE
50 µS
RETRIGGERABLE
ONE SHOT
-
+
SS LOW
270mV
SS LOW
COMPARATOR
FAULT
LATCH
SS
SS CLAMP
S
Q
+
-
COMP
VFB
R
Q
PWM
VREF
SET DOMINANT
COMPARATOR
+
-
ERROR
VREF
UV COMPARATOR
2.5V
AMPLIFIER
+
-
4.65V
-
+
START
BG
1/3
100nS
BLANKING
OV
UV
+
-
VREF
2.50V
1.45V
-
+
20K
3.0V
1.5V
12K
BLANKING
COMPARATOR
3.0V
ON
-
+
30K
OSCILLATOR
COMPARATOR
VC
S
R
Q
Q
-
+
Bi-Directional
RTCT
Synchronization
1mA
ON
GATE
OSC IN
VREF
36K
CLK OUT
+
-
NO EXT SYNC
4V
2V
-
+
EXT SYNC BLANKING
PGND
SYNC IN
VREF
SYNC OUT
100
SYNC
4.5K
2
ISL6721
Typical Application - 48V Input Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A
SP1
SP2
CR5
T1
+3.3V
+1.8V
ISOLATION
XFMR
C21
+
C15
+ C16
R21
VIN+ P9
C18
R24
CR4
+
C22
C19
+
C20
C17
C2
CR2
C5
RETURN
CR6
R1
R2
R16
R17
R19
36-75V
R18
C6
C1
C3
TP1
U2
Q1
C14
R4
R3
R15
R22
C13
R23
C4
U3
VIN-
R20
TP2
R25
U4
Q2
VC
PGND
VCC
D1
GATE
TP3
ISENSE
SYNC
SYNC
R14
VREF
SLOPE
LGND
SS
UV
OV
R5
TP4
R26
R6
TP5
RTCT
ISET
COMP
VFB
D2
R27
Q3
C12
R8
C11
R10
C7
C8
C9
VR1
R12
R7
R13
R11
R9
C10
3
ISL6721
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage, V
CC,
V
. . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
Thermal Resistance Junction to Ambient (Typical)
θ
( C/W)
C
JA
GATE . . . . . . . . . . . . . . . . GND - 0.3V to Gate Output Limit Voltage
PGND to LGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.3V
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
ESD Classification
16 Lead SOIC (Note 1) . . . . . . . . . . . . . . . . . . . . . .
16 Lead TSSOP (Note 1). . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . -55 C to 150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
80
105
o
o
o
o
o
(SOIC, TSSOP - Lead Tips Only)
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1250V
Operating Conditions
Temperature Range
ISL6721Ax . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 105 C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9-18 VDC
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
o
schematic. 9V < V
= V < 20V ±10%, Rt = 11kΩ, Ct = 330 pF, T = -40 to 105 C (Note 3), Typical values are
CC
C
A
o
at T = 25 C
A
PARAMETER
UNDER VOLTAGE LOCKOUT
START Threshold
TEST CONDITIONS
MIN
TYP
MAX
UNITS
7.95
8.25
7.70
0.55
100
200
4.5
8.55
8.20
1.00
175
V
V
STOP Threshold
7.40
Hysteresis
0.50
V
Start-Up Current, I
Vcc < START Threshold
-
-
-
-
µA
µA
mA
mA
CC
OC/OV Fault Operating Current, I
300
CC
Operating Current, I
10.0
12.0
CC
Operating Supply Current, I
REFERENCE VOLTAGE
Overall Accuracy
Includes 1nF GATE loading
8.0
C
o
Line, load, 0 - 105 C
4.95
4.90
5.00
5.00
5.05
5.05
V
o
Line, load, -40 - 105 C
o
Long Term Stability
Fault Voltage
T = 125 C, 1000 hours (Note 5)
A
-
5
4.65
4.80
165
-
-
4.75
4.95
250
-
mV
V
4.50
4.65
75
VREF Good Voltage
Hysteresis
V
mV
mA
mA
Operational Current
Current Limit
-10
-20
-
-
CURRENT SENSE
Input Impedance
Offset Voltage
-
5
0.10
-
-
kΩ
V
0.08
0
0.11
1.5
Input Voltage Range
Blanking Time
V
(Note 5)
30
60
100
0.81
ns
V/V
Gain, A
0.77
0.79
CS
4
ISL6721
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
o
schematic. 9V < V
= V < 20V ±10%, Rt = 11kΩ, Ct = 330 pF, T = -40 to 105 C (Note 3), Typical values are
CC
C
A
o
at T = 25 C (Continued)
A
PARAMETER
ERROR AMPLIFIER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Open Loop Voltage Gain
Gain-Bandwidth Product
Reference Voltage Initial Accuracy
Reference Voltage
(Note 5)
(Note 5)
60
-
90
15
-
-
dB
MHz
V
o
V
V
= COMP, T = 25 C (Note 5)
A
2.465
2.44
0.31
0.51
-2
2.515
2.515
0.33
0.75
0.1
2.565
2.590
0.35
0.88
2
FB
= COMP
o
V
FB
COMP to PWM Gain, A
COMP to PWM Offset
FB Input Bias Current
COMP Sink Current
COMP Source Current
COMP VOH
COMP = 4V, T = 25 C
A
V/V
V
COMP
COMP = 4V (Note 5)
V
= 0V
µA
mA
mA
V
FB
COMP = 1.5V, V = 2.7V
2
6
-
FB
COMP = 1.5V, V = 2.3V
-0.2
4.25
0.4
60
-0.5
4.4
-
FB
V
V
= 2.3V
= 2.7V
5.0
1.2
-
FB
FB
COMP VOL
0.8
V
PSRR
Frequency = 120Hz (Note 5)
80
dB
V
SS Clamp, V
SS = 2.5V, V = 0V, ISET = 2V
FB
2.4
2.5
2.6
COMP
OSCILLATOR
Frequency Accuracy
289
-
318
347
kHz
%
o
Frequency Variation with VCC
T = 105 C (F
- - F )/F
20V 9V 9V
2
2
3
3
o
T = -40 C (F
(Note 5)
(Note 5)
(Note 6)
(Note 5)
(Note 5)
(Note 5)
- - F )/F
20V 9V 9V
Temperature Stability
-
-
8
TBD
75
3
-
-
%
nS
%
V
Minimum Charge and Discharge Time
Maximum Duty Cycle
68
-
81
-
Comparator High Threshold - Free Running
Comparator High Threshold - with External SYNCH
Comparator Low Threshold
-
4
-
V
-
1.5
-
V
o
Discharge Current
0 - 105 C
0.75
0.70
1.0
1.0
1.2
1.2
mA
o
-40 - 105 C
SYNCHRONIZATION
Input High Threshold
Input Pulse Width
-
-
-
-
2.5
-
V
25
nS
Input Frequency Range
(Note 5)
0.65x Free
Running
1.0
MHz
Input Impedance
VOH
-
2.5
-
4.5
-
-
-
kΩ
V
R
R
= 4.5kΩ
LOAD
VOL
= open
-
0.1
55
V
LOAD
SYNCH Advance
SYNCH rising edge to GATE falling
edge, C = C = 100pF
-
25
nS
GATE
SYNCH
Output Pulse Width
C
= 100pF
50
-
-
nS
SYNCH
5
ISL6721
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
o
schematic. 9V < V
= V < 20V ±10%, Rt = 11kΩ, Ct = 330 pF, T = -40 to 105 C (Note 3), Typical values are
CC
C
A
o
at T = 25 C (Continued)
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START
Charging Current
SS = 2V
-40
4.26
30
-55
4.50
40
-70
4.74
55
µA
V
Charged Threshold Voltage
Initial Over Current Discharge Current
Sustained OC Threshold < SS <
Charged Threshold
µA
Sustained Over Current Threshold Voltage
Fault Discharge Current
Charged Threshold minus
SS = 2V
0.095
0.25
0.22
0.125
1.0
0.155
-
V
mA
V
Reset Threshold Voltage
SLOPE COMPENSATION
Charge Current
0.27
0.31
o
SLOPE = 2V, 0 - 105 C
-45
-41
-53
-53
-65
-65
µA
V/V
V
o
-40 - 105 C
Slope Compensation Gain
Fraction of slope voltage added to
0.095
0.100
0.105
I
(Note 5)
SENSE
Discharge Voltage
GATE OUTPUT
V
= 4.5V
-
0.1
0.2
RTCT
Gate Output Limit Voltage
V
= 20V, C
= 0mA
= 1nF,
GATE
11.0
13.5
1.5
16.0
2.2
V
V
V
A
C
I
OUT
Gate VOH
V
- GATE, V = 10V,
= 150mA
-
-
-
C
C
I
OUT
Gate VOL
GATE - PGND, IOUT = 150mA
IOUT = 10mA
1.2
0.6
1.5
0.8
Peak Output Current
Output “Faulted” Leakage
Rise Time
V
= 20V, C
= 1nF
GATE
1.0
-
C
(Note 5)
V
= 20V, UV = 0V, GATE = 0V
-
-1
2.6
-50
-
µA
mA
C
GATE = 2V
1.2
V
= 20V, C
= 1nF
= 1nF
-
-
-
60
15
-
100
nS
nS
nS
C
GATE
1V < GATE < 9V
Fall Time
V = 20V, C
C
40
GATE
1V < GATE < 9V
Minimum ON time
ISET = 0.5V; V = 0V; VC = 11V
FB
110
ISENSE to GATE w/10:1 Divider
RTCT = 4.75V through 1kΩ
(Note 5)
OVER CURRENT PROTECTION
Minimum ISET Voltage
-
-
-
0.35
-
V
V
Maximum ISET Voltage
1.2
150
Restart Delay
(Note 5)
295
445
mS
OV & UV VOLTAGE MONITOR
Over Voltage Threshold
2.4
1.38
1.41
20
2.5
1.45
1.53
50
2.6
1.52
1.62
100
V
V
Under Voltage Fault Threshold
Under Voltage Clear Threshold
Under Voltage Hysteresis Voltage
V
mV
6
ISL6721
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
o
schematic. 9V < V
= V < 20V ±10%, Rt = 11kΩ, Ct = 330 pF, T = -40 to 105 C (Note 3), Typical values are
CC
C
A
o
at T = 25 C (Continued)
A
PARAMETER
THERMAL PROTECTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
o
Thermal Shutdown
Thermal Shutdown Clear
Hysteresis
(Note 5)
(Note 5)
(Note 5)
120
105
-
130
120
10
140
135
-
C
o
C
o
C
NOTE:
3. Specifications at -40 C and 105 C are guaranteed by design, not production tested.
4. This is the V current consumed when the device is active but not switching. Does not include gate drive current.
o
o
CC
5. Guaranteed by design, not 100% tested in production.
6. This is the maximum duty cycle achievable using the specified values of RT and CT. Larger or smaller maximum duty cycles may be obtained
using other values for RT and CT. See Equations 1 - 4.
Typical Performance Curves
1.002
1.002
1
1
0.998
0.998
0.995
0.995
0.993
0.993
0.991
0.991
-40
-10
20
50
80
110
-40
-10
20
50
80
110
o
o
TEMPERATURE
TEMPERATURE
C
C
FIGURE 1. EA REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. VREF REFERENCE VOLTAGE vs TEMPERATURE
3
1-10
1.002
0.996
CT=
0.989
100pF
100
0.983
220pF
330pF
0.976
470pF
680pF
0.97
1000pF
-40
-10
20
50
80
110
10
10 20 30 40 506070 80 90 100
o
TEMPERATURE
C
2000pF
RT (kΩ)
FIGURE 4. CAPACITANCE vs FREQUENCY
FIGURE 3. OSCILLATOR FREQUENCY vs TEMPERATURE
7
ISL6721
OV - Over voltage monitor input pin. This signal is compared
to an internal 2.5V reference to detect an over voltage
condition.
Pin Descriptions
SLOPE - Means by which the ISENSE ramp slope may be
increased for improved noise immunity or improved control
loop stability for duty cycles greater than 50%. An internal
current source charges an external capacitor to GND during
each switching cycle. The resulting ramp is scaled and
added to the ISENSE signal.
UV - Under voltage monitor input pin. This signal is
compared to an internal 1.45V reference to detect an under
voltage condition.
ISENSE - This is the input to the current sense comparators.
The IC has two current sensing comparators, a PWM
comparator for peak current mode control, and an over
current protection comparator. The over current comparator
threshold is adjustable through the ISET pin.
SYNC - A bi-directional synchronization signal used to
coordinate the switching frequency of multiple units.
Synchronization may be achieved by connecting the SYNC
signal of each unit together or by using an external master
clock signal. The oscillator timing capacitor, C , is still
required, even if an external clock is used. The first unit to
assert this signal assumes control.
T
Exceeding the over-current threshold will start a delayed
shutdown sequence. Once an over current condition is
detected, the soft start charge current source is disabled and
a discharge current source is enabled. The soft start
capacitor begins discharging, and if it discharges to less
than 4.375V (Sustained Over Current Threshold), a
shutdown condition occurs and the GATE output is forced
low. At this point a reduced discharge current takes over until
the soft start voltage reaches 0.27V (Reset Threshold). The
GATE output remains low until the reset threshold is
attained. At this point a soft start cycle begins.
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, R , between V
and this pin and a
T
REF
timing capacitor, C , from this pin to LGND. The oscillator
T
produces a sawtooth waveform with a programmable
frequency range of 100kHz to 1.0MHz. The charge time, T ,
the discharge time, T , the switching frequency, Fsw, and
D
the maximum duty cycle, Dmax, can be calculated from the
C
following equations:
If the over current condition ceases, and then an additional
50 µS period elapses before the shutdown threshold is
reached, no shutdown occurs and the soft start voltage is
allowed to recharge.
(EQ. 1)
T
T
≈ 0.655 • R • C
S
C
D
T
T
LGND - LGND is a small signal reference ground for all
analog functions on this device.
0.001 • R – 3.6
T
T
-------------------------------------------
(EQ. 2)
(EQ. 3)
(EQ. 4)
≈ –R • C • LN
S
T
T
0.001 • R – 1.9
PGND - This pin provides a dedicated ground for the output
gate driver. The LGND and PGND pins should be connected
externally using a short printed circuit board trace close to
the IC. This is imperative to prevent large, high frequency
switching currents flowing through the ground metallization
1
Fsw = ---------------------
+ T
Hz
T
D
C
inside the IC. (Decouple V to PGND with a low ESR 0.1µF
C
Dmax = T • Fsw
or larger capacitor.)
C
GATE - This is the device output. It is a high current power
driver capable of driving the gate of a power MOSFET with
peak currents of 1.0A. This GATE output is actively held low
Figure 4 may be used as a guideline in selecting the
capacitor and resistor values required for a given frequency.
when V
CC
is below the UVLO threshold.
COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
The output high voltage is clamped to ~ 13.5V. Voltages
exceeding this clamp value should not be applied to the
GATE pin. The output stage provides very low impedance to
overshoot and undershoot.
The ISL6721 features a built-in full cycle soft start. Soft start
is implemented as a clamp on the maximum COMP voltage.
V
- This pin is for separate collector supply to the output
C
gate drive. Separate V and PGnd helps decouple the IC’s
analog circuitry from the high power gate drive noise.
C
FB - Feedback voltage input connected to the inverting input
of the error amplifier. The non-inverting input of the error
amplifier is internally tied to a reference voltage. Current
sense leading edge blanking is disabled when the FB input is
less than 2.0V.
(Decouple V to PGND with a low ESR 0.1µF or larger
C
capacitor.)
V
- V is the power connection for the device. Although
CC
CC
quiescent current, I , is low, it is dependent on the
CC
frequency of operation. To optimize noise immunity, bypass
8
ISL6721
V
to LGND with a ceramic capacitor as close to the V
CC
pulse is ignored if it occurs during the first 1/3 of the
CC
and LGND pins as possible.
switching cycle.
The total supply current (I plus I ) will be higher,
CC
During normal operation the RTCT voltage charges from 1.5
to 3.0V and back during each cycle. Clock and SYNC signals
are generated when the 3.0V threshold is reached. If an
external clock signal is detected during the latter 2/3 of the
charging cycle, the oscillator switches to external
synchronization mode and relies upon the external SYNC
signal to terminate the oscillator cycle. The generation of a
SYNC signal is inhibited in this mode. If the RTCT voltage
exceeds 4.0V (i.e. no external SYNC signal terminates the
cycle), the oscillator reverts to the internal clock mode and a
SYNC signal is generated.
C
depending on the load applied to GATE. Total current is the
sum of the quiescent current and the average gate current.
Knowing the operating frequency, Fsw, and the MOSFET
gate charge, Qg, the average GATE output current can be
calculated from:
Igate = Qg • Fsw
A
(EQ. 5)
VREF - The 5.00V reference voltage output. Bypass to
LGND with a 0.01µF or larger capacitor to filter this output as
needed. Using capacitance less than this value may result in
unstable operation.
Soft-Start Operation
The ISL6721 features soft-start using an external capacitor
in conjunction with an internal current source. Soft-start is
used to reduce voltage stresses and surge currents during
start up.
SS - Connect the soft start capacitor between this pin and
LGND to control the duration of soft start. The value of the
capacitor determines both the rate of increase of the duty
cycle during start up, and also controls the over current
shutdown delay.
Upon start up, the soft start circuitry clamps the error
amplifier output (COMP pin) to a value proportional to the
soft start voltage. The error amplifier output rises as the soft
start capacitor voltage rises. This has the effect of increasing
the output pulse width from zero to the steady state
operating duty cycle during the soft start period. When the
soft start voltage exceeds the error amplifier voltage, soft
start is completed. Soft start forces a controlled output
voltage rise. Soft-start occurs during start-up and after
recovery from a fault condition or over current shutdown. The
soft start voltage is clamped to 4.5V.
ISET - A DC voltage between 0.35 and 1.2V applied to this
input sets the pulse-by-pulse over current threshold. When
over current inception occurs, the SS capacitor begins to
discharge and starts the over current delayed shutdown
cycle.
Functional Description
Features
The ISL6721 current mode PWMs make an ideal choice for
low-cost flyback and forward topology applications requiring
enhanced control and supervisory capability. With adjustable
over and under voltage thresholds, over current threshold,
and hic-cup delay, a highly flexible design with minimal
external components is possible. Other features include
peak current mode control, adjustable soft-start, slope
compensation, adjustable oscillator frequency, and a bi-
directional synchronization clock input.
Gate Drive
The ISL6721 is capable of sourcing and sinking 1A peak
current. Separate collector supply (V ) and power ground
C
(PGnd) pins help isolate the IC’s analog circuitry from the
high power gate drive noise. To limit the peak current
through the IC, an external resistor may be placed between
the totem-pole output of the IC (GATE pin) and the gate of
the MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
Oscillator
The ISL6721 have a sawtooth oscillator with a
programmable frequency range to 1MHz, which can be
programmed with a resistor and capacitor on the RTCT pin.
(Please refer to Fig. 4 for the resistance and capacitance
required for a given frequency.)
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability. Slope compensation is a technique in
which the current feedback signal is modified by adding
additional slope to it. The minimum amount of slope
compensation required corresponds to 1/2 the inductor
downslope. However, adding excessive slope compensation
Implementing Synchronization
The oscillator can be synchronized to an external clock
applied at the SYNC pin or by connecting the SYNC pins of
multiple ICs together. If an external master clock signal is
used, it must be at least 65% of the free running frequency of
the oscillator for proper synchronization. The external master
clock signal should have a pulse width greater than 20ns. If
no master clock is used, the first device to assert SYNC
assumes control of the SYNC signal. An external SYNC
9
ISL6721
results in a control loop that behaves more as a voltage
mode controller than as current mode controller.
Otherwise another shutdown cycle occurs. A UV condition
also results in a shutdown fault, but the device does not
enter the low power mode and no restart delay occurs when
the fault clears.
DOWNSLOPE
CURRENT SENSE SIGNAL
l
A resistor divider between Vin and LGND to each input
determines the operational thresholds. The UV threshold
has a fixed hysteresis of 75mV nominal.
Over Current Operation
The over current threshold level is set by the voltage applied
at the ISET pin. Setting the over current level may be
accomplished by using a resistor divider network from VREF
to LGND. The ISET threshold should be set at a level that
corresponds to the desired peak output inductor current plus
the additive effects of slope compensation.
TIME
i
FIGURE 5.
The minimum amount of capacitance to place at the SLOPE
pin is:
Over current delayed shutdown is enabled once the soft start
cycle is complete. If an over current condition is detected,
the soft start charging current source is disabled and the
discharging current source is enabled. The soft start
capacitor is discharged at a rate of 40µA. At the same time a
50µS retriggerable one-shot timer is activated. It remains
active for 50µS after the over current condition stops. The
soft start discharge cycle cannot be reset until the one-shot
timer becomes inactive. If the soft start capacitor discharges
by more then 0.125V to 4.375V, the output is disabled and
the soft start capacitor is discharged. The output remains
–6
ton
Vslope
(EQ. 6)
--------------------
Cslope = 4.24×10
•
F
where ton is the On time and Vslope is the amount of voltage
to be added as slope compensation to the current feedback
signal. In general, the amount of slope compensation added
is 2 to 3 times the minimum required.
Example:
Assume the inductor current signal presented at the ISENSE
pin decreases 125mV during the Off period, and:
disabled and I
drops to 200µA for approximately 295ms.
CC
A new soft start cycle is then initiated. The shutdown and
restart behavior of the OC protection is often referred to as
hic-cup operation due to its repetitive start-up and shutdown
characteristic.
Switching Frequency, Fsw = 250kHz
Duty Cycle, D = 60%
ton = D/Fsw = 0.6/250E3 = 2.4µS
toff = (1 - D)/Fsw = 1.6µS
If the over current condition ceases at least 50µS prior to the
soft start voltage reaching 4.375V, the soft start charging and
discharging currents revert to normal operation and the soft
start voltage is allowed to recover.
Determine the downslope:
Downslope = 0.125V/1.6µS = 78mV/µS. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time.
Hic-cup OC protection may be defeated by setting ISET to a
voltage that exceeds the Error Amplifier current control
voltage, or about 1.5V.
1
--
Vslope = • 0.078 • 2.4 = 94mV
(EQ. 7)
2
Leading Edge Blanking
Therefore
The initial 100ns of the current feedback signal input at
ISENSE is removed by the leading edge blanking circuitry.
The blanking period begins when the GATE output leading
edge exceeds 3.0V. Leading edge blanking prevents current
spikes from parasitic elements in the power supply from
causing false trips of the PWM comparator and the over
current comparator.
–6
–6
2.4×10
-----------------------
≈ 110pF
(EQ. 8)
Cslope(min) = 4.24×10
•
0.094
An appropriate slope compensation capacitance for this
example would be 1/2 to 1/3 the calculated value, or
between 68 and 33pF.
Over and Under Voltage Monitor
Fault Conditions
The OV and UV signals are inputs to a window comparator
used to monitor the input voltage level to the converter. If the
voltage falls outside of the user designated operating range,
a shutdown fault occurs. For OV faults, the supply current,
A Fault condition occurs if VREF falls below 4.65V, the OV
input exceeds 2.50V, the UV input falls below 1.45V, or the
junction temperature of the die exceeds ~130 C. When a
Fault is detected the GATE output is disabled and the soft
start capacitor is quickly discharged. When the Fault
o
I
, is reduced to 200µA for ~ 295ms at which time recovery
CC
is attempted. If the fault is cleared, a soft start cycle begins.
10
ISL6721
condition clears and the soft start voltage is below the reset
threshold, a soft start cycle begins.
Pout: 10W
Efficiency: 70%
Ground Plane Requirements
Maximum Duty Cycle, Dmax: 0.45
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. Power ground
(PGND) can be separated from the logic ground (LGND) and
Transformer Design
The design of a flyback transformer is a non-trivial affair. It is
an iterative process which requires a great deal of
experience to achieve the desired result. It is a process of
many compromises, and even experienced designers will
produce different designs when presented with identical
requirements. The iterative design process is not presented
here for clarity.
connected at a single point. V should be bypassed directly
C
to PGND with good high frequency capacitors. The return
connection for input power and the bulk input capacitor
should be connected to the PGND ground plane.
The abbreviated design process follows:
Reference Design
• Select a core geometry suitable for the application.
Constraints of height, footprint, mounting preference, and
operating environment will affect the choice.
The Typical Application Schematic features the ISL6721 in a
conventional dual output 10W discontinuous mode flyback
DC-DC converter. The ISL6721EVAL1 demonstration unit
implements this design and is available for evaluation.
• Select suitable core material(s).
The input voltage range is from 36 to 75V DC, and the two
outputs are 3.3V @ 2.5A and 1.8V @ 1.0A. Cross regulation
is achieved using the weighted sum of the two outputs.
• Select maximum flux density desired for operation.
• Select core size. Core size will be dictated by the
capability of the core structure to store the required
energy, the number of turns that have to be wound, and
the wire gauge needed. Often the window area (the space
used for the windings) and power loss determine the final
core size. For flyback transformers, the ability to store
energy is the critical factor in determining the core size.
The cross sectional area of the core and the length of the
air gap in the magnetic path determine the energy storage
capability.
Circuit Element Descriptions
The converter design may be broken down into the following
functional blocks:
Input Storage and Filtering Capacitance: C1, C2, C3
Isolation Transformer: T1
Primary voltage Clamp: CR6, R24, C18
Start Bias Regulator: R1, R2, R6, Q3, VR1
Operating Bias and Regulator: R25, Q2, D1, C5, CR2, D2
Main MOSFET Power Switch: Q1
• Determine maximum desired flux density. Depending on
the frequency of operation, the core material selected, and
the operating environment, the allowed flux density must
be determined. The decision of what flux density to allow
is often difficult to determine initially. Usually the highest
flux density that produces an acceptable design is used,
but often the winding geometry dictates a larger core than
is required based on flux density and energy storage
calculations.
Current Sense Network: R4, R3, R23, C4
Feedback Network:, R13, R15, R16, R17, R18, R19, R20,
R26, R27, C13, C14, U2, U3
• Determine the number of primary turns.
• Determine the turns ratio.
Control Circuit:C7, C8, C9, C10, C11, C12, R5, R6, R8, R9,
R10, R11, R12, R14, R22
• Select the wire gauge for each winding.
• Determine winding order and insulation requirements.
• Verify the design.
Output Rectification and Filtering: CR4, CR5, C15, C16,
C19, C20, C21, C22
Secondary Snubber: R21, C17
Design Criteria
The following design requirements were selected:
Input Power:
Switching Frequency, Fsw: 200kHz
Vin: 36 - 75V
Pout/Efficiency = 14.3W (use 15W)
Max On Time: Ton(max) = Dmax/Fsw = 2.25µS
Average Input Current: Iavg(in) = Pin/Vin(min) = 0.42A
Vout(1): 3.3V @ 2.5A
Vout(2): 1.8V @ 1.0A
Vout(bias): 12V @ 50mA
11
ISL6721
-3
Peak Primary Current:
lg = 1.56 • 10
m
2 • Iavg(in)
Fsw • Ton(max)
(EQ. 9)
Ippk = --------------------------------------------- = 1.87
A
The flux density ∆B is only 0.069T or 690 gauss, a relatively
low value.
Maximum Primary Inductance:
Since
Vin(min) • Ton(max)
2
Lp(max) = ----------------------------------------------------------- = 43.3
µH
(EQ. 10)
µ
• N • Aeff
(EQ. 13)
o
p
Ippk
L
= ----------------------------------------
µH
p
lg
Choose desired primary inductance to be 40µH.
the number of primary turns, N , may be calculated. The
p
result is N = 40 turns. The secondary turns may be
calculated as follows:
The core structure must be able to deliver a certain amount
of energy to the secondary on each switching cycle in order
to maintain the specified output power.
p
Ig • 〈 Vout + Vd〉 • Tr
(EQ. 14)
--------------------------------------------------------
N ≤
s
N
• Ippk • µ • Aeff
o
p
〈 Vout + Vd〉
---------------------------------
(EQ. 11)
∆w = Pout •
joules
Fsw • Vout
where Tr is the time required to reset the core. Since
discontinuous MMF mode operation is desired, the core
must completely reset during the off time. To maintain
discontinuous mode operation, the maximum time allowed to
reset the core is Tsw - Ton(max) where Tsw = 1/Fsw. The
minimum time is application dependent and at the designers
discretion knowing that the secondary winding RMS current
and ripple current stress in the output capacitors increases
where ∆w is the amount of energy required to be transferred
each cycle and Vd is the drop across the output rectifier.
The capacity of a gapped ferrite core structure to store
energy is dependent on the volume of the airgap and can be
expressed as:
2 • µ • ∆w
3
o
Vg = Aeff • lg = -----------------------------
m
(EQ. 12)
with decreasing reset time. The calculation for maximum N
2
s
∆B
for the 3.3 V output using T = Tsw - Ton (max) = 2.75µS is
5.52 turns.
where Aeff is the effective cross sectional area of the core in
2
m , lg is the length of the airgap in meters, µ is the
The determination of the number of secondary turns is also
dependent on the number of outputs and the required turns
ratios required to generate them. If schottky output rectifiers
are used and we assume a forward voltage drop of 0.45V,
the required turns ratio for the two output voltages, 3.3V and
1.8V, is 5:3.
o
-7
permeability of free space (4π • 10 ), and ∆B is the change
in flux density in Tesla.
A core structure having less airgap volume than calculated
will be incapable of providing the full output power over some
portion of its operating range. On the other hand, if the
length of the airgap becomes large, magnetic field fringing
around the gap occurs. This has the effect of increasing the
airgap volume. Some fringing is usually acceptable, but
excessive fringing can cause increased losses in the
windings around the gap resulting in excessive heating.
Once a suitable core and gap combination are found, the
iterative design cycle begins. A design is developed and
checked for ease of assembly and thermal performance. If
the core does not allow adequate space for the windings,
then a core with a larger window area is required. If the
transformer runs hot, it may be necessary to lower the flux
density (more primary turns, lower operating frequency),
select a less lossy core material, change the geometry of the
windings (winding order), use heavier gauge wire or multi-
filar windings, and/or change the type of wire used (Litz wire,
for example).
With a turns ratio of 5:3 for the secondary windings, we will
use N = 5 turns and N = 3 turns. Checking the reset time
s1 s2
using these values for the number of secondary turns yields
a duration of Tr = 2.33µS or about 47% of the switching
period, an acceptable result.
The bias winding turns may be calculated similarly, only a
diode forward drop of 0.7V is used. The rounded off result is
17 turns for a 12V bias.
The next step is to determine the wire gauge. The RMS
current in the primary winding may be calculated from:
Ton(max)
3 • Tsw
Ip(rms) = Ippk • ----------------------------
A
(EQ. 15)
The peak and RMS current values in the remaining windings
may be calculated from:
For simplicity, only the final design is further described.
An EPCOS EFD 20/10/7 core using N87 material gapped to
2
2 • Iout • Tsw
(EQ. 16)
(EQ. 17)
Ispk = -------------------------------------
A
an A value of 25 nH/N was chosen. It has more than the
L
Tr
required air gap volume to store the energy required, but was
needed for the window area it provides.
Tsw
Irms = 2 • Iout • --------------
A
-6
2
3 • Tr
Aeff = 31 • 10
m
12
ISL6721
The RMS current for the primary winding is 0.72A, for the
3.3V output, 4.23A, for the 1.8V output, 1.69A, and for the
bias winding, 85mA.
where Rdson is the ON resistance of the MOSFET and
Iprms is the RMS primary current. Determining the
conduction losses is complicated by the variation of Rdson
with temperature. As junction temperature increases, so
does Rdson, which increases losses and raises the junction
temperature more, and so on. It is possible for the device to
enter a thermal runaway situation without proper
To minimize the transformer leakage inductance, the primary
was split into two sections connected in parallel and
positioned such that the other windings were sandwiched
between them. The output windings were configured so that
the 1.8V winding is a tap off of the 3.3V winding. Tapping the
1.8V output requires that the shared portion of the
o
heatsinking. As a general rule of thumb, doubling the 25 C
Rdson specification yields a reasonable value for estimating
o
the conduction losses at 125 C junction temperature.
secondary conduct the combined current of both outputs.
The secondary wire gauge must be selected accordingly.
The switching losses have two components, capacitive
switching losses and voltage/current overlap losses. The
capacitive losses occur during turn on of the device and may
be calculated as follows:
The determination of current carrying capacity of wire is a
compromise between performance, size, and cost. It is
affected by many design constraints such as operating
frequency (harmonic content of the waveform) and the
winding proximity/geometry. It generally ranges between 250
and 1000 circular mils per ampere. A circular mil is defined
as the area of a circle 0.001” (1 mil) in diameter. As the
frequency of operation increases, the AC resistance of the
wire increases due to skin and proximity effects. Using
heavier gauge wire may not alleviate the problem. Instead
multiple strands of wire in parallel must be used. In some
cases Litz wire is required.
2
1
2
--
Pswcap = • Cfet • Vin • Fsw
W
(EQ. 19)
where Cfet is the equivalent output capacitance of the
MOSFET. Device output capacitance is specified on
datasheets as Coss and is non-linear with applied voltage.
To find the equivalent discrete capacitance, Cfet, a charge
model is used. Using a known current source, the time
required to charge the MOSFET drain to the desired
operating voltage is determined and the equivalent
capacitance may be calculated.
The winding configuration selected is:
Primary #1: 40T, 2 #30 bifilar
Ichg • t
Cfet = -------------------
F
(EQ. 20)
V
Secondary: 5T, 0.003” (3 mil) copper foil tapped at 3T
Bias: 17T #32
The other component of the switching loss is due to the
overlap of voltage and current during the switching transition.
A switching transition occurs when the MOSFET is in the
process of either turning on or off. Since the load is
Primary #2: 40T, 2 #30 bifilar
The internal spacing and insulation system was designed for
1500 VDC dielectric withstand rating between the primary
and secondary windings.
inductive, there is no overlap of voltage and current during
the turn on transition, so only the turn off transition is of
significance. The power dissipation may be estimated as:
Power MOSFET Selection
1
x
--
(EQ. 21)
Psw ≈ • Ippk • Vin • Tol • Fsw
Selection of the main switching MOSFET requires
consideration of the voltage and current stresses that will be
encountered in the application, the power dissipated by the
device, its size, and its cost.
where Tol is the duration of the overlap period and x ranges
from about 3 - 6 in typical applications and depends on
where the waveforms intersect. This estimate may predict
higher dissipation than is realized because a portion of the
turn off drain current is attributable to the charging of the
device output capacitance (Coss) and is not dissipative
during this portion of the switching cycle.
The input voltage range of the converter is 36 - 75V DC. This
suggests a MOSFET with a voltage rating of 150V is
required due to the flyback voltage likely to be seen on the
primary of the isolation transformer.
The losses associated with MOSFET operation may be
divided into three categories: conduction, switching, and
gate drive.
Ippk
The conduction losses are due to the MOSFET’s ON
resistance.
2
Pcond = Rdson • Iprms
W
(EQ. 18)
VD-S
Tol
FIGURE 6.
13
ISL6721
The final component of MOSFET loss is caused by the
charging of the gate capacitance through the device gate
resistance. Depending on the relative value of any external
resistance in the gate drive circuit, a portion of this power will
be dissipated externally.
The change in voltage due to the change in charge of the
output capacitor, ∆Q, determines how much capacitance is
required on the output.
–6
(Ispk – Iout) • Tr
(10.73 – 2.5) • 2.33×10
---------------------------------------------
C ≥
= ------------------------------------------------------------------ = 960µF
2 • ∆V
2 • 0.010
(EQ. 24)
(EQ. 22)
Pgate = Qg • Vg • Fsw
W
ESL adds to the ripple and noise voltage in proportion to the
rate of change of current into the capacitor (V = L • di/dt).
Once the losses are known, the device package must be
selected and the heatsinking method designed. Since the
design requires a small surface mount part, a SOIC-8
package was selected. A Fairchild FDS2570 MOSFET was
selected based on these criteria. The overall losses are
estimated at 400mW.
–9
V • dt
di
0.030 • 200×10
--------------
(EQ. 25)
L ≤
= --------------------------------------------- = 0.56nH
10.73
Capacitors having high capacitance usually do not have
sufficiently low ESL. High frequency capacitors such as
surface mount ceramic or film are connected in parallel with
the high capacitance capacitors to address the effects of
ESL. A combination of high frequency and high ripple
capability capacitors is used to achieve the desired overall
performance. The analysis of the 1.8V output is similar to
that of the 3.3V output and is omitted for brevity. Two
OSCON 4SEP560M (560µF) electrolytic capacitors and a
22µF X5R ceramic 1210 capacitor were selected for both the
3.3 and 1.8V outputs. The 4SEP560M electrolytic capacitors
are each rated at 4520mA ripple current and 13mΩ of ESR.
The ripple current rating of just one of these capacitors is
adequate, but two are needed to meet the minimum ESR
and capacitance values.
Output Filter Design
In a flyback design, the primary concern for the design of the
output filter is the capacitor ripple current stress and the
ripple and noise specification of the output.
The current flowing in and out of the output capacitors is the
difference between the winding current and the output
current. The peak secondary current, Ispk, is 10.73A for the
3.3V output and 4.29A for the 1.8V output. The current
flowing into the output filter capacitor is the difference
between the winding current and the output current. Looking
at the 3.3V output, the peak winding current is Ispk =
10.73A. The capacitor must store this amount minus the
output current of 2.5A, or 8.23A. The RMS ripple current in
the 3.3V output capacitor is about 3.5 Arms. The RMS ripple
current in the 1.8V output capacitor is about 1.4 Arms
The bias output is of such low power and current that it
places negligible stress on its filter capacitor. A single 0.1µF
ceramic capacitor was selected.
Voltage deviation on the output during the switching cycle
(ripple and noise) is caused by the change in charge of the
output capacitance, the equivalent series resistance (ESR),
and equivalent series inductance (ESL). Each of these
components must be assigned a portion of the total ripple
and noise specification. How much to allow for each
contributor is dependent on the capacitor technology used.
Control Loop Design
The major components of the feedback control loop are a
programmable shunt regulator, an opto-coupler, and the
inverting amplifier of the ISL6721. The opto-coupler is used
to transfer the error signal across the isolation barrier. The
opto-coupler offers a convenient means to cross the isolation
barrier, but it adds complexity to the feedback control loop. It
adds a pole at about 10kHz and a significant amount of gain
variation due the current transfer ratio (CTR). The CTR of
the opto-coupler varies with initial tolerance, temperature,
forward current, and age.
For purposes of this discussion we will assume the following:
3.3V output: 100mV total output ripple and noise
ESR: 60mV
Capacitor ∆Q: 10mV
ESL: 30mV
1.8V output: 50mV total output ripple and noise
ESR: 30mV
Capacitor ∆Q: 5mV
ESL: 15mV
For the 3.3V output:
∆V
Ispk – Iout
0.060
10.73 – 2.5
-----------------------------
ESR ≤
= ---------------------------- = 7.3mΩ
(EQ. 23)
14
ISL6721
A block diagram of the feedback control loop follows in
Figure 7.
determining ISET, the internal gain and offset of the ISENSE
signal in the control IC must be taken into account. The
maximum peak primary current was determined earlier to be
1.87A, so a choice of 2.25A peak primary current for current
PRIMARY SIDE AMPLIFIER
limit is reasonable. A current gain, A
selected to achieve this.
, of 0.5 V/A was
EXT
+
-
REF
POWER
STAGE
VOUT
PWM
Z3
(EQ. 26)
ISET = 2.25 • 0.8 • 0.5 + 0.100 = 1.00
V
Z4
ERROR AMPLIFIER
Z2
The control to output transfer function may be represented
as [2]
ISOLATION
s
-
Z1
1 + ------
ω
v
R • L • F
o s sw
z
o
----------------
----- = K • ----------------------------------- •
(EQ. 27)
REF
+
s
v
2
c
1 + ------
ω
p
FIGURE 7.
if we ignore the current feedback sampled-data effects.
I
spk(max)
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. The primary
side amplifier located in the control IC is used as a unity gain
inverting amplifier and provides no loop compensation. A
Type 2 error amplifier configuration was selected as a
precaution in case operation in continuous mode should
occur at some operating point.
K = -------------------------
V
c(max)
R
L
= LoadResistance
o
s
= SecondaryInductance
2
1
ω
= --------------------
or
or
f
= -----------------------------
p
p
R
• C
π • R • C
o
o
o
o
1
1
Vout
ω
= -------------------
f = --------------------------------------
z
z
R • C
2 • π • R • C
c
o
c o
C
= OutputCapacitance
o
-
R
V
= OutputCapacitanceESR
= ControlVoltageRange
Verror
c
REF
+
c(max)
The value of K may be determined by assuming all of the
output power is delivered by the 3.3V output at the threshold
of current limit. The maximum power allowed was
determined earlier as 15 watts, so
FIGURE 8. TYPE 2 ERROR AMPLIFIER
Development of a small signal model for current mode
control is rather complex. The method of reference [1] was
selected for its ability to accurately predict loop behavior. To
further simplify the analysis, the converter will be modeled
as a single output supply with all of the output capacitance
reflected to the 3.3V output. Once the “single” output system
is compensated, adjustments to the compensation will be
required based on actual loop measurements.
P
out
–6
15
3.3
-----------
2 •
• Tsw
-------
2 •
• 5×10
V
out
Tr
I
= -------------------------------------- = ----------------------------------------- = 19.5
A
spk(max)
–6
2.33×10
1
--------------------
v
= V
• A
• A •
CS
= 2.93
V
c(max)
ISENSE
EXT
A
COMP
The first parameter to determine is the peak current
feedback loop gain. Since this application is low power, a
resistor in series with the source of the power switching
MOSFET is used for the current feedback signal. For higher
power applications, a resistor would dissipate too much
power and current transformer would be used instead.
where A
EXT
is the external gain of the current feedback
is the IC internal gain, and A is the gain
network, A
CS
COMP
between the error amplifier and the PWM comparator.
The Type 2 compensation configuration has two poles and
one zero. The first pole is at the origin, and provides the
integration characteristic which results in excellent DC
regulation. Referring to the Typical Application Schematic,
There is limited flexibility to adjust the current loop behavior
due to the need to provide over current protection. Current
limit and the current loop gain are determined by the current
sense resistor and the ISET threshold. ISET was set at 1.0V,
near its maximum, to minimize noise effects. When
15
ISL6721
the remaining pole and zero for the compensator are located
at:
A Bode plot of the closed loop system at low line, max load
appears below.
C
+ C
14
1
13
------------------------------------------------------------ --------------------------------------------
50
f
=
≈
(EQ. 28)
(EQ. 29)
pc
2 • π • R • C • C
2 • π • R • C
15 14
15
14
13
40
30
20
10
1
0
f
= --------------------------------------------
zc
-10
2 • π • R • C
15
13
-20
-30
-40
The ratio of R15 to the parallel combination of R17 and R18
determine the mid band gain of the error amplifier.
-50
0.01
0.1
1
10
100
FREQUENCY(kHz)
R
• (R + R
)
18
15
17
A
= -----------------------------------------------
(EQ. 30)
FIGURE 9A. GAIN
midband
R
• R
18
17
From (EQ. 27), it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitance ESR. These variations must be
considered when compensating the control loop. The worst
case small signal operating point for the converter is at
minimum Vin, maximum load, maximum Cout, and minimum
ESR.
200
150
100
50
0
-50
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the
bandwidth to about Fsw/4. For this example, the bandwidth
will be further limited due to the low GBWP of the LM431-
based Error Amplifier and the opto-coupler. A bandwidth of
approximately 5kHz was selected.
-100
0.01
0.1
1
10
100
FREQUENCY (kHz)
FIGURE 9B. PHASE MARGIN
For the EA compensation, the first pole is placed at the origin
by default (C14 is an integrating capacitor). The first zero is
placed below the crossover frequency, f , usually around
co
1/3 f . The second pole is placed at the lower of the ESR
co
zero or at one half of the switching frequency. The midband
gain is then adjusted to obtain the desired crossover
frequency. If the phase margin is not adequate, the
crossover frequency may have to be reduced.
Using this technique to determine the compensation, the
following values for the EA components were selected.
R17 = R18 = R15 = 1kΩ
R20 = open
C13 = 100nF
C14 = 100pF
16
ISL6721
4.375V OC fault threshold at which point the IC enters the
Regulation Performance
fault shutdown mode. Trace 2 shows the behavior of the
timing capacitor voltage during a shutdown fault. Most of the
functions of the IC are de-powered during a fault, and the
oscillator is among those functions. During a fault, the IC is
turned off until the restart delay has timed out. After the
delay, power is restored and the IC resumes normal
operation. Trace 3 is the GATE output during the soft start
cycle and OC fault.
TABLE 1. OUTPUT LOAD REGULATION, V = 48V
IN
I
(A), 3.3V
0
I
(A), 1.8V
V
(V), 3.3V V
(V), 1.8V
1.825
OUT
OUT
OUT
3.351
OUT
0.030
0.030
0.030
0.030
0.030
0.030
0030
0.030
0.52
0.52
0.52
0.52
0.52
0.52
0.52
1.05
1.05
1.05
1.05
1.05
1.05
1.55
1.55
1.55
1.55
1.55
2.07
2.07
2.07
2.07
2.62
2.62
2.62
3.14
3.14
0.39
0.88
1.38
1.87
2.39
2.89
3.37
0
3.281
3.251
3.223
3.204
3.185
3.168
3.153
3.471
3.283
3.254
3.233
3.218
3.203
3.191
3.619
3.290
3.254
3.235
3.220
3.207
3.699
3.306
3.260
3.239
3.224
3.762
3.329
3.270
3.245
3.819
3.355
3.282
3.869
3.383
1.956
1.988
2.014
2.029
2.057
2.084
2.103
1.497
1.800
1.836
1.848
1.855
1.859
1.862
1.347
1.730
1.785
1.805
1.814
1.820
1.265
1.682
1.750
1.776
1.789
1.201
1.645
1.722
1.752
1.142
1.612
1.697
1.091
1.581
0.39
0.88
1.38
1.87
2.39
2.89
0
0.39
0.88
1.38
1.87
2.39
0
NOTE:
Trace 1: SYNC Output
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
FIGURE 10. TYPICAL WAVEFORMS
0.39
0.88
1.38
1.87
0
0.39
0.88
1.38
0
0.39
0.88
0
.39
Waveforms
NOTE:
Trace 1: SS
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
Typical waveforms can be found in Figures 10 through 12.
Figure 10 shows the steady state operation of the sawtooth
oscillator waveform at RTCT (Trace 2), the SYNC output
pulse (Trace 1), and the GATE output to the converter FET
(Trace 3). Figure 11 shows the converter behavior while
operating in an over current fault condition. Trace 1 is the soft
start voltage, which increases from zero to 4.5V, at which
point the OC fault function is enabled. The OC condition is
detected and the soft start capacitor is discharged to the
FIGURE 11. SOFT START W/OVER CURRENT FAULT
Figure 12 shows the switching FET waveforms during steady
state operation. Trace 1 is drain - source voltage and Trace 2
is gate - source voltage.
17
ISL6721
TABLE 2. (Continued)
REFERENCE
DESIGNATOR VALUE
DESCRIPTION
Resistor, 0603, 1%
R7, R9, R11,
10.0K
R26, R27
R12
38.3K
1.00K
Resistor, 0603, 1%
Resistor, 0603, 1%
R13, R15, R17,
R18, R19, R25
R14
R16
R21
R22
R24
R3, R23
R4
10
Resistor, 0603, 1%
165
Resistor, 0603, 1%
10.0
5.11
3.92K
100
Resistor, 1206, 1%
Resistor, 0603, 1%
Resistor, 2512, 1%
Resistor, 0603, 1%
NOTE:
Trace 1: V
Trace 3: V
1.00
221K
75.0K
Resistor, 2512, 1%
D-S
G-S
R5
Resistor, 0603, 1%
FIGURE 12. GATE AND DRAIN-SOURCE WAVEFORMS
R6
Resistor, 0603, 1%
Component List
R8, R20
T1
OMIT
TABLE 2.
Transformer, MIDCOM 31555
Opto-coupler, NEC PS2801-1
Shunt Reference, National LM431BIM3
PWM, Intersil ISL6721IB
Zener, 15V, Zetex BZX84C15
REFERENCE
DESIGNATOR VALUE
U2
DESCRIPTION
U3
C1, C2, C3
C5, C13
1.0µF
0.1µF
560µF
Capacitor, 1812, X7R, 100V, 20%
Capacitor, 0603, X7R, 25V, 10%
Capacitor, Radial, SANYO 4SEP560M
U4
VR1
C15, C16, C19,
C20
References
C17
470pF
.01µF
22µF
Capacitor, 0603, COG, 50V, 5%
Capacitor, 0805, X7R, 50V, 10%
Capacitor, 1210, X5R, 10V, 20%
Capacitor, 0603, COG, 50V, 5%
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
C18
C21, C22
C4, C14
C6
[2] Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode
Power Supply Design Seminar, SEM-700, 1990.
100pF
1500pF Capacitor, Disc, Murata
DE1E3KX152MA5BA01
C7
C8
Zero Ohm Jumper, 0603
330pF
Capacitor, 0603, COG, 50V, 5%
C9, C10, C11,
C12
0.22µF Capacitor, 0603, X7R, 16V, 10%
CR2, CR6
CR4, CR5
D1
Diode, Fairchild ES1C
Diode, IR 12CWQ03FN
Zener, 18V, Zetex BZX84C18
Diode, Schottky, BAT54C
FET, Fairchild FDS2570
Transistor, Zetex FMMT491A
Transistor, ON MJD31C
D2
Q1
Q2
Q3
R1, R2
R10
1.00K
20.0K
Resistor, 1206, 1%
Resistor, 0603, 1%
18
ISL6721
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
GAUGE
PLANE
SYMBOL
MAX
0.043
0.006
0.037
0.012
0.008
0.201
0.177
MIN
-
MAX
1.10
0.15
0.95
0.30
0.20
5.10
4.50
NOTES
A
A1
A2
b
-
-
0.002
0.033
0.0075
0.0035
0.193
0.169
0.05
0.85
0.19
0.09
4.90
4.30
-
1
2
3
-
L
0.25
0.010
0.05(0.002)
SEATING PLANE
A
9
-A-
c
-
D
D
3
-C-
E1
e
4
α
0.026 BSC
0.65 BSC
-
A2
e
A1
c
E
0.246
0.020
0.256
0.028
6.25
0.50
6.50
0.70
-
b
0.10(0.004)
L
6
0.10(0.004) M
C
A M B S
N
16
16
7
o
o
o
o
0
8
0
8
-
α
NOTES:
Rev. 1 2/02
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
19
ISL6721
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INCHES MILLIMETERS
INDEX
M
M
B
0.25(0.010)
H
SYMBOL
MIN
MAX
0.069
0.010
0.019
0.010
0.394
0.157
MIN
1.35
0.10
0.35
0.19
9.80
3.80
MAX
1.75
NOTES
AREA
E
A
A1
B
C
D
E
e
0.053
0.004
0.014
0.007
0.386
0.150
-
-B-
0.25
-
0.49
9
1
2
3
L
0.25
-
10.00
4.00
3
SEATING PLANE
A
4
-A-
o
D
h x 45
0.050 BSC
1.27 BSC
-
H
h
0.228
0.010
0.016
0.244
0.020
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
-C-
α
µ
5
e
A1
L
6
C
B
0.10(0.004)
N
α
16
16
7
M
M
S
B
o
o
o
o
0.25(0.010)
C
A
0
8
0
8
-
Rev. 1 02/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
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