ISL6754_技术文档

ISL6754

¬

Data Sheet

September 29, 2008

FN6754.1

ZVS Full-Bridge PWM Controller with

Features

Adjustable Synchronous Rectifier Control

• Adjustable Resonant Delay for ZVS Operation

The ISL6754 is a high-performance extension of the Intersil

family of zero-voltage switching (ZVS) full-bridge PWM

controllers. Like the ISL6752, it achieves ZVS operation by

driving the upper bridge FETs at a fixed 50% duty cycle while

the lower bridge FETs are trailing-edge modulated with

adjustable resonant switching delays.

• Synchronous Rectifier Control Outputs with Adjustable

Delay/Advance

• Voltage- or Current-Mode Control

• 3% Current Limit Threshold

• Adjustable Average Current Limit

• Adjustable Deadtime Control

• 175µA Start-up Current

Adding to the ISL6752’s feature set are average current

monitoring and soft-start. The average current signal may be

used for average current limiting, current sharing circuits and

average current mode control. Additionally, the ISL6754

supports both voltage- and current-mode control.

• Supply UVLO

• Adjustable Oscillator Frequency Up to 2MHz

• Internal Over-Temperature Protection

• Buffered Oscillator Sawtooth Output

• Fast Current Sense to Output Delay

• Adjustable Cycle-by-Cycle Peak Current Limit

• 70ns Leading Edge Blanking

• Multi-Pulse Suppression

The ISL6754 features complemented PWM outputs for

synchronous rectifier (SR) control. The complemented

outputs may be dynamically advanced or delayed relative to

the PWM outputs using an external control voltage.

This advanced BiCMOS design features precision deadtime

and resonant delay control, and an oscillator adjustable to

2MHz operating frequency. Additionally, Multi-Pulse

Suppression ensures alternating output pulses at low duty

cycles where pulse skipping may occur.

• Pb-Free (RoHS Compliant)

Ordering Information

Applications

PART

NUMBER

(Note)

TEMP.

RANGE

(°C)

PART

MARKING

PACKAGE

(Pb-free)

PKG.

DWG. #

• ZVS Full-Bridge Converters

• Telecom and Datacom Power

• Wireless Base Station Power

• File Server Power

ISL6754AAZA* 6754 AAZ

-40 to +105 20 Ld QSOP M20.15

*Add -T suffix to part number for tape and reel packaging.

NOTE: These Intersil Pb-free plastic packaged products employ

special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination

finish, which is RoHS compliant and compatible with both SnPb and

Pb-free soldering operations). Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

• Industrial Power Systems

Pinout

ISL6754

(20 LD QSOP)

TOP VIEW

VREF

1

2

20

SS

19 VADJ

VERR

CTBUF

RTD

3

18

17

16

15

14

13

VDD

4

OUTLL

OUTLR

OUTUL

OUTUR

OUTLLN

5

RESDEL

CT

6

FB

7

RAMP

CS

8

9

12 OUTLRN

11 GND

10

IOUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6754

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V

Signal Pins. . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V

. . . . . . . . . . . . . . . . . . . GND - 0.3V to +22.0V

Thermal Resistance Junction to Ambient (Typical)

20 Lead QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

θ

(°C/W)

88

DD

JA

DD

+ 0.3V

REF

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V

REF

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A

Latchup (Note 3) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C

Operating Conditions

Temperature Range

ISL6754AAxx . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . .9VDC to 16VDC

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. All voltages are with respect to GND.

3. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are using a pulse limited to 50mA.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2

and “Typical Application schematics” beginning on page 3. 9V < V

< 20V, RTD = 10.0kΩ, CT = 470pF,

DD

= -40°C to +105°C, Typical values are at T = +25°C; Parameters with MIN and/or MAX limits are 100%

T

A

tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not

production tested.

PARAMETER

SUPPLY VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

-

20

400

15.5

9.00

7.50

-

V

µA

mA

V

Start-Up Current, I

V

= 5.0V

DD

-

175

11.0

8.75

7.00

1.75

DD

Operating Current, I

R

, C = 0

LOAD OUT

DD

UVLO START Threshold

UVLO STOP Threshold

Hysteresis

8.00

6.50

-

V

REFERENCE VOLTAGE

Overall Accuracy

I

= 0mA to 10mA

4.850

-

5.000

5.150

V

VREF

Long Term Stability

T

= +125°C, 1000 hours (Note 4)

3

-

mV

mA

A

Operational Current (source)

Operational Current (sink)

Current Limit

-10

5

-

V

= 4.85V

-15

-

-100

REF

CURRENT SENSE

Current Limit Threshold

CS to OUT Delay

VERR = V

Excl. LEB

0.97

1.00

1.03

-

V

ns

Ω

REF

-

35

Leading Edge Blanking (LEB) Duration

CS to OUT Delay + LEB

CS Sink Current Device Impedance

Input Bias Current

-

70

-

T

= +25°C

-

150

20

1.0

4.15

-

A

V

= 1.1V

= 0.3V

-

CS

-1.0

3.85

3.9

-

µA

V/V

V

I

Sample and Hold Buffer Amplifier Gain

Sample and Hold VOH

T

= +25°C

4.00

OUT

A

V

= max, I

= -300μA

-

CS

LOAD

Sample and Hold VOL

= 0.00V, I

= 10μA

0.3

V

LOAD

FN6754.1

September 29, 2008

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ISL6754

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2

and “Typical Application schematics” beginning on page 3. 9V < V

< 20V, RTD = 10.0kΩ, CT = 470pF,

DD

= -40°C to +105°C, Typical values are at T = +25°C; Parameters with MIN and/or MAX limits are 100%

T

A

tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not

production tested. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

RAMP

RAMP Sink Current Device Impedance

RAMP to PWM Comparator Offset

Bias Current

V

= 1.1V

-

80

-

20

95

Ω

RAMP

T

= +25°C

65

mV

μA

A

V

= 0.3V

-5.0

-2.0

RAMP

PULSE WIDTH MODULATOR

Minimum Duty Cycle

VERR < 0.6V

-

94

97

99

-

0

-

%

V

Maximum Duty Cycle (per half-cycle)

VERR = 4.20V, V

= 0V (Note 5)

-

CS

RTD = 2.00kΩ, CT = 220pF

RTD = 2.00kΩ, CT = 470pF

-

Zero Duty Cycle VERR Voltage

VERR to PWM Comparator Input Offset

VERR to PWM Comparator Input Gain

Common Mode (CM) Input Range

ERROR AMPLIFIER

0.85

0.7

0.31

0

1.20

0.9

0.35

4.45

T

= +25°C

0.8

0.33

-

V

A

V/V

V

(Note 4)

Input Common Mode (CM) Range

GBWP

(Note 4)

0

5

-

V

MHz

V

REF

-

VERR VOL

I

= 2mA

= 0mA

-

0.4

-

LOAD

VERR VOH

4.20

0.8

-

V

VERR Pull-Up Current Source

EA Reference

VERR = 2.5V

= +25°C

1.0

0.600

1.3

mA

V

T

0.594

0.590

0.606

0.612

A

EA Reference + EA Input Offset Voltage

OSCILLATOR

V

Frequency Accuracy, Overall

(Note 4)

165

-10

-

183

-

201

10

kHz

%

Frequency Variation with V

Temperature Stability

T

= +25°C, (F

- - F

)/F

10V 10V

0.3

4.5

1.5

-200

20

1.7

%

DD

A

20V

V

= 10V, |F

- F

|/F

-

%

DD

-40°C

0°C 0°C

|F

- F

|/F

(Note 4)

-

%

0°C

= +25°C

105°C 25°C

Charge Current

T

-193

19

-207

23

µA

µA/µA

V

A

Discharge Current Gain

CT Valley Voltage

CT Peak Voltage

CT Pk-Pk Voltage

RTD Voltage

Static Threshold

Static Value

0.75

2.75

1.92

1.97

0

0.80

2.80

2.00

-

0.88

2.88

2.05

2.03

2.00

2.05

0.44

0.10

V

RESDEL Voltage Range

V

CTBUF Gain (V

/V

)

V

= 0.8V, 2.6V

= 0.8V

1.95

0.34

-

2.0

0.40

-

V/V

V

CTBUFP-P CTP-P

CT

CTBUF Offset from GND

CTBUF VOH

ΔV(I

= 0mA, I

LOAD

= -2mA), V = 2.6V

CT

V

LOAD

CTBUF VOL

= 2mA, I

LOAD

= 0mA), V = 0.8V

CT

-

V

FN6754.1

September 29, 2008

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ISL6754

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2

and “Typical Application schematics” beginning on page 3. 9V < V

< 20V, RTD = 10.0kΩ, CT = 470pF,

DD

= -40°C to +105°C, Typical values are at T = +25°C; Parameters with MIN and/or MAX limits are 100%

T

A

tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not

production tested. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

SOFT-START

Charging Current

SS = 3V

SS = 2V

-60

4.410

10

-70

4.500

-

-80

4.590

-

μA

V

SS Clamp Voltage

SS Discharge Current

Reset Threshold Voltage

OUTPUT

mA

V

T

= +25°C

0.23

0.27

0.33

A

High Level Output Voltage (VOH)

Low Level Output Voltage (VOL)

Rise Time

I

= -10mA, V

- VOH

-

0.5

1.0

V

OUT

DD

= 10mA, VOL - GND

-

0.5

C

= 220pF, V

= 15V (Note 4)

-

110

200

150

1.25

-

ns

V

OUT

DD

Fall Time

-

90

-

UVLO Output Voltage Clamp

V

= 7V, I

LOAD

= 1mA (Note 6)

-

DD

Output Delay/Advance Range

V

= 2.50V

2

-

ns

V

ADJ

OUTLLN/OUTLRN relative to OUTLL/OUTLR

V

< 2.425V

> 2.575V

-40

40

-300

300

5.000

2.425

ADJ

V

-

ADJ

Delay/Advance Control Voltage Range

OUTLxN Delayed

2.575

0

-

OUTLLN/OUTLRN relative to OUTLL/OUTLR

OUTLxN Advanced

T = +25°C (OUTLx Delayed) (Note 7)

A

-

V

Delay Time

ADJ

V

= 0

-

300

105

70

-

ns

ADJ

V

= 0.5V

= 1.0V

= 1.5V

= 2.0V

ADJ

V

ADJ

V

55

ADJ

V

50

ADJ

T

= +25°C (OUTLxN Delayed)

A

V

= V

-

300

100

68

-

ns

ADJ

REF

V

- 0.5V

- 1.0V

- 1.5V

- 2.0V

ADJ

V

ADJ

V

55

ADJ

V

48

ADJ

THERMAL PROTECTION

Thermal Shutdown

(Note 4)

-

140

125

15

-

°C

Thermal Shutdown Clear

Hysteresis, Internal Protection

NOTES:

4. Limits established by characterization and are not production tested.

5. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained

using other values for these components. See Equations 1 through 3.

6. Adjust V

below the UVLO stop threshold prior to setting at 7V.

DD

7. When OUTLx is delayed relative to OUTLxN (V

< 2.425V), the delay duration as set by V

ADJ

should not exceed 90% of the CT discharge

ADJ

time (deadtime) as determined by CT and RTD.

FN6754.1

September 29, 2008

7

ISL6754

Typical Performance Curves

25

24

23

22

21

20

19

18

1.02

1.01

1

0.99

0.98

-40 -25 -10

5

20

35

50 65

80 95 110

0

200

400

600

800

1000

TEMPERATURE (¬¨Ð

RTD CURRENT (¬¨¬

FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE

FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT

3

1-10

4

1-10

CT = 1000pF

CT = 680pF

CT = 470pF

3

1-10

RTD = 10kΩ

100

CT = 100pF

CT = 220pF

RTD = 50kΩ

RTD = 100kΩ

CT = 330pF

100

10

0

10 20 30 40 50 60 70 80 90 100

0.1

1

10

RTD (kΩ)

CT (nF)

FIGURE 3. DEADTIME (DT) vs CAPACITANCE

FIGURE 4. CAPACITANCE vs FREQUENCY

magnitude of the current that discharges CT. The CT

Pin Descriptions

discharge current is nominally 20x the resistor current. The

PWM deadtime is determined by the timing capacitor

discharge duration. The voltage at RTD is nominally 2.00V.

VDD - VDD is the power connection for the IC. To optimize

noise immunity, bypass VDD to GND with a ceramic

capacitor as close to the VDD and GND pins as possible.

CS - This is the input to the overcurrent comparator. The

overcurrent comparator threshold is set at 1.00 V nominal.

The CS pin is shorted to GND at the termination of either

PWM output.

VDD is monitored for supply voltage undervoltage lock-out

(UVLO). The start and stop thresholds track each other

resulting in relatively constant hysteresis.

GND - Signal and power ground connections for this device.

Due to high peak currents and high frequency operation, a

low impedance layout is necessary. Ground planes and

short traces are highly recommended.

Depending on the current sensing source impedance, a

series input resistor may be required due to the delay

between the internal clock and the external power switch.

This delay may result in CS being discharged prior to the

power switching device being turned off.

VREF - The 5.00V reference voltage output having 3%

tolerance over line, load and operating temperature. Bypass

to GND with a 0.1μF to 2.2μF low ESR capacitor.

RAMP - This is the input for the sawtooth waveform for the

PWM comparator. The RAMP pin is shorted to GND at the

termination of the PWM signal. A sawtooth voltage

waveform is required at this input. For current-mode control

this pin is connected to CS and the current loop feedback

signal is applied to both inputs. For voltage-mode control,

the oscillator sawtooth waveform may be buffered and used

to generate an appropriate signal, RAMP may be connected

to the input voltage through a RC network for voltage feed

forward control, or RAMP may be connected to VREF

CT - The oscillator timing capacitor is connected between

this pin and GND. It is charged through an internal 200μA

current source and discharged with a user adjustable current

source controlled by RTD.

RTD - This is the oscillator timing capacitor discharge

current control pin. The current flowing in a resistor

connected between this pin and GND determines the

FN6754.1

September 29, 2008

8

ISL6754

through a RC network to produce the desired sawtooth

waveform.

control range. This behavior provides the user increased

accuracy when selecting a shorter delay/advance duration.

OUTUL and OUTUR - These outputs control the upper

bridge FETs and operate at a fixed 50% duty cycle in

alternate sequence. OUTUL controls the upper left FET and

OUTUR controls the upper right FET. The left and right

designation may be switched as long as they are switched in

conjunction with the lower FET outputs, OUTLL and OUTLR.

When the PWM outputs are delayed relative to the SR

outputs (VADJ < 2.425V), the delay time should not exceed

90% of the deadtime as determined by RTD and CT.

VERR - The control voltage input to the inverting input of the

PWM comparator. The output of an external error amplifier

(EA) is applied to this input, either directly or through an

opto-coupler, for closed loop regulation. VERR has a

nominal 1mA pull-up current source.

RESDEL - Sets the resonant delay period between the

toggle of the upper FETs and the turn on of either of the

lower FETs. The voltage applied to RESDEL determines

when the upper FETs switch relative to a lower FET turning

on. Varying the control voltage from 0 to 2.00V increases the

resonant delay duration from 0 to 100% of the deadtime. The

control voltage divided by 2 represents the percent of the

deadtime equal to the resonant delay. In practice the

maximum resonant delay must be set lower than 2.00V to

ensure that the lower FETs, at maximum duty cycle, are OFF

prior to the switching of the upper FETs.

When VERR is driven by an opto-coupler or other current

source device, a pull-up resistor from VREF is required to

linearize the gain. Generally, a pull-up resistor on the order

of 5kΩ is acceptable.

FB - FB is the inverting inputs to the error amplifier (EA). The

amplifier may be used as the error amplifier for voltage

feedback or used as the average current limit amplifier (IEA).

If the amplifier is not used, FB should be grounded.

OUTLL and OUTLR - These outputs control the lower

bridge FETs, are pulse width modulated, and operate in

alternate sequence. OUTLL controls the lower left FET and

OUTLR controls the lower right FET. The left and right

designation may be switched as long as they are switched in

conjunction with the upper FET outputs, OUTUL and

OUTUR.

IOUT - Output of the 4X buffer amplifier of the sample and

hold circuitry that captures and averages the CS signal.

SS - Connect the soft-start timing capacitor between this pin

and GND to control the duration of soft-start. The value of

the capacitor and the internal current source determine the

rate of increase of the duty cycle during start-up.

SS may also be used to inhibit the outputs by grounding

through a small transistor in an open collector/drain

configuration.

OUTLLN and OUTLRN - These outputs are the

complements of the PWM (lower) bridge FETs. OUTLLN is

the complement of OUTLL and OUTLRN is the complement

of OUTLR. These outputs are suitable for control of

synchronous rectifiers. The phase relationship between

each output and its complement is controlled by the voltage

applied to VADJ.

CTBUF - CTBUF is the buffered output of the sawtooth

oscillator waveform present on CT and is capable of

sourcing 2mA. It is offset from ground by 0.40V and has a

nominal valley-to-peak gain of 2. It may be used for slope

compensation.

VADJ - A 0V to 5V control voltage applied to this input sets

the relative delay or advance between OUTLL/OUTLR and

OUTLLN/OUTLRN. The phase relationship between

OUTUL/OUTUR and OUTLL/OUTLR is maintained

regardless of the phase adjustment between OUTLL/OUTLR

and OUTLLN/OUTLRN.

Functional Description

Features

The ISL6754 PWM is an excellent choice for low cost ZVS

full-bridge applications requiring adjustable synchronous

rectifier drive. With its many protection and control features,

a highly flexible design with minimal external components is

possible. Among its many features are a very accurate

overcurrent limit threshold, thermal protection, a buffered

sawtooth oscillator output suitable for slope compensation,

synchronous rectifier outputs with variable delay/advance

timing, and adjustable frequency.

Voltages below 2.425V result in OUTLLN/OUTLRN being

advanced relative to OUTLL/OUTLR. Voltages above

2.575V result in OUTLLN/OUTLRN being delayed relative to

OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero

phase difference. A weak internal 50% divider from VREF

results in no phase delay if this input is left floating.

The range of phase delay/advance is either zero or 40 to

300ns with the phase differential increasing as the voltage

deviation from 2.5V increases. The relationship between the

control voltage and phase differential is non-linear. The gain

(Δt/ΔV) is low for control voltages near 2.5V and rapidly

increases as the voltage approaches the extremes of the

If synchronous rectification is not required, please consider

the ISL6755 controller.

Oscillator

The ISL6754 has an oscillator with a programmable

frequency range to 2MHz, which can be programmed with a

resistor and capacitor.

FN6754.1

September 29, 2008

9

ISL6754

The switching period is the sum of the timing capacitor

charge and discharge durations. The charge duration is

determined by CT and a fixed 200µA internal current source.

The discharge duration is determined by RTD and CT.

operation. The DC blocking capacitors used in voltage-mode

bridge topologies become unbalanced, as does the flux in

the transformer core. Average current limit will prevent the

instability and allow continuous operation in current limit

provided the control loop is designed with adequate

bandwidth.

3

T

≈ 11.5 ⋅ 10 ⋅ CT

S

(EQ. 1)

C

D

The propagation delay from CS exceeding the current limit

threshold to the termination of the output pulse is increased

by the leading edge blanking (LEB) interval. The effective

delay is the sum of the two delays and is nominally 105ns.

–9

(EQ. 2)

T

≈ (0.06 ⋅ RTD ⋅ CT) + 50 ⋅ 10

S

1

------------

T

= T + T =

D

S

(EQ. 3)

The current sense signal applied to the CS pin connects to

the peak current comparator and a sample and hold

SW

C

F

SW

averaging circuit. After a 70ns leading edge blanking (LEB)

delay, the current sense signal is actively sampled during the

on time, the average current for the cycle is determined, and

where T and T are the charge and discharge times,

C

D

respectively, CT is the timing capacitor in Farads, RTD is the

discharge programming resistance in ohms, T is the

SW

is the oscillator frequency. One

the result is amplified by 4x and output on the I

pin. If an

OUT

oscillator period, and F

SW

RC filter is placed on the CS input, its time constant should

not exceed ~50ns or significant error may be introduced on

output switching cycle requires two oscillator cycles. The

actual times will be slightly longer than calculated due to

internal propagation delays of approximately 10ns/transition.

This delay adds directly to the switching duration, but also

causes overshoot of the timing capacitor peak and valley

voltage thresholds, effectively increasing the peak-to-peak

voltage on the timing capacitor. Additionally, if very small

discharge currents are used, there will be increased error

due to the input impedance at the CT pin. The maximum

recommended current through RTD is 1mA, which produces

a CT discharge current of 20mA.

I

.

OUT

The maximum duty cycle, D, and percent deadtime, DT, can

be calculated from:

T

C

(EQ. 4)

------------

D =

T

SW

DT = 1 – D

(EQ. 5)

CHANNEL 1 (YELLOW): OUTLL

CHANNEL 3 (BLUE): CS

CHANNEL 2 (RED): OUTLR

CHANNEL 4 (GREEN): IOUT

Overcurrent Operation

FIGURE 5. CS INPUT vs I

OUT

Two overcurrent protection mechanisms are available to the

power supply designer. The first method is cycle-by-cycle

peak overcurrent protection which provides fast response.

The cycle-by-cycle peak current limit results in pulse-by-pulse

duty cycle reduction when the current feedback signal

Figure 5 shows the relationship between the CS signal and

under steady state conditions. I is 4x the average

of CS. Figure 6 shows the dynamic behavior of the current

averaging circuitry when CS is modulated by an external

I

OUT

sine wave. Notice I

is updated by the sample and hold

exceeds 1.0V. When the peak current exceeds the threshold,

the active output pulse is immediately terminated. This results

in a decrease in output voltage as the load current increases

beyond the current limit threshold. The ISL6754 operates

continuously in an overcurrent condition without shutdown.

OUT

circuitry at the termination of the active output pulse.

The second method is a slower, averaging method which

produces constant or “brick-wall” current limit behavior. If

voltage-mode control is used, the average overcurrent

protection also maintains flux balance in the transformer by

maintaining duty cycle symmetry between half-cycles. If

voltage-mode control is used in a bridge topology, it should

be noted that peak current limit results in inherently unstable

FN6754.1

September 29, 2008

10

ISL6754

The EA available on the ISL6754 may also be used as the

voltage EA for the voltage feedback control loop rather than

the current EA as described above. An external op-amp may

be used as either the current or voltage EA providing the

circuit is not allowed to source current into VERR. The

external EA must only sink current, which may be

accomplished by adding a diode in series with its output.

The 4x gain of the sample and hold buffer allows a range of

150 - 1000mV peak on the CS signal, depending on the

resistor divider placed on I

. The overall bandwidth of the

OUT

average current loop is determined by the integrating current

EA compensation and the divider on I

.

OUT

1

20

19

18

17

16

15

14

13

VREF

SS

CHANNEL 1 (YELLOW): OUTLL

CHANNEL 3 (BLUE): CS

CHANNEL 2 (RED): OUTLR

CHANNEL 4 (GREEN): IOUT

2

3

VERR

VDD

ISL6754

FIGURE 6. DYNAMIC BEHAVIOR OF CS vs I

4

OUTLL

OUTLR

OUTUL

OUTUR

N/C

OUT

5

The average current signal on I

remains accurate

OUT

C10

6

provided the output inductor current remains continuous

(CCM operation). Once the inductor current becomes

-

7

FB

0.6V

+

discontinuous (DCM operation), I

represents 1/2 the

OUT

8

peak inductor current rather than the average current. This

occurs because the sample and hold circuitry is active only

during the on time of the switching cycle. It is unable to

detect when the inductor current reaches zero during the off

time.

150 - 1000 mV

S&H

4x

9

12 GND

11 GND

CS

10

IOUT

R6

R5

R4

If average overcurrent limit is desired, I

may be used

with the error amplifier of the ISL6754. Typically I is

OUT

divided down and filtered as required to achieve the desired

amplitude. The resulting signal is input to the current error

amplifier (IEA). The IEA is similar to the voltage EA found in

most PWM controllers, except it cannot source current.

Instead, VERR has a separate internal 1mA pull-up current

source.

FIGURE 7. AVERAGE OVERCURRENT IMPLEMENTATION

The current EA cross-over frequency, assuming R6 >>

(R4||R5), is:

1

(EQ. 6)

-----------------------------------

f

=

Hz

CO

2π ⋅ R6 ⋅ C10

Configure the IEA as an integrating (Type I) amplifier using

the internal 0.6V reference. The voltage applied at FB is

integrated against the 0.6V reference. The resulting signal,

VERR, is applied to the PWM comparator where it is

compared to the sawtooth voltage on RAMP. If FB is less

than 0.6V, the IEA will be open loop (can’t source current),

VERR will be at a level determined by the voltage loop, and

the duty cycle is unaffected. As the output load increases,

where f

CO

is the cross-over frequency. A capacitor in parallel

with R4 may be used to provide a double-pole roll-off.

The average current loop bandwidth is normally set to be

much less than the switching frequency, typically less than

5kHz and often as slow as a few hundred hertz or less. This

is especially useful if the application experiences large

surges. The average current loop can be set to the steady

state overcurrent threshold and have a time response that is

longer than the required transient. The peak current limit can

be set higher than the expected transient so that it does not

interfere with the transient, but still protects for short-term

larger faults. In essence a 2-stage overcurrent response is

possible.

I

will increase, and the voltage applied to FB will

OUT

increase until it reaches 0.6V. At this point the IEA will

reduce VERR as required to maintain the output current at

the level that corresponds to the 0.6V reference. When the

output current again drops below the average current limit

threshold, the IEA returns to an open loop condition, and the

duty cycle is again controlled by the voltage loop.

The average current control loop behaves much the same

as the voltage control loop found in typical power supplies

except it regulates current rather than voltage.

The peak overcurrent behavior is similar to most other PWM

controllers. If the peak current exceeds 1.0V, the active

output pulse is terminated immediately.

FN6754.1

September 29, 2008

11

ISL6754

If voltage-mode control is used in a bridge topology, it should

selected so that the ramp amplitude reaches 1.0V at

be noted that peak current limit results in inherently unstable

operation. DC blocking capacitors used in voltage-mode

bridge topologies become unbalanced, as does the flux in

the transformer core. The average overcurrent circuitry

prevents this behavior by maintaining symmetric duty cycles

for each half-cycle. If the average current limit circuitry is not

used, a latching overcurrent shutdown method using

external components is recommended.

minimum input voltage within the duration of one half-cycle.

1

2

20

19

18

17

16

15

14

13

12

VIN

3

4

ISL6754

R3

C7

5

6

7

The CS to output propagation delay is increased by the

leading edge blanking (LEB) interval. The effective delay is

the sum of the two delays and is 130ns maximum.

8

RAMP

9

10

GND 11

Voltage Feed Forward Operation

Voltage feed forward is a technique used to regulate the

output voltage for changes in input voltage without the

intervention of the control loop. Voltage feed forward is

implemented in voltage-mode control loops, but is redundant

and unnecessary in peak current-mode control loops.

FIGURE 9. VOLTAGE FEED FORWARD CONTROL

The charging time of the ramp capacitor is:

Voltage feed forward operates by modulating the sawtooth

ramp in direct proportion to the input voltage. Figure 8

demonstrates the concept.

V

⎛

⎞

⎟

⎠

RAMP(PEAK)

---------------------------------------

t = –R3 ⋅ C7 ⋅ ln 1 –

S

⎜

(EQ. 7)

V

⎝

IN(MIN)

For optimum performance, the maximum value of the

VIN

capacitor should be limited to 10nF. The maximum DC

current through the resistor should be limited to 2mA

maximum. For example, if the oscillator frequency is

400kHz, the minimum input voltage is 300V, and a 4.7nF

ramp capacitor is selected, the value of the resistor can be

determined by rearranging Equation 7.

ERROR VOLTAGE

RAMP

CT

–6

–t

-------------------------------------------------------------------------

–2.5 ⋅ 10

------------------------------------------------------------

=

R3 =

–9

1

⎞

---------

V

⎛

⎞

⎟

⎠

⎛

RAMP(PEAK)

4.7 ⋅ 10 ⋅ ln 1 –

---------------------------------------

C7 ⋅ ln 1 –

⎜

⎝

⎠

300

V

⎝

IN(MIN))

OUTLL, LR

= 159

kΩ

(EQ. 8)

FIGURE 8. VOLTAGE FEED FORWARD BEHAVIOR

where t is equal to the oscillator period minus the deadtime.

If the deadtime is short relative to the oscillator period, it can

be ignored for this calculation.

Input voltage feed forward may be implemented using the

RAMP input. An RC network connected between the input

voltage and ground, as shown in Figure 9, generates a

voltage ramp whose charging rate varies with the amplitude

of the source voltage. At the termination of the active output

pulse, RAMP is discharged to ground so that a repetitive

sawtooth waveform is created. The RAMP waveform is

compared to the VERR voltage to determine duty cycle. The

selection of the RC components depends upon the desired

input voltage operating range and the frequency of the

oscillator. In typical applications, the RC components are

If feed forward operation is not desired, the RC network may

be connected to V

rather than the input voltage.

REF

Alternatively, a resistor divider from CTBUF may be used as

the sawtooth signal. Regardless, a sawtooth waveform must

be generated on RAMP as it is required for proper PWM

operation.

Gate Drive

The ISL6754 outputs are capable of sourcing and sinking

10mA (at rated VOH, VOL) and are intended to be used in

conjunction with integrated FET drivers or discrete bipolar

totem pole drivers. The typical on resistance of the outputs is

50Ω.

FN6754.1

September 29, 2008

12

ISL6754

V can be solved for in terms of input voltage, current

Slope Compensation

n

transducer components, and output inductance yielding:

Peak current-mode control requires slope compensation to

improve noise immunity, particularly at lighter loads, and to

prevent current loop instability, particularly for duty cycles

greater than 50%. Slope compensation may be

T

⋅ V ⋅ R

CS

O

N

SW

1

S

⎝

π

P

⎛

⎞

----------------------------------------- ------- --

V

=

⋅

+ D – 0.5

V

(EQ. 15)

e

⎠

N

⋅ L

N

CT

O

accomplished by summing an external ramp with the current

feedback signal or by subtracting the external ramp from the

voltage feedback error signal. Adding the external ramp to

the current feedback signal is the more popular method.

where R

is the current sense burden resistor, N is the

CT

CS

current transformer turns ratio, L is the output inductance,

O

V

is the output voltage, and N and N are the secondary

O

S P

and primary turns, respectively.

From the small signal current-mode model [1] it can be

shown that the naturally-sampled modulator gain, Fm,

without slope compensation, is:

The inductor current, when reflected through the isolation

transformer and the current sense transformer to obtain the

current feedback signal at the sense resistor yields:

N

⋅ R

D ⋅ T

N

S

N

P

⎛

⎜

⎝

⎛

⎜

⎝

⎞⎞

⎟⎟

⎠⎠

1

S

CS

SW

-------------------

Fm =

------------------------

--------------------

-------

(EQ. 16)

(EQ. 9)

V

=

I

+

V

⋅

– V

O

V

CS

O

IN

SnTsw

N

⋅ N

2L

O

P

CT

where Sn is the slope of the sawtooth signal and Tsw is the

duration of the half-cycle. When an external ramp is added,

the modulator gain becomes:

where V

is the voltage across the current sense resistor

CS

and I is the output current at current limit.

O

Since the peak current limit threshold is 1.00V, the total

current feedback signal plus the external ramp voltage must

sum to this value.

1

(EQ. 10)

--------------------------------------

---------------------------

Fm =

=

(Sn + Se)Tsw

m SnTsw

c

V

+ V

= 1

CS

(EQ. 17)

where Se is slope of the external ramp and

Se

e

-------

= 1 +

m

(EQ. 11)

c

Sn

Substituting Equations 15 and 16 into Equation 17 and

solving for R yields:

CS

⋅ N

The criteria for determining the correct amount of external

ramp can be determined by appropriately setting the

damping factor of the double-pole located at half the

oscillator frequency. The double-pole will be critically

damped if the Q-factor is set to 1, and over-damped for

Q > 1, and under-damped for Q < 1. An under-damped

condition can result in current loop instability.

N

1

P

CT

----------------------- ------------------------------------------------------

R

=

⋅

Ω

(EQ. 18)

CS

N

V

O

1

π

D

2

S

⎛

⎝

⎞

⎠

-------

-- ---

+

I

+

T

O

SW

L

O

For simplicity, idealized components have been used for this

discussion, but the effect of magnetizing inductance must be

considered when determining the amount of external ramp

to add. Magnetizing inductance provides a degree of slope

compensation to the current feedback signal and reduces

the amount of external ramp required. The magnetizing

inductance adds primary current in excess of what is

reflected from the inductor current in the secondary.

1

(EQ. 12)

-------------------------------------------------

Q =

π(m (1 – D) – 0.5)

c

where D is the percent of on time during a half cycle. Setting

Q = 1 and solving for S yields:

e

1

π

1

⎛⎛

⎝⎝

⎞

– 1

(EQ. 13)

--

-------------

S

= S

+ 0.5

V

⋅ DT

SW

e

n

IN

⎠

1 – D

(EQ. 19)

-------------------------------

ΔI

=

A

P

L

m

Since S and S are the on time slopes of the current ramp

n

e

where V is the input voltage that corresponds to the duty

IN

and the external ramp, respectively, they can be multiplied

by T to obtain the voltage change that occurs during T

cycle D and L is the primary magnetizing inductance. The

.

m

ON ON

effect of the magnetizing current at the current sense

resistor, R , is:

CS

1

π

1

⎛⎛

⎝⎝

⎞

– 1

--

-------------

V

= V

+ 0.5

(EQ. 14)

e

n

⎠

1 – D

ΔI ⋅ R

P

CS

(EQ. 20)

-------------------------

ΔV

=

V

CS

N

where V is the change in the current feedback signal during

CT

n

the on time and V is the voltage that must be added by the

e

external ramp.

FN6754.1

September 29, 2008

13

ISL6754

If ΔV

CS

is greater than or equal to V , then no additional

Example:

e

slope compensation is needed and R

becomes:

CS

V

L

= 280V

= 12V

IN

N

CT

-------------------------------------------------------------------------------------------------------------------------------------

R

=

CS

O

N

DT

N

V

⋅ DT

⎛

⎞⎞

⎟⎟

⎠⎠

S

SW

S

IN SW

-------

----------------

-------

-------------------------------

⋅ I

+

⋅ V

⋅

– V

O

+

⎜

O

IN

= 2.0µH

N

P

2L

O

N

P

L

O

⎝

m

(EQ. 21)

Np/Ns = 20

Lm = 2mH

If ΔV is less than Ve, then Equation 16 is still valid for the

CS

value of R , but the amount of slope compensation added

CS

I

= 55A

O

by the external ramp must be reduced by ΔV

.

CS

Oscillator Frequency, Fsw = 400kHz

Duty Cycle, D = 85.7%

Adding slope compensation may be accomplished in the

ISL6754 using the CTBUF signal. CTBUF is an amplified

representation of the sawtooth signal that appears on the CT

pin. It is offset from ground by 0.4V and is 2x the peak-to-

peak amplitude of CT (0.4V to 4.4V). A typical application

sums this signal with the current sense feedback and applies

the result to the CS pin as shown in Figure 10.

N

= 50

CT

R6 = 499Ω

Solve for the current sense resistor, R , using Equation 18.

CS

R

= 15.1Ω.

CS

Determine the amount of voltage, V , that must be added to

e

the current feedback signal using Equation 15.

1

2

20

19

Ve = 153mV

3

18

CTBUF

Next, determine the effect of the magnetizing current from

Equation 20.

4

17

5

16

ISL6754

R9

6

15

ΔV

CS

= 91mV

7

14

Using Equation 23, solve for the summing resistor, R9, from

CTBUF to CS.

8

RAMP

CS

13

9

12

R9 = 30.1kΩ

R6

10

GND 11

R_CS

C4

Determine the new value of R , R’ , using Equation 24.

CS CS

R’

CS

= 15.4Ω

The above discussion determines the minimum external

ramp that is required. Additional slope compensation may be

considered for design margin.

FIGURE 10. ADDING SLOPE COMPENSATION

If the application requires deadtime less than about 500ns,

the CTBUF signal may not perform adequately for slope

compensation. CTBUF lags the CT sawtooth waveform by

300ns to 400ns. This behavior results in a non-zero value of

CTBUF when the next half-cycle begins when the deadtime

is short.

Assuming the designer has selected values for the RC filter

placed on the CS pin, the value of R9 required to add the

appropriate external ramp can be found by superposition.

(D(V

– 0.4) + 0.4) ⋅ R6

CTBUF

------------------------------------------------------------------------------

(EQ. 22)

V

– ΔV

=

CS

V

e

R6 + R9

Rearranging to solve for R9 yields:

Under these situations, slope compensation may be added

by externally buffering the CT signal as shown in Figure 11.

(D(V

– 0.4) – V + ΔV

+ 0.4) ⋅ R6

CS

CTBUF

e

------------------------------------------------------------------------------------------------------------------

R9 =

Ω

V

– ΔV

CS

e

(EQ. 23)

The value of R

determined in Equation 18 or 21 must be

CS

rescaled so that the current sense signal presented at the

CS pin is that predicted by Equation 16. The divider created

by R6 and R9 makes this necessary.

R6 + R9

R9

----------------------

⋅ R

CS

(EQ. 24)

R′

=

CS

FN6754.1

September 29, 2008

14

ISL6754

1

2

20

19

VREF

CT

ISL6754

3

18

DEADTIME

OUTLL

4

17

PWM

5

16

CT

6

15

R9

7

14

PWM

OUTLR

OUTUR

8

RAMP

CS

13

9

12

R6

RESONANT

DELAY

10

GND 11

OUTUL

RESDEL

WINDOW

R_CS

C4

CT

FIGURE 12. BRIDGE DRIVE SIGNAL TIMING

To understand how the ZVS method operates one must

include the parasitic elements of the circuit and examine a

full switching cycle.

FIGURE 11. ADDING SLOPE COMPENSATION USING CT

Using CT to provide slope compensation instead of CTBUF

requires the same calculations, except that Equations 22

and 23 require modification. Equation 22 becomes:

VIN+

UL

UR

D1

VOUT+

RTN

L_L

2D ⋅ R6

R6 + R9

----------------------

V

– ΔV

=

CS

V

(EQ. 25)

e

and Equation 23 becomes:

LL

LR

D2

(2D – V + ΔV ) ⋅ R6

e

CS

------------------------------------------------------------

(EQ. 26)

R9 =

Ω

VIN-

V

– ΔV

CS

e

FIGURE 13. IDEALIZED FULL-BRIDGE

The buffer transistor used to create the external ramp from

CT should have a sufficiently high gain (>200) so as to

minimize the required base current. Whatever base current

is required reduces the charging current into CT and will

reduce the oscillator frequency.

In Figure 13, the power semiconductor switches have been

replaced by ideal switch elements with parallel diodes and

capacitance, the output rectifiers are ideal, and the

transformer leakage inductance has been included as a

discrete element. The parasitic capacitance has been

lumped together as switch capacitance, but represents all

parasitic capacitance in the circuit including winding

capacitance. Each switch is designated by its position, upper

left (UL), upper right (UR), lower left (LL), and lower right

(LR). The beginning of the cycle, shown in Figure 14, is

arbitrarily set as having switches UL and LR on and UR and

LL off. The direction of the primary and secondary currents

ZVS Full-Bridge Operation

The ISL6754 is a full-bridge zero-voltage switching (ZVS)

PWM controller that behaves much like a traditional hard-

switched topology controller. Rather than drive the diagonal

bridge switches simultaneously, the upper switches (OUTUL,

OUTUR) are driven at a fixed 50% duty cycle and the lower

switches (OUTLL, OUTLR) are pulse width modulated on

the trailing edge.

are indicated by I and I , respectively.

P

S

VIN+

UL

UR

I_S

D1

VOUT+

RTN

L_L

I_P

LL

LR

D2

VIN-

FIGURE 14. UL - LR POWER TRANSFER CYCLE

FN6754.1

September 29, 2008

15

ISL6754

The UL - LR power transfer period terminates when switch

LR turns off as determined by the PWM. The current flowing

in the primary cannot be interrupted instantaneously, so it

must find an alternate path. The current flows into the

parasitic switch capacitance of LR and UR which charges

the node to VIN and then forward biases the body diode of

upper switch UR.

where τ is the resonant transition time, L is the leakage

L

inductance, C is the parasitic capacitance, and R is the

P

equivalent resistance in series with L and C .

L

P

The resonant delay is always less than or equal to the

deadtime and may be calculated using Equation 28.

V

resdel

2

-------------------

τ

=

⋅ DT

S

(EQ. 28)

resdel

VIN+

UL

UR

I_S

D1

where τ

resdel

is the desired resonant delay, V is a

resdel

VOUT+

RTN

L_L

voltage between 0V and 2V applied to the RESDEL pin, and

DT is the deadtime (see Equations 1 through 5).

I_P

When the upper switches toggle, the primary current that

was flowing through UL must find an alternate path. It

charges/discharges the parasitic capacitance of switches UL

and LL until the body diode of LL is forward biased. If

RESDEL is set properly, switch LL will be turned on at this

time. The output inductor does not assist this transition. It is

LL

LR

D2

VIN-

FIGURE 15. UL - UR FREE-WHEELING PERIOD

The primary leakage inductance, L , maintains the current

L

VIN+

which now circulates around the path of switch UL, the

transformer primary, and switch UR. When switch LR opens,

the output inductor current free-wheels through both output

diodes, D1 and D2. During the switch transition, the output

inductor current assists the leakage inductance in charging

the upper and lower bridge FET capacitance.

UL

UR

I_S

D1

VOUT+

RTN

L_L

I_P

LL

LR

D2

The current flow from the previous power transfer cycle

tends to be maintained during the free-wheeling period

because the transformer primary winding is essentially

shorted. Diode D1 may conduct very little or none of the

free-wheeling current, depending on circuit parasitics. This

behavior is quite different than occurs in a conventional

hard-switched full-bridge topology where the free-wheeling

current splits nearly evenly between the output diodes, and

flows not at all in the primary.

VIN-

FIGURE 16. UPPER SWITCH TOGGLE AND RESONANT

TRANSITION

purely a resonant transition driven by the leakage

inductance.

The second power transfer period commences when switch

LL closes. With switches UR and LL on, the primary and

secondary currents flow as indicated in Figure 17.

This condition persists through the remainder of the half-

cycle.

VIN+

During the period when CT discharges, also referred to as

the deadtime, the upper switches toggle. Switch UL turns off

and switch UR turns on. The actual timing of the upper

switch toggle is dependent on RESDEL which sets the

resonant delay. The voltage applied to RESDEL determines

how far in advance the toggle occurs prior to a lower switch

turning on. The ZVS transition occurs after the upper

switches toggle and before the diagonal lower switch turns

on. The required resonant delay is 1/4 of the period of the LC

resonant frequency of the circuit formed by the leakage

inductance and the parasitic capacitance. The resonant

transition may be estimated from Equation 27.

UL

UR

D1

VOUT+

RTN

L_L

LL

LR

D2

VIN-

FIGURE 17. UR - LL POWER TRANSFER CYCLE

The UR - LL power transfer period terminates when switch

LL turns off as determined by the PWM. The current flowing

in the primary must find an alternate path. The current flows

into the parasitic switch capacitance which charges the node

π

2

1

-------------------------------------

τ =

(EQ. 27)

2

1

R

-------------- ---------

–

2

L

L C

L

P

4L

to V and then forward biases the body diode of upper

IN

switch UL. As before, the output inductor current assists in

this transition. The primary leakage inductance, L ,

L

FN6754.1

September 29, 2008

16

ISL6754

maintains the current, which now circulates around the path

of switch UR, the transformer primary, and switch UL. When

switch LL opens, the output inductor current free-wheels

predominantly through diode D1. Diode D2 may actually

conduct very little or none of the free-wheeling current,

depending on circuit parasitics. This condition persists

through the remainder of the half-cycle.

opposite PWM output, i.e. OUTLL and OUTLRN are paired

together and OUTLR and OUTLLN are paired together.

CT

OUTLL

VIN+

UL

UR

I_S

D1

OUTLR

VOUT+

RTN

L_L

I_P

OUTLLN

(SR1)

LL

LR

OUTLRN

(SR2)

D2

VIN-

FIGURE 18. UR - UL FREE-WHEELING PERIOD

FIGURE 20. BASIC WAVEFORM TIMING

When the upper switches toggle, the primary current that

was flowing through UR must find an alternate path. It

charges/discharges the parasitic capacitance of switches UR

and LR until the body diode of LR is forward biased. If

RESDEL is set properly, switch LR will be turned on at this

time.

Referring to Figure 20, the SRs alternate between being both

on during the free-wheeling portion of the cycle (OUTLL/LR

off), and one or the other being off when OUTLL or OUTLR is

on. If OUTLL is on, its corresponding SR must also be on,

indicating that OUTLRN is the correct SR control signal.

Likewise, if OUTLR is on, its corresponding SR must also be

on, indicating that OUTLLN is the correct SR control signal.

VIN+

UL

UR

I_S

D1

A useful feature of the ISL6754 is the ability to vary the

phase relationship between the PWM outputs (OUTLL, OUT

LR) and the their complements (OUTLLN, OUTLRN) by

±300ns. This feature allows the designer to compensate for

differences in the propagation times between the PWM FETs

VOUT+

RTN

L_L

I_P

LL

LR

D2

and the SR FETs. A voltage applied to V

phase relationship.

controls the

ADJ

VIN-

FIGURE 19. UPPER SWITCH TOGGLE AND RESONANT

TRANSITION

CT

The first power transfer period commences when switch LR

closes and the cycle repeats. The ZVS transition requires

that the leakage inductance has sufficient energy stored to

OUTLL

fully charge the parasitic capacitances. Since the energy

2

stored is proportional to the square of the current (1/2 L I ),

L P

OUTLR

the ZVS resonant transition is load dependent. If the leakage

inductance is not able to store sufficient energy for ZVS, a

discrete inductor may be added in series with the

transformer primary.

OUTLLN

(SR1)

OUTLRN

(SR2)

Synchronous Rectifier Outputs and Control

The ISL6754 provides double-ended PWM outputs, OUTLL

and OUTLR, and synchronous rectifier (SR) outputs,

OUTLLN and OUTLRN. The SR outputs are the

complements of the PWM outputs. It should be noted that

the complemented outputs are used in conjunction with the

FIGURE 21. WAVEFORM TIMING WITH PWM OUTPUTS

DELAYED, 0V < V < 2.425V

ADJ

FN6754.1

September 29, 2008

17

ISL6754

On/Off Control

The ISL6754 does not have a separate enable/disable

control pin. The PWM outputs, OUTLL/OUTLR, may be

disabled by pulling VERR to ground. Doing so reduces the

duty cycle to zero, but the upper 50% duty cycle outputs,

OUTUL/OUTUR, will continue operation. Likewise, the SR

outputs OUTLLN/OUTLRN will be active high.

CT

OUTLL

OUTLR

Pulling Soft-Start to ground will disable all outputs and set

them to a low condition

OUTLLN

(SR1)

Fault Conditions

A fault condition occurs if V

REF

or V fall below their

DD

OUTLRN

(SR2)

undervoltage lockout (UVLO) thresholds or if the thermal

protection is triggered. When a fault is detected the outputs

are disabled low. When the fault condition clears the outputs

are re-enabled.

FIGURE 22. WAVEFORM TIMING WITH SR OUTPUTS

DELAYED, 2.575V < VADJ < 5.00V

An overcurrent condition is not considered a fault and does

not result in a shutdown.

Setting VADJ to V

/2 results in no delay on any output.

REF

The no delay voltage has a ±75mV tolerance window.

Control voltages below the V /2 zero delay threshold

Thermal Protection

REF

cause the PWM outputs, OUTLL/LR, to be delayed. Control

voltages greater than the V /2 zero delay threshold cause

Internal die over temperature protection is provided. An

integrated temperature sensor protects the device should

the junction temperature exceed +140°C. There is

approximately +15°C of hysteresis.

REF

the SR outputs, OUTLLN/LRN, to be delayed. It should be

noted that when the PWM outputs, OUTLL/LR, are delayed,

the CS to output propagation delay is increased by the

amount of the added delay.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the

The delay feature is provided to compensate for mismatched

propagation delays between the PWM and SR outputs as

may be experienced when one set of signals crosses the

primary-secondary isolation boundary. If required, individual

output pulses may be stretched or compressed as required

using external resistors, capacitors, and diodes.

device. A good ground plane must be employed. V

and

DD

should be bypassed directly to GND with good high

V

REF

frequency capacitance.

References

[1] Ridley, R., “A New Continuous-Time Model for Current

Mode Control”, IEEE Transactions on Power

Electronics, Vol. 6, No. 2, April 1991.

When the PWM outputs are delayed, the 50% upper outputs

are equally delayed, so the resonant delay setting is

unaffected.

FN6754.1

September 29, 2008

18

ISL6754

Shrink Small Outline Plastic Packages (SSOP)

Quarter Size Outline Plastic Packages (QSOP)

N

M20.15

INDEX

0.25(0.010)

M

B M

H

AREA

20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

(0.150” WIDE BODY)

E

GAUGE

PLANE

-B-

INCHES

MIN

MILLIMETERS

SYMBOL

MAX

0.069

0.010

0.061

0.012

0.010

0.344

0.157

MIN

1.35

0.10

-

MAX

1.75

0.25

1.54

0.30

0.25

8.74

3.98

NOTES

1

2

3

A

A1

A2

B

0.053

0.004

-

L

-

0.25

0.010

SEATING PLANE

A

-

-A-

D

h x 45¬

0.008

0.007

0.337

0.150

0.20

0.18

8.56

3.81

9

C

D

E

-

-C-

α

3

A2

e

A1

4

C

B

0.10(0.004)

e

0.025 BSC

0.635 BSC

-

0.17(0.007) M

C

A M B S

H

h

0.228

0.0099

0.016

0.244

0.0196

0.050

5.80

0.26

0.41

6.19

0.49

1.27

-

5

NOTES:

L

6

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

N

α

20

7

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

0°

8°

0°

8°

-

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

Rev. 1 6/04

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable dam-

bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” di-

mension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6754.1

September 29, 2008

19


型号：	ISL6754
厂家：	Intersil
描述：	ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control ZVS全桥PWM控制器，可调节同步整流控制控制器
文件：	总19页 (文件大小：534K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6754 [INTERSIL]

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