ISL70001SRHF [INTERSIL]
Rad Hard and SEE Hard 6A Synchronous Buck Regulator; 抗辐射,并请参阅硬盘6A同步降压稳压器型号: | ISL70001SRHF |
厂家: | Intersil |
描述: | Rad Hard and SEE Hard 6A Synchronous Buck Regulator |
文件: | 总17页 (文件大小:583K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Rad Hard and SEE Hard 6A Synchronous Buck Regulator
ISL70001SEH
Features
The ISL70001SEH is a radiation hardened and SEE hardened
high efficiency monolithic synchronous buck regulator with
integrated MOSFETs. This single chip power solution operates
over an input voltage range of 3V to 5.5V and provides a tightly
regulated output voltage that is externally adjustable from 0.8V
to ~85% of the input voltage. Output load current capacity is 6A
• ±1% Reference Voltage Over Line, Load, Temperature and
Radiation
• Current Mode Control for Excellent Dynamic Response
• Full Mil-Temp Range Operation (T = -55°C to +125°C)
A
• High Efficiency > 90%
for T < +145°C.
J
• Fixed 1MHz Operating Frequency
• Operates from 3V to 5.5V Supply
• Adjustable Output Voltage
High integration and class leading radiation tolerance makes
the ISL70001SEH an ideal choice to power many of today’s
small form factor applications. Two devices can be
- Two External Resistors Set V
OUT
• Bi-directional SYNC Pin Allows Two Devices to be Synchronized
180° Out-of-Phase
from 0.8V to ~85% of V
IN
synchronized to provide a complete power solution for large
scale digital ICs, like field programmable gate arrays (FPGAs),
that require separate core and I/O voltages.
• Device Enable with Comparator Type Input
• Power-Good Output Voltage Monitor
• Adjustable Analog Soft-Start
Applications
• FPGA, CPLD, DSP, CPU Core or I/O Voltages
• Low-Voltage, High-Density Distributed Power Systems
• Input Undervoltage, Output Undervoltage and Output
Overcurrent Protection
Related Literature
• ISL70001SRHEVAL1Z Evaluation Board, AN1518
• Starts Into Pre-Biased Load
• Electrically Screened to DLA SMD 5962-09225
• QML Qualified per MIL-PRF-38535 Requirements
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed in the Ordering Information table on page 2 must
be used when ordering.
• Radiation Hardness
- Total Dose [50-300rad(Si)/s] . . . . . . . . . . .100krad(Si) min
- Total Dose [<10mrad(Si)/s] . . . . . . . . . . . . .50krad(Si) min
Detailed Electrical Specifications for these devices are contained
in SMD 5962-09225. This link is also available on the
ISL70001SEH device information page on the Intersil web site.
• SEE Hardness
- SEL and SEB LET . . . . . . . . . . . . 86.4MeV/mg/cm min
2
-6
eff
2
2
- SEFI X-section (LET = 86.4MeV/mg/cm ) 1.4 x 10 cm
eff
max
2
- SET LET (< 1 Pulse Perturbation) 86.4MeV/mg/cm min
eff
95
90
85
80
75
70
5V SUPPLY
ISL70001SEH
CORE
AUX
I/O
SYNCH
RAD TOLERANT
FPGA
RAD HARD LDO
ISL70001SEH
0
1
2
3
4
5
6
LOAD CURRENT (A)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. EFFICIENCY 5V INPUT TO 3.3V OUTPUT, T = +25°C
A
November 30, 2011
FN7956.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL70001SEH
Functional Block Diagram
POWER-ON
RESET (POR)
PORSEL
PVINx
CURRENT
SENSE
SLOPE
COMPENSATION
SOFT
START
SS
PWM
CONTROL
LOGIC
GATE
DRIVE
LXx
EA
GM
FB
COMPENSATION
PGNDx
UV
POWER-GOOD
PGOOD
REF
PWM
REFERENCE
0.6V
TDI
BIT
TDO
TRIM
ZAP
SYNC
M/S
Ordering Information
PART NUMBER
(Note 2)
TEMP. RANGE
(°C)
ORDERING NUMBER
5962R0922502VXC
5962R0922502V9A
ISL70001SRHF/PROTO
ISL70001SRHX/SAMPLE
ISL70001SRHEVAL1Z
NOTES:
PACKAGE
ISL70001SEHVF (Note 1)
ISL70001SEHVX
-55 to +125
-55 to +125
-55 to +125
-55 to +125
48 Ld CQFP (Pb-Free)
Die
ISL70001SRHF/PROTO (Note 1)
ISL70001SRHX/SAMPLE
Evaluation Board
48 Ld CQFP (Pb-Free)
Die
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70001SEH. For more information on MSL, please see Tech Brief
TB363.
FN7956.0
November 30, 2011
2
ISL70001SEH
Pin Configuration
ISL70001SEH
(48 LD CQFP)
TOP VIEW
6
5
4
3
2
1
48 47 46 45 44 43
42
PVIN3
LX3
7
M/S
ZAP
TDI
41
40
39
38
37
8
PGND3
PGND3
PGND4
PGND4
LX4
9
10
11
12
13
14
15
16
17
18
TDO
PGOOD
SS
36
35
34
33
32
31
DVDD
DVDD
DGND
DGND
AGND
AGND
PVIN4
PVIN4
PVIN5
PVIN5
LX5
19 20 21 22 23 24 25 26 27 28 29 30
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2, 27, 28, 29, 30,
37, 38, 39, 40, 47,
48
PGNDx
These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins
directly to the ground plane. These pins should also connect to the negative terminals of the input and output
capacitors. Locate the input and output capacitors as close as possible to the IC.
3, 26, 31, 36, 41,
46
LXx
These pins are the outputs of the corresponding internal power blocks and should be connected to the output
filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize
voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The
Schottky diode should be located as close as possible to the IC.
4, 5, 24, 25, 32, 33,
34, 35, 42, 43, 44,
45
PVINx
SYNC
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly
to PGNDx with ceramic capacitors located as close as possible to the IC.
6
This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the
SYNC input of another ISL70001SEH. When configured as an input (Slave Mode), this pin accepts the SYNC
output from another ISL70001SEH or an external clock. Synchronization of the slave unit is 180° out-of-phase
with respect to the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the
frequency must be within the range of 1MHz ±20%.
7
M/S
This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For SYNC = Output
(Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND.
8
9
ZAP
TDI
This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND.
This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.
This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.
10
11
TDO
PGOOD
This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output
voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,
independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin
to DGND with a 10nF ceramic capacitor to mitigate SEE.
FN7956.0
November 30, 2011
3
ISL70001SEH
Pin Descriptions(Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
12
SS
This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output
ramp time in accordance with Equation 1:
t
= C ⋅ V ⁄ I
REF SS
(EQ. 1)
SS
SS
where:
t
C
= Soft-start output ramp time
= Soft-start capacitor
SS
SS
V
= Reference voltage (0.6V typical)
REF
I
= Soft-start charging current (23µA typical)
SS
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
13, 14
DVDD
These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the
IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter
components as close as possible to the IC.
15, 16
17, 18
19
DGND
AGND
AVDD
REF
These pins are the digital ground associated with the internal digital control circuitry. Connect these pins
directly to the ground plane.
These pins are the analog ground associated with the internal analog control circuitry. Connect these pins
directly to the ground plane.
This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω
resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC.
20
This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor
located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or
sinking) is available from this pin.
21
FB
This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and
from FB to AGND to adjust the output voltage in accordance with Equation 2:
V
= V
⋅ [1 + (R ⁄ R )]
REF T B
(EQ. 2)
OUT
where:
= Output voltage
V
OUT
V
= Reference voltage (0.6V typical)
REF
R = Top divider resistor (Must be 1kΩ)
T
R
= Bottom divider resistor
B
The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate SEE
and to improve stability margins.
22
23
EN
This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and
programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF
ceramic capacitor to mitigate SEE.
PORSEL
This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V
supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply
voltages between 5V and 3.3V, connect this pin to DGND.
FN7956.0
November 30, 2011
4
ISL70001SEH
Typical Application Schematic
LX1
LX2
LX3
LX4
LX5
LX6
PVIN1
PVIN2
PVIN3
PVIN4
PVIN5
PVIN6
5V
100µF
1µF
1µF
1µH
1.8V
6A
470µF
20V
3A
1kΩ
1
AVDD
FB
1µF
ISL70001SEH
0V TO 5.5V
499Ω
AGND
DVDD
1
PGOOD
10nF
1µF
VSENSE
SYNC
REF
DGND
EN
220nF
10nF
M/S
PORSEL
TDI
SS
TDO
ZAP
100nF
FIGURE 3. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION
FN7956.0
November 30, 2011
5
ISL70001SEH
Typical Application Schematic(Continued)
LX1
LX2
LX3
LX4
LX5
LX6
PVIN1
PVIN2
PVIN3
PVIN4
PVIN5
PVIN6
3.3V
100µF
1µF
1µF
1µH
1.8V
6A
470µF
20V
3A
4.7nF
1kΩ
1
DVDD
FB
1µF
ISL70001SEH
0V TO 5.5V
499Ω
DGND
1
PGOOD
AVDD
10nF
1µF
VSENSE
SYNC
REF
AGND
EN
220nF
M/S
10nF
PORSEL
TDI
SS
TDO
ZAP
100nF
FIGURE 4. 3.3V INPUT SUPPLY VOLTAGE WITH SLAVE MODE SYNCHRONIZATION
FN7956.0
November 30, 2011
6
ISL70001SEH
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V;
GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for V < 4.5V,
IN
SYNC = LXx = Open Circuit; PGOOD is pulled up to V with a 1k resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a
IN
100nF capacitor; I
OUT
= 0A; T = T = +25°C. (Note 3). Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total iodizing
A J
dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total iodizing dose of 50krad(Si) with exposure at a low dose rate
of <10mrad(Si)/s.
MIN
MAX
PARAMETER
POWER SUPPLY
TEST CONDITIONS
(Note 4)
TYP
(Note 4)
UNITS
Operating Supply Current
V
V
V
V
= 5.5V
= 3.6V
40
25
6
65
45
12
6
mA
mA
mA
mA
IN
IN
IN
IN
Shutdown Supply Current
= 5.5V, EN = GND
= 3.6V, EN = GND
3
OUTPUT VOLTAGE
Reference Voltage Tolerance
Output Voltage Tolerance
0.594
-2
0.6
0
0.606
2
V
V
V
I
= 0.8V to 2.5V for V = 4.5V to 5.5V,
IN
%
OUT
OUT
OUT
= 0.8V to 2.5V for V = 3V to 3.6V,
IN
= 0A to 6A (Notes 5, 6)
Feedback (FB) Input Leakage Current
PWM CONTROL LOGIC
Oscillator Accuracy
V
= 5.5V, V = 0.6V
FB
-1
0
1
µA
IN
0.85
.8
1
1
1.15
1.2
MHz
MHz
ns
ns
ns
ns
V
External Oscillator Range
Minimum LXx On Time
V
V
V
V
= 5.5V, Test Mode
= 5.5V, Test Mode
= 3V, Test Mode
= 3V, Test Mode
110
40
150
50
1.3
1.2
0
150
100
210
100
IN
IN
IN
IN
Minimum LXx Off Time
Minimum LXx On Time
Minimum LXx Off Time
Master/Slave (M/S) Input Voltage
Input High Threshold
Input Low Threshold
V
- 0.5
IN
0.5
1
V
Master/Slave (M/S) Input Leakage Current
Synchronization (SYNC) Input Voltage
V
= 5.5V, M/S = GND or V
-1
µA
V
IN
IN
Input High Threshold, M/S = GND
Input Low Threshold, M/S = GND
2.3
1.7
1.5
0
1
1
V
Synchronization (SYNC) Input Leakage
Current
V
= 5.5V, M/S = GND, SYNC = GND or V
-1
µA
IN
IN
Synchronization (SYNC) Output Voltage
V
V
- V @ I = -1mA
IN OH OH
0.15
0.15
0.4
0.4
V
V
@ I = 1mA
OL OL
POWER BLOCKS
Upper Device r
Lower Device r
V
V
V
V
= 3V, 0.4A Per Power Block, Test Mode (Note 6)
= 3V, 0.4A Per Power Block, Test Mode (Note 6)
= 5.5V, EN = LXx = GND, Single LXx Output
122
77
-1
215
146
0
346
236
mΩ
mΩ
µA
DS(ON)
IN
IN
IN
IN
DS(ON)
LXx Output Leakage
= 5.5V, EN = GND, LXx = V , Single LXx Output
IN
0
15
µA
Deadtime
Efficiency
Within a Single Power Block or between Power
Blocks (Note 6)
1.7
5
ns
V
V
= 3.3V, V
OUT
= 1.8V, I
= 3A
90
92
%
%
IN
IN
OUT
= 5V, V
OUT
= 2.5V, I
OUT
= 3A
FN7956.0
November 30, 2011
7
ISL70001SEH
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V;
GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for V < 4.5V,
IN
SYNC = LXx = Open Circuit; PGOOD is pulled up to V with a 1k resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a
IN
100nF capacitor; I
OUT
= 0A; T = T = +25°C. (Note 3). Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total iodizing
A J
dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total iodizing dose of 50krad(Si) with exposure at a low dose rate
of <10mrad(Si)/s. (Continued)
MIN
MAX
PARAMETER
POWER-ON RESET
TEST CONDITIONS
(Note 4)
TYP
(Note 4)
UNITS
POR Select (PORSEL)
Input High Threshold
Input Low Threshold
= 5.5V, PORSEL = GND or V
V
- 0.5
1.4
1.2
0
V
V
IN
0.5
1
POR Select (PORSEL) Input Leakage
Current
V
-1
µA
IN
IN
VIN POR
Rising Threshold, PORSEL = V
4.1
225
2.65
90
4.25
325
2.8
175
0.6
0
4.45
425
2.95
260
0.64
3
V
mV
V
IN
Hysteresis, PORSEL = V
IN
Rising Threshold, PORSEL = GND
Hysteresis, PORSEL = GND
Rising/Falling Threshold
mV
V
Enable (EN) Input Voltage
Enable (EN) Input Leakage Current
Enable (EN) Sink Current
SOFT-START
0.56
-3
V
= 5.5V, EN = GND or V
µA
µA
IN
IN
EN = 0.3V
6.4
11
16.6
Soft-Start Source Current
Soft-Start Discharge ON-Resistance
Soft-Start Discharge Time
POWER-GOOD SIGNAL
Rising Threshold
SS = GND
20
23
2.2
256
27
µA
Ω
4.7
Clock Cycles
V
V
V
V
V
V
as a % of V , Test Mode
REF
107
2
111
3.5
115
5
%
%
FB
FB
FB
FB
IN
Rising Hysteresis
as a % of V , Test Mode
REF
Falling Threshold
as a % of V , Test Mode
REF
85
2
89
93
5
%
Falling Hysteresis
as a % of V , Test Mode
REF
3.5
%
Power-Good Drive
= 3V, PGOOD = 0.4V, EN = GND
= PGOOD = 5.5V
7.3
8.2
mA
µA
Power-Good Leakage
0.001
1
IN
PROTECTION FEATURES
Undervoltage Monitor
Undervoltage Trip Threshold
Undervoltage Recovery Threshold
Overcurrent Monitor
V
V
= 3V, V as a % of V , Test mode
FB REF
71
84
75
88
79
92
%
%
IN
= 3V, V as a % of V , Test mode
FB REF
IN
Overcurrent Trip Level
LX4 Power Block, Test Mode, (Note 7)
= 3V, SS interval = 200µs, Test Mode, Fault
1.3
1.9
0.8
2.5
5
A
Overcurrent or Short-Circuit Duty-Cycle
V
%
IN
interval divided by hiccup interval
NOTES:
3. Typical values shown are not guaranteed. Guaranteed min/max values are provided in the SMD.
4. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5. Limits do not include tolerance of external feedback resistors. The 0A to 6A output current range may be reduced by Minimum LXx On Time and
Minimum LXx Off Time specifications.
6. Limits established by characterization or analysis and are not production tested.
7. During an output short-circuit, peak current through the power block(s) can continue to build beyond the overcurrent trip level by up to 3A. With all six
power blocks connected, peak current through the power blocks and output inductor could reach (6 x 2.5A) + 3A = 18A. The output inductor must
support this peak current without saturating.
FN7956.0
November 30, 2011
8
ISL70001SEH
output current. See the “Typical Application Schematic” on
page 5 for pin connection guidance.
Functional Description
The ISL70001SEH is a monolithic, fixed frequency, current-mode
synchronous buck regulator with user configurable power blocks.
Two ISL70001SEH devices can be used to provide a total DC/DC
solution for FPGAs, CPLDs, DSPs and CPUs.
A scaled pilot device associated with each power block provides
current feedback. Power block 4 contains the master pilot device
and this is why it must be connected to the output inductor.
The ISL70001SEH utilizes peak current-mode control with
integrated compensation and switches at a fixed frequency of
1MHz. Two ISL70001SEH devices can be synchronized 180°
out-of-phase to reduce input RMS ripple current. These attributes
reduce the number and size of external components required,
while providing excellent output transient response. The
internal synchronous power switches are optimized for high
efficiency and good thermal performance.
Main Control Loop
During normal operation, the internal top power switch is turned
on at the beginning of each clock cycle. Current in the output
inductor ramps up until the current comparator trips and turns
off the top power MOSFET. The bottom power MOSFET turns on
and the inductor current ramps down for the rest of the cycle.
The current comparator compares the output current at the
ripple current peak to a current pilot. The error amplifier monitors
The chip features a comparator type enable input that provides
flexibility. It can be used for simple digital on/off control or,
alternately, can provide undervoltage lockout capability by
using two external resistors to precisely sense the level of an
external supply voltage. A power-good signal indicates when the
output voltage is within ±11% typical of the nominal output
voltage.
V
and compares it with an internal reference voltage. The
OUT
output voltage of the error amplifier drives a proportional current
to the pilot. If V is low, the current level of the pilot is
OUT
increased and the trip off current level of the output is increased.
The increased output current raises V
with the reference voltage.
until it is in agreement
OUT
Output Voltage Selection
The output voltage of the ISL70001SEH can be adjusted using an
external resistor divider as shown in Figure 6.
Regulator start-up is controlled by an analog soft-start circuit,
which can be adjusted from approximately 2ms to 200ms by
using an external capacitor.
The ISL70001SEH incorporates fault protection for the
regulator. The protection circuits include input undervoltage,
output undervoltage, and output overcurrent.
V
= 0.6V
= 220nF
= 1k
= 4.7nF
REF
REF
T
C
L
OUT
C
R
C
V
OUT
LXx
Power Blocks
C
OUT
The power output stage of the regulator consists of six 1A
capable power blocks that are paralleled to provide full 6A
output current capability. The block diagram in Figure 5 shows a
top level view of the individual power blocks.
C
R
C
T
ERROR
AMPLIFIER
FB
-
V
REF
REF
R
B
+
C
REF
PVIN1
LX1
PGND1
PVIN6
LX6
PGND6
POWER BLOCK 1
POWER BLOCK 2
POWER BLOCK 3
POWER BLOCK 6
POWER BLOCK 5
POWER BLOCK 4
FIGURE 6. OUTPUT VOLTAGE SELECTION
R should be selected as 1kΩ to mitigate SEE. R should be
shunted by a 4.7nF ceramic capacitor, C , to mitigate SEE and to
improve loop stability margins. The REF pin should be bypassed
to AGND with a 220nF ceramic capacitor to mitigate SEE. It
should be noted that no current (sourcing or sinking) is available
from the REF pin. R can be determined from Equation 3. The
designer can configure the output voltage from 0.8V to 85% of
the input voltage.
PVIN2
LX2
PGND2
T
T
PVIN5
LX5
PGND5
C
PVIN3
LX3
PGND3
PVIN4
LX4
PGND4
B
V
(EQ. 3)
FIGURE 5. POWER BLOCK DIAGRAM
REF
– V
REF
-------------------------------
= R ⋅
T
R
B
V
OUT
Each power block has a power supply input pin, PVINx, a phase
output pin, LXx, and a power supply ground pin, PGNDx. All PVINx
pins must be connected to a common power supply rail and all
PGNDx pins must be connected to a common ground. LXx pins
should be connected to the output inductor based on the
required load current, but must include the LX4 pin. For example,
if 3A of output current is needed, any three LXx pins can be
connected to the inductor as long as one of them is the LX4 pin.
The unused LXx pins should be left unconnected. Connecting all
six LXx pins to the output inductor provides a maximum 6A of
Switching Frequency/Synchronization
The ISL70001SEH features an internal oscillator running at a
fixed frequency of 1MHz ±15% over recommended operating
conditions. The regulator can be configured to run from the
internal oscillator or can be synchronized to another
ISL70001SEH or an SEE hardened external clock with a
frequency range of 1MHz ±20%.
FN7956.0
November 30, 2011
9
ISL70001SEH
To run the regulator from the internal oscillator, connect the M/S
pin to DVDD. In this case, the output of the internal oscillator
appears on the SYNC pin. To synchronize the regulator to the
SYNC output of another ISL70001SEH regulator or to an SEE
hardened external clock, connect the M/S pin to DGND. In this
case, the SYNC pin is an input that accepts an external
V
I
C
= 0.6V
= 11µA
R
EN
V
IN1
= 10nF
EN
PVINx
synchronizing signal. When synchronizing multiple devices, Slave
regulators are synchronized 180° out-of-phase with respect to
the SYNC output of a Master regulator or to an external clock.
V
IN2
ENABLE
COMPARATOR
R1
R2
Operation Initialization
EN
+
The ISL70001SEH initializes based on the state of the power-on
reset (POR) monitor of the PVINx inputs and the state of the EN
input. Successful initialization prompts a soft-start interval, and
the regulator begins slowly ramping the output voltage. Once the
commanded output voltage is within the proper window of
operation, the power-good signal changes state from low to high,
indicating proper regulator operation.
C
V
R
EN
-
POR
LOGIC
I
EN
FIGURE 7. ENABLE CIRCUIT
Power-On Reset
The POR circuitry prevents the controller from attempting to
soft-start before sufficient bias is present at the PVINx pins.
With the part enabled and the I current sink off, the disable
EN
level is set by the resistor divider. The disable level is defined by
Equation 5.
The POR threshold of the PVINx pins is controlled by the PORSEL
pin. For a nominal 5V supply voltage, PORSEL should be
connected to DVDD. For a nominal 3.3V supply voltage, PORSEL
should be connected to DGND. For nominal supply voltages
between 5V and 3.3V, PORSEL should be connected to DGND.
The POR rising and falling thresholds are shown in the “Electrical
Specifications” table on page 8.
R1
R2
(EQ. 5)
-------
= V ⋅ 1 +
R
V
DISABLE
The difference between the enable and disable levels provides
adjustable hysteresis so that noise on V does not interfere
IN2
with the enabling or disabling of the regulator.
To mitigate SEE, the EN pin should be bypassed to the AGND pin
with a 10nF ceramic capacitor.
Hysteresis between the rising and falling thresholds ensures that
small perturbations on PVINx seen during turn-on/turn-off of the
regulator do not cause inadvertent turn-off/turn-on of the
regulator. When the PVINx pins are below the POR rising
threshold, the internal synchronous power MOSFET switches are
turned off, and the LXx pins are held in a high-impedance state.
Soft-Start
Once the POR and enable circuits are satisfied, the regulator
initiates a soft-start. Figure 8 shows that the soft-start circuit
clamps the error amplifier reference voltage to the voltage on an
external soft-start capacitor connected to the SS pin.
Enable and Disable
After the POR input requirement is met, the ISL70001SEH
remains in shutdown until the voltage at the enable input rises
above the enable threshold. As shown in Figure 7, the enable
circuit features a comparator type input. In addition to simple
logic on/off control, the enable circuit allows the level of an
external voltage to precisely gate the turn-on/turn-off of the
V
I
R
= 0.6V
= 23µA
= 2.2Ω
REF
SS
V
OUT
D
R
T
FB
regulator. An internal I current sink with a typical value of
11µA is only active when the voltage on the EN pin is below the
R
EN
B
ERROR
AMPLIFIER
SS
enable threshold. The current sink pulls the EN pin low. As V
IN2
rises, the enable level is not set exclusively by the resistor divider
from V
-
C
SS
+
+
REF
.
IN2
V
REF
PWM
LOGIC
C
R
REF
D
With the current sink active, the enable level is defined by
I
SS
Equation 4. R1 is the resistor from the EN pin to V
the resistor from the EN pin to the AGND pin.
and R2 is
IN2
R1
R2
-------
+ I ⋅ R1
EN
V
= V
⋅
1 +
(EQ. 4)
ENABLE
R
Once the voltage at the EN pin reaches the enable threshold, the
current sink turns off.
I
EN
FIGURE 8. SOFT-START CIRCUIT
FN7956.0
November 30, 2011
10
ISL70001SEH
The soft-start capacitor is charged by an internal I current
is a fixed percentage of the reference voltage. Once the
SS
source. As the soft-start capacitor is charged, the output voltage
comparator trips, indicating a valid undervoltage condition, a
3-bit undervoltage counter increments. The counter is reset if the
feedback voltage rises back above the undervoltage threshold,
plus a specified amount of hysteresis outlined in the “Electrical
Specifications” table on page 8. If the 3-bit counter overflows, the
undervoltage protection logic shuts down the regulator.
slowly ramps to the set point determined by the reference
voltage and the feedback network. Once the voltage on the SS
pin is equal to the internal reference voltage, the soft-start
interval is complete. The controlled ramp of the output voltage
reduces the inrush current during start-up. The soft-start output
ramp interval is defined in Equation 6 and is adjustable from
approximately 2ms to 200ms. The value of the soft-start
After the regulator shuts down, it enters a delay interval
equivalent to the soft-start interval, which allows the device to
cool. The undervoltage counter is reset when the device enters
the delay interval. The protection logic initiates a normal
soft-start once the delay interval ends. If the output successfully
soft-starts, the power-good signal goes high, and normal
operation continues. If undervoltage conditions continue to exist
during the soft-start interval, the undervoltage counter must
overflow before the regulator shuts down again. This hiccup
mode continues indefinitely until the output soft-starts
successfully.
capacitor, C , should range from 8.2nF to 8.2µF, inclusive. The
SS
peak inrush current can be computed from Equation 7. The soft-
start interval should be long enough to ensure that the peak
inrush current plus the peak output load current does not exceed
the overcurrent trip level of the regulator.
V
REF
------------
t
= C
⋅
(EQ. 6)
SS
SS
I
SS
V
OUT
------------
I
= C
⋅
(EQ. 7)
INRUSH
OUT
t
SS
Overcurrent Protection
The soft-start capacitor is immediately discharged by a 2.2Ω
resistor whenever POR conditions are not met or EN is pulled low.
The soft-start discharge time is equal to 256 clock cycles.
A pilot device integrated into the PMOS transistor of Power Block 4
samples current each cycle. This current feedback is scaled and
compared to an overcurrent threshold based on the number of
power blocks connected. Each additional power block connected
beyond Power Block 4 increases the overcurrent limit by 2A. For
example, if three power blocks are connected, the typical current
limit threshold would be 3 x 2A = 6A.
Power-Good
The power-good (PGOOD) pin is an open-drain logic output that
indicates when the output voltage of the regulator is within
regulation limits. The power-good pin pulls low during shutdown
and remains low when the controller is enabled. After a
successful soft-start, the PGOOD pin releases, and the voltage
rises with an external pull-up resistor. The power-good signal
transitions low immediately when the EN pin is pulled low.
If the sampled current exceeds the overcurrent threshold, a 3-bit
overcurrent counter increments by one LSB. If the sampled current
falls below the threshold before the counter overflows, the counter
is reset. Once the overcurrent counter reaches 111, the regulator
shuts down.
The power-good circuitry monitors the FB pin and compares it to
the rising and falling thresholds shown in the “Electrical
Specifications” table on page 8. If the feedback voltage exceeds
the typical rising limit of 111% of the reference voltage, the
PGOOD pin pulls low. The PGOOD pin continues to pull low until
the feedback voltage falls to a typical of 107.5% of the reference
voltage. If the feedback voltage drops below a typical of 89% of
the reference voltage, the PGOOD pin pulls low. The PGOOD pin
continues to pull low until the feedback voltage rises to a typical
92.5% of the reference voltage. The PGOOD pin then releases
and signals the return of the output voltage to within the
power-good window.
After the regulator shuts down, it enters a delay interval,
equivalent to the soft-start interval, which allows the device to
cool. The overcurrent counter is reset when the device enters the
delay interval. The protection logic initiates a normal soft-start
once the delay interval ends. If the output successfully
soft-starts, the power-good signal goes high, and normal
operation continues. If overcurrent conditions continue to exist
during the soft-start interval, the overcurrent counter must
overflow before the regulator shut downs the output again. This
hiccup mode continues indefinitely until the output soft-starts
successfully.
The PGOOD pin can be pulled up to any voltage from 0V to 5.5V,
independently from the supply voltage. The pull-up resistor
should have a nominal value from 1kΩ to 10kΩ. The PGOOD pin
should be bypassed to DGND, with a 10nF ceramic capacitor to
mitigate SEE.
Note: To prevent severe negative ringing that can disturb the
overcurrent counter, it is recommended that a Schottky diode of
appropriate rating be added from the LXx pins to the PGNDx pins.
Feedback Loop Compensation
To reduce the number of external components and to simplify the
process of determining compensation components, the
ISL70001SEH PWM controller has an internally compensated
error amplifier.
Fault Monitoring and Protection
The ISL70001SEH actively monitors output voltage and current
to detect fault conditions. Fault conditions trigger protective
measures to prevent damage to the regulator and external load
device.
Due to the current loop feedback in peak current mode control, the
modulator has a single pole response with -20dB slope at a
frequency determined by the load (Equation 8):
1
Undervoltage Protection
A hysteretic comparator monitors the FB pin of the regulator. The
feedback voltage is compared to an undervoltage threshold that
------------------------------------
=
F
(EQ. 8)
PO
2π ⋅ R ⋅ C
O
OUT
FN7956.0
November 30, 2011
11
ISL70001SEH
where R is load resistance and C
OUT
capacitance. For this type of modulator, a Type 2 compensation
circuit is usually sufficient.
is the output load
Output Filter Design
O
The output inductor and the output capacitor bank together form
a low-pass filter responsible for smoothing the pulsating voltage
at the phase node. The filter must also provide the transient
energy until the regulator can respond. Since the filter has low
bandwidth relative to the switching frequency, it limits the
system transient response. The output capacitors must supply or
sink current while the current in the output inductor increases or
decreases to meet the load demand.
Figure 9 shows a Type 2 amplifier and its response, along with
the responses of the current mode modulator and the converter.
C2
C1
R2
CONVERTER
R1
EA
OUTPUT CAPACITOR SELECTION
TYPE 2 EA
The critical load parameters in choosing the output capacitors are
the maximum size of the load step (ΔI
), the load-current slew
STEP
rate (di/dt), and the maximum allowable output voltage deviation
G
= 25.1dB
EA
MODULATOR
under transient loading (ΔV ). Capacitors are characterized
MAX
F
F
P
Z
according to their capacitance, ESR (Equivalent Series Resistance)
and ESL (Equivalent Series Inductance).
F
PO
F
C
At the beginning of a load transient, the output capacitors supply all
of the transient current. The output voltage initially deviates by an
amount approximated by the voltage drop across the ESL. As the
load current increases, the voltage drop across the ESR increases
linearly until the load current reaches its final value. Neglecting the
contribution of inductor current and regulator response, the output
voltage initially deviates by an amount shown in Equation 11.
FIGURE 9. FEEDBACK LOOP COMPENSATION
The Type 2 amplifier, in addition to the pole at origin, has a
zero-pole pair that causes a flat gain region at frequencies
between the zero and the pole (Equations 9 and 10).
1
di
-----
ΔV
≈
ESL ×
+ [ESR × ΔI
]
STEP
(EQ. 11)
MAX
-----------------------------
F
=
= 8.6kHz
dt
Z
(EQ. 9)
2π ⋅ R ⋅ C
2
1
The filter capacitors selected must have sufficiently low ESL and
ESR such that the total output voltage deviation is less than the
maximum allowable ripple.
1
-----------------------------
2π ⋅ R ⋅ C
F
=
= 546kHz
(EQ. 10)
P
1
2
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but larger ESR.
Minimizing the ESL of the high-frequency capacitors allows them
to support the output voltage as the current increases.
Minimizing the ESR of the bulk capacitors allows them to supply
the increased current with less output voltage deviation.
Zero frequency and amplifier high-frequency gain were chosen to
satisfy typical applications. The crossover frequency will appear
at the point where the modulator attenuation equals the
amplifier high frequency gain. The only task that the system
designer has to complete is to specify the output filter capacitors
to position the load main pole somewhere within one decade
lower than the amplifier zero frequency. Equation 13 on page 12
approximates the amount of capacitance needed to achieve an
optimal pole location depending on the number of LXx pins
connected. With this type of compensation, plenty of phase
margin is easily achieved due to zero-pole pair phase ‘boost’.
Ceramic capacitors with X7R dielectric are recommended.
Alternately, a combination of low ESR solid tantalum capacitors
and ceramic capacitors with X7R dielectric may be used.
The ESR of the bulk capacitors is responsible for most of the
output voltage ripple. As the bulk capacitors sink and source the
Conditional stability may occur only when the main load pole is
positioned too much to the left side on the frequency axis due to
excessive output filter capacitance. In this case, the ESR zero
placed within the 1.2kHz to 30kHz range gives some additional
phase ‘boost’. Some phase boost is also be achieved by
inductor AC ripple current, a voltage, V
, develops across
P-P(MAX)
the bulk capacitor according to Equation 12.
(V – V
)V
OUT OUT
IN
----------------------------------------------
= ESR ×
V
(EQ. 12)
P-P(MAX)
L
× f × V
s IN
OUT
connecting the recommended capacitor C in parallel with the
C
upper resistor R of the divider that sets the output voltage value,
as demonstrated in Figure 6.
T
Another consideration in selecting the output capacitors is loop
stability. The total output capacitance sets the dominant pole of
the PWM. Because the ISL70001SEH uses integrated
compensation techniques, it is necessary to restrict the output
capacitance in order to optimize loop stability. The
recommended load capacitance can be estimated using
Equation 13.
Component Selection Guide
This design guide is intended to provide a high-level explanation
of the steps necessary to create a power converter. It is assumed
the reader is familiar with many of the basic skills and
techniques referenced below. In addition to this guide, Intersil
provides a complete evaluation board that includes schematic,
BOM, and an example PCB layout (see Ordering Information
table on page 2).
1.8V
------------
C
= 75μF × NumberofLXxPinsConnected ×
OUT
V
OUT
(EQ. 13)
FN7956.0
November 30, 2011
12
ISL70001SEH
Another stability requirement on the selection of the output
capacitor is that the ‘ESR zero’ (f ) be placed at 60kHz to
90kHz. This range is set by an internal, single compensation zero
at 8.6kHz. This ESR zero location contributes to increased phase
margin of the control loop; therefore (Equation 14):
Input Capacitor Selection
ZESR
Input capacitors are responsible for sourcing the AC component
of the input current flowing into the switching power devices.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the switching power devices,
which is related to duty cycle. The maximum RMS current
required by the regulator is closely approximated by Equation 19.
1
----------------------------------------------
ESR =
(EQ. 14)
2π(f
)(C
)
OUT
ZESR
2
V
V
– V
V
⎛
⎜
⎝
⎛
⎜
⎝
⎞
⎟
⎠
⎞
2
OUT
1
12
IN
OUT
OUT
-----------------
------
--------------------------------- -----------------
I
=
×
I
+
×
×
⎟
In conclusion, the output capacitors must meet three criteria:
RMS
OUT
V
V
L
× f
⎠
MAX
MAX
IN
IN
OUT
s
1. They must have sufficient bulk capacitance to sustain the
output voltage during a load transient while the output
inductor current is slewing to the value of the load transient.
(EQ. 19)
The important parameters to consider when selecting an input
capacitor are the voltage rating and the RMS ripple current
rating. For reliable operation, select capacitors with voltage
ratings at least 1.5x greater than the maximum input voltage.
The capacitor RMS ripple current rating should be higher than
the largest RMS ripple current required by the circuit.
2. The ESR must be sufficiently low to meet the desired output
voltage ripple due to the output inductor current.
3. The ESR zero should be placed, in a rather large range, to
provide additional phase margin.
Ceramic capacitors with X7R dielectric are recommended.
Alternately, a combination of low ESR solid tantalum capacitors
and ceramic capacitors with X7R dielectric may be used. The
ISL70001SEH requires a minimum effective input capacitance of
100µF for stable operation.
OUTPUT INDUCTOR SELECTION
Once the output capacitors are selected, the maximum allowable
ripple voltage, V
, determines the lower limit on the
inductance as shown in Equation 15.
P-P(MAX)
(V – V
)V
OUT OUT
IN
-------------------------------------------------
L
≥ ESR ×
(EQ. 15)
OUT
Derating Current Capability
f × V × V
P-P(MAX)
s
IN
Most space programs issue specific derating guidelines for parts,
but these guidelines take the pedigree of the part into account.
For instance, a device built to MIL-PRF-38535, such as the
ISL70001, is already heavily derated from a current density
standpoint. However, a mil-temp or commercial IC that is
up-screened for use in space applications may need additional
current derating to ensure reliable operation because it was not
built to the same standards as the ISL70001.
Since the output capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the transient,
the capacitor voltage becomes slightly depleted. The output
inductor must be capable of assuming the entire load current
before the output voltage decreases more than ΔV
. This
MAX
places an upper limit on inductance.
Equation 16 gives the upper limit on output inductance for the
case when the trailing edge of the current transient causes a
greater output voltage deviation than the leading edge.
Equation 17 addresses the leading edge. Normally, the trailing
edge dictates the inductance selection because duty cycles are
usually <50%. Nevertheless, both inequalities should be
evaluated, and inductance should be governed based on the
Figure 10 shows the maximum average output current of the
ISL70001 with respect to junction temperature. These plots take
into account the worst-case current share mismatch in the power
blocks and the current density requirement of MIL-PRF-38535
2
(< 2 x 105 A/cm ). The plot clearly shows that the ISL70001 can
handle 12.1A at +125°C from a worst-case current density
standpoint, but the part is limited to 7.8A because that is the
lower limit of the current limit threshold with all six power blocks
connected.
lower of the two results. In each equation, L
is the output
OUT
inductance, C
OUT
is the total output capacitance, and ΔI is
L(P-P)
the peak-to-peak ripple current in the output inductor.
2 ⋅ C
⋅ V
OUT
OUT
(EQ. 16)
13
L
L
≤ --------------------------------------- ΔV
– (ΔI ⋅ ESR)
L(P-P)
OUT
MAX
2
(ΔI
)
12.14
STEP
12
11
2 ⋅ C
10.18
OUT
10
⎛
⎞
MINIMUM OCP
≤ -------------------------- ΔV
– (ΔI
⋅ ESR)
V
– V
IN OUT
(EQ. 17)
OUT
MAX
L(P-P)
2
⎝
⎠
(ΔI
)
LEVEL = 7.8A
9
8
7
6
5
4
STEP
8.57
The other concern when selecting an output inductor is to ensure
there is adequate slope compensation when the regulator is
operated above 50% duty cycle. Since the internal slope
compensation is fixed, output inductance should satisfy
Equation 18 to ensure this requirement is met.
7.25
6.16
6A @ +146°C
5.3
120
125
130
135
140
145
150
155
4.32μH
JUNCTION TEMPERATURE (°C)
(EQ. 18)
-----------------------------------------------------------------------------------
≥
L
OUT
NumberofLXxPinsConnected
FIGURE 10. CURRENT vs TEMPERATURE
FN7956.0
November 30, 2011
13
ISL70001SEH
PCB Design
L
V
OUT
OUT
LXx
3A
PCB design is critical to high-frequency switching regulator
performance. Careful component placement and trace routing
are necessary to reduce voltage spikes and minimize
undesirable voltage drops. Selection of a suitable thermal
interface material is also required for optimum heat dissipation
and to provide lead strain relief. See Table 1 on page 16 for
layout x-y coordinates.
C
OUT
R
C
S
S
R
C
C
T
PGNDx
FB
ERROR
AMPLIFIER
-
PCB Plane Allocation
V
R
REF
REF
B
+
Four layers of 2-ounce copper are recommended. Layer 2 should
be a dedicated ground plane with all critical component ground
connections made with vias to this layer. Layer 3 should be a
dedicated power plane split between the input and output power
rails. Layers 1 and 4 should be used primarily for signals but can
also provide additional power and ground islands, as required.
C
REF
FIGURE 11. SCHOTTKY DIODE AND R-C SNUBBER
PCB Layout
Use a small island of copper to connect the LXx pins of the IC to
the output inductor on Layers 1 and 4. To minimize capacitive
coupling to the power and ground planes, void the copper on
Layers 2 and 3 adjacent to the island. Place most of the island of
Layer 4 to minimize the amount of copper that must be voided
from the ground plane (Layer 2).
PCB Component Placement
Components should be placed as close as possible to the IC to
minimize stray inductance and resistance. Prioritize the
placement of bypass capacitors on the pins of the IC in the order
shown: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors),
EN, PGOOD, PVINx (bulk capacitors).
Keep all other signal traces as short as possible.
For an example layout, see AN1518.
Locate the output voltage resistive divider as close as possible to
the FB pin of the IC. The top leg of the divider should connect
directly to the POL (Point of Load), and the bottom leg of the
divider should connect directly to AGND. The junction of the
resistive divider should connect directly to the FB pin.
Thermal Management
For optimum thermal performance, place a pattern of vias on the
top layer of the PCB directly underneath the IC. Connect the vias
to the ground plane on Layer 2, which serves as a heat sink. To
ensure good thermal contact, thermal interface material such as
a Sil-Pad or thermally conductive epoxy should be used to fill the
gap between the vias and the bottom of the IC.
Locate a Schottky clamp diode as close as possible to the LXx
and PGNDx pins of the IC. A small series R-C snubber connected
from the LXx pins to the PGNDx pins may be used to damp high
frequency ringing on the LXx pins, if desired, see Figure 11.
Lead Strain Relief
For strain relief, a Sil-Pad or a thin layer of thermally conductive
epoxy can be used to raise the bottom of the IC from the PCB
surface so that a slight bend can be added to the leads of the IC.
FN7956.0
November 30, 2011
14
ISL70001SEH
BACKSIDE FINISH
Die Characteristics
Die Dimensions
Silicon
ASSEMBLY RELATED INFORMATION
5720µm x 5830µm (225.2 mils x 229.5 mils)
Thickness: 483µm ± 25.4µm (19.0 mils ± 1 mil)
Substrate Potential
PGND
Interface Materials
ADDITIONAL INFORMATION
Worst Case Current Density
GLASSIVATION
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm
5
2
< 2 x 10 A/cm
Transistor Count
TOP METALLIZATION
25030
Type: AlCu (0.5%)
Thickness: 2.7µm ±0.4µm
Layout Characteristics
SUBSTRATE
Step and Repeat
Type: Silicon
Isolation: Junction
5720µm x 5830µm
Connect PGND to PGNDx
Metallization Mask Layout
ISL70001SEH
LX1
PGND1
LX2
PVIN2
PVIN3
SYNC PVIN1
PGND2
M/S
ZAP
TDI
LX3
TDO
PGND3
PGND4
PGOOD
SS
LX4
DVDD
PVIN4
PVIN5
LX5
DGND
PGND
AGND
AVDD REF
FB
EN PORSEL
PVIN6
LX6
PGND6
PGND5
FN7956.0
November 30, 2011
15
ISL70001SEH
TABLE 1. LAYOUT X-Y COORDINATES
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
PER PAD
PAD NAME
PAD NUMBER
AVDD
REF
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
478
865
263
263
135
135
135
135
135
521
521
521
521
135
135
135
135
135
135
135
521
521
521
521
521
521
521
135
135
135
135
135
135
135
135
135
135
135
135
135
135
135
135
135
135
135
135
521
521
521
521
521
521
521
135
135
135
135
135
135
135
135
135
135
135
135
135
135
333
333
135
135
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
2
2
1
1
FB
1295
1751
2151
2838
3449
4060
4845
5449
5449
5449
5449
5449
5449
5449
4941
4137
3449
2838
2227
1578
962
263
EN
263
PORSEL
PVIN6
LX6
263
188
188
PGND6
PGND5
LX5
188
188
925
PVIN5
PVIN4
LX4
1651
2263
2874
3485
4096
4745
5559
5559
5559
5559
5559
5559
5559
5559
5280
4910
4540
4170
3777
3425
2566
1538
1018
654
PGND4
PGND3
LX3
PVIN3
PVIN2
LX2
PGND2
PGND1
LX1
2
PVIN1
SYNC
M/S
3
4
544
5
226
ZAP
6
226
TDI
7
226
TDO
8
226
PGOOD
SS
9
226
10
11
12
13
14
226
DVDD
DGND
PGND
AGND
226
226
226
226
FN7956.0
November 30, 2011
16
ISL70001SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN7956.0
CHANGE
November 30, 2011
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL70001SEH
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7956.0
November 30, 2011
17
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