ISL70218SRHMF [INTERSIL]

Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers; 抗辐射双路36V精密单电源,轨到轨输出,低功耗运算放大器
ISL70218SRHMF
型号: ISL70218SRHMF
厂家: Intersil    Intersil
描述:

Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers
抗辐射双路36V精密单电源,轨到轨输出,低功耗运算放大器

运算放大器 CD
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Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail  
Output, Low-Power Operational Amplifiers  
ISL70218SRH  
Features  
The ISL70218SRH is a dual, low-power precision amplifier  
optimized for single-supply applications. This op amp features  
a common mode input voltage range extending to 0.5V below  
the V- rail, a rail-rail differential input voltage range, and  
rail-to-rail output voltage swing, which makes it ideal for  
single-supply applications where input operation at ground is  
important.  
• Wide Single and Dual Supply Range . . . . . . . .3V to 36V Max.  
• Low Current Consumption . . . . . . . . . . . . . . . . . . 850µA, Typ.  
• Low Input Offset Voltage. . . . . . . . . . . . . . . . . . . . . . 40µV, Typ.  
• Rail-to-Rail Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mV  
• Rail-to-Rail Input Differential Voltage Range for Comparator  
Applications  
• Operating Temperature Range. . . . . . . . . . .-55°C to +125°C  
• Below-ground (V-) Input Capability to -0.5V.  
This op amp features low power, low offset voltage, and low  
temperature drift, making it ideal for applications requiring  
both high DC accuracy and AC performance. This amplifier is  
designed to operate over a single supply range of 3V to 36V or a  
split supply voltage range of +1.8V/-1.2V to ±18V. The  
combination of precision and small footprint provides the user  
with outstanding value and flexibility relative to similar  
competitive parts.  
• Low Noise Voltage . . . . . . . . . . . . . . . . . . . . . . 5.6nV/Hz, Typ.  
• Low Noise Current . . . . . . . . . . . . . . . . . . . . . .355fA/Hz, Typ.  
• Offset Voltage Temperature Drift. . . . . . . . . . . 0.3µV/°C, Typ.  
• No Phase Reversal  
• Radiation Tolerance  
Applications for this amplifier include precision  
instrumentation, data acquisition, precision power supply  
controls, and industrial controls.  
- High Dose Rate. . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)  
- Low Dose Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)  
- SEL/SEB LETTH (VS = ±18V) . . . . . . . . . . 86.4 MeV/mg/cm2  
The ISL70218SRH is available in a 10 Ld hermetic ceramic  
flatpack and operates over the extended temperature range of  
-55°C to +125°C.  
Applications  
• Precision Instruments  
• Active Filter Blocks  
Related Literature  
• See AN1653, “ISL70218SRH Evaluation Board User’s  
Guide”  
• Data Acquisition  
• Power Supply Control  
• Industrial Process Control  
R
F
400  
100k  
+25°C  
LOAD  
300  
+3V  
to 40V  
R
-
IN  
+125°C  
200  
IN-  
-
V
OUT  
V+  
10kΩ  
R
SENSE  
100  
0
ISL70218SRH  
R
+
V-  
IN  
IN+  
+
10kΩ  
-100  
GAIN = 10  
-40°C  
R
+
REF  
-200  
-300  
-400  
-55°C  
100kΩ  
V
REF  
-16  
-15  
-14  
-13 13  
14  
15  
16  
INPUT COMMON MODE VOLTAGE (V)  
FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE  
VOLTAGE, VS = ±15V  
FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, LOW-SIDE  
CURRENT SENSE AMPLIFIER  
August 17, 2011  
FN7871.1  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved  
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.  
All other trademarks mentioned are the property of their respective owners.  
1
ISL70218SRH  
Pin Configurations  
ISL70218SRH  
(10 LD FLATPACK)  
TOP VIEW  
OUT_A  
-IN_A  
+IN_A  
NC  
1
2
3
4
5
10  
9
V+  
OUT_B  
-IN_B  
+IN_B  
NC  
-
+
8
+
-
7
V-  
6
Pin Descriptions  
PIN NUMBER  
PIN NAME  
EQUIVALENT CIRCUIT  
Circuit 2  
DESCRIPTION  
1
2
OUT_A  
-IN_A  
+IN_A  
NC  
Amplifier A output  
Circuit 1  
Amplifier A inverting input  
Amplifier A non-inverting input  
No connect  
3
Circuit 1  
4
5
V-  
Circuit 1, 2, 3  
Negative power supply  
No connect  
6
NC  
7
+IN_B  
-IN_B  
OUT_B  
V+  
Circuit 1  
Circuit 1  
Amplifier B non-inverting input  
Amplifier B inverting input  
Amplifier B output  
8
9
Circuit 2  
10  
Circuit 1, 2, 3  
Positive power supply  
V
+
V
+
V
+
CAPACITIVELY  
TRIGGERED ESD  
CLAMP  
OUT  
IN-  
IN  
+
V
-
V
-
V
-
CIRCUIT 1  
CIRCUIT 2  
CIRCUIT 3  
Ordering Information  
ORDERING NUMBER  
PART NUMBER  
TEMP RANGE (°C)  
-55 to +125  
PACKAGE  
10 Ld Flatpack  
10 Ld Flatpack  
DIE  
PKG. DWG. #  
K10.A  
K10.A  
ISL70218SRHMF  
ISL70218 SRHMF  
ISL70218SRHF/PROTO  
ISL70218SRHMX  
ISL70218 SRHF /PROTO  
-55 to +125  
-55 to +125  
ISL70218SRHX/SAMPLE  
ISL70218SRHMEVAL1Z  
NOTES:  
-55 to +125  
DIE  
Evaluation Board  
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both  
SnPb and Pb-free soldering operations.  
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70218SRH. For more information on MSL, please seeTech Brief  
TB363.  
FN7871.1  
August 17, 2011  
2
ISL70218SRH  
Absolute Maximum Ratings  
Thermal Information  
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V  
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA  
Maximum Differential Input Voltage . . . . . . . . 36V or V- - 0.5V to V+ + 0.5V  
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . 36V or V- - 0.5V to V+ + 0.5V  
Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA  
Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . . . . Indefinite  
ESD Tolerance  
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 3kV  
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 300V  
Charged Device Model (Tested per CDM-22CI0ID). . . . . . . . . . . . . . . 2kV  
Thermal Resistance (Typical)  
10 Ld Flatpack Package (Notes 3, 4). . . . .  
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C  
θ
JA (°C/W)  
130  
θ
JC (°C/W)  
20  
Recommended Operating Conditions  
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C  
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C  
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3V (+1.8V/-1.2V) to 30V (±15V)  
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product  
reliability and result in failures not covered by warranty.  
NOTES:  
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.  
4. For θJC, the “case temp” location is the center of the package underside.  
Electrical Specifications V ±15V, V = 0, V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply over  
S
CM  
O
L
A
the operating temperature range, -55°C to +125°C.  
MIN  
MAX  
PARAMETER  
VOS  
DESCRIPTION  
Offset Voltage  
CONDITIONS  
(Note 5)  
TYP  
40  
(Note 5)  
UNIT  
µV  
230  
290  
1.4  
280  
365  
50  
µV  
TCVOS  
Offset Voltage Drift  
0.3  
44  
µV/°C  
µV  
ΔVOS  
Input Offset Voltage Match  
µV  
IOS  
Input Offset Current  
-50  
-75  
4
nA  
75  
nA  
IB  
Input Bias Current  
-575  
-800  
(V-) - 0.5  
V-  
-230  
nA  
nA  
VCMIR  
CMRR  
PSRR  
AVOL  
VOH  
Common Mode Input Voltage Range  
Common-Mode Rejection Ratio  
Power Supply Rejection Ratio  
Open-Loop Gain  
Guaranteed by CMRR Test  
(V+) + 1.8  
(V+) - 1.8  
V
V
VCM = V- to V+ -1.8V  
100  
97  
118  
dB  
VCM = V- to V+ -1.8V  
dB  
VS = 3V to 40V,  
105  
100  
120  
115  
124  
-
dB  
VCMIR = Valid Input Voltage  
dB  
RL = 10kΩ to ground  
O = -13V to +13V  
130  
dB  
V
dB  
Output Voltage High,  
V+ to VOUT  
RL = 10kΩ  
RL = 10kΩ  
110  
120  
70  
mV  
mV  
mV  
mV  
mA  
mA  
mA  
mA  
V
VOL  
Output Voltage Low,  
VOUT to V-  
80  
IS  
Supply Current/Amplifier  
0.85  
1.1  
1.4  
IS+  
IS-  
Source Current Capability  
Sink Current Capability  
Supply Voltage Range  
10  
10  
3
VSUPPLY  
Guaranteed by PSRR  
40  
FN7871.1  
August 17, 2011  
3
ISL70218SRH  
Electrical Specifications V ±15V, V = 0, V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply over  
S
CM  
O
L
A
the operating temperature range, -55°C to +125°C. (Continued)  
MIN  
MAX  
PARAMETER  
DESCRIPTION  
CONDITIONS  
(Note 5)  
TYP  
4
(Note 5)  
UNIT  
MHz  
AC SPECIFICATIONS  
GBW  
Gain Bandwidth Product  
ACL = 101, VOUT = 100mVP-P  
RL = 2k  
;
enp-p  
Voltage Noise  
0.1Hz to 10Hz, VS = ±18V  
f = 10Hz, VS = ±18V  
f = 100Hz, VS = ±18V  
f = 1kHz, VS = ±18V  
f = 10kHz, VS = ±18V  
f = 1kHz, VS = ±18V  
300  
8.5  
nVP-P  
nV/Hz  
nV/Hz  
nV/Hz  
nV/Hz  
fA/Hz  
%
en  
en  
Voltage Noise Density  
Voltage Noise Density  
Voltage Noise Density  
Voltage Noise Density  
Current Noise Density  
Total Harmonic Distortion + Noise  
5.8  
en  
5.6  
en  
5.6  
in  
355  
0.0003  
THD + N  
1kHz, G = 1, VO = 3.5VRMS,  
RL = 10kΩ  
TRANSIENT RESPONSE  
SR  
Slew Rate  
AV = 1, RL = 2kΩ, VO = 10VP-P  
±1.2  
100  
V/µs  
ns  
tr, tf, Small  
Signal  
Rise Time  
10% to 90% of VOUT  
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,  
R
L = 2kΩ to VCM  
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,  
L = 2kΩ to VCM  
AV = 1, VOUT = 10VP-P, Rf = 0Ω  
L = 2kΩ to VCM  
Fall Time  
90% to 10% of VOUT  
100  
8.5  
ns  
µs  
R
ts  
Settling Time to 0.01%  
10V Step; 10% to VOUT  
R
Electrical Specifications V ±5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the  
S
CM  
O
A
operating temperature range, -55°C to +125°C.  
MIN  
MAX  
PARAMETER  
VOS  
DESCRIPTION  
Offset Voltage  
CONDITIONS  
(Note 5)  
TYP  
40  
(Note 5)  
UNIT  
µV  
ΔVOS  
Input Offset Voltage Match  
Input Offset Current  
44  
4
µV  
nA  
IOS  
IB  
Input Bias Current  
-230  
nA  
V
VCMIR  
Common Mode Input Voltage Range  
Guaranteed by CMRR Test  
(V-) - 0.5  
V-  
(V+) + 1.8  
(V+) - 1.8  
V
CMRR  
PSRR  
AVOL  
Common-Mode Rejection Ratio  
Power Supply Rejection Ratio  
Open-Loop Gain  
V
V
CM = V- - 0.5V to V+ - 1.8  
CM = V- to V+ -1.8V  
117  
124  
130  
dB  
VS = 3V to 40V,  
CMIR = Valid Input Voltage  
dB  
dB  
V
RL = 10kΩ to ground  
O = -3V to +3V  
V
VOH  
Output Voltage High,  
V+ to VOUT  
RL = 10kΩ  
65  
70  
38  
45  
0.85  
8
mV  
mV  
mV  
mV  
mA  
mA  
mA  
VOL  
Output Voltage Low,  
RL = 10kΩ  
VOUT to V-  
IS  
IS+  
IS-  
Supply Current/Amplifier  
Source Current Capability  
Sink Current Capability  
8
FN7871.1  
August 17, 2011  
4
ISL70218SRH  
Electrical Specifications V ±5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the  
S
CM  
O
A
operating temperature range, -55°C to +125°C.  
MIN  
MAX  
PARAMETER  
DESCRIPTION  
CONDITIONS  
(Note 5)  
TYP  
(Note 5)  
UNIT  
AC SPECIFICATIONS  
GBW  
enp-p  
en  
Gain Bandwidth Product  
Voltage Noise  
3.2  
320  
9
MHz  
nVP-P  
0.1Hz to 10Hz  
f = 10Hz  
Voltage Noise Density  
Voltage Noise Density  
Voltage Noise Density  
Voltage Noise Density  
Current Noise Density  
nV/Hz  
nV/Hz  
nV/Hz  
nV/Hz  
fA/Hz  
%
en  
f = 100Hz  
f = 1kHz  
5.7  
en  
5.5  
en  
f = 10kHz  
f = 1kHz  
5.5  
in  
380  
0.0003  
THD + N  
Total Harmonic Distortion + Noise  
1kHz, G = 1, VO = 1.25VRMS,  
RL = 10kΩ  
TRANSIENT RESPONSE  
SR  
Slew Rate  
AV = 1, RL = 2kΩ, VO = 4VP-P  
±1  
V/µs  
ns  
tr, tf, Small  
Signal  
Rise Time  
10% to 90% of VOUT  
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,  
100  
R
L = 2kΩ to VCM  
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,  
L = 2kΩ to VCM  
AV = 1, VOUT = 4VP-P, Rf = 0Ω  
L = 2kΩ to VCM  
Fall Time  
90% to 10% of VOUT  
100  
4
ns  
µs  
R
ts  
Settling Time to 0.01%  
4V Step; 10% to VOUT  
R
NOTE:  
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.  
Post Radiation Characteristics V ±15V, V = 0V, V = 0V, R = Open, T = +25°C, unless otherwise noted. This data is typical  
S
CM  
O
L
A
test data post radiation exposure at a rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose radiation. These  
are not limits nor are they guaranteed.  
PARAMETER  
VOS  
DESCRIPTION  
Offset Voltage  
CONDITIONS  
50k RAD  
35  
75k RAD  
35  
100k RAD  
35  
UNIT  
µV  
IOS  
Input Offset Current  
2
3
5
nA  
IB  
Input Bias Current  
200  
129  
130  
131.6  
400  
128  
130  
131.1  
575  
nA  
CMRR  
PSRR  
AVOL  
Common-Mode Rejection Ration  
Power Supply Rejection Ratio  
Open-Loop Gain  
V
CM = -13V to +13V  
S = ±2.25V to ±15V  
127  
dB  
V
130  
dB  
VO = -13V to +13V  
131.1  
dB  
RL = 10kΩ to ground  
VOH  
VOL  
IS  
Output Voltage High  
V+ to VOUT  
RL = 10kΩ to ground  
71  
54  
74  
57  
76  
59  
mV  
mV  
µA  
Output Voltage Low  
RL = 10kΩ to ground  
VOUT to V-  
Supply Current/Amplifier  
830  
830  
830  
TRANSIENT RESPONSE  
SR Slew Rate  
AV = 10, RL = 2kΩ, VO = 4VP-P  
1.24  
1.23  
1.22  
V/µs  
FN7871.1  
August 17, 2011  
5
ISL70218SRH  
Post Radiation Characteristics V ±15V, V = 0V, V = 0V, R = Open, T = +25°C, unless otherwise noted. This data is typical  
S
CM  
O
L
A
test data post radiation exposure at a rate of 10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose radiation. These are  
not limits nor are they guaranteed.  
PARAMETER  
DESCRIPTION  
Offset Voltage  
CONDITIONS  
20k RAD  
21  
50k RAD  
15  
100k RAD  
10  
UNIT  
µV  
VOS  
IOS  
IB  
Input Offset Current  
Input Bias Current  
8
10  
10  
nA  
130  
625  
130  
130  
nA  
IS  
Supply Current/Amplifier  
615  
600  
µA  
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.  
400  
300  
200  
100  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
+25°C  
+125°C  
V
= ±15V  
S
-100  
-200  
-300  
-400  
-40°C  
-55°C  
V
= ±5V  
S
-16  
-15  
-14  
-13 13  
14  
15  
16  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
TEMPERATURE (°C)  
INPUT COMMON MODE VOLTAGE (V)  
FIGURE 4. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE  
VOLTAGE, VS = ±15V  
FIGURE 3. VOS vs TEMPERATURE  
0
-150  
-50  
-100  
-150  
-200  
-250  
-300  
-350  
-400  
-450  
-500  
V
= +40V  
S
-200  
-250  
-300  
-350  
-400  
V
= +30V  
S
V
= +3.0V  
S
V
= +4.5V  
S
V
= +10V  
S
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
(V)  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
V
S
TEMPERATURE (°C)  
FIGURE 5. IBIAS vs VS  
FIGURE 6. IBIAS vs TEMPERATURE vs SUPPLY  
FN7871.1  
August 17, 2011  
6
ISL70218SRH  
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)  
132  
130  
128  
126  
124  
122  
120  
118  
116  
114  
112  
110  
132  
130  
128  
126  
124  
122  
120  
118  
116  
114  
112  
110  
CHANNEL-A  
CHANNEL-A  
CHANNEL-B  
CHANNEL-B  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
TEMPERATURE (°C)  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
TEMPERATURE (°C)  
FIGURE 7. CMRR vs TEMPERATURE, VS = ±15V  
FIGURE 8. CMRR vs TEMPERATURE, VS = ±5V  
140  
140  
135  
130  
125  
120  
115  
110  
105  
100  
130  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
V
= ±15V  
S
SIMULATION  
0
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
TEMPERATURE (°C)  
1m 0.01 0.1  
1
10 100 1k 10k 100k 1M 10M 100M 1G  
FREQUENCY (Hz)  
FIGURE 9. CMRR vs FREQUENCY, VS = ±15V  
FIGURE 10. PSRR vs TEMPERATURE, VS = ±15V  
140  
130  
120  
110  
100  
90  
140  
130  
120  
110  
100  
90  
PSRR+  
PSRR+  
80  
80  
70  
70  
60  
60  
50  
50  
40  
30  
V
= ±15V  
= 1  
40  
30  
V
= ±5V  
A = 1  
V
S
S
A
V
20  
10  
0
20  
10  
0
C
R
= 4pF  
= 10k  
= 1V  
C
R
= 4pF  
= 10k  
= 1V  
L
L
PSRR-  
PSRR-  
L
L
V
V
CM  
P-P  
CM P-P  
-10  
10  
-10  
10  
100  
1k  
10k  
100k  
1M  
10M  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 11. PSRR vs FREQUENCY, VS = ±15V  
FIGURE 12. PSRR vs FREQUENCY, VS = ±5V  
FN7871.1  
August 17, 2011  
7
ISL70218SRH  
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)  
200  
180  
160  
140  
120  
100  
80  
60  
40  
20  
0
-20  
-40  
-60  
-80  
-100  
70  
60  
50  
40  
30  
20  
10  
0
R
= 10k, R = 10Ω  
G
F
A
= 1000  
CL  
PHASE  
R
= 10k, R = 100Ω  
G
F
V
= ±5V & ±15V  
= 4pF  
= 2k  
S
A
= 100  
= 10  
CL  
C
R
V
L
L
= 100mV  
OUT  
P-P  
A
CL  
GAIN  
R
= 10k, R = 1kΩ  
F
G
A
= 1  
CL  
V
R
= ±15V  
= 1MΩ  
S
R
= 0, R = ∞  
F
G
L
-10  
100  
1k  
10k  
100k  
1M  
10M  
1m 0.01 0.1  
1
10 100 1k 10k 100k 1M 10M100M 1G  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 14. FREQUENCY RESPONSE vs CLOSED LOOP GAIN  
FIGURE 13. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V  
1
0
1
0
-1  
-2  
-3  
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-9  
-4  
-5  
-6  
-7  
-8  
-9  
R
= OPEN, 100k, 10k  
R = OPEN, 100k, 10k  
L
L
R
= 1k  
R
= 1k  
L
L
V
= ±15V  
= 4pF  
= +1  
V
= ±5V  
= 4pF  
= +1  
R
= 499  
R
= 499  
L
S
S
L
C
C
R
= 100  
R = 100  
L
L
L
L
A
A
V
V
R
= 49.9  
R = 49.9  
L
L
V
= 100mV  
V
= 100mV  
OUT  
p-p  
OUT  
p-p  
1k  
10k  
100k  
1M  
10M  
100  
1k  
10k  
100k  
1M  
10M  
100  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 15. GAIN vs FREQUENCY vs RL, VS = ±15V  
FIGURE 16. GAIN vs FREQUENCY vs RL, VS = ±5V  
1
0
1
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-9  
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-9  
V
V
= ±1.5V  
S
V
S
V
= 10mV  
V = 50mV  
OUT  
= ±5V  
S
OUT  
P-P  
= ±15V  
V
= ±5V  
= 4pF  
= +1  
P-P  
S
C
R
A
= 4pF  
= 10k  
= +1  
L
L
C
V
= 100mV  
L
OUT  
P-P  
P-P  
A
V
V
= 500mV  
V
OUT  
R
= INF  
V
= 100mV  
L
OUT  
P-P  
V
= 1V  
P-P  
OUT  
100  
1k  
10k  
100k  
1M  
10M  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 18. GAIN vs FREQUENCY vs SUPPLY VOLTAGE  
FIGURE 17. GAIN vs FREQUENCY vs OUTPUT VOLTAGE  
FN7871.1  
August 17, 2011  
8
ISL70218SRH  
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)  
100  
90  
80  
70  
60  
50  
40  
42  
40  
38  
36  
34  
32  
30  
28  
26  
24  
22  
20  
V
R
= ±15V  
= 10k  
V
R
= ±5V  
= 10k  
S
S
L
L
V
V
OH  
OH  
V
OL  
V
OL  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
TEMPERATURE (°C)  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
TEMPERATURE (°C)  
FIGURE 19. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,  
S = ±15V, RL = 10k  
FIGURE 20. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,  
VS = ±5V, RL = 10k  
V
1.0  
0.1  
1.0  
V
= ±5V and ±15V  
V = ±5V and ±15V  
S
S
+125°C  
+25°C  
+125°C  
+25°C  
0.1  
0.01  
0.01  
-55°C  
1.0  
-55°C  
1.0  
0.001  
0.001  
0.001  
0.01  
0.1  
LOAD CURRENT (mA)  
10  
0.001  
0.01  
0.1  
LOAD CURRENT (mA)  
10  
FIGURE 21. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT,  
VS = ±5V and ±15V  
FIGURE 22. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT,  
VS = ±5V and ±15V  
15  
14  
5
V
A
R
V
= ±15V  
= 2  
4
3
2
V
A
R
V
= ±5V  
= 2  
S
S
13  
12  
11  
V
V
+125°C  
+75°C  
+125°C  
+75°C  
= R = 100k  
= R = 100k  
F
G
F
G
= ±7.5V-DC  
= ±2.5V-DC  
IN  
IN  
-55°C  
10  
1
-55°C  
-40°C  
-10  
-1  
0°C  
-11  
-12  
-13  
-14  
-15  
-40°C  
0°C  
-2  
-3  
-4  
-5  
+25°C  
+25°C  
0
2
4
6
8
10 12 14 16 18 20 22 24  
I-FORCE (mA)  
0
2
4
6
8
10 12 14 16 18 20 22 24  
I-FORCE (mA)  
FIGURE 23. OUTPUT VOLTAGE SWING vs LOAD CURRENT, VS = ±15V  
FIGURE 24. OUTPUT VOLTAGE SWING vs LOAD CURRENT, VS = ±5V  
FN7871.1  
August 17, 2011  
9
ISL70218SRH  
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)  
1600  
1400  
1200  
1000  
800  
1100  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
V
= ±21V  
S
V
= ±15V  
S
V
= ±2.25V  
S
600  
400  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
TEMPERATURE (°C)  
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42  
(V)  
V
SUPPLY  
FIGURE 25. SUPPLY CURRENT vs TEMPERATURE vs SUPPLY  
VOLTAGE  
FIGURE 26. SUPPLY CURRENT vs SUPPLY VOLTAGE  
100  
10  
1
100  
10  
1
100  
10  
100  
10  
1
V
= ±18V  
V = ±5V  
S
S
INPUT NOISE VOLTAGE  
INPUT NOISE VOLTAGE  
INPUT NOISE CURRENT  
INPUT NOISE CURRENT  
1
0.1  
100k  
0.1  
0.1  
0.1  
100k  
0.1  
0.1  
1
10  
100  
1k  
10k  
1
10  
100  
1k  
10k  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 27. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs  
FREQUENCY, VS = ±18V  
FIGURE 28. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs  
FREQUENCY, VS = ±5V  
500  
500  
V
= ±5V  
= 10k  
V
= ±18V  
= 10k  
S
S
400  
300  
200  
100  
0
400  
300  
200  
100  
0
A
A
V
V
-100  
-200  
-300  
-400  
-500  
-100  
-200  
-300  
-400  
-500  
0
1
2
3
4
5
6
7
8
9
10  
0
1
2
3
4
5
6
7
8
9
10  
TIME (s)  
TIME (s)  
FIGURE 29. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±18V  
FIGURE 30. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±5V  
FN7871.1  
August 17, 2011  
10  
ISL70218SRH  
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)  
0.1  
0.1  
-55°C  
V
= ±15V  
= 4pF  
= 2k  
V
= ±15V  
= 4pF  
= 10k  
= 10V  
-55°C  
S
S
C
R
V
C
R
V
L
L
L
L
A
= 10  
A = 10  
V
V
+25°C  
= 10V  
+25°C  
OUT  
P-P  
OUT  
P-P  
+125°C  
0.01  
0.01  
C-WEIGHTED  
22Hz TO 500kHz  
C-WEIGHTED  
22Hz TO 500kHz  
+125°C  
0.001  
0.0001  
0.001  
0.0001  
-55°C  
= 1  
-55°C  
= 1  
+25°C  
+125°C  
+25°C  
+125°C  
A
A
V
V
10  
100  
1k  
10k  
100k  
10  
100  
1k  
FREQUENCY (Hz)  
10k  
100k  
FREQUENCY (Hz)  
FIGURE 31. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10,  
RL = 2k  
FIGURE 32. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10,  
RL = 10k  
1.0  
1.0  
V
C
R
= ±15V  
= 4pF  
= 2k  
C-WEIGHTED  
22Hz TO 22kHz  
V
C
R
= ±15V  
= 4pF  
= 10k  
C-WEIGHTED  
22Hz TO 22kHz  
S
S
L
L
L
L
f = 1kHz  
f = 1kHz  
0.1  
0.01  
0.1  
0.01  
A
= 10  
V
A
= 10  
V
+125°C  
+125°C  
-55°C  
+25°C  
-55°C  
+25°C  
0.001  
0.0001  
0.001  
0.0001  
A
= 1  
25  
V
A
= 1  
-55°C  
30  
V
-55°C  
30  
+125°C  
20  
+25°C  
10  
+125°C  
20  
)
P-P  
+25°C  
10  
0
5
15  
(V  
0
5
15  
(V  
25  
V
V
)
P-P  
OUT  
OUT  
FIGURE 33. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,  
AV = 1, 10, RL = 2k  
FIGURE 34. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,  
AV = 1, 10, RL = 10k  
6
2.4  
V
= ±15V  
= 1  
= 2k  
V
= ±5V  
= 1  
S
S
2.0  
1.6  
1.2  
0.8  
A
A
V
V
4
2
R
C
R
C
= 2k  
= 4pF  
L
L
L
L
= 4pF  
0.4  
0
0
-0.4  
-0.8  
-1.2  
-1.6  
-2.0  
-2.4  
-2  
-4  
-6  
0
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
0
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
TIME (µs)  
TIME (µs)  
FIGURE 35. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V  
FIGURE 36. LARGE SIGNAL 4V STEP RESPONSE, VS = ±5V  
FN7871.1  
August 17, 2011  
11  
ISL70218SRH  
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)  
6
5
100  
V
V
= ±5V  
= ±5.9V  
S
V
= ±15V  
AND  
= ±5V  
= 1  
= 2k  
= 4pF  
S
80  
IN  
4
V
S
60  
INPUT  
A
3
V
40  
R
C
L
L
2
20  
1
OUTPUT  
0
0
-1  
-2  
-3  
-4  
-5  
-6  
-20  
-40  
-60  
-80  
-100  
0
1
2
3
4
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8  
TIME (µs)  
2
TIME (ms)  
FIGURE 38. NO PHASE REVERSAL  
FIGURE 37. SMALL SIGNAL TRANSIENT RESPONSE,  
V
S = ±5V, ±15V  
0
200  
160  
120  
80  
20  
0
-40  
-80  
V
A
R
V
= ±15V  
= 100  
= 10k  
INPUT  
S
V
INPUT  
L
-4  
16  
12  
8
= 100mV  
IN  
P-P  
OVERDRIVE = 1V  
-8  
OUTPUT  
-12  
-120  
-160  
-200  
OUTPUT  
V
= ±15V  
= 100  
= 10k  
S
A
V
-16  
-20  
40  
4
R
V
L
= 100mV  
IN  
P-P  
OVERDRIVE = 1V  
0
0
40  
0
4
8
12  
16  
20  
24  
28 32 36  
40  
0
4
8
12  
16  
20  
24  
28  
32  
36  
TIME (µs)  
TIME (µs)  
FIGURE 39. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,  
S = ±15V  
FIGURE 40. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,  
VS = ±15V  
V
6
5
4
3
2
60  
50  
40  
30  
20  
0
-10  
-20  
-30  
-40  
-50  
-60  
0
V
= ±5V  
= 100  
= 10k  
S
A
V
-1  
-2  
-3  
-4  
INPUT  
R
V
L
= 50mV  
IN  
P-P  
OVERDRIVE = 1V  
OUTPUT  
OUTPUT  
INPUT  
V
A
R
V
= ±5V  
= 100  
= 10k  
S
V
1
0
L
10  
0
-5  
-6  
= 50mV  
IN  
P-P  
OVERDRIVE = 1V  
0
4
8
12  
16  
20  
24  
28  
32  
36  
40  
0
4
8
12  
16  
20  
24  
28 32 36  
40  
TIME (µs)  
TIME (µs)  
FIGURE 41. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,  
S = ±5V  
FIGURE 42. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,  
VS = ±5V  
V
FN7871.1  
August 17, 2011  
12  
ISL70218SRH  
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)  
100  
100  
V
= ±15V  
V
= ±5V  
S
S
A
= 10  
A
= 10  
V
V
10  
10  
A
= 100  
A
= 100  
V
V
1
1
0.10  
0.01  
0.10  
0.01  
A
= 1  
A
= 1  
V
V
1
10  
100  
1k  
10k  
100k  
1M  
10M  
1
10  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 43. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V  
FIGURE 44. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±5V  
60  
60  
V
V
= ±5V  
V
V
= ±15V  
S
S
= 100mV  
= 100mV  
OUT  
P-P  
OUT  
P-P  
50  
40  
30  
20  
10  
0
50  
40  
30  
20  
10  
0
A
= 1  
A
= 1  
V
V
A
= 10  
A
= 10  
V
V
A
= -1  
V
A
= -1  
V
0.001  
0.01  
0.1  
1
10  
100  
0.001  
0.010  
0.100  
1
10  
100  
LOAD CAPACITANCE (nF)  
LOAD CAPACITANCE (nF)  
FIGURE 45. OVERSHOOT vs CAPACITIVE LOAD, VS = ±15V  
FIGURE 46. OVERSHOOT vs CAPACITIVE LOAD, VS = ±5V  
30  
30  
V
R
= ±15V  
= 10k  
V
= ±15V  
= 1  
S
S
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
8
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
A
L
V
I
-SINK  
SC  
6
4
2
I
-SOURCE  
SC  
0
1k  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
TEMPERATURE (°C)  
10k  
100k  
1M  
FREQUENCY (Hz)  
FIGURE 47. IMAX OUTPUT VOLTAGE vs FREQUENCY  
FIGURE 48. SHORT CIRCUIT CURRENT vs TEMPERATURE, VS  
±15V  
=
FN7871.1  
August 17, 2011  
13  
ISL70218SRH  
Applications Information  
Functional Description  
R
F
V+  
The ISL70218SRH is a dual, 3.2MHz, single-supply, rail-to-rail  
output amplifier with a common mode input voltage range  
extending to a range of 0.5V below the V- rail. The input stage is  
optimized for precision sensing of ground-referenced signals in  
single-supply applications. The input stage is able to handle large  
input differential voltages without phase inversion, making this  
amplifier suitable for high-voltage comparator applications. The  
bipolar design features high open loop gain and excellent DC  
input and output temperature stability. This op amp features very  
low quiescent current of 850µA, and low temperature drift. The  
device is fabricated in a new precision 40V complementary  
bipolar DI process and is immune from latch-up for up to a 36V  
supply range.  
R
R
-
IN  
-
V
-
IN  
+
IN  
+
V
+
R
IN  
L
R
G
V-  
FIGURE 49. INPUT ESD DIODE CURRENT LIMITING  
Output Drive Capability  
The bipolar rail-to-rail output stage features low saturation levels  
that enable an output voltage swing to less than 15mV when the  
total output load (including feedback resistance) is held below  
50µA (Figures 21 and 22). With ±15V supplies, this can be  
achieved by using feedback resistor values >300k.  
Operating Voltage Range  
The op amp is designed to operate over a single supply range of 3V  
to 36V or a split supply voltage range of +1.8V/-1.2V to ±18V. The  
device is fully characterized at 30V (±15V). Both DC and AC  
performance remain virtually unchanged over the complete  
operating voltage range. Parameter variation with operating  
voltage is shown in the “Typical Performance Curves” beginning on  
page 6.  
The output stage is internally current limited. Output current limit  
over temperature is shown in Figures 23 and 24. The amplifiers  
can withstand a short circuit to either rail as long as the power  
dissipation limits are not exceeded. This applies to only one  
amplifier at a time for the dual op amp. Continuous operation  
under these conditions may degrade long-term reliability.  
The input common mode voltage to the V+ rail (V+ - 1.8V over the  
full temperature range) may limit amplifier operation when  
operating from split V+ and V- supplies. Figure 4 shows the  
common mode input voltage range variation over temperature.  
The amplifiers perform well when driving capacitive loads  
(Figures 45 and 46). The unity gain, voltage follower (buffer)  
configuration provides the highest bandwidth but is also the  
most sensitive to ringing produced by load capacitance found in  
BNC cables. Unity gain overshoot is limited to 35% at  
capacitance values to 0.33nF. At gains of 10 and higher, the  
device is capable of driving more than 10nF without significant  
overshoot.  
Input Stage Performance  
The ISL70218SRH PNP input stage has a common mode input  
range extending up to 0.5V below ground at +25°C. Full amplifier  
performance is guaranteed for input voltage down to ground (V-)  
over the -55°C to +125°C temperature range. For common mode  
voltages down to -0.5V below ground (V-), the amplifiers are fully  
functional, but performance degrades slightly over the full  
temperature range. This feature provides excellent CMRR, AC  
performance, and DC accuracy when amplifying low-level,  
ground-referenced signals.  
Output Phase Reversal  
Output phase reversal is a change of polarity in the amplifier  
transfer function when the input voltage exceeds the supply  
voltage. The ISL70218SRH is immune to output phase reversal  
out to 0.5V beyond the rail (VABS MAX) limit (Figure 38).  
The input stage has a maximum input differential voltage equal  
to a diode drop greater than the supply voltage and does not  
contain the back-to-back input protection diodes found on many  
similar amplifiers. This feature enables the device to function as  
a precision comparator by maintaining very high input  
impedance for high-voltage differential input comparator  
voltages. The high differential input impedance also enables the  
device to operate reliably in large signal pulse applications,  
without the need for anti-parallel clamp diodes required on  
MOSFET and most bipolar input stage op amps. Thus, input  
signal distortion caused by nonlinear clamps under high slew  
rate conditions is avoided.  
Single Channel Usage  
The ISL70218SRH is a dual op amp. If the application requires  
only one channel, the user must configure the unused channel to  
prevent it from oscillating. The unused channel oscillates if the  
input and output pins are floating. This results in  
higher-than-expected supply currents and possible noise  
injection into the channel being used. The proper way to prevent  
oscillation is to short the output to the inverting input, and  
ground the positive input (Figure 50).  
-
In applications in which one or both amplifier input terminals is  
at risk of exposure to voltages beyond the supply rails,  
current-limiting resistors may be needed at each input terminal  
(see Figure 49, RIN+, RIN-) to limit current through the  
power-supply ESD diodes to 20mA.  
+
FIGURE 50. PREVENTING OSCILLATIONS IN UNUSED CHANNELS  
FN7871.1  
August 17, 2011  
14  
ISL70218SRH  
PDMAX for each amplifier can be calculated using Equation 2:  
Power Dissipation  
It is possible to exceed the +150°C maximum junction  
temperatures under certain load and power supply conditions. It  
is therefore important to calculate the maximum junction  
temperature (TJMAX) for all applications to determine if power  
supply voltages, load conditions, or package type need to be  
modified to remain in the safe operating area. These parameters  
are related using Equation 1:  
V
OUTMAX  
(EQ. 2)  
------------------------  
PD  
= V × I  
+ (V - V ) ×  
OUTMAX  
MAX  
S
qMAX  
S
R
L
where  
• PDMAX = Maximum power dissipation of one amplifier  
• VS = Total supply voltage  
(EQ. 1)  
• IqMAX = Maximum quiescent supply current of one amplifier  
• VOUTMAX = Maximum output voltage swing of the application  
• RL = Load resistance  
T
= T  
+ θ xPD  
MAX JA MAXTOTAL  
JMAX  
where  
• PDMAXTOTAL is the sum of the maximum power dissipation of  
each amplifier in the package (PDMAX  
)
• TMAX = Maximum ambient temperature  
ΘJA = Thermal resistance of the package  
FN7871.1  
August 17, 2011  
15  
ISL70218SRH  
TOP METALLIZATION  
Package Characteristics  
Weight of Packaged Device  
Type: AlCu (99.5%/0.5%)  
Thickness: 30kÅ  
0. 4029 grams (Typical)  
BACKSIDE FINISH  
Lid Characteristics  
Silicon  
Finish: Gold  
Potential: Floating  
PROCESS  
PR40  
Die Characteristics  
ASSEMBLY RELATED INFORMATION  
Die Dimensions  
SUBSTRATE POTENTIAL  
1565µm x 2125µm (62mils x 84mils)  
Thickness: 355µm ± 25µm (14 mils ± 1 mil)  
Unbiased  
ADDITIONAL INFORMATION  
Interface Materials  
WORST CASE CURRENT DENSITY  
< 2 x 105 A/cm2  
GLASSIVATION  
Type: Nitrox  
Thickness: 15kÅ  
Metallization Mask Layout  
OUT_A  
-IN_A  
+IN_A  
V-  
+IN_B  
-IN_B  
OUT_A  
V+  
FN7871.1  
August 17, 2011  
16  
ISL70218SRH  
Revision History  
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make  
sure you have the latest revision.  
DATE  
REVISION  
FN7871.1  
CHANGE  
8/17/11  
Removed coming soon from parts ISL70218SRHMF AND ISL70218SRHMX AND ISL70218SRHX/SAMPLE in  
Ordering Information Table.  
8/9/2011  
FN7871.0  
Initial Release  
Products  
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products  
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.  
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a  
complete list of Intersil product families.  
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on  
intersil.com: ISL70218SRH  
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff  
FITs are available from our website at: http://rel.intersil.com/reports/search.php  
For additional products, see www.intersil.com/product_tree  
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted  
in the quality certifications found at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time  
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be  
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third  
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN7871.1  
August 17, 2011  
17  
ISL70218SRH  
Ceramic Metal Seal Flatpack Packages (Flatpack)  
K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)  
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
e
A
A
INCHES MILLIMETERS  
MIN  
D
SYMBOL  
MAX  
0.115  
0.022  
0.019  
0.009  
0.006  
0.290  
0.260  
0.280  
-
MIN  
1.14  
0.38  
0.38  
0.10  
0.10  
-
MAX  
2.92  
0.56  
0.48  
0.23  
0.15  
7.37  
6.60  
7.11  
-
NOTES  
-A-  
-B-  
PIN NO. 1  
ID AREA  
A
b
0.045  
0.015  
0.015  
0.004  
0.004  
-
-
b
-
E1  
b1  
c
-
S1  
0.004  
H
A - B  
D
0.036  
H
A - B  
D
S
M
S
S
M
S
-
c1  
D
-
3
E
0.240  
-
6.10  
-
-
C
Q
E
E1  
E2  
E3  
e
3
-D-  
A
0.125  
0.030  
3.18  
0.76  
-
-H-  
-C-  
-
-
7
L
E2  
L
E3  
E3  
0.050 BSC  
1.27 BSC  
-
SEATING AND  
BASE PLANE  
c1  
LEAD FINISH  
k
0.008  
0.250  
0.026  
0.005  
-
0.015  
0.370  
0.045  
-
0.20  
6.35  
0.66  
0.13  
-
0.38  
9.40  
1.14  
-
2
L
-
BASE  
METAL  
Q
S1  
M
N
8
(c)  
6
b1  
0.0015  
0.04  
-
M
M
(b)  
10  
10  
-
SECTION A-A  
Rev. 0 3/07  
NOTES:  
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark. Alternately, a tab (dimension k)  
may be used to identify pin one.  
2. If a pin one identification mark is used in addition to a tab, the lim-  
its of dimension k do not apply.  
3. This dimension allows for off-center lid, meniscus, and glass  
overrun.  
4. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness. The maximum lim-  
its of lead dimensions b and c or M shall be measured at the cen-  
troid of the finished lead surfaces, when solder dip or tin plate  
lead finish is applied.  
5. N is the maximum number of terminal positions.  
6. Measure dimension S1 at all four corners.  
7. For bottom-brazed lead packages, no organic or polymeric mate-  
rials shall be molded to the bottom of the package to cover the  
leads.  
8. Dimension Q shall be measured at the point of exit (beyond the  
meniscus) of the lead from the body. Dimension Q minimum  
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-  
der dip lead finish is applied.  
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
10. Controlling dimension: INCH.  
FN7871.1  
August 17, 2011  
18  

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