ISL75052SEHFE/PROTO_技术文档

1.5A, Rad Hard, Positive, High Voltage LDO

ISL75052SEH

Features

The ISL75052SEH is a radiation hardened, single output LDO

specified for an output current of 1.5A. The device operates from

an input voltage range of 4.0V to 13.2V and provides for output

voltages of 0.6V to 12.7V. The output is adjustable based on a

resistor divider setting. Dropout voltages as low as 75mV (at

0.5A) typical can be realized using the device. This allows the

• DLA SMD 5962-13220

• Input supply range 4.0V to 13.2V.

• Output Current up to 1.5A at a T = +150°C

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• Best in class Accuracy ±1.5%

- Over line, load and temperature

• Ultra Low Dropout:

user to improve the system efficiency by lowering V to nearly

IN

V

.

OUT

- 75mV Dropout (typ) @ 0.5A

- 225mV Dropout (typ) @ 1.5A

The ENABLE feature allows the part to be placed into a low

shutdown current mode of 165µA (typ). When enabled the device

operates with a low ground current of 11mA (typ), which provides

for operation with Low Quiescent Power consumption.

• Noise of 100µV

(typ) between 300Hz to 300kHz

RMS

• SET mitigation with no added filtering/diodes

• Shutdown Current of 165µA (typ)

• Externally adjustable Output Voltage

• PSRR 65dB (typ) @ 1kHz

The device has superior transient response and is designed

keeping Single Event Effects in mind. This results in reduction of

the magnitude of SET seen on the output. There is no need for

additional protection diodes and filters.

• ENable and PGood Feature

COMP pin is provided to enable the use of external

• Programmable Soft-Start/In-rush Current Limiting

• Adjustable Overcurrent Protection

• Over-Temperature Shutdown

compensation. This is achieved by connecting a resistor and

capacitor from COMP to ground. The device is stable with

Tantalum capacitors as low as 47µF (KEMET T525 series) and

provides excellent regulation all the way from no Load to full

Load. The programmable soft-start allows one to program the

inrush current by means of the decoupling capacitor used on the

BYP pin. The OCP pin allows the short circuit output current limit

threshold to be programmed by means of a resistor from OCP pin

to GND. The OCP setting range is from a 0.16A min to 3.2A max.

The resistor sets the constant current threshold for the output

under fault conditions. The thermal shutdown disables the output

if the device temperature exceeds the specified value, it will

subsequently enter a ON/OFF cycle till the fault is removed.

• Stable with 47µF Min Tantalum Capacitor

• Package 16 Ld Flat Pack

• Radiation Environment

- High Dose Rate (50-300rad(Si)/s) . . . . . . . . . 100krad(Si)

- Low Dose Rate (0.01rad(Si)/s). . . . . . . . . . . . 100krad(Si)*

- SET/SEL/SEB. . . . . . . . . . . . . . . . . . . . . . . . ..86 MeV.cm2/mg

*Product capability established by initial characterization. The

"EH" version is acceptance tested on a wafer-by-wafer basis to

50krad(Si) at low dose rate.

Applications

• LDO regulator for Space Power Systems

• DSP, FPGA and µP Core Power Supplies

• Post Regulation of SMPS and Down Hole Drilling

Related Literature

See AN1850, "ISL75052SEH Evaluation Board User's Guide"

See AN1851, "SEE Testing of the ISL75052SEH"

See AN1852, "Radiation Report of the ISL75052SEH"

0.30

EN

VIN

0.25

0.20

0.15

0.10

0.05

0.00

+150°C

3,4,5 VIN

VOUT

ADJ

1,2

+125°C

16

8

BYP

15

14

13

12

VOUT

2.5V

ISL75052SEH

OCP EN

0.1µF

200µF

25°C

9

VCCX

PG

GND

2.2k

0.1µF 200µF

10

COMP

15.8k

2.2n

Ω

300

0.1µF

22k

VIN

4.87k

1nF

22k

PG

0

0.5

1.0

1.5

OUT

2.0

I

(A)

LOAD

FIGURE 2. DROPOUT vs I

FIGURE 1. TYPICAL APPLICATION

May 29, 2013

FN8456.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners

1

ISL75052SEH

Block Diagram

COMP

OCP

3.8V

LDO

VIN

VCCX

CURRENT

LIMIT

600mV

BYP

REFERENCE

BIAS

VOUT

POWER

PDMOS

THERMAL

SHUTDOWN

EN

UVLO

ADJ

PG

DELAY

540mV

GND

Typical Applications

EN

1

2

3

4

5

VOUT

VIN

16

15

14

BYP

ADJ

EN

VIN

GND 13

COMP 12

GND 11

PG 10

VCCX

ISL75052SEH

VIN

NC

22k

10k

100µF 100µF

0.1µF

1nF

PG

6

7

8

NC

VOUT = 2.5V

100µF

Ω

300

OCP

VCCX

9

15.8k

2.2k

0.1µF

100µF

NC = No connect pin can be connected

to either VIN or GND

2.2nF

4.87k

0.1µF

FIGURE 3.

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ISL75052SEH

Pin Configuration

ISL75052SEH

(16 Ld CDFP)

TOP VIEW

VOUT

VIN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

BYP

ADJ

EN

VIN

GND

VIN

COMP

TMODE

NC

PG

OCP

VCCX

DOTTED LINE SHOWS METAL BOTTOM

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

ESD CIRCUIT

Circuit 1

3, 4, 5

VIN

Input supply pins.

10

PG

This pin is logic high when V

is not in regulation.

is in regulation signal. A logic low defines when V

OUT

Circuit 2

OUT

13

9

GND

GND pin. Pin 13 is also connected to the metal lid of the package.

Circuit 2

VCCX

The 3.8V internal bus is pinned out to accept a decoupling capacitor. Connect a 0.1µF Circuit 2

ceramic capacitor from VCCX pin to GND.

1, 2

12

15

6, 7

16

8

VOUT

COMP

ADJ

Output voltage pins.

Circuit 1

Circuit 2

Add compensation capacitor & resistor between COMP and GND.

ADJ pin allows V

OUT

to be programmed with an external resistor divider.

NC

No connect. May be grounded if needed.

BYP

Connect a 0.1µF capacitor from BYP pin to GND, to filter the internal VREF.

OCP pin allows the Current limit to be programmed with an external resistor.

OCP

EN

14

11

V

independent chip enable. TTL and CMOS compatible.

IN

TMODE

Test Mode pin, must be connected to GND.

Bottom

Metallization

The metal surface on the bottom surface of the package is floating. For mounting

instructions see “Bottom Metal Mounting Guidelines” on page 8.

PAD

ESD_CL_12V

ESD_RC_7V

GND

ESD CIRCUIT 1

ESD CIRCUIT 2

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ISL75052SEH

Ordering Information

ORDERING

INTERNAL

PART

TEMP

PACKAGE

NUMBER

MKT. NUMBER

MARKING

RANGE (°C)

(RoHS Compliant)

PKG DWG. #

K16.E

5962R1322001VXC

5962R1322001V9A

ISL75052SEHF/SAMPLE

ISL75052SEHFE/PROTO

ISL75052SEHEV1ZB

NOTE:

ISL75052SEHVFE

Q 5962R13 22001VXC

-55 to +125

16 Ld CDFP

Die

ISL75052SEHVX

ISL75052SEHX/SAMPLE

ISL75052SEHFE/PROTO

Evaluation Board

Die Sample

16 Ld CDFP

ISL75052 SEHFE /PROTO

K16.E

1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations.

FN8456.0

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ISL75052SEH

Absolute Maximum Ratings

Thermal Information

V

Relative to GND without ion beam (Note 2) . . . . . . . . . . -0.3 to +16.0V

Relative to GND under ion beam (Note 2) . . . . . . . . . . . -0.3 to +14.7V

Relative to GND (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +14.7V

Thermal Resistance (Typical)

16 Ld CDFP Package (Notes 5, 6) . . . . . . .

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

θ

_JA(°C/W)

26

θ

_JC(°C/W)

IN

4.5

OUT

PG,EN,OCP/ADJ,COMP,REFIN,REFOUT relative to GND (Note 2) . . . -0.3to

+6.5VDC

Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

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Recommended Operating Conditions (Notes 3)

Radiation Information

Ambient Temperature Range (T ) . . . . . . . . . . . . . . . . . . .-55°C to +125°C

A

Junction Temperature (T ) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

J

Maximum Total Dose

V

Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V to 13.2V

High Dose(Dose Rate = 50 - 300radSi/s) . . . . . . . . . . . .100 krads (Si)

IN

V

Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5V to 12.7V

Low Dose(Dose Rate = 10milliradSi/s) (Note 4). . . . . . 100 krads (Si)

OUT

2

PG, EN, OCP/ADJ relative to GND . . . . . . . . . . . . . . . . . . . . . . . .0V to +5.5V

SET (V

OUT

within ±5% During Events . . . . . . . . . . . . . . . .86MeV/mg/cm

2

SEL/B (No Latchup/Burnout. . . . . . . . . . . . . . . . . . . . . . . . 86MeV/mg/cm

The output capacitance used for SEE testing is 2x100µF for C and C

,

IN

OUT

100nF for BYPASS

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

2. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions

define limits where specifications are guaranteed.

3. Refer to “Bottom Metal Mounting Guidelines” on page 8.

4. Product capability established by initial characterization. The "EH" version is acceptance tested on a wafer by wafer basis to 50 krad(Si) at low dose

rate.

5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

TechBrief TB379

6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

7. Electromigration specification defined as lifetime average junction temperature of +150°C where max rated DC current = lifetime average current.

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:

V

= V

OUT

+ 0.5V, V

OUT

= 4.0V, C = C

IN

= 2x100µF 60mΩ, KEMET type T541X107N025AH or equivalent, T = +25°C, I = 0A. Applications must follow

OUT J L

IN

thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 7 of the data sheet

and Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure T = T

J

A

defines guaranteed limits.

MIN

MAX

PARAMETER

DC CHARACTERISTICS

DC Output Voltage Accuracy

SYMBOL

TEST CONDITIONS

(Note 8) TYP (Note 8) UNITS

V

OUT

Resistor adjust to: 2.5V and 5.0V

OUT

V

= 2.5V, 4.0V < V < 5.0V; 0A < I

IN

< 1.5A,

-1.5

-2.0

-1.5

-2.0

0.2

1.5

2.0

1.5

2.0

%

OUT

T = -55°C to +125°C

LOAD

J

V

= 2.5V, 4.0V < V < 5.0V; 0A < I

IN

OUT

T = +25°C, Post Rad.

J

V

= 5.0V, 5.5V < V < 6.9V; 0A < I

IN

OUT

T = -55°C to +125°C

J

V

= 5.0V, 5.5V < V < 6.9V, 0A < I

IN

OUT

T = +25°C, Post Rad.

J

V

OUT

Resistor adjust to: 10.0V

= 10.0V, 10.5V < V < 13.2V, I

V

0A,

-1.5

-2.0

-1.5

-2.0

0.2

1.5

2.0

1.5

2.0

%

OUT

T =-55°C to +125°C

IN

LOAD =

J

V

= 10.0V, 10.5V < V < 13.2V, I

IN

OUT

T = +25°C, Post Rad.

LOAD =

J

V

= 10.0V, V = 10.5V, I

IN

= 1.5A, V =13.2V,

IN

OUT

LOAD

= 1.0A, T = -55°C to +125°C

I

LOAD

J

V

= 10.0V, V = 10.5V; I

IN LOAD

=1.5A, V =13.2V,

IN

OUT

I

= 1.0A, T = +25°C, Post Rad.

LOAD

J

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ISL75052SEH

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:

V

= V

OUT

+ 0.5V, V

OUT

= 4.0V, C = C

IN

= 2x100µF 60mΩ, KEMET type T541X107N025AH or equivalent, T = +25°C, I = 0A. Applications must follow

OUT J L

IN

thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 7 of the data sheet

and Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure T = T

J

A

defines guaranteed limits. (Continued)

MIN

MAX

PARAMETER

VCCX Pin

SYMBOL

TEST CONDITIONS

(Note 8) TYP (Note 8) UNITS

V

T = -55°C to +125°C; 4V < V < 13.2V; I

= 0A

;

3.7

591

588

3.9

600

4.1

609

612

V

VCCX

J

IN LOAD

ADJ Pin

V

T = -55°C to +125°C

mV

ADJ

J

ADJ Pin

V

T = 25°C, Post Rad

J

ADJ

BYP

BYP Pin

V

4.0V < V < 13.2V; I

IN

=0A

LOAD

T = -55°C to +125°C

,

J

DC Input Line Regulation

DC Output Load Regulation

ADJ Input Current

4.0V < V < 13.2V, V

IN

= 2.5V

= 5.0V

1

8

20

mV

µA

OUT

5.5V < V < 13.2V, V

IN

OUT

10.5V < V < 13.2V, V

IN OUT

= 10.0V

1

10

V

= 2.5V; 0A < I

= 5.0V; 0A < I

< 1.5A, V = 4.0V

IN

0.3

1.3

0.1

9

OUT

LOAD

< 1.5A, V = 5.5V

18

IN

< 1.5A, V = 10.5V

= 10.0V; 0A < I

= 0.6V

36

LOAD

IN

V

1

ADJ

Ground Pin Current

I

V

= 2.5V; I

= 0A, 4.0V < V < 13.2V

IN

6

8

10

mA

µA

Q

OUT

LOAD

Ground Pin Current

V

= 1.5A, 4.0V < V < 13.2V

IN

12

Ground Pin Current

= 10.0V, I

= 0A, 11.0V < V < 13.2V

IN

15

20

LOAD

Ground Pin Current

= 10.0V, I

= 1.5A, 11.0V < V < 13.2V

IN

20

25

Ground Pin Current in Shutdown

Dropout Voltage (Note 10)

I

ENABLE Pin = 0V, V = 4.0V

IN

70

120

300

160

300

400

0.32

SHDNL

I

ENABLE Pin = 0V, V = 13.2V

IN

165

75

µA

SHDNH

V

I

= 0.5A, V

= 1.0A, V

= 1.5A, V

= 3.6V and 12.7V

mV

A

DO

LOAD

OUT

150

225

0.24

Output Short Circuit Current for 16

Ld FP

ISCL

V

SET = 4.0V, V

OUT

= 3k, Note 12)

+ 0.5V < V < 13.2V,

IN

0.16

1.6

OUT

R

SET

Output Short Circuit Current for 16

Ld FP

ISCH

V

SET = 4.0V, V

OUT

= 300Ω, Note 12)

+ 0.5V < V < 13.2V,

IN

2.4

3.2

196

25

A

OUT

R

SET

Thermal Shutdown Temperature

(Note 9)

V

+ 0.5V < V < 13.2V

IN

154

175

°C

TSD

OUT

Thermal Shutdown Hysteresis

(Rising Threshold) (Note 9)

V

+ 0.5V < V < 13.2V

IN

TSDn

OUT

AC CHARACTERISTICS

Input Supply Ripple Rejection

(Note 9)

PSRR

PM

V

= 300mV, f = 1kHz, I

= 1.5A;

55

60

40

50

10

65

70

50

dB

°

P-P

LOAD

= 4.9V, V

= 4.0V

IN

OUT

Input Supply Ripple Rejection

(Note 9)

V

= 300mV, f = 120Hz, I

= 5mA;

LOAD

P-P

= 4.9V, V

= 2.5V

IN

OUT

Input Supply Ripple Rejection

(Note 9)

V

= 300mV, f = 100kHz, I

= 1.5A;

LOAD

P-P

= 4.9V, V

= 4.0V

IN

OUT

Phase Margin, (Note 9)

V

= 2.5V, 4.0V and 10V, C

= 2x100µF,

OUT

R

=22k, C

= 1nF

COMP

Gain Margin, (Note 9)

GM

V

= 2.5V, 4.0V and 10V C

= 2x100µF,

dB

OUT

R

= 22k, C

= 1nF

COMP

= 10mA, BW = 300Hz < f < 300kHz, BYPASS to

Output Noise Voltage, (Note 9)

I

100

µV

RMS

LOAD

GND capacitor = 0.2µF

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ISL75052SEH

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:

V

= V

OUT

+ 0.5V, V

OUT

= 4.0V, C = C

IN

= 2x100µF 60mΩ, KEMET type T541X107N025AH or equivalent, T = +25°C, I = 0A. Applications must follow

OUT J L

IN

thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 7 of the data sheet

and Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure T = T

J

A

defines guaranteed limits. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 8) TYP (Note 8) UNITS

DEVICE START-UP CHARACTERISTICS

Enable Pin Characteristics

Turn-on Threshold

4.0V < V < 13.2V

IN

0.5

0.8

1.2

1

V

Enable Pin Leakage Current

V

= 13.2V, EN = 5.5V

µA

ms

IN

Enable Pin Propagation Delay (EN

V

= 4.5V, V

OUT

= 4.0V, I

= 1.5A,

0.5

1.4

1.1

170

1.0

IN

LOAD

step 1.2V to V

OUT

= 100mV)

C

= 22µF, C

= 0.2µF

OUT

BYP

Enable Pin Turn-on Delay

(EN step 1.2V to PGOOD)

V

C

= 4.5V, V

= 4.0V, I

3.0

2.5

ms

mV

IN

OUT

= 2x100µF, C

= 0.2µF

OUT

BYP

= 4.0V, I

Enable Pin Turn-on Delay

(EN step 1.2V to PGOOD)

V

C

= 4.5V, V

= 1.5A,

IN

OUT

= 22µF, C

LOAD

= 0.2µF

OUT

BYP

Hysteresis (Falling Threshold)

PG Pin Characteristics

4.0V < V < 13.2V

75

IN

V

Error Flag Rising Threshold

Error Flag Falling Threshold

Error Flag Hysteresis

83

80

88

86

2.5

5

94

91

%V

OUT

%V

1.75

Error Flag Low Voltage

Error Flag Leakage Current

I

= 1mA

100

400

1

mV

SINK

= 10mA

5

mV

µA

SINK

V

= 13.2V, PG = 5.5V

IN

8. Parameters with bold face MIN and/or MAX limits are 100% tested at -55°C, 25°C and 125°C.

9. Limits established by characterization and are not production tested.

10. Dropout is defined by the difference in supply V and V

IN OUT

when the supply produces a 2% drop in V from its nominal value.

OUT

11. Refer to thermal package guidelines in “Bottom Metal Mounting Guidelines” on page 8..

12. OCP recovery overshoot should be within ±4% of the nominal VOUT setpoint.

13. SET performance of <±5% at LET = 86MeV.cm2/mg has been evaluated at V

0.1µF CDR04 X7R capacitor. Capacitor on BYP = 0.1µF CDR04 X7R.

= >2.5V with C = C

IN

= 2x100µF 10V 60mΩ in parallel with

OUT

OUTPUT CAPACITOR

Applications Information

Input Voltage Requirements

It is recommended to use a combination of Tantalum and

Ceramic capacitors to achieve a good volume to capacitance

ratio. The recommended combination is a 2x100µF 60mΩ rated,

KEMET T541 series tantalum capacitor, in parallel with a 0.1µF

MIL-PRF-49470 ceramic capacitor to be connected to V

Ground pins of the LDO with PCB traces no longer than 0.5cm.

This RH LDO will work from a V in the range of 4.0V to 13.2V.

IN

The input supply can have a tolerance of as much as ±10% for

conditions noted in the specification table. The minimum

guaranteed input voltage is 4.0V. However, due to the nature of

and

OUT

an LDO, V must be some margin higher than the output voltage

plus dropout at the maximum rated current of the application if

IN

INPUT CAPACITOR

It is recommended to use a combination of Tantalum and

Ceramic capacitors to achieve a good capacitance to volume

ratio. The recommended combination is a 2x100µF 60mΩ rated,

KEMET T541 series tantalum capacitor in parallel with a 0.1µF

active filtering (PSRR) is expected from V to V . The Dropout

spec of this family of LDOs has been generously specified in

order to allow design for efficient operation.

IN OUT

External Capacitor Requirements

MIL-PRF-49470 ceramic capacitor to be connected to V and

Ground pins of the LDO with PCB traces no longer than 0.5cm.

IN

GENERAL GUIDELINE

Current Limit Protection

External capacitors are required for proper operation. Careful

attention must be paid to layout guidelines and selection of

capacitor type and value to ensure optimal performance.

The RH LDO incorporates protection against overcurrent due to

any short or overload condition applied to the output pin. The

current limit circuit performs as a constant current source when

the output current exceeds the current limit threshold which can

be adjusted by means of a resistor connected between the OCP

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May 29, 2013

7

ISL75052SEH

pin and GND. If the short or overload condition is removed from

, then the output returns to normal voltage mode regulation.

Bottom Metal Electrical Potential

V

OUT

The package bottom metal is electrically isolated and unbiased.

The bottom metal may be electrically connected to any potential

which offers the best thermal path through conductive mounting

materials (conductive epoxy, solder, etc.) or may be left unbiased

through the use of electrically non-conductive mounting

In the event of an overload condition the LDO will begin to cycle

on and off due to the die temperature exceeding thermal fault

condition. However, one may never witness thermal cycling if the

heatsink used for the package can keep the die temperature

below the limits specified for thermal shutdown. The ROCP can

be calculated using the equation:

materials (non-conductive epoxy, Sil-pad, kapton film, etc.).

Bottom Metal Mounting Guidelines

The package bottom is a solderable metal surface. The following

JESD51-5 guidelines may be used to mount the package:

(EQ. 1)

R

= 893 ⁄ I

OCP

• Place a thermal land on the PCB under the bottom metal.

Where:

= The OCP resistor value in ohms.

• The land should be approximately the same size to 1mm

larger than the 0.19x0.41inch bottom metal.

R

OCP

I

= The required OCP threshold in amps.

OCP

• Place an array of thermal vias below the thermal land.

• Via array size: ~4 x 9 = 36 thermal vias

ESD Clamps

The ESD_CL_12V ESD clamps break down at nominally 17V. The

ESD_RC_7V clamps break down at nominally 7.5V with a

tolerance of ±10%. The PG pin has a diode to GND. The VOUT pin

has a diode to VIN (see “Pin Descriptions” on page 3).

• Via diameter: ~0.3mm drill diameter with plated copper on

the inside of each via.

• Via pitch: ~1.2mm.

Vias should drop to and contact as much buried metal area as

feasible to provide the best thermal path.

COMP Pin

This pin helps compensate the device for various load conditions.

For 4.0V < VIN < 6.0V use RCOMP = 40k and CCOMP = 1nF. For

6V < VIN < 13.2V use RCOMP = 40k and CCOMP = 4.7nF. The

max current of the COMP pin when shorted to GND is 160µA.

Thermal Fault Protection

In the event the die temperature exceeds +170°C (typ.) the

output of the LDO will shut down until the die temperature can

cool down to +150°C (typ.). The level of power combined with the

Undervoltage Lockout

thermal impedance of the package (θ of 5°C/W for the 16 Ld

JC

CDFP package) will determine if the junction temperature

exceeds the thermal shutdown temperature specified in the

specification table (see “Bottom Metal Mounting Guidelines” on

page 8).

The undervoltage lockout function detects when VCCX exceeds

3.2V. When that level is reached, the LDO feedback loop is

closed and the LDO can begin regulating. This is achieved by

freeing the BYP net to charge up and act as a reference voltage

to the EA. Prior to that happening, the LDO Power PMOS device is

clamped off.

FN8456.0

May 29, 2013

8

ISL75052SEH

Typical Operating Performance

2.605

2.600

2.595

2.590

2.585

2.580

2.575

2.570

2.565

2.560

2.555

10.35

10.30

10.25

10.20

10.15

10.10

10.05

10.00

V

AT 25°C

V

= 12V

V

= 10.8V

OUT

IN

V

AT 125°C

OUT

V

AT -55°C

V

= 13.2V

V

= 14.7V

OUT

IN

0

2

4

6

8

10

12

14

16

18

0

0.2

0.4

0.6

0.8

(A)

1.0

1.2

1.4

1.6

V

(V)

I

IN

OUT

FIGURE 4. LINE REGULATION vs TEMPERATURE (°C),

FIGURE 5A. LOAD REGULATION V

= 10.17V AT 25°C

OUT

V

= 2.579V, I

= 0mA

OUT

10.35

10.30

10.35

10.30

10.25

10.20

10.15

10.10

10.05

10.00

V

= 10.8V

V

= 12V

IN

10.25

10.20

10.15

10.10

10.05

10.00

V

= 12V

IN

V

= 10.8V

IN

V

= 14.7V

IN

V

= 13.2V

IN

V

= 14.7V

0.6

IN

V

= 13.2V

1.4

IN

0

0.2

0.4

0.6

0.8

(A)

1.0

1.2

1.4

0

0.2

0.4

0.8

(A)

1.0

1.2

1.6

I

OUT

FIGURE 5B. LOAD REGULATION V

= 10.13V AT 125°C

FIGURE 5C. LOAD REGULATION V

= 10.22V AT -55°C

OUT

2.61

2.60

2.59

2.61

2.60

2.59

V

= 12V

IN

V

= 10.5V

IN

V

= 4.5V

IN

V

= 4.0V

2.58

2.57

2.56

2.55

2.54

2.53

2.52

2.58

2.57

2.56

2.55

2.54

2.53

2.52

IN

V

= 14.7V

IN

V

= 13.2V

IN

V

= 5.5V

IN

V

= 5.0V

IN

0

0.2

0.4

0.6

0.8

(A)

1.0

1.2

1.4

0

0.2

0.4

0.6

0.8

(A)

1.0

1.2

1.4

1.6

I

OUT

FIGURE 6A. LOAD REGULATION V

= 2.567V AT 25°C

FIGURE 6B. LOAD REGULATION V

= 2.571V AT 125°C

OUT

FN8456.0

May 29, 2013

9

ISL75052SEH

Typical Operating Performance(Continued)

2.61

2.60

2.59

2.58

2.57

2.56

2.55

2.54

2.53

2.52

13.00

12.95

12.90

12.85

12.80

12.75

12.70

12.65

12.60

12.55

12.50

V

= 12V

IN

V

= 10.5V

IN

V

= 13.2V

IN

V

= 14.7V

= 16.2V

IN

V

= 14.7V

IN

V

= 13.2V

IN

V

IN

0

0.2

0.4

0.6

0.8

(A)

1.0

1.2

1.4

1.6

0

0.2

0.4

0.6

0.8

(A)

1.0

1.2

1.4

1.6

I

OUT

FIGURE 6C. LOAD REGULATION V

= 2.564V AT -55°C

FIGURE 7A. LOAD REGULATION V

= 12.75V AT 25°C

OUT

13.00

12.95

12.90

12.85

12.80

12.75

13.00

12.95

12.90

12.85

12.80

V

= 14.7V

V

= 13.2V

IN

12.75

12.70

12.65

12.60

12.55

12.50

V

= 16.2V

IN

V

= 14.7V

V

= 13.2V

IN

12.70

12.65

12.60

12.55

12.50

V

= 16.2V

IN

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0

0.2

0.4

0.6

0.8

(A)

1.0

1.2

1.4

1.6

I

(A)

I

OUT

FIGURE 7B. LOAD REGULATION V

= 12.63V AT 125°C

FIGURE 7C. LOAD REGULATION V

= 12.7V AT -55°C

OUT

Timebase = 500µs/DIV

V

= 20mV/DIV

OUT

V

= 20mV/DIV

OUT

I

= 500mA/DIV

OUT

I

= 500mA/DIV

OUT

FIGURE 8. LOAD STEP RESPONSE, 25°C, V = 4.0V, V

IN OUT

= 2.5V,

FIGURE 9. LOAD STEP RESPONSE, 25°C, V = 4.0V, V

IN OUT

= 2.5V,

I

= 0A to 1.6A, C

= 200µF, 30mΩ

OUT

I

= 0.15A to 1.6A, C

= 200µF, 30mΩ

OUT

FN8456.0

May 29, 2013

10

ISL75052SEH

Typical Operating Performance(Continued)

Timebase = 500µs/DIV

V

= 50mV/DIV

V

= 50mV/DIV

OUT

I

= 500mA/DIV

I

= 500mA/DIV

OUT

FIGURE 9B. LOAD STEP RESPONSE, 25°C, V = 13.2V, V

IN OUT

= 10V,

FIGURE 9A. LOAD STEP RESPONSE, 25°C, V = 13.2V, V

IN OUT

= 10V,

I

= 0.15A to 1.5A, C

= 200µF, 30mΩ

I

= 0A to 1.5A, C

= 200µF, 30mΩ

OUT

60

50

180

150

120

90

70

60

50

40

30

180

150

120

90

PHASE (°)

40

30

20

60

20

10

30

10

30

0

-10

-20

-30

-40

-50

-60

-70

-10

-20

-30

-40

-50

-60

-30

-60

-90

-120

-150

-180

-30

-60

-90

-120

-150

-180

GAIN (dB)

500

5k

50k

FREQUENCY (Hz)

500k

500

5k

50k

500k

FREQUENCY (Hz)

FIGURE 10. GAIN PHASE PLOTS, V = 4V, V

IN

= 2.5V, I

= 200µF, 30mΩ,

= 0.2A,

FIGURE 11. GAIN PHASE PLOTS, V = 4V, V

IN

= 2.5V, I = 1.5A,

OUT

= 200µF, 30mΩ,

OUT

R

= 22k, C

= 1nF, C

R

= 22k, C = 1nF, C

COMP

PHASE MARGIN = 98.68°, GAIN MARGIN = 23.01dB

PHASE MARGIN = 84.56°, GAIN MARGIN = 18.06dB

-30

-40

125°C PSRR (dB)

-50

-60

-70

25°C PSRR (dB)

-80

-55°C PSRR (dB)

10k

-90

-100

100

1k

100k

FREQUENCY (Hz)

FIGURE 12. PSRR, V = 4.9V, V

IN

= 4.0V, I

= 1.5A, R

COMP

= 22k, C

= 1nF, C = 200µF, 30mΩ

OUT

COMP

FN8456.0

May 29, 2013

11

ISL75052SEH

Typical Operating Performance(Continued)

Timebase = 1ms/DIV

C1 to C4 = 1V/DIV

Timebase = 1ms/DIV

C1 to C4 = 1V/DIV

EN

V

IN

OUT

P

GOOD

FIGURE 13. 25°C START-UP WITH ENABLE, V = 4V, V

IN OUT

= 2.5V,

FIGURE 14. 25°C START-UP WITH ENABLE, V = 4V, V = 2.5V,

IN OUT

I

= 0.1A

I

= 1.5A

OUT

Timebase = 5ms/DIV

C1 to C4 = 1V/DIV

Timebase = 5ms/DIV

C1 to C4 = 1V/DIV

V

OUT

V

OUT

V

IN

P

GOOD

EN

FIGURE 15. 25°C SHUTDOWN WITH ENABLE, V = 4V, V

IN OUT

= 2.5V,

FIGURE 16. 25°C SHUTDOWN WITH ENABLE, V = 4V, V

IN OUT

= 2.5V,

I

= 0.1A

I

= 1.5A

OUT

Timebase = 200µs/DIV

EN

V

IN

V

OUT

P

GOOD

FIGURE 17. 25°C PROPAGATION DELAY, V = 4.5V, V

IN

= 4V, I

= 1.5A, EN 50% TO V 5%

OUT

FN8456.0

May 29, 2013

12

ISL75052SEH

TOP METALLIZATION

Package Characteristics

Weight of Packaged Device

Type: AlCu (99.5%/0.5%)

Thickness: 2.7µm ± 0.4µm

0.59 Grams (Typical)

SUSTRATE

Lid Characteristics

Type: Silicon

Finish: Gold

Potential: Connected to Pin 13 (GND)

Case Isolation to Any Lead: 20 x 10 Ω (min)

BACKSIDE FINISH

Silicon

9

ASSEMBLY RELATED INFORMATION

Die Characteristics

Die Dimensions

SUBSTRATE POTENTIAL

Ground

2819μm x 5638μm (111 mils x 222 mils).

Thickness: 304.8μm ± 25.4μm (12.0 mils ± 1 mil).

ADDITIONAL INFORMATION

Interface Materials

WORST CASE CURRENT DENSITY

5

2

< 2 x 10 A/cm

GLASSIVATION

Type: Silicon Oxide and Silicon Nitride

Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm

TRANSISTOR COUNT

1074

PROCESS

0.6µm BiCMOS Junction Isolated

FN8456.0

May 29, 2013

13

ISL75052SEH

Metallization Mask Layout

TABLE 1. DIE LAYOUT X-Y COORDINATES

PAD

1

X

Y

DX

185

5508

185

DY

450

449

2689

450

185

450

185

184

450

NAME

VOUT

VIN

PIN#

1,2

3,4,5

8

1019

1249

2764

3070

3300

5037

5253

5099

4635

3824

2840

1799

668

1021

390

2

3

1354

1030

399

4

VIN

5

VIN

6

256

OCP

VCCX

PG

7

1635

2436

1660

2436

2381

1972

1652

9

8

10

9

TMODE

COMP

VIN

11

10

11

12

13

14

15

16

12

3,4,5

13

GND

EN

14

168

ADJ

15

168

BYP

16

789

VOUT

1,2

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8456.0

May 29, 2013

14

ISL75052SEH

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that

you have the latest revision.

DATE

REVISION

FN8456.0

CHANGE

May 29, 2013

Initial Release

About Intersil

Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management

semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal

computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting

www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at

http://www.intersil.com/en/support/qualandreliability.html#reliability

FN8456.0

May 29, 2013

15

ISL75052SEH

Package Outline Drawing

K16.E

16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

Rev 1, 1/12

0.015 (0.38)

PIN NO. 1

0.008 (0.20) ID OPTIONAL

1

2

A

0.050 (1.27 BSC)

PIN NO. 1

ID AREA

0.420

0.400

0.005 (0.13)

MIN

4

TOP VIEW

0.022 (0.56)

0.015 (0.38)

0.115 (2.92)

0.009 (0.23)

0.004 (0.10)

0.045 (1.14)

0.026 (0.66)

0.085 (2.16)

6

0.278 (7.06)

0.262 (6.65)

-D-

-H-

-C-

0.370 (9.40)

0.250 (6.35)

0.198 (5.03)

0.182 (4.62)

BOTTOM

METAL

0.03 (0.76) MIN

7

SEATING AND

BASE PLANE

SIDE VIEW

BOTTOM METAL

0.005 (0.127) REF.

OFFSET FROM

CERAMIC EDGE

OPTIONAL

PIN 1 INDEX

BOTTOM VIEW

NOTES:

Index area: A notch or a pin one identification mark shall be located

adjacent to pin one and shall be located within the shaded area shown.

The manufacturer’s identification shall not be used as a pin one

identification mark. Alternately, a tab may be used to identify pin one.

1.

0.006 (0.15)

0.004 (0.10)

LEAD FINISH

2. If a pin one identification mark is used in addition to a tab, the limits

of the tab dimension do not apply.

0.009 (0.23)

0.004 (0.10)

BASE

METAL

3. The maximum limits of lead dimensions (section A-A) shall be

measured at the centroid of the finished lead surfaces, when solder

dip or tin plate lead finish is applied.

0.019 (0.48)

0.015 (0.38)

4. Measure dimension at all four corners.

0.0015 (0.04)

MAX

5. For bottom-brazed lead packages, no organic or polymeric materials

shall be molded to the bottom of the package to cover the leads.

0.022 (0.56)

0.015 (0.38)

6. Dimension shall be measured at the point of exit (beyond the

meniscus) of the lead from the body. Dimension minimum shall

be reduced by 0.0015 inch (0.038mm) maximum when solder dip

lead finish is applied.

3

SECTION A-A

7. The bottom of the package is a solderable metal surface.

8. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

9. Dimensions: INCH (mm). Controlling dimension: INCH.

FN8456.0

May 29, 2013

16


型号：	ISL75052SEHFE/PROTO
厂家：	Intersil
描述：	1.5A, Rad Hard, Positive, High Voltage LDO
文件：	总16页 (文件大小：657K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL75052SEHFE/PROTO [INTERSIL]

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