ISL78010 [INTERSIL]
Automotive Grade TFT-LCD Power Supply; 汽车级TFT- LCD电源
| 型号： | ISL78010 |
| 厂家： | 
Intersil |
| 描述： | Automotive Grade TFT-LCD Power Supply |
| 文件： | 总18页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL78010
®
Data Sheet
May 30, 2007
FN6501.0
Automotive Grade TFT-LCD Power Supply
Features
The ISL78010 is a multiple output regulator for use in all
TFT-LCD automotive applications. It features a single boost
converter with an integrated 2A FET, two positive LDOs for
• 2A current FET
• 3V to 5V input
• Up to 20V boost output
• 1% regulation on boost output
V
V
and V
generation, and a single negative LDO for
ON
LOGIC
generation. The boost converter can be programmed
OFF
to operate in either P-mode for optimal transient response or
PI-mode for improved load regulation.
• V
-V
-V
-V
or
sequence control
LOGIC BOOST OFF ON
V
-V -V -V
LOGIC OFF BOOST ON
The ISL78010 includes fault protection for all four channels.
Once a fault is detected on either the V
• Programmable sequence delay
• Fully fault protected
, V
or V
BOOST ON
OFF
channels, the device is latched off until the input supply or
EN is cycled. If a fault is detected on the V channel,
LOGIC
the device is latched off until the input supply is cycled. The
channel is not affected by the EN function.
• Thermal shutdown
• Internal soft-start
V
LOGIC
The ISL78010 also includes an integrated start-up sequence
for V , V , V , then V or for V , V
• 32 Ld 5x5 TQFP packages
• Pb-free plus anneal available (RoHS compliant)
,
LOGIC BOOST OFF ON LOGIC OFF
V
, and V . The latter sequence requires a single
BOOST ON
external transistor. The timing of the start-up sequence is set
using an external capacitor.
Applications
• All Automotive LCD Displays
The ISL78010 comes in a 32 Ld 5x5 TQFP package and is
specified for operation over a -40°C to +105°C temperature
range.
Pinout
ISL78010
(32 LD 5X5 TQFP)
TOP VIEW
Ordering Information
PART NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL78010ANZ*
78010ANZ 32 Ld 5x5 TQFP
Q32.5x5
*Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
32 31 30 29 28 27 26 25
NC
1
VREF
NC
24
NC
DELB
NC
2
3
4
5
6
7
8
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
23
22
21
20
19
18
17
PGND
PGND
PGND
PGND
NC
LX
NC
DRVP
NC
FBN
9 10 11 12 13 14 15 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL78010
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
V
V
V
V
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . .-40°C to +105°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Continuous Junction Temperature . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
DELB
DRVP
DRVN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
DD
LX
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
DRVL
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications
V
= 5V, V
= 11V, I
= 200mA, V
= 15V, V
= -5V, V
= 2.5V, limits over -40°C to
DD
BOOST
LOAD
ON
OFF
LOGIC
+105°C temperature range, unless otherwise specified.
PARAMETER
SUPPLY
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
V
Supply Voltage
3
5.5
2.5
V
S
I
Quiescent Current
Enabled, LX not switching
Disabled
1.7
mA
µA
S
750
900
CLOCK
f
Oscillator Frequency
900
1000
1100
kHz
OSC
BOOST
V
V
Boost Output Range
5.5
20
V
V
BOOST
FBB
Boost Feedback Voltage
T
= +25°C
= +25°C
1.192
1.188
1.205
1.205
0.9
1.218
1.222
A
V
V
V
FBB Fault Trip Point
Reference Voltage
V
F_FBB
REF
T
1.19
1.187
85
1.215
1.215
1.235
1.238
V
A
V
D
Maximum Duty Cycle
Current Switch
%
MAX
LXMAX
LEAK
I
I
2.0
A
Switch Leakage Current
Switch ON-Resistance
Boost Efficiency
V
= 16V
10
µA
mΩ
%
LX
r
320
92
DS(ON)
Eff
I(V
ΔV
ΔV
See curves
Pl mode, V
85
)
Feedback Input Bias Current
Line Regulation
= 1.35V
50
500
nA
%/V
%
FBB
FBB
= 4.7nF, I = 100mA, V = 3V to 5.5V
OUT IN
/ΔV
C
0.05
3
BOOST
IN
INT
INT
/ΔI
BOOST BOOST
Load Regulation - “P” Mode
C
pin strapped to V
,
DD
< 250mA
50mA < I
LOAD
ΔV
/ΔI
Load Regulation - “PI” Mode
C
= 4.7nF, 50mA < I < 250mA
0.1
4.7
%
V
BOOST BOOST
INT
O
V
V
V
CINT Pl Mode Select Threshold
4.8
CINT_T
LDO
ON
FBP Regulation Voltage
I
I
= 0.2mA, T = +25°C
A
1.176
1.172
0.82
1.2
1.2
1.224
1.228
0.92
V
V
FBP
DRVP
DRVP
= 0.2mA
falling
V
FBP Fault Trip Point
V
V
V
0.87
V
F_FBP
FBP
I
FBP Input Bias Current
FBP Effective Transconductance
= 1.35V
-250
250
nA
ms
FBP
FBP
GMP
= 25V, I
DRVP
= 0.2mA to 2mA
50
DRVP
FN6501.0
May 30, 2007
2
ISL78010
Electrical Specifications
V
= 5V, V
= 11V, I
LOAD
= 200mA, V
= 15V, V
= -5V, V
= 2.5V, limits over -40°C to
DD
BOOST
ON
OFF
LOGIC
+105°C temperature range, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
Load Regulation
ON
CONDITION
MIN
TYP
-0.5
4
MAX
UNIT
%
ΔV /ΔI(V
ON
)
V
I(V ) = 0mA to 20mA
ON
ON
I
I
DRVP Sink Current Max
DRVP Leakage Current
V
V
= 1.1V, V
= 1.5V, V
= 25V
= 35V
2
mA
µA
DRVP
FBP
FBP
DRVP
DRVP
0.1
5
L_DRVP
V
LDO
OFF
V
FBN Regulation Voltage
I
I
= 0.2mA, T = +25°C
A
0.173
0.171
0.38
0.203
0.203
0.43
0.233
0.235
0.48
V
V
FBN
DRVN
DRVN
= 0.2mA
falling
V
FNN Fault Trip Point
V
V
V
V
F_FBN
FBN
I
FBN Input Bias Current
FBN Effective Transconductance
= 0.2V
-250
250
nA
mS
%
FBN
FBN
GMN
= -6V, I
= 0.2mA to 2mA
50
DRVN
DRVN
ΔV
/
V
Load Regulation
I(V
) = 0mA to 20mA
-0.5
OFF
OFF
OFF
ΔI(V
)
OFF
I
I
DRVN Source Current Max
DRVN Leakage Current
V
V
= 0.3V, V
= -6V
2
4
mA
µA
DRVN
L_DRVN
FBN
FBN
DRVN
= 0V, V
= -20V
0.1
5
DRVN
V
LDO
LOGIC
V
FBL Regulation Voltage
I
I
= 1mA, T = +25°C
A
1.176
1.174
0.82
1.2
1.2
1.224
1.226
0.92
V
V
FBL
DRVL
DRVL
= 1mA
falling
V
FBL Fault Trip Point
V
V
V
0.87
V
F_FBL
FBL
I
FBL Input Bias Current
FBL Effective Transconductance
= 1.35V
-500
500
nA
mS
%
FBL
FBL
G
= 2.5V, I
= 1mA to 8mA
) = 100mA to 500mA
200
0.5
ML
DRVL
DRVL
ΔV
/
V
Load Regulation
I(V
LOGIC
LOGIC
LOGIC
ΔI(V
)
LOGIC
I
I
DRVL Sink Current Max
V
V
= 1.1V, V
= 2.5V
= 5.5V
8
16
mA
µA
DRVL
L_DRL
FBL
FBL
DRVL
DRVL
I
= 1.5V, V
0.1
5
L_DRVL
SEQUENCING
t
t
t
t
I
Turn On Delay
Soft-start Time
Delay Between A
Delay Between V
C
C
C
C
= 0.22µF
= 0.22µF
= 0.22µF
= 0.22µF
30
2
ms
ms
ms
ms
µA
mA
ON
DLY
SS
DLY
and V
10
17
50
1.4
DEL1
DEL2
DELB
VDD
OFF
DLY
and V
ON
OFF
DLY
DELB Pull-down Current
V
V
> 0.6V
< 0.6V
DELB
DELB
FAULT DETECTION
t
Fault Time Out
C
= 0.22µF
DLY
50
140
15
ms
°C
FAULT
OT
Over-temperature Threshold
PG Pull-down Current
I
VPG > 0.6V
VPG < 0.6V
µA
mA
PG
1.7
LOGIC ENABLE
V
V
Logic High Threshold
Logic Low Threshold
Logic Low Bias Current
Logic High Bias Current
2.3
12
V
V
HI
0.8
2
LO
I
I
0.2
18
µA
µA
LOW
HIGH
at V
= 5V
24
EN
FN6501.0
May 30, 2007
3
ISL78010
Pin Descriptions
PIN NAME
PIN NUMBER
DESCRIPTION
1, 2, 4, 6, 8, 10, 12,
16, 18, 23, 32
NC
Not connected
3
DELB
LX
Open drain output for gate drive of optional V
Drain of the internal N-Channel boost FET
delay FET
BOOST
5
9
FBP
Positive LDO voltage feedback input pin; regulates to 1.2V nominal
Positive LDO base drive; open drain of an internal N-Channel FET
Logic LDO base drive; open drain of an internal N-Channel FET
Logic LDO voltage feedback input pin; regulates to 1.2V nominal
Low noise signal ground
7
DRVP
DRVL
FBL
11
13
14, 27
SGND
DRVN
FBN
15
Negative LDO base drive; open drain of an internal P-Channel FET
Negative LDO voltage feedback input pin; regulates to 0.2V nominal
Power ground, connected to source of internal N-Channel boost FET
Bandgap reference output voltage; bypass with a 0.1µF to SGND
17
19, 20, 21, 22
PGND
VREF
CINT
24
25
V
integrator output; connect capacitor to SGND for PI-mode or connect to V
for P-mode
DD
BOOST
operation
26
28
29
30
FBB
EN
Boost regulator voltage feedback input pin; regulates to 1.2V nominal
Enable pin; High = Enable; Low or floating = Disable
Positive supply
VDD
PG
Push-pull gate drive of optional fault protection FET; when chip is disabled or when a fault has been
detected, this is high
31
CDLY
A capacitor connected from this pin to SGND sets the delay time for start-up sequence and sets the fault
timeout time
Typical Performance Curves
T = +25°C, unless otherwise specified.
A
100
100
A
= 9V
VDD
80
80
60
40
20
0
A
= 12V
VDD
A
= 15V
A
= 12V
VDD
VDD
A
= 15V
VDD
60
40
20
0
A
= 9V
VDD
0
100
200
(mA)
300
400
0
200
400
(mA)
600
800
I
I
OUT
OUT
FIGURE 2. V
EFFICIENCY AT V = 5V (PI-MODE)
IN
FIGURE 1. V
EFFICIENCY AT V = 3V (PI-MODE)
IN
BOOST
BOOST
FN6501.0
May 30, 2007
4
ISL78010
Typical Performance Curves
T
= +25°C, unless otherwise specified. (Continued)
A
100
100
A
= 9V
VDD
80
80
60
40
20
0
A
= 12V
VDD
A
= 12V
VDD
A
= 15V
VDD
A
= 15V
VDD
60
40
20
0
A
= 9V
VDD
0
100
200
I
300
(mA)
400
500
0
200
400
(mA)
600
800
I
OUT
OUT
FIGURE 4. V
EFFICIENCY AT V = 5V (P-MODE)
IN
FIGURE 3. V
EFFICIENCY AT V = 3V (P-MODE)
IN
BOOST
BOOST
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0
-0.2
-0.4
-0.6
-0.8
A
= 9V
VDD
A
= 9V
VDD
A
= 15V
VDD
A
= 12V
VDD
A
= 15V
VDD
A
= 12V
VDD
-0.7
0
-1.0
0
100
200
(mA)
300
400
200
400
600
800
I
OUT
I
(mA)
OUT
FIGURE 5. V
LOAD REGULATION AT V = 3V (PI-MODE)
IN
FIGURE 6. V
LOAD REGULATION AT V = 5V (PI-MODE)
IN
BOOST
BOOST
0
-1
-2
-3
-4
-5
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
A
= 9V
VDD
A
= 9V
VDD
A
= 15V
VDD
A
= 12V
600
VDD
A
= 15V
VDD
A
= 12V
VDD
0
200
400
(mA)
800
0
100
200
300
(mA)
400
500
I
OUT
I
OUT
FIGURE 8. V
LOAD REGULATION AT V = 5V (P-MODE)
IN
BOOST
FIGURE 7. V
LOAD REGULATION AT V = 3V (P-MODE)
IN
BOOST
FN6501.0
May 30, 2007
5
ISL78010
Typical Performance Curves
T
= +25°C, unless otherwise specified. (Continued)
A
0.05
0.04
0.03
0.02
0.01
0
0
-0.5
-1.0
1.5
-2.0
-2.5
-0.01
-0.02
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
V
IN
IN
FIGURE 9. V
LINE REGULATION (PI-MODE)
FIGURE 10. V
LINE REGULATION (P-MODE)
BOOST
BOOST
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1.4
0
-0.6
0
20
40
60
80
100
20
40
(mA)
60
80
I
(mA)
I
OUT
OUT
FIGURE 12. V
LOAD REGULATION
FIGURE 11. V
LOAD REGULATION
OFF
ON
0
-0.2
V
CDLY
-0.4
-0.6
-0.8
-1.0
-1.2
V
REF
V
BOOST
V
LOGIC
C
= 220nF
DLY
0
100 200 300 400 500 600 700
I
(mA)
TIME (10ms/DIV)
OUT
FIGURE 14. START-UP SEQUENCE
FIGURE 13. V
LOAD REGULATION
LOGIC
FN6501.0
May 30, 2007
6
ISL78010
Typical Performance Curves
T
= +25°C, unless otherwise specified. (Continued)
A
V
BOOST
V
BOOST_DELAY
V
LOGIC
V
LOGIC
V
OFF
V
OFF
C
= 220nF
V
DLY
ON
C
= 220nF
DLY
V
ON
TIME (10ms/DIV)
TIME (10ms/DIV)
FIGURE 15. START-UP SEQUENCE
FIGURE 16. START-UP SEQUENCE
V
V
I
= 5V
= 13V
V
V
I
= 5V
= 13V
IN
OUT
= 30mA
IN
OUT
= 200mA
OUT
OUT
TIME (400ns/DIV)
TIME (400ns/DIV)
FIGURE 17. LX WAVEFORM - DISCONTINUOUS MODE
FIGURE 18. LX WAVEFORM - CONTINUOUS MODE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.8
1.515W
1.5
1.2
0.9
0.6
0.3
0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6501.0
May 30, 2007
7
ISL78010
Boost Converter
Applications Information
The main boost converter is a current mode PWM converter
at a fixed frequency of 1MHz, which enables the use of low
profile inductors and multi-layer ceramic capacitors. This
results in a compact, low cost power system for LCD panel
design.
The ISL78010 provide a highly integrated multiple output
power solution for TFT-LCD automotive applications. The
system consists of one high efficiency boost converter and
three linear-regulator controllers (V , V
, and V )
ON OFF
LOGIC
with multiple protection functions. A block diagram is shown
in Figure 20. Table 1 lists the recommended components.
The ISL78010 is designed for continuous current mode, but
it can also operate in discontinuous current mode at light
load. In continuous current mode, current flows continuously
in the inductor during the entire switching cycle in steady
state operation. The voltage conversion ratio in continuous
current mode is given by Equation 1:
The ISL78010 integrates an N-Channel MOSFET boost
converter to minimize external component count and cost.
The A
, V , V
, and V
output voltages are
VDD ON OFF
LOGIC
independently set using external resistors. V , V
ON OFF
voltages require external charge pumps which are post
regulated using the integrated LDO controllers.
A
1
VDD
---------------
-------------
=
(EQ. 1)
V
1 – D
IN
TABLE 1. RECOMMENDED TYPICAL APPLICATION
DIAGRAM COMPONENTS
where D is the duty cycle of the switching MOSFET.
DESIGNATION
C , C , C
DESCRIPTION
Figure 21 shows the block diagram of the boost regulator. It
uses a summing amplifier architecture consisting of GM
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
10µF, 16V X7R ceramic capacitor (1206)
TDK C3216X7RIC106M
1
2
3
C
, C
20 31
4.7µF, 25V X5R ceramic capacitor (1206)
TDK C3216X5R1A475K
D
1A, 20V low leakage Schottky rectifier (CASE
457-04) ON SEMI MBRM120ET3
1
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by
Equation 2:
D
, D , D
200mA, 30V Schottky barrier diode (SOT-23)
Fairchild BAT54S
11 12 21
L
6.8µH, 1.3A Inductor
TDK SLF6025T-6R8M1R3-PF
1
Q
-2.4, -20V P-Channel 1.8V specified
PowerTrench MOSFET (SuperSOT-3)
Fairchild FDN304P
1
Q
Q
Q
200mA, 40V NPN amplifier (SOT-23)
Fairchild MMBT3904
2
3
4
R
+ R
2
R
1
1
(EQ. 2)
--------------------
A
=
× V
VDD
REF
200mA, 40V PNP amplifier (SOT-23)
Fairchild MMBT3906
The current through the MOSFET is limited to 2A peak. This
restricts the maximum output current based on Equation 3:
-2A, -30V single P-Channel logic level
PowerTrench MOSFET (SuperSOT-3)
Fairchild FDN360P
ΔI
V
IN
V
O
L
⎛
⎝
⎞
⎠
--------
---------
I
=
I
–
LMT
×
OMAX
(EQ. 3)
2
Q
1A, 30V PNP low saturation amplifier (SOT-23)
Fairchild FMMT549
5
Where ΔIL is peak to peak inductor ripple current, and is set
by Equation 4:
V
D
f
S
IN
(EQ. 4)
--------- ----
ΔI
=
×
L
L
where f is the switching frequency.
S
FN6501.0
May 30, 2007
8
ISL78010
EN
REFERENCE
GENERATOR
VREF
SGND
OSCILLATOR
SLOPE COMP OSC
COMPENSATION
LX
PWM
LOGIC
Σ
BUFFER
CONTROLLER
VOLTAGE
AMPLIFIER
FBB
GM
AMPLIFIER
CINT
CURRENT
AMPLIFIER
PGND
DRVP
UVLO
COMPARATOR
EN
CURRENT REF
VDD
PG
CURRENT
LIMIT COMPARATOR
SHUTDOWN
AND
START-UP
CONTROL
+
-
VREF
BUFFER
THERMAL
SHUTDOWN
FBP
UVLO
COMPARATOR
DELB
CDLY
DRVN
SS
+
SS
+
0.2V
VREF
DRVL
FBL
-
-
BUFFER
BUFFER
FBN
0.4V
UVLO
COMPARATOR
UVLO
COMPARATOR
FIGURE 20. BLOCK DIAGRAM
FN6501.0
May 30, 2007
9
ISL78010
SHUTDOWN
AND STARTUP
CONTROL
CLOCK
SLOPE
COMPENSATION
IFB
CURRENT
AMPLIFIER
PWM
IREF
LX
LOGIC
BUFFER
IFB
FBB
GM
AMPLIFIER
IREF
VOLTAGE
AMPLIFIER
REFERENCE
GENERATOR
PGND
CINT
FIGURE 21. BLOCK DIAGRAM OF THE BOOST REGULATOR
FN6501.0
May 30, 2007
10
ISL78010
NOTE: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
in Equation 7 assumes the effective value of the capacitor at a
Table 2 gives typical values (margins are considered 10%,
3%, 20%, 10%, and 15%) on V , V , L, f , and I
:
IN OMAX
O
S
C
OUT
TABLE 2. TYPICAL V , V , L, f , AND I
VALUES
particular voltage and not the manufacturer’s stated value, measured
IN
O
S
OMAX
at zero volts.
f
I
S
OMAX
(A)
Compensation
V
(V)
V
(V)
O
L (µH)
6.8
(MHz)
IN
The ISL78010 can operate in either P-mode or PI-mode.
P-mode may be preferred in applications where excellent
transient load performance is required but regulation is not
3.3
3.3
3.3
5
9
1
1
1
1
1
1
0.490686
0.307353
0.197353
0.743464
0.465686
0.29902
12
15
9
6.8
6.8
critical. Connecting the C
pin directly to V will enable
INT
IN
P-mode; For better load regulation, use PI-mode with a
6.8
4.7nF capacitor in series with a 10k resistor between C
INT
5
12
15
6.8
and ground. This value may be reduced to improve transient
performance, however, very low values will reduce loop
stability. Figures 5 through 10 show a comparison of P-mode
vs PI-mode performance.
5
6.8
Input Capacitor
An input capacitor is used to supply the peak charging
current to the converter. It is recommended that C be
larger than 10µF. The reflected ripple voltage will be smaller
with larger C . The voltage rating of input capacitor should
Boost Feedback Resistors
IN
As the boost output voltage, A
VDD
, is reduced below 12V the
effective voltage feedback in the IC increases the ratio of
voltage to current feedback at the summing comparator
IN
be larger than the maximum input voltage.
because R decreases relative to R . To maintain stable
2
1
operation over the complete current range of the IC, the
voltage feedback to the FBB pin should be reduced
Boost Inductor
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH are to match the internal slope
compensation. The inductor must be able to handle the
following average and peak current:
proportionally, as A
is reduced, by means of a series
resistor-capacitor network (R and C ) in parallel with R ,
VDD
7
7
1
with a pole frequency (f ) set to approximately 10kHz for C
p
2
(effective) = 10µF and 4kHz for C (effective) = 30µF.
2
–1
1
1
I
⎛⎛
⎝⎝
⎞
--------------------- ------
–
⎞
(EQ. 5)
(EQ. 8)
O
R
C
=
=
-------------
7
7
I
I
=
⎠
⎠
0.1 × R
R
LAVG
2
1
1 – D
ΔI
L
1
(EQ. 6)
--------
+
= I
------------------------------------------------
2 × 3.142 × f × R
LPK
LAVG
2
(EQ. 9)
p
7
Rectifier Diode
PI-Mode C
(C ) and R )
(R
INT 23 INT 10
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The rectifier
diode must meet the output current and peak inductor
current requirements.
The IC is designed to operate with a minimum C capacitor
23
of 4.7nF and a minimum C (effective) = 10µF.
2
Note that, for high voltage A
, the voltage coefficient of
VDD
ceramic capacitors (C ) reduces their effective capacitance
2
greatly; a 16V, 10µF ceramic can drop to around 3µF at 15V.
Output Capacitor
To improve the transient load response of A
VDD
in PI-mode,
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging and discharging of the output
capacitor.
a resistor may be added in series with the C capacitor. The
23
larger the resistor the lower the overshoot but at the expense
of stability of the converter loop - especially at high currents.
With L = 10µH, A
VDD
= 15V, C = 4.7nF, C (effective)
23
2
should have a capacitance of greater than 10µF. R
(R )
INT
7
can have values up to 5kΩ for C (effective) up to 20µF and
2
V
– V
I
O
1
f
S
O
IN
(EQ. 7)
up to 10k for C (effective) up to 30µF.
----------------------- --------------- ----
V
= I
× ESR +
LPK
×
×
2
RIPPLE
V
C
O
OUT
Larger values of R
INT
(R ) may be possible if maximum
7
A
load currents less than the current limit are used. To
VDD
ensure A
For low ESR ceramic capacitors, the output ripple is
stability, the IC should be operated at the
VDD
maximum desired current and then the transient load
response of A should be used to determine the
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
VDD
maximum value of R
.
INT
FN6501.0
May 30, 2007
11
ISL78010
Operation of the DELB Output Function
V
V
BOOST
IN
An open drain DELB output is provided to allow the boost
output voltage, developed at C (See “Typical Application
2
Diagram” on page 17), to be delayed via an external switch
(Q ) to a time after the V supply and negative V
charge pump supply have achieved regulation during the
start-up sequence shown in Figures 14 and 16. This then
LX
4
BOOST
OFF
FB
ISL78010
allows the A
and V
supplies to start-up from 0V
(D ) if Q
VDD
ON
instead of the normal offset voltage of V -V
IN DIODE
1
4
were not present.
When DELB is activated by the start-up sequencer, it sinks
50µA allowing a controlled turn-on of Q and charge-up of
FIGURE 22. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
4
C . C can be used to control the turn-on time of Q to
9
16
4
reduce inrush current into C . The potential divider formed
9
Linear-Regulator Controllers (V , V
, and
ON LOGIC
by R and R can be used to limit the V
voltage of Q if
9
8
GS
4
V
)
OFF
The ISL78010 includes three independent linear-regulator
controllers, in which two are positive output voltage (V
required by the voltage rating of this device. When the
voltage at DELB falls to less than 0.6V, the sink current is
increased to ~1.2mA to firmly pull DELB to 0V.
ON
, and
and V
V
), and one is negative. The V , V
LOGIC
ON OFF
linear-regulator controller functional diagrams,
The voltage at DELB is monitored by the fault protection
LOGIC
applications circuits are shown in Figures 23, 24, and 25
respectively.
circuit so that if the initial 50µA sink current fails to pull DELB
below ~0.6V after the start-up sequencing has completed,
then a fault condition will be detected and a fault time-out
Calculation of the Linear Regulator Base-Emitter
ramp will be initiated on the C
capacitor (C ).
7
DEL
Resistors (R , R
and R
)
BL BP
BN
Operation of the PG Output Function
For the pass transistor of the linear regulator, low frequency
gain (h ) and unity gain frequency (f ) are usually specified
The PG output consists of an internal pull-up PMOS device to
FE
T
in the datasheet. The pass transistor adds a pole to the loop
transfer function at f = f /h . Therefore, in order to
V , to turn-off the external Q protection switch and a current
limited pull-down NMOS device which sinks ~15µA allowing a
IN
1
p
T FE
maintain phase margin at low frequency, the best choice for
a pass device is often a high frequency low gain switching
transistor. Further improvement can be obtained by adding a
controlled turn-on of Q gate capacitance. C is used to
1
O
control how fast Q turns-on - limiting inrush current into C .
1
1
When the voltage at the PG pin falls to less than 0.6V, the PG
sink current is increased to ~1.2mA to firmly pull the pin to 0V.
base-emitter resistor R (R , R , R
in the Functional
BE BP BL BN
Block Diagrams on page 13), which increase the pole
The voltage at PG is monitored by the fault protection circuit
so that if the initial 15µA sink current fails to pull PG below
~0.6V after the start-up sequencing has completed, then a
fault condition will be detected and a fault time-out ramp will
frequency to: f = f *(1+ h *re/R )/h , where
p
T
FE BE FE
re = KT/qIc. So choose the lowest value R in the design
BE
as long as there is still enough base current (I ) to support
B
the maximum output current (I ).
C
be initiated on the C
capacitor (C ).
7
DEL
We will take as an example the V
linear regulator. If a
LOGIC
Cascaded MOSFET Application
Fairchild FMMT549 PNP transistor is used as the external
pass transistor (Q in the application diagram) then for a
A 20V N-Channel MOSFET is integrated in the boost
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed
as shown in Figure 22. The voltage rating of the external
5
maximum V
operating requirement of 500mA, the data
LOGIC
sheet indicates h (min) = 100.
FE
The base-emitter saturation voltage is: Vbe_max = 1.25V
(note this is normally a Vbe ~ 0.7V, however, for the Q
MOSFET should be greater than V
.
BOOST
5
transistor an internal Darlington arrangement is used to
increase it's current gain, giving a 'base-emitter' voltage of
2 x V ).
BE
(Note that using a high current Darlington PNP transistor for
Q requires that V > V
+ 2V. Should a lower input
voltage be required, then an ordinary high gain PNP
5
IN LOGIC
transistor should be selected for Q so as to allow a lower
5
collector-emitter saturation voltage).
FN6501.0
May 30, 2007
12
ISL78010
For the ISL78010, the minimum drive current is:
V
OR V
PROT
IN
(3V TO 6V)
I
(min) = 8mA
DRVL
(EQ. 10)
LDO_LOG
0.9V
The minimum base-emitter resistor, R , can now be
BL
calculated as:
R
BL
500Ω
PG_LDOL
+
-
Q5
(1.3V TO 3.6V)
R
(min) = V (max) ⁄ (I
(min) – I ⁄ h (min)) =
DRVL C FE
V
BL
BE
LOGIC
DRVL
(EQ. 11)
1.25V ⁄ (8mA – 500mA ⁄ 100) = 417Ω
C
LOG
10µF
R
R
This is the minimum value that can be used - so, we now
choose a convenient value greater than this minimum value;
say 500Ω. Larger values may be used to reduce quiescent
current, however, regulation may be adversely affected, by
L1
L2
FBL
-
+
GML
20kΩ
supply noise if R is made too high in value.
BL
V
1: N1
BOOST
LX
0.1µF
LDO_ON
0.9V
FIGURE 25. V
FUNCTIONAL BLOCK DIAGRAM
LOGIC
PG_LDOP
CP (TO 36V)
0.1µF
+
-
36V
ESD
CLAMP
The V
ON
power supply is used to power the positive supply
R
of the row driver in the LCD panel. The DC/DC consists of an
external diode-capacitor charge pump powered from the
inductor (LX) of the boost converter, followed by a low
dropout linear regulator (LDO_ON). The LDO_ON regulator
uses an external PNP transistor as the pass element. The
on-board LDO controller is a wide band (>10MHz)
transconductance amplifier capable of 4mA drive current,
which is sufficient for up to 40mA or more output current
under the low dropout condition (forced beta of 10). Typical
BP
7kΩ
Q3
DRVP
FBP
V
(TO 35V)
ON
R
R
P1
P2
C
ON
+
-
GMP
20kΩ
1: Np
V
voltage supported by the ISL78010 ranges from +15V
ON
to +36V. A fault comparator is also included for monitoring
the output voltage. The undervoltage threshold is set at 25%
below the 1.2V reference.
FIGURE 23. V
FUNCTIONAL BLOCK DIAGRAM
ON
The V
OFF
power supply is used to power the negative
supply of the row driver in the LCD panel. The DC/DC
consists of an external diode-capacitor charge pump
powered from the inductor (LX) of the boost converter,
followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an external NPN transistor as the
pass element. The on-board LDO controller is a wide band
(>10MHz) transconductance amplifier capable of 4mA drive
current, which is sufficient for up to 40mA or more output
current under the low dropout condition (forced beta of 10).
LX
0.1µF
CP (TO -26V)
LDO_OFF
V
REF
0.1µF
PG_LDON
0.4V
-
+
R
N2
20kΩ
Typical V
voltage supported by the ISL78010 ranges
FBN
OFF
from -5V to -20V. A fault comparator is also included for
monitoring the output voltage. The undervoltage threshold is
set at 200mV above the 0.2V reference level.
1: Nn
R
N1
V
(TO -20V)
OFF
-
+
The V
power supply is used to power the logic circuitry
LOGIC
DRVN
C
Q2
OFF
GMN
within the LCD panel. The DC/DC may be powered directly
from the low voltage input, 3.3V or 5.0V, or it may be
powered through the fault protection switch. The
R
BN
3kΩ
36V
ESD
CLAMP
LDO_LOGIC regulator uses an external PNP transistor as
the pass element. The on-board LDO controller is a wide
band (>10MHz) transconductance amplifier capable of
16mA drive current, which is sufficient for up to 160mA or
FIGURE 24. V
FUNCTIONAL BLOCK DIAGRAM
OFF
FN6501.0
May 30, 2007
13
ISL78010
more output current under the low dropout condition (forced
beta of 10). Typical V voltage supported by the
CHARGE PUMP
OUTPUT
VDD
V
LOGIC
ISL78010 ranges from +1.3V to V
IN
OR A
- 0.2V. A fault
DD
comparator is also included for monitoring the output
7kΩ
voltage. The undervoltage threshold is set at 25% below the
1.2V reference.
Q3
DRVP
NPN
CASCODE
TRANSISTOR
V
ON
Set-Up Output Voltage
Refer to the “Typical Application Diagram” on page 17, the
ISL78010
output voltages of V , V
, and V
are determined
ON OFF
LOGIC
by Equations 12, 13 and 14:
FBP
R
⎛
⎞
⎟
⎠
12
(EQ. 12)
---------
V
= V
× 1 +
⎜
ON
REF
R
⎝
11
R
22
(EQ. 13)
(EQ. 14)
---------
V
= V
+
× (V
– V
REF
)
OFF
REFN
REFN
R
21
FIGURE 26. CASCODE NPN TRANSISTOR CONFIGURATION
FOR HIGH CHARGE PUMP OUTPUT VOLTAGE
(>36V)
R
⎛
⎞
42
---------
V
= V
× 1 +
⎜
⎟
⎠
LOGIC
REF
R
⎝
41
where V
= 1.2V, V = 0.2V.
REFN
LX
REF
0.1µF
Resistor networks in the order of 250kΩ, 120kΩ and 10kΩ
are recommended for V , V and V , respectively.
A
ON OFF LOGIC
VDD
0.1µF
Charge Pump
To generate an output voltage higher than V
7kΩ
, single or
BOOST
multiple stages of charge pumps are needed. The number of
stages is determined by the input and output voltage. For
positive charge pump stages:
0.1µF
0.1µF
DRVP
Q3
V
ON
0.47µF
(>36V)
0.1µF
ISL78010
V
+ V
– V
CE INPUT
OUT
(EQ. 15)
-------------------------------------------------------------
≥
N
POSITIVE
V
– 2 × V
F
INPUT
0.22µF
FBP
where V
is the dropout voltage of the pass component of
the linear regulator. It ranges from 0.3V to 1V depending on
CE
the transistor. V is the forward-voltage of the charge pump
F
rectifier diode.
FIGURE 27. THE LINEAR REGULATOR CONTROLS ONE
STAGE OF CHARGE PUMP
The number of negative charge pump stages is given by:
V
+ V
CE
– 2 × V
F
OUTPUT
(EQ. 16)
------------------------------------------------
≥
N
Discontinuous/Continuous Boost Operation and
its Effect on the Charge Pumps
NEGATIVE
V
INPUT
The ISL78010 V
and V
architecture uses LX
OFF
ON
switching edges to drive diode charge pumps from which
LDO regulators generate the V and V supplies. It can
To achieve high efficiency and low material cost, the lowest
number of charge pump stages which can meet the above
requirements, is always preferred.
ON
OFF
be appreciated that should a regular supply of LX switching
High Charge Pump Output Voltage (>36V)
Applications
edges be interrupted, for example, during discontinuous
operation at light A
boost load currents, then this may
affect the performance of V and V regulation -
VDD
In the applications where the charge pump output voltage is
over 36V, an external NPN transistor needs to be inserted
ON
OFF
depending on their exact loading conditions at the time.
between DRVP pin and base of pass transistor Q as shown
3
To optimize V /V
regulation, the boundary of
ON OFF
discontinuous/continuous operation of the boost converter
can be adjusted, by suitable choice of inductor given V
in Figure 26; or the linear regulator can control only one
stage charge pump and regulate the final charge pump
output as shown in Figure 27.
,
IN
V
, switching frequency and the A
current loading, to
OUT VDD
be in continuous operation.
FN6501.0
May 30, 2007
14
ISL78010
Equation 17 gives the boundary between discontinuous and
continuous boost operation. For continuous operation (LX
switching every clock cycle) we require that:
output until the boost is enabled internally. The delayed
output appears at A
.
VDD
V
soft-starts at the beginning of the third ramp. The
BOOST
soft-start ramp depends on the value of the C
I
(load) > D × (1 – D) × V
IN
capacitor.
AVDD
DLY
of 220nF, the soft-start time is ~2ms.
(EQ. 17)
--------------------------------------------------------------------------------------
2 × L × f
For C
OSC
DLY
V
and V
turn on when input voltage (V )
DD
REF
LOGIC
where the duty cycle, D = (A
- V )/A
IN VDD
VDD
exceeds 2.5V. When a fault is detected, the outputs and the
input protection will turn off but V will stay on.
For example, with V = 5V, f
IN
we find continuous operation of the boost converter can be
guaranteed for:
= 1.0MHz and A = 12V
VDD
OSC
REF
turns on at the start of the fourth peak. At the fifth
V
OFF
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q to generate a delayed V output.
(EQ. 18)
(EQ. 19)
(EQ. 20)
L = 10μH and I
> 61mA
> 89mA
> 184mA
AVDD
4
BOOST
V
is enabled at the beginning of the sixth ramp. A
, DELB and V
OFF ON
,
ON
PG, V
VDD
are checked at end of this ramp.
L = 6.8μH and I
L = 3.3μH and I
AVDD
AVDD
Fault Protection
Once the start-up sequence is complete, the voltage on the
capacitor remains at 1.15V until either a fault is
Charge Pump Output Capacitors
C
DLY
detected or the EN pin is disabled. If a fault is detected, the
voltage on C rises to 2.4V at which point the chip is
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by Equation 21:
DLY
disabled until the power is recycled or enable is toggled.
Component Selection for Start-Up Sequencing and
Fault Protection
I
OUT
(EQ. 21)
------------------------------------------------------
C
≥
OUT
2 × V
× f
OSC
RIPPLE
The C
capacitor is typically set at 220nF and is required
to stabilize the V output. The range of C is from
REF
REF
22nF to 1µF and should not be more than five times the
capacitor on C to ensure correct start-up operation.
REF
where f
is the switching frequency.
OSC
DEL
capacitor is typically 220nF and has a usable
Start-Up Sequence
Figure 28 shows a detailed start-up sequence waveform. For
a successful power up, there should be six peaks at V
The C
DEL
.
range from 47nF minimum to several microfarads - only
CDLY
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
limited by the leakage in the capacitor reaching µA levels.
C
should be at least 1/5 of the value of C
(See
the fault time-out will
DEL
above). Note that with 220nF on C
REF
When the input voltage is higher than 2.5V, an internal
DEL
current source starts to charge C
using a fast ramp followed by a slow ramp. During the initial
slow ramp, the device checks whether there is a fault
to an upper threshold
be typically 50ms and the use of a larger/smaller value will
vary this time proportionally (e.g. 1µF will give a fault time-
out period of typically 230ms).
CDLY
condition. If no fault is found, C
is discharged after the
CDLY
Fault Sequencing
first peak and V
REF
turns on.
The ISL78010 has advanced fault detection systems which
protects the IC from both adjacent pin shorts during
operation and shorts on the output supplies.
During the second ramp, the device checks the status of
and over-temperature. At the peak of the second
V
REF
ramp, PG output goes low and enables the input protection
PMOS Q . Q is a controlled FET used to prevent in-rush
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the “Layout
Recommendation” on page 17 and “Component Selection
for Start-Up Sequencing and Fault Protection” on page 15 to
avoid problems during initial evaluation and prototype PCB
generation.
1
1
current into V
before V
is enabled internally.
BOOST
BOOST
Its rate of turn on is controlled by C . When a fault is
o
detected, M1 will turn off and disconnect the inductor from
V
.
IN
With the input protection FET on, NODE1 (See “Typical
Application Diagram” on page 17) will rise to ~V . Initially
IN
the boost is not enabled so V
BOOST
rises to V -V
IN DIODE
through the output diode. Hence, there is a step at V
BOOST
during this part of the start-up sequence. If this step is not
desirable, an external P-MOSFET can be used to delay the
FN6501.0
May 30, 2007
15
ISL78010
V
CDLY
V
IN
EN
V
REF
V
BOOST
t
ON
t
OS
V
LOGIC
V
OFF
t
DEL1
DELAYED
V
BOOST
t
DEL2
V
t
ON
DEL3
START-UP SEQUENCE
TIMED BY C
DLY
FIGURE 28. START-UP SEQUENCE
FN6501.0
May 30, 2007
16
ISL78010
4. All feedback networks should sense the output voltage
Over-Temperature Protection
directly from the point of load, and be as far away from LX
node as possible.
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of +140°C, the device will shut
down.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point near the main
decoupling capacitors.
Layout Recommendation
6. A signal ground plane, separate from the power ground
plane, should be used for ground return connections for
feedback resistor networks (R , R , R ) and the V
REF
Device performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
1
11 41
capacitor, C , the C
capacitor C and the
22 DELAY
7
integrator capacitor C
.
23
7. Minimize feedback input track lengths to avoid switching
noise pick-up.
There are some general guidelines for layout:
8. Connect all "NC" pins to the ground plane to improve the
thermal performance and switching noise immunity
between pins.
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
A demo board is available to illustrate the proper layout
implementation.
2. Place V
and V
bypass capacitors close to the pins.
DD
REF
3. Minimize the length of traces carrying fast signals and
high current.
Typical Application Diagram
LX
A
VDD
(12V)
L
D
1
1
Q
NODE 1
Q
4
1
V
IN
C
9
C
C
6.8µH
0
1
C -C
2
10µF
X2
R
C
3
9
16
22nF
46.5kΩ
R
2
0.1µF
1nF
10µF
x2
1MΩ
PG
LX
FBB
R
OPEN
OPEN
7
R
1
5kΩ
R
8
C
7
C
7
10kΩ
CDELAY
VDD
C
10
0.22µF
4.7µF
DELB
CINT
R
10Ω
6
6
7
LX
R
10
4.7nF
1nF
C
23
C
R
4.7µF
10kΩ
10kΩ
C
P
C
C
11
13
0.1µF
0.1µF
EN
R
13
V
0.1µF
REF
C
41
C
C
14
0.1µF
12
0.1µF
7kΩ
NODE 1
VREF
C
D
D
11
22
0.1µF
12
R
DRVP
FBP
Q
43
3
V
(15V)
ON
R
230kΩ
12
500Ω
*
R
C
15
11
20kΩ
C
24
Q
DRVL
FBL
5
0.47µF
R
LX
42
V
LOGIC
(2.5V)
*
0.1µF
R
41
5kΩ
C
5.4kΩ
31
4.7µF
R
23
C
*
25
0.1µF
3kΩ
*
D
21
DRVN
FBN
Q
V
2
OFF
(-5V)
R
104k
22
R
C
21
20k
20
4.7µF
SGND
PGND
*
V
REF
NOTE: SGND should be connected to PGND at one point only.
FN6501.0
May 30, 2007
17
ISL78010
Thin Plastic Quad Flatpack Packages (TQFP)
Q32.5x5 (JEDEC MS-026AAA ISSUE B)
32 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
MILLIMETERS
D
D1
SYMBOL
MIN
-
MAX
1.20
0.15
1.05
0.27
0.23
7.10
5.10
7.10
5.10
0.75
NOTES
-D-
A
A1
A2
b
-
0.05
0.95
0.17
0.17
6.90
4.90
6.90
4.90
0.45
-
-B-
-
-A-
6
b1
D
-
E
E1
3
D1
E
4, 5
3
e
E1
L
4, 5
-
PIN 1
N
32
7
e
0.50 BSC
-
SEATING
PLANE
-H-
A
Rev. 0 2/07
NOTES:
0.08
0.003
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
-C-
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane
0.08
0.003
.
-C-
D
S
A-B
C
S
M
4. Dimensions D1 and E1 to be determined at datum plane -H- .
b
o
o
5. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm (0.010 inch) per side.
11 -13
0.020
b1
MIN
0.008
o
6. Dimension b does not include dambar protrusion. Allowable dam-
bar protrusion shall not cause the lead width to exceed the max-
imum b dimension by more than 0.08mm (0.003 inch).
0
MIN
0.09/0.16
0.004/0.006
A2
A1
GAGE
PLANE
7. “N” is the number of terminal positions.
BASE METAL
WITH PLATING
L
0.09/0.20
o
o
11 -13
0.25
0.010
0.004/0.008
o
o
0 -7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6501.0
May 30, 2007
18
相关型号：
ISL78010ANZ
Automotive Grade TFT-LCD Power Supply; TQFP32; Temp Range: -40° to 105°C
RENESAS
ISL78010ANZ-T
Automotive Grade TFT-LCD Power Supply; TQFP32; Temp Range: -40° to 105°C
RENESAS
ISL78010ANZ-TK
SWITCHING REGULATOR, 1.1kHz SWITCHING FREQ-MAX, PQFP32, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MS-026AAA, TQFP-32
RENESAS
©2020 ICPDF网 联系我们和版权申明