ISL80111IRAJZ [INTERSIL]
Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS LDOs;
| 型号： | ISL80111IRAJZ |
| 厂家： | 
Intersil |
| 描述： | Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS LDOs 光电二极管 输出元件 调节器 |
| 文件： | 总17页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS
LDOs
ISL80111, ISL80112, ISL80113
Features
The ISL80111, ISL80112, and ISL80113 are ultra low dropout
LDOs providing the optimum balance between performance, size
and power consumption in size constrained designs for data
communication, computing, storage and medical applications.
These LDOs are specified for 1A, 2A and 3A of output current and
• Ultra low dropout: 75mV at 3A, (typ)
• Excellent V PSRR: 70dB at 1kHz (typ)
IN
• ±1.6% guaranteed V
OUT
accuracy for -40ºC < T < +125ºC
J
• Very fast load transient response
are optimized for low voltage conversions.Operating with a V of
IN
• Extensive protection and reporting features
1V to 3.6V and with a legacy 3.3V to 5V on the BIAS, the V
OUT
is
• V range: 1V to 3.6V, V
IN OUT
range: 0.8V to 3.3V
adjustable from 0.8V to 3.3V. With a V PSRR greater than 40dB
IN
at 100kHz makes these LDOs an ideal choice in noise sensitive
• Small 10 Ld 3x3 DFN package
applications. The guaranteed ±1.6% V
accuracy overall
OUT
conditions lends these parts to suppling an accurate voltage to
the latest low voltage digital ICs.
Applications
• Noise-sensitive instrumentation and medical systems
• Data acquisition and data communication systems
• Storage, telecommunications and server equipment
• Low voltage DSP, FPGA and ASIC core power supplies
• Post-regulation of switched mode power supplies
An enable input allows the part to be placed into a low quiescent
current shutdown mode. A submicron CMOS process is utilized for
this product family to deliver best-in-class analog performance
and overall value for applications in need of input voltage
conversions typically below 2.5V. It also has the superior load
transient regulation unique to a NMOS power stage. These LDOs
consume significantly lower quiescent current as a function of
load compared to bipolar LDOs.
100
90
80
70
60
50
40
30
20
10
0
ISL80111, ISL80112, ISL80113
3A
2A
1A
1.0V
VOUT
1.2V ±5%
1
2
9
VOUT
VOUT
VIN
VIN
VIN
C
10µF
C
IN
10
OUT
10µF
3.3V ±10%
VBIAS
4
7
VBIAS
6
3
C
PGOOD
PG
BIAS
1µF
R
1.0kΩ
3
ADJ
ENABLE
EN
R
4
1.0kΩ
GND
5
OPEN DRAIN COMPATIBLE
-40
25
85
125
TEMPERATURE (°C)
FIGURE 1. TYPICAL APPLICATION SCHEMATIC
FIGURE 2. DROPOUT VOLTAGE OVER-TEMP AND I
OUT
100
80
60
40
20
0
1.015
1.010
1.005
1.000
0.995
0.990
0.985
I
= 1A
OUT
I
= 0A
OUT
I
= 2A
OUT
I
= 3A
OUT
BIAS = 5V
V
V
C
= 3.3V
IN
OUT
OUT
= 2.5V
= 10µF
-40
0
25
85
125
100
1k
10k
FREQUENCY (Hz)
100k
1M
TEMPERATURE (°C)
FIGURE 3. V PSRR vs LOAD CURRENT (ISL80113)
IN
FIGURE 4. ΔV vs TEMPERATURE
ADJ
November 1, 2013
FN7841.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL80111, ISL80112, ISL80113
Block Diagram
VIN
VBIAS
CURRENT
LIMIT
BIAS
UVLO
VIN
UVLO
POWER NMOS
IL
M3
M1
VIN
R7
DRIVER
EN
IL/10,000
VOUT
THERMAL
SHUTDOWN
EN
EN
ADJ
PG
-
EN
+
ENABLE
M7
-
+
-
M
500mV
2
+
+
-
*R3
425mV
GND
Pin Configuration
Pin Descriptions
ISL80111, ISL80112, ISL80113
(10 LD 3X3 DFN)
PIN
NUMBER
PIN NAME
VOUT
DESCRIPTION
Output voltage pin. Range 0.8V to 3.3V
TOP VIEW
1, 2
3
VOUT
VOUT
ADJ
1
2
3
4
5
10 VIN
ADJ
ADJ pin for externally setting V . Range
OUT
0.5V to V
VIN
9
8
7
6
OUT
NC
4
VBIAS
Bias voltage pin for internal control circuits.
Range 2.9V to 5.5V
EPAD
(GND)
VBIAS
GND
ENABLE
PG
5
6
GND
PG
Ground pin
V
in regulation signal. Logic low defines
OUT
when V
BIAS
is not in regulation. Range 0V to
OUT
7
ENABLE
V
independent chip enable. TTL and CMOS
IN
compatible. Range 0V to V
BIAS
8
NC
VIN
No Connect
9, 10
Input supply pins. Range 1.0V to 3.6V
EPAD
EPAD at ground potential. It is recommended
to solder the EPAD to the ground plane.
FN7841.2
November 1, 2013
2
ISL80111, ISL80112, ISL80113
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
V
(V)
TEMP RANGE
PACKAGE
(Pb-Free)
PKG
DWG. #
OUT
(°C)
ISL80111IRAJZ
1ADJ
2ADJ
3ADJ
ADJ
ADJ
ADJ
-40 to +85
-40 to +85
-40 to +85
10 Ld 3x3 DFN
L10.3x3
ISL80112IRAJZ
ISL80113IRAJZ
ISL80111EVAL1Z
ISL80112EVAL1Z
ISL80113EVAL1Z
NOTES:
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
ISL80111 Evaluation Board
ISL80112 Evaluation Board
ISL80113 Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL80111, ISL80112, and ISL80113. For more information on MSL
please see Tech Brief TB363.
FN7841.2
November 1, 2013
3
ISL80111, ISL80112, ISL80113
Absolute Maximum Ratings (Note4)
Thermal Information
V
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 to +6V
Relative to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +4V
Thermal Resistance (Typical)
10 Ld 3x3 DFN Package (Notes 7, 8). . . . .
θ
(°C/W)
48
θ
JC
(°C/W)
4
IN
OUT
JA
PG, ENABLE, SENSE/ADJ, Relative to GND (Note 5) . . . . . . . . . -0.3 to +6V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
PG Rated Current (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
V
BIAS
ESD Rating
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . 4000V
Machine Model (Tested per JESD22-115-A) . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V
Latch Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions (Notes 4, 6)
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
V
V
V
Relative to GND (ISL80113) (Note 9) . . . . . . . . . . . . V
Relative to GND (ISL80112) (Note 9) . . . . . . . . . . . . V
Relative to GND (ISL80111) (Note 9) . . . . . . . . . . . . V
+ 0.4V to 5V
+ 0.3V to 5V
+ 0.2V to 5V
IN
IN
IN
OUT
OUT
OUT
Nominal V
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 3.3V
OUT
PG, ENABLE, SENSE/ADJ, SS Relative to GND . . . . . . . . . . . . . . .0V to 5.5V
V
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 5.5V
BIAS
BIAS
Relative to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8V minimum
OUT
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Absolute maximum ratings define limits of safe operation. Extended operation at these conditions may compromise reliability. Exceeding these limits
will result in damage. Recommended operating conditions define limits where specifications are guaranteed.
5. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
6. Electromigration specification defined as lifetime average junction temperature of +110°C where maximum rated DC current = lifetime average
current.
7. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
8. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
9. Minimum operating voltage applied to V is 1V if V - V < 1V
IN IN DO
Electrical Specifications Unless otherwise specified, V = V
+ 0.4V, V
= 2.9V, V
OUT
= 1.2V, C = 1µF, C = 10µF,
BIAS IN
IN
OUT
BIAS
C
= 2.2µF, T = +25°C, I = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. Please
OUT
refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply over junction temperature (T ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure T = T where datasheet limits
J
L
J
J
A
are defined.
MIN
MAX
PARAMETER
DC CHARACTERISTICS
SYMBOL
TEST CONDITIONS
(Note 10) TYP (Note 10) UNITS
V
UVLO
UVLO_BIAS_r
UVLO_BIAS_f
V
V
Rising
Falling
2.3
2.1
0.2
502
2.9
2.8
V
V
BIAS
BIAS
BIAS
1.55
494
V
UVLO Hysteresis
UVLO
V
BIAS
B_HYS
DC ADJ Pin Voltage Accuracy
V
1.0V ≤ V ≤ 3.6V, I
IN LOAD
= 0A, 2.9V ≤ V
≤ 5.5V,
BIAS
510
mV
ADJ
V
= V
OUT
ADJ
DC Input Line Regulation
DC Bias Line Regulation
DC Output Load Regulation
Feedback Input Current
ΔV
V
+ 0.4V ≤ V ≤ 3.6V
IN
0.01
0.3
-0.2
10
0.9
1.4
2
mV
mV
mV
nA
OUT
OUT
OUT
OUT
ΔV
ΔV
2.9V<V
<5.5V with respect to ADJ pin
BIAS
0A ≤ I
≤ 3A
-2
LOAD
V
= 0.5V
80
10
ADJ
V
V
Quiescent Current
Quiescent Current
I
(V
VOUT = 2.5V
VOUT = 3.3,
8
mA
mA
IN
IN
Q
IN)
IN)
I
(V
10.6
Q
FN7841.2
November 1, 2013
4
ISL80111, ISL80112, ISL80113
Electrical Specifications Unless otherwise specified, V = V
+ 0.4V, V
= 2.9V, V
OUT
= 1.2V, C = 1µF, C = 10µF,
BIAS IN
IN
OUT
BIAS
C
= 2.2µF, T = +25°C, I = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. Please
OUT
refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply over junction temperature (T ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure T = T where datasheet limits
J
L
J
J
A
are defined. (Continued)
MIN
MAX
PARAMETER
SYMBOL
(V
TEST CONDITIONS
(Note 10) TYP (Note 10) UNITS
V
V
Quiescent Current
I
VOUT = 1.0V
3.5
2.9
3
mA
mA
µA
IN
Q
IN)
Quiescent Current
I
(V
0 ≤ I ≤ 3A, V
= 5.5V
4.6
20
BIAS
Q
BIAS)
L
BIAS
Ground Pin Current in
Shutdown
I
SHDN
ENABLE Pin = 0.2V, T = +125°C
J
V
Dropout Voltage
V
I
I
I
I
I
I
= 1A, V
= 2A, V
= 3A, V
= 1A, V
= 2A, V
= 3A, V
= 1.2V, 2.9V ≤ V
= 1.2V, 2.9V ≤ V
= 1.2V, 2.9V ≤ V
= 1.2V
≤ 5V
≤ 5V
≤ 5V
27
53
90
115
140
1.3
1.4
1.5
mV
mV
mV
V
IN
(Note 11)
DO(VIN)
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
OUT
OUT
OUT
OUT
OUT
OUT
BIAS
BIAS
BIAS
75
V
Dropout Voltage
V
1.1
1.2
1.3
BIAS
DO(BIAS)
(Note 11)
= 1.2V
V
= 1.2V
V
OVERCURRENT PROTECTION
Output Short Circuit Current
(3A Version)
ISC
V
V
V
= 0.2V
= 0.2V
= 0.2V
5.2
3.2
2.2
A
A
A
OUT
OUT
OUT
Output Short Circuit Current
(2A Version)
Output Short Circuit Current
(1A Version)
OVER-TEMPERATURE PROTECTION
Thermal Shutdown
Temperature
TSD
160
20
°C
°C
Thermal Shutdown
Hysteresis
TSDn
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR(V
)
f = 120Hz, I
f = 120Hz, I
= 1A
= 1A
80
60
100
7
dB
dB
IN
LOAD
PSRR(V
)
BIAS
LOAD
Output Noise Voltage
Spectral Noise Density
e
I
I
I
= 10mA, BW = 100Hz ≤ f ≤ 100kHz
= 3A, f = 10Hz
µV
N(RMS)
LOAD
LOAD
LOAD
RMS
e
µV/√Hz
N
= 3A, f = 100Hz
3
µV √Hz
/
DEVICE START-UP CHARACTERISTICS
EN Start-up Time
t
C
C
= 10µF, I
LOAD
= 1A
50
µs
µs
EN
OUT
OUT
BIAS Start-up Time
t
= 10µF, EN = BIAS
100
BIAS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold (Rising)
Hysteresis (Rising Threshold)
PG PIN CHARACTERISTICS
PG Flag Falling Threshold
PG Flag Hysteresis
V
+ 0.4V ≤ V ≤ 3.6V, 2.9V ≤ V
IN
≤ 5.5V
400
60
680
260
850
330
mV
mV
OUT
BIAS
1.2V ≤ V ≤ 3.6V, 2.9V ≤ V
IN
≤ 5.5V
BIAS
PG
2.9V ≤ V
2.9V ≤ V
≤ 5.5V
≤ 5.5V
71
82
93
%V
%V
TH
BIAS
BIAS
OUT
PGHYS
9.3
OUT
FN7841.2
November 1, 2013
5
ISL80111, ISL80112, ISL80113
Electrical Specifications Unless otherwise specified, V = V
+ 0.4V, V
= 2.9V, V
OUT
= 1.2V, C = 1µF, C = 10µF,
BIAS IN
IN
OUT
BIAS
C
= 2.2µF, T = +25°C, I = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. Please
OUT
refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply over junction temperature (T ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure T = T where datasheet limits
J
L
J
J
A
are defined. (Continued)
MIN
MAX
PARAMETER
PG Flag Low Voltage
PG Flag Leakage Current
PG Flag Sink Current
NOTES:
SYMBOL
TEST CONDITIONS
(Note 10) TYP (Note 10) UNITS
I
= 500µA
90
11
10
130
300
mV
nA
SINK
PG = V
= 5.5V
BIAS
7
mA
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. Dropout is defined by the difference in supply (V , V
IN BIAS
) and V
OUT
when the supply produces a 2% drop in V from its nominal value, output
OUT
voltage set to 2.5V.
12. For normal operation, V must always be less than or equal to the voltage applied to V
. Part is protected against fault conditions where V can
IN
IN BIAS
be greater than V
.
BIAS
FN7841.2
November 1, 2013
6
ISL80111, ISL80112, ISL80113
Typical Operating Performance Unless otherwise noted, V = 1.8V, V
= 3.3V, V
OUT
= 1.2V, C = C
IN
= 10µF,
OUT
IN
BIAS
T = +25°C, I
J
= 0A.
LOAD
100
90
80
70
60
50
40
30
20
10
0
18
16
14
12
10
8
3A V
BIAS
= 3.3V
2A V
BIAS
= 3.3V
3A V
BIAS
= 5V
2A V
BIAS
= 5V
6
4
1A V
BIAS
= 3.3V
125
2
1A V
BIAS
= 5V
0
-40
25
TEMPERATURE (°C)
500.0 500.5 501.0 501.5 502.0 502.5 503.0 503.5 504.0
@ +25°C (mV)
V
ADJ
FIGURE 5. DROPOUT vs V
FIGURE 6. V
DISTRIBUTION
BIAS
ADJ
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
-0.60
-0.70
-0.80
-0.90
-1.00
I
= 0A - 3A
125
OUT
-40
0
25
TEMPERATURE (°C)
85
125
-40
0
25
TEMPERATURE (°C)
85
FIGURE 7. ΔV
ADJ
vs TEMPERATURE
FIGURE 8. LOAD REGULATION vs TEMPERATURE
1.2200
1.2175
1.2150
1.2125
1.2100
1.2075
1.2050
1.2025
1.2000
1.1975
1.1950
1.1925
1.205
1.204
1.203
1.202
1.201
1.200
1.199
1.198
1.197
1.196
1.195
V
= 3.7V
V
= 1.6V, V
2.0
= 2.9V
BIAS
IN
BIAS
2.5
1.1900
0
0.5
1.0
1.5
3.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
INPUT VOLTAGE (V)
LOAD CURRENT (A)
FIGURE 9. LOAD REGULATION, V
vs I
FIGURE 10. V LINE REGULATION
IN
OUT
OUT
FN7841.2
November 1, 2013
7
ISL80111, ISL80112, ISL80113
Typical Operating Performance Unless otherwise noted, V = 1.8V, V
= 3.3V, V
OUT
= 1.2V, C = C
IN
= 10µF,
OUT
IN
BIAS
T = +25°C, I
J
= 0A. (Continued)
LOAD
1.205
1.204
1.203
1.202
1.201
1.200
1.199
1.198
1.197
1.196
4.5
4.0
3.5
3.0
2.5
2.0
1.5
BIAS = 5V
BIAS = 2.9V
V
= 1.6V
IN
1.195
2.9
3.2
3.5
3.8
4.1
4.4
4.7 5.0
0
1
2
3
BIAS VOLTAGE (V)
OUTPUT CURRENT(A)
FIGURE 11. V
LINE REGULATION
FIGURE 12. BIAS GROUND CURRENT vs LOAD CURRENT
BIAS
11
10
9
3.2
3.0
2.8
2.6
2.4
2.2
V
= 5V
BIAS
= 3.3V
V
OUT
8
V
V
= 3.3V
BIAS
7
= 1.8V
OUT
6
5
V
= 5V
BIAS
= 1.8V
V
= 5V
V
V
= 3.3V
= 1.0V
BIAS
= 1.0V
BIAS
V
OUT
4
3
V
OUT
OUT
V
V
= 3.3V
= 0.8V
V
V
= 5V
BIAS
BIAS
= 0.8V
2
1
V
= 0.8V
OUT
OUT
2.6
VIN INPUT VOLTAGE (V)
OUT
3.4
2.0
2.9
1.0
1.4
1.8
2.2
3.0
3.8
3.2
3.5
3.8
4.1
4.4
4.7
5.0
BIAS VOLTAGE (V)
FIGURE 13. INPUT GROUND CURRENT vs V and V
IN
FIGURE 14. INPUT GROUND CURRENT vs V
BIAS
OUT
3.2
3.1
3.45
3.25
3.05
2.85
2.65
2.45
2.25
2.05
1.85
V
= 5V
= 0.8V
V
= 5V
= 1.2V
V
= 5V
BIAS
BIAS
BIAS
= 2.5V
3.0
2.9
2.8
2.7
2.6
2.5
2.4
V
V
V
OUT
OUT
OUT
V
= 3.3V
= 0.8V
V
V
= 3.3V
= 1.2V
BIAS
BIAS
V
OUT
OUT
V
V
= 3.3V
= 2.5V
BIAS
OUT
2.3
2.2
V
= 1.6V
IN
1.0
1.4
1.8
2.2
2.6
3.0
3.4
3.8
2.9
3.2
3.5
3.8
4.1
4.4
4.7
5.0
INPUT VOLTAGE (V)
BIAS VOLTAGE (V)
FIGURE 15. BIAS GROUND CURRENT vs V and V
IN
FIGURE 16. BIAS GROUND CURRENT vs V
BIAS
OUT
FN7841.2
November 1, 2013
8
ISL80111, ISL80112, ISL80113
Typical Operating Performance Unless otherwise noted, V = 1.8V, V
= 3.3V, V
OUT
= 1.2V, C = C
IN
= 10µF,
OUT
IN
BIAS
T = +25°C, I
J
= 0A. (Continued)
LOAD
12
10
8
EN
V
OUT
6
4
PGOOD
V
V
= 5.0V
= 3.6V
BIAS
2
OUT
I
IN
0
1.0
1.5
1.8
2.5
3.3
OUTPUT VOLTAGE(V)
FIGURE 18. ENABLE START-UP WITH PGOOD
FIGURE 17. V I vs VOUT VOLTAGE
IN Q
ISL80111 CURRENT LIMITING @ 2.1A
DURING TURN-ON OC EVENT
V
OUT
EN
PGOOD
V
OUT
PGOOD
I
IN
I
OUT
C
= 1000µF
LOAD
FIGURE 19. ISL8011X INTO AND OUT OF THERMAL SHUTDOWN
FIGURE 20. ISL80111 ENABLED INTO OVERCURRENT
ISL80113 CURRENT LIMITING @ 5A
DURING TURN-ON OC EVENT
ISL80112 CURRENT LIMITING @ 3.4A
DURING TURN-ON OC EVENT
EN
EN
V
V
OUT
OUT
PGOOD
PGOOD
I
I
IN
IN
C
= 1000µF
C
= 1000µF
LOAD
LOAD
FIGURE 22. ISL80113 ENABLED INTO OVERCURRENT
FIGURE 21. ISL80112 ENABLED INTO OVERCURRENT
FN7841.2
November 1, 2013
9
ISL80111, ISL80112, ISL80113
Typical Operating Performance Unless otherwise noted, V = 1.8V, V
= 3.3V, V
OUT
= 1.2V, C = C
IN
= 10µF,
OUT
IN
BIAS
T = +25°C, I
= 0A. (Continued)
LOAD
J
I
= 200mA
I
= 1.1A
OUT
OUT
I
=100mA
I
= 0.1A
OUT
OUT
V
(5mV/DIV)
V
(20mV/DIV)
OUT
OUT
TIME (20µs/DIV)
TIME (20µs/DIV)
FIGURE 23. 100mA LOAD TRANSIENT RESPONSE
FIGURE 24. 1A LOAD TRANSIENT RESPONSE
I
= 2.1A
OUT
I
= 3.1A
OUT
I
= 0.1A
I
= 0.1A
OUT
OUT
V
(20mV/DIV)
V
(50mV/DIV)
OUT
OUT
TIME (20µs/DIV)
TIME (20µs/DIV)
FIGURE 25. 2A LOAD TRANSIENT RESPONSE
FIGURE 26. 3A LOAD TRANSIENT RESPONSE
100
100
BIAS = 5V
BIAS = 5V
V
V
= 3.3V
IN
OUT
V
V
= 3.3V
IN
80
60
40
20
0
= 2.5V
= 10µF
80
60
40
20
0
= 2.5V
= 10µF
OUT
C
OUT
C
OUT
I
= 1A
OUT
I
= 0A
OUT
I
= 2A
OUT
I
= 0A
OUT
I
= 3A
OUT
I
= 2A
OUT
I
= 3A
OUT
I
= 1A
OUT
100
1k
10k
FREQUENCY (Hz)
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 28. BIAS PSRR vs LOAD CURRENT
FIGURE 27. V PSRR vs LOAD CURRENT
IN
FN7841.2
November 1, 2013
10
ISL80111, ISL80112, ISL80113
Typical Operating Performance Unless otherwise noted, V = 1.8V, V
= 3.3V, V
OUT
= 1.2V, C = C
IN
= 10µF,
OUT
IN
BIAS
T = +25°C, I
J
= 0A. (Continued)
LOAD
100
80
60
40
20
100
80
60
40
20
0
BIAS = 3.3V
BIAS = 3.3V
V
V
= 1.5V
I
= 0A
IN
OUT
OUT
V
V
= 1.5V
IN
OUT
= 1.0V
= 10µF
= 1.0V
= 10µF
C
OUT
C
OUT
I
= 2A
OUT
I
= 1A
OUT
I
= 2A
OUT
I
= 0A
OUT
I
= 3A
I
= 1A
OUT
OUT
I
= 3A
OUT
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 29. V
PSRR vs LOAD CURRENT
FIGURE 30. V
PSRR vs LOAD CURRENT
BIAS
VIN
100
80
100
80
60
40
20
0
BIAS = 5V
BIAS = 5V
V
V
= 3.3V
IN
V
V
= 3.3V
IN
= 2.5V
OUT
= 2.5V
OUT
I
= 3A
OUT
I
= 1A
OUT
60
C
= 10µF
C
= 2.2µF
OUT
OUT
C
= 10µF
C
= 2.2µF
OUT
OUT
40
C
= 20µF
OUT
10k
C
= 20µF
OUT
20
0
100
1k
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FREQUENCY (Hz)
FIGURE 31. V PSRR vs C
IN
FIGURE 32. V PSRR vs C
IN
OUT
OUT
100
80
100
80
60
40
20
0
BIAS = 5V
BIAS = 5V
V
V
= 3.3V
I
= 1A
V
= 3.3V
IN
OUT
IN
= 2.5V
V
= 2.5V
= 5x2.2µF
OUT
OUT
C
= 5x2.2µF
I
= 1A
C
OUT
OUT
OUT
60
I
I
= 0A
OUT
= 2A
I
= 0A
OUT
OUT
I
= 3A
OUT
40
20
0
I
= 2A
OUT
I
= 3A
OUT
100
1k
10k
FREQUENCY (Hz)
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 33. V PSRR vs LOAD CURRENT
IN
FIGURE 34. V
PSRR vs LOAD CURRENT
BIAS
FN7841.2
November 1, 2013
11
ISL80111, ISL80112, ISL80113
Typical Operating Performance Unless otherwise noted, V = 1.8V, V
= 3.3V, V
OUT
= 1.2V, C = C = 10µF,
IN OUT
IN
BIAS
T = +25°C, I
J
= 0A. (Continued)
LOAD
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1000
100
10
V
V
V
= 5V
BIAS
= 3.8V
300 lfm
IN
= 3.3V
OUT
= 3A
I
OUT
V
V
V
= 3.8V
= 1.28V
= 1V
= 3A
BIAS
IN
OUT
0 lfm
1
I
OUT
0.1
0.1
25 30 35 40 45 50 55 60 65 70 75 80 85 105 125
TEMPERATURE (°C)
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 35. CONTINUOUS POWER LIMIT vs AIR TEMP AND FLOW
FIGURE 36. INPUT VOLTAGE NOISE vs BIAS VOLTAGE
PGOOD pin should not be pulled up to a voltage source greater
than V . A PGOOD fault can be caused by the output voltage
Functional Description
BIAS
going below 84% of the nominal output voltage. PGOOD does not
function during thermal shutdown as the V is less than the
The ISL80111, ISL80112 and ISL80113 are high-performance,
low-dropout regulators featuring an NMOS pass device. Benefits
of using an NMOS as a pass device include low input voltage,
stability over a wide range of output capacitors, and ultra low
dropout voltage. The ISL80111, ISL80112 and ISL80113 are
ideal for post regulation of switch mode power supplies.
OUT
minimum regulation voltage during that time.
Output Voltage Selection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
The ISL80111, ISL80112 and ISL80113 also integrate enable,
power-good indicator, current limit protection, and thermal
shutdown functions into a space-saving 3x3 DFN package.
programmed to any level between 0.8V and 4V. Referring to
Figure 1 the external resistor divider, R and R , is used to set
3
4
Input Voltage Requirements
the output voltage as shown in Equation 1. The recommended
value for R is 500Ω to 1kΩ. R is then chosen according to
4
3
The VIN pin provides the high current to the drain of the NMOS
pass transistor. The specified minimum input voltage is 1V and
dropout voltage for this family of LDOs has been conservatively
specified.
Equation 2.
R
⎛
⎜
⎝
⎞
3
------
(EQ. 1)
(EQ. 2)
V
= 0.5V ×
+ 1
⎟
OUT
R
4
⎠
Bias Voltage Requirements
V
The V
input powers the internal control circuits, reference
OUT
0.5V
BIAS
voltage, and LDO gate driver. The difference between the V
⎛
⎝
⎞
---------------
R
= R
×
4
– 1
3
⎠
BIAS
BIAS
voltage and the output voltage must be greater than the V
dropout voltage specified in the “Electrical Specifications” table
Current Limit Protection
beginning on Page 4. The minimum V
input is 2.9V.
The ISL80111, ISL80112, and ISL80113 incorporate protection
against overcurrent due to a short, overload condition applied to
the output and the in-rush current that occurs at start-up. The
LDO performs as a constant current source when the output
current exceeds the current limit threshold noted in “Electrical
Specifications” on page 4. If the short or overload condition is
BIAS
Enable Operation
The ENABLE turn-on threshold is typically 600mV with a
hysteresis of 100mV. This pin must not be left floating. When this
pin is not used, it must be tied to V
. A 1kΩ to 10kΩ pull-up
BIAS
removed from V , then the output returns to normal voltage
resistor is required for applications that use open collector or
open drain outputs to control the ENABLE pin.
OUT
mode regulation. In the event of an overload condition, the LDO
might begin to cycle on and off due to the die temperature
exceeding the thermal fault condition.
Soft-start Operation
The ISL8011x has an internal 100µs typical soft-start function to
prevent excessive in-rush current during start-up.
Thermal Fault Protection
If the die temperature exceeds (typically) +160°C, the LDO
output shuts down until the die temperature cools to (typically)
+140°C. The level of power, combined with the thermal
impedance of the package (+48°C/W), determines whether the
junction temperature exceeds the thermal shutdown
temperature.
Power-good Operation
The PGOOD flag is an open-drain NMOS that can sink up to 10mA
during a fault condition. Applications not using this feature must
connect this pin to ground. The PGOOD pin requires an external
pull-up resistor, which is typically connected to the V
pin. The
OUT
FN7841.2
November 1, 2013
12
ISL80111, ISL80112, ISL80113
See Figure 35 for maximum continuous power dissipation
46
44
42
40
38
36
34
guidance for ambient temperature and linear air flow rate. This
graph ignores the insignificant power dissipation contribution of
the BIAS pin.
External Capacitor
Requirements
External capacitors are required for proper operation. To ensure
optimal performance, careful attention must be paid to the
layout guidelines and selection of capacitor type and value.
2
4
6
8
10
12
14
16
18
20
22
24
2
EPAD-MOUNT COPPER LAND AREA ON PCB (mm )
Input Capacitor
The minimum input capacitor required for proper operation is
10µF with a ceramic dielectric. This minimum capacitor must be
FIGURE 37. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS θ vs EPAD-MOUNT COPPER LAND
JA
AREA ON PCB
For safe operation, ensure that power dissipation calculated in
connected to the V and ground pins of the LDO no further than
IN
Equation 3 (P ) is less than the maximum allowable power
D
0.5cm away.
dissipation, P
.
D(MAX)
Output Capacitor
The ISL8011x applies state-of-the-art internal compensation to
simplify selection of the output capacitor. Stable operation over
The DFN package uses the copper area on the PCB as a heat
sink. For heat sinking, the EPAD of this package must be
soldered to the copper plane (GND plane). Figure 37 shows a
curve for the θ of the DFN package for different copper area
sizes.
the full temperature range, V range, V
extremes is guaranteed for all capacitor types and values,
range, and load
JA
IN OUT
assuming a 1µF X5R/X7R is used for local bypass on V . This
OUT
and ground
General PowerPAD Design Considerations
The following is an example of how to use vias to remove heat
from the IC.
minimum capacitor must be connected to the V
pins of the LDO no further than 0.5cm away.
OUT
Lower-cost Y5V and Z5U type ceramic capacitors are acceptable,
if the size of the capacitor is larger, to compensate for the
significantly lower tolerance over X5R/X7R types. Additional
capacitors of any value, in ceramic, POSCAP, or alum/tantalum
electrolytic types, can be placed in parallel to improve PSRR at
higher frequencies or load-transient AC output voltage
tolerances.
Filling the thermal pad area with vias is recommended. A typical
via array is to fill the thermal pad footprint with vias spaced such
that they are center on center 3x the radius apart from each
other. Keep the vias small but not so small that their inside
diameter prevents solder from wicking through the holes during
reflow.
Bias Capacitor
The minimum input capacitor required for proper operation is
1µF with a ceramic dielectric. This minimum capacitor must be
connected to the V
and ground pins of the LDO no further
than 0.5cm away. When the VBIAS pin is connected to the V
BIAS
IN
pin, a total of 10µF of X5R/X7R connected to the V pin and
IN
ground is sufficient.
Power Dissipation and Thermals
Power Dissipation
Junction temperature must not exceed the range specified in the
“Recommended Operating Conditions” section on Page 4. Power
dissipation can be calculated with Equation 3.
FIGURE 38. PCB VIA PATTERN
Connect all vias to the round plane. For efficient heat transfer, it
is important that the vias have low thermal resistance. Do not
use “thermal relief” patterns to connect the vias. It is important
to have a complete connection of the plated through-hole to each
plane.
P
= (V – V
) × I
+ V
× IQ(BIAS) + V × IQ(V
)
IN
D
IN
OUT
OUT
BIAS
IN
(EQ. 3)
The maximum allowable junction temperature, T
J(MAX)
, and the
maximum expected ambient temperature, T
, determine
the maximum allowable power dissipation, as shown in
A(MAX)
Equation 4, where θ is the junction-to-ambient thermal
JA
resistance.
(EQ. 4)
P
= (T
– T ) ⁄ θ
J(MAX) A JA
D(MAX)
FN7841.2
November 1, 2013
13
ISL80111, ISL80112, ISL80113
These LDOs consume significantly lower quiescent current as a
function of load compared to bipolar LDOs. This lower
consumption translates into higher efficiency and the ability to
consider packages with smaller footprints. The quiescent current
has been modestly compromised in design to enable leading
class fast load transient response and load regulation.
ISL80111, ISL80112, ISL80113
Split Supply LDO Evaluation
Board User Guide
Description
The ISL8011XEVAL1Z provides a simple platform to evaluate
performance of the ISL8011X family of split supply LDOs.
Jumpers are provided to easily set popular output voltages.
What’s Inside
• The evaluation kit contains the following:
• The ISL80113EVAL1Z with the appropriate parts installed
• The ISL80111, ISL80112, ISL80113 data sheet
The ISL80111, ISL80112, and ISL80113 are single-output LDOs
specified for 1A, 2A, 3A of output current and are optimized for
less than 2.5V and less output voltage conversions. The
ISL8011X supports V voltages down to 1V, provided a standard
IN
legacy 3.3V or 5V is applied on the V
is adjustable from 0.8V to 3.3V.
pin. The output voltage
Test Steps
BIAS
1. Select the desired output voltage by shorting one of the
jumpers from JP2 through JP5.
An enable input, having a threshold < 1V, allows the part to be
placed into a low quiescent current shutdown mode. A submicron
CMOS process is utilized for this product family to deliver
best-in-class analog performance and overall value for
applications in need of input voltage conversions to typically
below 2.5V. It also has the superior load transient regulation
unique to a NMOS power stage.
2. Connect both the BIAS and VIN supplies and the load. Enable
the IC using jumper JP6 (bottom position) or via a signal on
the center post, observe the output.
3. The shipped configuration is enabled and V
= 3.3V.
4. Scope shots taken from ISL8011XEVAL1Z boards.
OUT
FIGURE 39. ISL80113EVAL1Z (TOP PCB LEFT, PHOTOGRAPH RIGHT)
FN7841.2
November 1, 2013
14
ISL80111, ISL80112, ISL80113
Schematic
Bill of Materials
REFERENCE
PART
DESIGNATOR
VALUE
DESCRIPTION
MANUFACTURER
NUMBER
U1
ISL80111, ISL80112 or ISL80113 as noted on Intersil
the evaluation board
ISL80111IRAJZ,
ISL80112IRAJZ,
ISL80113IRAJZ
C1, C3
10µF
CAP, SMD, 0805, 50V, 10%
Generic
C2
R1
R2
R3
R4
R5
R6
R7
1µF
CAP, SMD, 0603
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
Generic
1kꢀ
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
RES, SMD, 0603, 1%
Jumper
2.05kꢀ
2.61kꢀ
4.02kꢀ
5.62kꢀ
1kꢀ
100kꢀ
JP1, JP2, JP3,
JP4, JP5, JP6
TP1, TP2, TP3
TP4, TP5, TP6
Terminal Connector
Generic
FN7841.2
November 1, 2013
15
ISL80111, ISL80112, ISL80113
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
FN7841.2
CHANGE
Electrical Spec table: Bold the Min and Max values.
November 1, 2013
Page 4- Electrical Spec table title area: Removed “Unless otherwise noted, all parameters are guaranteed
over the conditions specified as follows” and replaced by “Unless otherwise specified”.
Updated POD to latest revision from rev 7 to rev 8. The changes as follow: Corrected L-shaped leads in
Bottom view and land pattern so that they align with the rest of the leads (L shaped leads were shorter)
June 5, 2012
FN7841.1
Ordering Information table on Page 3: Changed evaluation board names from: ISL80111IRAJEVALZ,
ISL80112IRAJEVALZ and ISL80113IRAJEVALZ to ISL80111EVAL1Z, ISL80112EVAL1Z and
ISL80113VAL1Z.
Changed POD L10.3x3 on Page 17 to latest revision from Rev 6 to Rev 7. Change to POD is as follows:
Removed package outline and included center to center distance between lands on recommended land
pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and
0.30mm from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.
Figure 6 VADJ Distribution , corrected "Y" scale units from (0.18, 0.16, 0.14, 0.12, 0.10, 0.08, 0.06, 0.04,
0.02, and 0.00) to (18, 16,14,12,10, 8, 6, 4, 2, and 0).
Electrical Specifications table on Page 4 "Added UVLO rising spec to show max of 2.9V so implementation
at 3.3V is not a math problem".
March 30 2012
FN7841.0
Initial Release and Added “UVLO _BIAS _r” spec on pg 4. Modified Figures 13 - 17.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7841.2
November 1, 2013
16
ISL80111, ISL80112, ISL80113
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 8, 7/12
5
3.00
A
B
PIN #1 INDEX AREA
1
2
5
PIN 1
INDEX AREA
10 x 0.23
(4X)
0.10
1.60
10x 0.35
TOP VIEW
BOTTOM VIEW
A B
C
M
0.10
(4X)
0.415
0.23
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
4
0.20 REF
0.05
C
1.60
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
4.
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5.
FN7841.2
November 1, 2013
17
相关型号：
ISL80111IRAJZ-T
Ultra Low Dropout 1A Low Input Voltage NMOS LDOs; DFN10; Temp Range: -40° to 85°C
RENESAS
ISL80111IRAJZ-T7A
Ultra Low Dropout 1A Low Input Voltage NMOS LDOs; DFN10; Temp Range: -40° to 85°C
RENESAS
ISL80112IRAJZ-T
Ultra Low Dropout 2A Low Input Voltage NMOS LDOs; DFN10; Temp Range: -40° to 85°C
RENESAS
ISL80113IRAJZ-T
Ultra Low Dropout 3A Low Input Voltage NMOS LDOs; DFN10; Temp Range: -40° to 85°C
RENESAS
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