ISL8088IRZ [INTERSIL]
Dual 800mA Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator; 双800毫安低静态电流2.25MHz的高效率同步降压型稳压器
| 型号： | ISL8088IRZ |
| 厂家： | 
Intersil |
| 描述： | Dual 800mA Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator |
| 文件： | 总18页 (文件大小：1567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 800mA Low Quiescent Current 2.25MHz High
Efficiency Synchronous Buck Regulator
ISL8088
Features
• Internal Current Mode Compensation
• 100% Maximum Duty Cycle for Lowest Dropout
• Selectable Forced PWM Mode and PFM Mode
• External Synchronization up to 4MHz
• Start-up with Pre-biased Output
The ISL8088 is a high efficiency, dual synchronous
step-down DC/DC regulator that can deliver up to 800mA
continuous output current per channel. The supply
voltage range of 2.75V to 5.5V allows the use of a single
Li+ cell, three NiMH cells or a regulated 5V input. The
current mode control architecture enables very low duty
cycle operation at high frequency with fast transient
response and excellent loop stability. The ISL8088
operates at 2.25MHz switching frequency allowing the
use of small, low cost inductors and capacitors. Each
channel is optimized for generating an output voltage as
low as 0.6V.
• Soft-Stop Output Discharge During Disabled
• Internal Digital Soft-Start - 2ms
• Power-Good (PG) Output with 1ms Delay
Applications*(see page 17)
• DC/DC POL Modules
The ISL8088 has a user configurable mode of
operation-forced PWM mode and PFM/PWM mode. The
forced PWM mode operation reduces noise and RF
interference while the PFM mode operation provides high
efficiency by reducing switching losses at light loads. In
PFM mode of operation, both channels draw a total
quiescent current of only 30µA hence enabling high light
load efficiency in order to maximize battery life.
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Test and Measurement Systems
• Li-ion Battery Power Devices
• Bar Code Readers
The ISL8088 offers a 1ms Power-Good (PG) to monitor
both output at power-up. When shutdown, ISL8088
discharges the outputs capacitor. Other features include
internal digital soft-start, enable for power sequence,
overcurrent protection, and thermal shutdown. The
ISL8088 is offered in a 3mmx3mm 10 Ld DFN package
with 1mm maximum height. The complete converter
2
occupies less than 1.8cm area.
Efficiency Characteristics Curve Pin Configuration
ISL8088
(10 LD 3X3 DFN)
100
TOP VIEW
90
80
70
60
50
40
2.5V
-PFM
OUT
FB1
FB2
1
2
3
4
5
10
1.8V
OUT
-PFM
EN1
VIN
LX1
NC
EN2
PG
9
8
7
6
2.5V
-PWM
OUT
1.8V
OUT
- PWM
LX2
SYNC
11 PGND
VIN = 5V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
September 21, 2009
FN6858.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8088
Pin Descriptions
DFN
SYMBOL
DESCRIPTION
1
FB1
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error
amplifier. The output voltage is set by an external resistor divider connected to FB1. With a properly
selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter
losses) and the 0.6V reference. There is an internal compensation to meet a typical application. In addition,
the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1 regulator
output voltage.
2
EN1
Regulator Channel 1 enable pin. Enable the output, V
, when driven to high. Shutdown the V
and
OUT1
OUT1
discharge output capacitor when driven to low. Do not leave this pin floating.
Input supply voltage. Connect 10µF ceramic capacitor to power ground.
Switching node connection for Channel 1. Connect to one terminal of inductor for V
Recommended to connect this pin to the exposed pad.
3
4
5
6
VIN
LX1
.
OUT1
NC
SYNC
Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground
for forced PWM mode. Connect to an external function generator for Synchronization, and negative edge
trigger. Do not leave this pin floating.
7
8
LX2
PG
Switching node connection for Channel 2. Connect to one terminal of inductor for V .
OUT2
1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the
and V voltages. There is an internal 1MΩ pull-up resistor.
V
OUT1
OUT2
9
EN2
FB2
Regulator Channel 2 enable pin. Enable the output, V
, when driven to high. Shutdown the V
and
OUT2
OUT2
discharge output capacitor when driven to low. Do not leave this pin floating.
10
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error
amplifier. The output voltage is set by an external resistor divider connected to FB2. With a properly
selected divider, the output voltage can be set to any voltage between the power-rail (reduced by converter
losses) and the 0.6V reference. There is an internal compensation to meet a typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2
regulator output voltage.
11 Exposed Pad The exposed pad must be connected to the PGND pin for proper electrical performance. Add as much vias
as possible for optimal thermal performance.
FN6858.0
September 21, 2009
2
ISL8088
Typical Application
L1
2.2µH
OUTPUT1
2.5V/800mA
LX1
C2
10µF
C3
10pF
PGND
FB1
R2
316k
INPUT 2.75V TO 5.5V
VIN
EN1
R3
100k
C1
10µF
ISL8088
EN2
L2
2.2µH
OUTPUT2
1.8V/800mA
LX2
PG
C4
10µF
C5
10pF
PGND
FB2
R5
SYNC
200k
R6
100k
PGND
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8088IRZ
8088
8088
-40 to +85
-40 to +85
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3C
L10.3x3C
ISL8088IRZ-T (Note 1)
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8088. For more information on MSL please see
techbrief TB363.
FN6858.0
September 21, 2009
3
ISL8088
Absolute Maximum Ratings (Reference to GND)
Thermal Information
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
IN
Thermal Resistance (Typical, Notes 4, 5)
10 Ld 3x3 DFN Package . . . . . . .
Storage Temperature Range. . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
JA (°C/W)θJC (°C/W)
V
. . . . . . . . . . . . . . . . . . . . . . .. . . . .-0.3V to 7V (20ms)
IN
49
4
EN1, EN2, PG, SYNC. . . . . . . . . . . . . . . -0.3V to V + 0.3V
IN
LX1, LX2 . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
LX1, LX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V (100ns)
. . . . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to 7V (20ms)
FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Recommended Operating Conditions
V
Supply Voltage Range . . . . . . . . . . . . . . .2.75V to 5.5V
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
IN
Load Current Range Per Channel. . . . . . . . . . 0mA to 800mA
Ambient Temperature Range . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range . . . . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended
operating conditions: T = -40°C to +85°C, V = 2.75V to 5.5V, EN1 = EN2 = VIN, SYNC =
A
IN
0V, L = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, IOUT1 = IOUT2 = 0A to 800mA. (Typical values
are at T = +25°C, VIN = 3.6V). Boldface limits apply over the operating temperature
A
range, -40°C to +85°C.
MIN
MAX
PARAMETER
INPUT SUPPLY
Undervoltage Lockout Threshold
SYMBOL
TEST CONDITIONS
(Note 6) TYP (Note 6) UNITS
V
V
Rising
Falling
2.5
2.4
30
2.75
V
V
IN
UVLO
2.1
Quiescent Supply Current
I
SYNC = V , EN1 = EN2 = V , no
IN IN
50
µA
VIN
load at the output and no switches
switching.
VFB1 = VFB2 = 0.7V
SYNC = GND, EN1 = EN2 = VIN,
0.1
6.5
1
mA
µA
F = 2.25MHz, no load at the output
S
Shut Down Supply Current
OUTPUT REGULATION
FB1, FB2 Regulation Voltage
FB1, FB2 Bias Current
Line Regulation
I
V
= 5.5V, EN1 = EN2 = GND
IN
12
SD
V
0.590
0.6
0.1
0.2
0.610
V
FB_
I
VFB = 0.55V
= V + 0.5V to 5.5V (minimal
µA
FB_
V
%/V
IN
O
2.75V, I
= 0A)
OUT
Soft-Start Ramp Time Cycle
OVERCURRENT PROTECTION
Peak Overcurrent Limit
2
ms
I
I
0.95
0.95
180
180
1.2
1.2
1.6
1.6
A
pk1
A
pk2
Peak SKIP Limit
I
V
= 3.6V
250
250
360
360
mA
mA
skip1
skip2
IN
I
LX1, LX2
P-Channel MOSFET ON-Resistance
V
V
= 5.5V, I = 200mA
180
320
350
450
mΩ
mΩ
IN
IN
O
= 2.75V, I = 200mA
O
FN6858.0
September 21, 2009
4
ISL8088
Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended
operating conditions: T = -40°C to +85°C, V = 2.75V to 5.5V, EN1 = EN2 = VIN, SYNC =
A
IN
0V, L = 2.2µH, C1 = 10µF, C2 = C4 = 10µF, IOUT1 = IOUT2 = 0A to 800mA. (Typical values
are at T = +25°C, VIN = 3.6V). Boldface limits apply over the operating temperature
A
range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
= 5.5V, I = 200mA
(Note 6) TYP (Note 6) UNITS
N-Channel MOSFET ON-Resistance
V
V
180
320
100
2.25
350
450
mΩ
mΩ
%
IN
IN
O
= 2.75V, I = 200mA
O
LX_ Maximum Duty Cycle
PWM Switching Frequency
Synchronization Range
LX Minimum On-Time
Soft Discharge Resistance
PG
F
1.8
2.7
2.7
4
MHz
MHz
ns
S
SYNC = 0 (forced PWM mode)
EN = LOW
100
130
R
80
100
Ω
DIS_
Output Low Voltage
PG Pull-up Resistor
Sinking 1mA, VFB = 0.5V
0.3
V
1
MΩ
%
Internal P
Low Rising Threshold
Percentage of nominal regulation
voltage
88
82
92
96
91
GOOD
Internal P
Low Falling Threshold
Percentage of nominal regulation
voltage
89
%
GOOD
Delay Time (Rising Edge)
Internal P Delay Time (Falling Edge)
1
1
ms
µs
2
GOOD
EN1, EN2, SYNC
Logic Input Low
0.4
V
Logic Input High
1.4
V
SYNC Logic Input Leakage Current
Enable Logic Input Leakage Current
Thermal Shutdown
I
Pulled up to 5.5V
0.1
0.1
150
25
1
1
µA
µA
°C
°C
SYNC
I
EN_
Thermal Shutdown Hysteresis
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
FN6858.0
September 21, 2009
5
ISL8088
Typical Operating Performance
(Unless otherwise noted) operating conditions are:
T = +25°C, V = 2.75V to 5.5V, EN = V , L = L = 2.2µH,
A
IN
IN
1
2
C = 10µF, C = C = 10µF, V
= 2.5V, V
= 1.8V,
1
2
4
OUT1
OUT2
I
= I
100
90
= 0A to 800mA.
OUT1
OUT2
100
90
80
80
2.5V
OUT
- PWM
2.5V
- PFM
OUT
70
60
50
40
70
1.5V
OUT
- PWM
- PWM
1.8V
1.8V
OUT
- PFM
1.5V
OUT
- PFM
1.2V
OUT
1.2V
- PFM
OUT
60
PWM
OUT -
50
40
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7 0.8
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
PFM
OUTPUT LOAD
OUTPUT LOAD (A)
FIGURE 2. EFFICIENCY vs LOAD 2.25MHz 3.3V
FIGURE 1. EFFICIENCY vs LOAD 2.25MHz 3.3V
PWM
IN
IN
100
90
100
90
80
80
2.5V
OUT
- PWM
70
70
60
50
40
1.5V
OUT
- PFM
3.3V
OUT
- PFM
3.3V
0.1
- PWM
1.2V
1.5V
OUT
- PWM
OUT
1.2V
0.3
- PFM
OUT
60
50
40
- PWM
1.8V - PWM
OUT
OUT
1.8V
- PFM
2.5V
OUT
- PFM
OUT
0.0
0.1
0.2
0.4
0.5
0.6
0.7
0.8
0.0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 3. EFFICIENCY vs LOAD 2.25MHz 5V
IN
PWM
FIGURE 4. EFFICIENCY vs LOAD 2.25MHz 5V
IN
PFM
0.30
1.23
5V
IN
PFM MODE
5V
3.3V
- PWM MODE
0.25
0.20
0.15
0.10
0.05
0.00
IN
1.22
1.21
1.20
1.19
1.18
1.17
PWM MODE
IN
5V
IN
- PWM MODE
5V
IN
- PFM MODE
3.3V V
IN
PFM
3.3V V
IN
PWM
3.3V
- PFM
IN
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 6. V
REGULATION vs LOAD 2.25MHz
PFM
FIGURE 5. POWER DISSIPATION vs LOAD 2.25MHz
1.8V PWM
OUT
1.2V
OUT
OUT
FN6858.0
September 21, 2009
6
ISL8088
Typical Operating Performance
(Unless otherwise noted) operating conditions are:
T = +25°C, V = 2.75V to 5.5V, EN = V , L = L = 2.2µH,
A
IN
IN
1
2
C = 10µF, C = C = 10µF, V
= 2.5V, V
= 1.8V,
1
2
4
OUT1
OUT2
I
= I
= 0A to 800mA. (Continued)
OUT1
OUT2
1.56
1.84
5 V
IN
PFM MODE
5 V
IN
PFM MODE
1.55
1.54
1.53
1.52
1.51
1.50
1.83
3.3V V
IN
PFM
1.82
1.81
3.3V V
IN
PFM
5V
IN
PWM MODE
1.80
1.79
1.78
3.3V V
IN
PWM
3.3V V
PWM
0.2
IN
5V
IN
PWM MODE
0.2
0.0
0.1
0.3
0.4
0.5
0.6
0.7
0.8
0.0
0.1
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 8. V
REGULATION vs LOAD 2.25MHz
FIGURE 7. V
REGULATION vs LOAD 2.25MHz
OUT
OUT
1.5V
1.8V
OUT
OUT
2.55
2.54
2.53
2.52
2.51
2.50
2.49
3.42
3.40
3.38
3.36
3.34
3.32
3.30
5V V
IN
PFM
5V V
IN
PFM
3.3V V
IN
PFM
5V V
IN
PWM
5V V
IN
PWM
3.3V V
IN
PWM
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 10. V
REGULATION vs LOAD 2.25MHz
FIGURE 9. V
REGULATION vs LOAD 2.25MHz
OUT
3.3V
OUT
2.5V
OUT
OUT
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.83
1.82
1.81
1.80
1.79
1.78
1.77
0A LOAD
0A LOAD PWM
0.4A LOAD
0.8A LOAD
0.4A LOAD PWM
0.8A LOAD PWM
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 11. OUTPUT VOLTAGE REGULATION vs V
FIGURE 12. OUTPUT VOLTAGE REGULATION vs V
IN
IN
1.8V
PWM MODE
1.8V
PFM MODE
OUT
OUT
FN6858.0
September 21, 2009
7
ISL8088
Typical Operating Performance
(Unless otherwise noted) operating conditions are:
T = +25°C, V = 2.75V to 5.5V, EN = V , L = L = 2.2µH,
A
IN
IN
1
2
C = 10µF, C = C = 10µF, V
= 2.5V, V
= 1.8V,
1
2
4
OUT1
OUT2
I
= I
= 0A to 800mA. (Continued)
OUT1
OUT2
500ns/DIV
500ns/DIV
LX1 2V/DIV
LX2 2V/DIV
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT2
OUT1
I
0.5A/DIV
I
0.5A/DIV
L1
L2
FIGURE 14. STEADY STATE OPERATION AT NO LOAD
CHANNEL 2 (PWM)
FIGURE 13. STEADY STATE OPERATION AT NO LOAD
CHANNEL 1 (PWM)
LX1 2V/DIV
500ns/DIV
500ns/DIV
LX2 2V/DIV
V
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 20mV/DIV
0.5A/DIV
OUT2
I
L1
0.5A/DIV
I
L2
FIGURE 16. STEADY STATE OPERATION AT NO LOAD
CHANNEL 2 (PFM)
FIGURE 15. STEADY STATE OPERATION AT NO LOAD
CHANNEL 1 (PFM)
LX2 2V/DIV
LX1 2V/DIV
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT2
OUT1
I
0.5A/DIV
L1
500ns/DIV
I
0.5A/DIV
L2
500ns/DIV
FIGURE 18. STEADY STATE OPERATION WITH FULL
LOAD CHANNEL 2
FIGURE 17. STEADY STATE OPERATION WITH FULL
LOAD CHANNEL 1
FN6858.0
September 21, 2009
8
ISL8088
Typical Operating Performance
(Unless otherwise noted) operating conditions are:
T = +25°C, V = 2.75V to 5.5V, EN = V , L = L = 2.2µH,
A
IN
IN
1
2
C = 10µF, C = C = 10µF, V
= 2.5V, V
= 1.8V,
1
2
4
OUT1
OUT2
I
= I
= 0A to 800mA. (Continued)
OUT1
OUT2
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT2
OUT1
I
L1
0.5A/DIV
I
0.5A/DIV
L2
50µs/DIV
50µs/DIV
FIGURE 20. LOAD TRANSIENT CHANNEL 2 (PWM)
FIGURE 19. LOAD TRANSIENT CHANNEL 1 (PWM)
LX2 2V/DIV
LX1 2V/DIV
V
RIPPLE 50mV/DIV
OUT1
V
RIPPLE 50mV/DIV
OUT2
50µs/DIV
50µs/DIV
I
0.5A/DIV
I
0.5A/DIV
L2
L1
FIGURE 22. LOAD TRANSIENT CHANNEL 2 (PFM)
FIGURE 21. LOAD TRANSIENT CHANNEL 1 (PFM)
50µs/DIV
50µs/DIV
EN2 2V/DIV
V
0.5V/DIV
EN1 2V/DIV
OUT2
V
1V/DIV
OUT1
I
0.5A/DIV
L2
I
0.5A/DIV
L1
PG 5V/DIV
PG 5V/DIV
FIGURE 23. SOFT-START WITH NO LOAD CHANNEL 1
(PWM)
FIGURE 24. SOFT-START WITH NO LOAD CHANNEL 2
(PWM)
FN6858.0
September 21, 2009
9
ISL8088
Typical Operating Performance
(Unless otherwise noted) operating conditions are:
T = +25°C, V = 2.75V to 5.5V, EN = V , L = L = 2.2µH,
A
IN
IN
1
2
C = 10µF, C = C = 10µF, V
= 2.5V, V
= 1.8V,
1
2
4
OUT1
OUT2
I
= I
= 0A to 800mA. (Continued)
OUT1
OUT2
50µs/DIV
50µs/DIV
EN2 2V/DIV
EN1 2V/DIV
V
0.5V/DIV
OUT2
V
1V/DIV
OUT1
I
0.5A/DIV
L2
0.5A/DIV
I
L
PG 5V/DIV
PG 5V/DIV
FIGURE 25. SOFT-START AT NO LOAD CHANNEL 1
(PFM)
FIGURE 26. SOFT-START AT NO LOAD CHANNEL 2
(PFM)
50µs/DIV
50µs/DIV
EN1 2V/DIV
EN2 2V/DIV
V
1V/DIV
OUT1
V
0.5V/DIV
OUT2
I
0.5A/DIV
L1
I
0.5A/DIV
L2
PG 5V/DIV
PG 5V/DIV
FIGURE 27. SOFT-START AT FULL LOAD CHANNEL 1
FIGURE 28. SOFT-START AT FULL LOAD CHANNEL 2
EN2 5V/DIV
1ms/DIV
1ms/DIV
EN1 5V/DIV
V
0.5V/DIV
OUT2
V
1V/DIV
OUT1
I
0.5A/DIV
L2
I
0.5A/DIV
L1
PG 5V/DIV
PG 5V/DIV
FIGURE 30. SOFT-DISCHARGE SHUTDOWN CHANNEL 2
FIGURE 29. SOFT-DISCHARGE SHUTDOWN CHANNEL 1
FN6858.0
September 21, 2009
10
ISL8088
Typical Operating Performance
(Unless otherwise noted) operating conditions are:
T = +25°C, V = 2.75V to 5.5V, EN = V , L = L = 2.2µH,
A
IN
IN
1
2
C = 10µF, C = C = 10µF, V
= 2.5V, V
= 1.8V,
1
2
4
OUT1
OUT2
I
= I
= 0A to 800mA. (Continued)
OUT1
OUT2
200ns/DIV
200ns/DIV
LX1 2V/DIV
LX1 2V/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
V
RIPPLE 20mV/DIV
I
0.5A/DIV
OUT1
L1
V
RIPPLE 20mV/DIV
I
0.5A/DIV
OUT1
L1
FIGURE 31. CH1 STEADY STATE OPERATION AT NO
LOAD (PFM) WITH FREQUENCY = 4MHz
FIGURE 32. CH1 STEADY STATE OPERATION AT FULL
LOAD (PFM) WITH FREQUENCY = 4MHz
200ns/DIV
200ns/DIV
LX2 2V/DIV
LX2 2V/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
I
0.5A/DIV
L2
V
RIPPLE 20mV/DIV
OUT2
V
RIPPLE 20mV/DIV
OUT2
I
0.5A/DIV
L2
FIGURE 34. CH2 STEADY STATE OPERATION AT FULL
LOAD (PFM) WITH FREQUENCY = 4MHz
FIGURE 33. CH2 STEADY STATE OPERATION AT NO
LOAD (PFM) WITH FREQUENCY = 4MHz
100ns/DIV
100ns/DIV
LX1 5V/DIV
LX1 5V/DIV
LX2 5V/DIV
LX2 5V/DIV
SYNCH 5V/DIV
SYNCH 5V/DIV
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT1
OUT1
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT2
OUT2
FIGURE 36. CH1 AND CH2 STEADY STATE OPERATION
AT FULL LOAD (PFM) WITH
FIGURE 35. CH1 AND CH2 STEADY STATE OPERATION
AT NO LOAD (PFM) WITH
FREQUENCY = 4MHz
FREQUENCY = 4MHz
FN6858.0
September 21, 2009
11
ISL8088
Typical Operating Performance
(Unless otherwise noted) operating conditions are:
T = +25°C, V = 2.75V to 5.5V, EN = V , L = L = 2.2µH,
A
IN
IN
1
2
C = 10µF, C = C = 10µF, V
= 2.5V, V
= 1.8V,
1
2
4
OUT1
OUT2
I
= I
= 0A to 800mA. (Continued)
OUT1
OUT2
PHASE1 5V/DIV
LX1 5V/DIV
I
0.5A/DIV
L1
V
1V/DIV
OUT1
V
1V/DIV
I
0.5A/DIV
OUT1
L1
500µs/DIV
10µs/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 37. OUTPUT SHORT CIRCUIT CHANNEL 1
FIGURE 38. OUTPUT SHORT CIRCUIT RECOVERY
CHANNEL 1
500µs/DIV
10µs/DIV
PHASE2 5V/DIV
LX2 5V/DIV
V
0.5V/DIV
OUT2
I
0.5A/DIV
L2
I
0.5A/DIV
L2
V
1V/DIV
OUT2
PG 5V/DIV
PG 5V/DIV
FIGURE 39. OUTPUT SHORT CIRCUIT CHANNEL 2
FIGURE 40. OUTPUT SHORT CIRCUIT RECOVERY
CHANNEL 2
2.4
VIN 6V IOUT2 OC
VIN 6V IOUT1 OC
2.0
1.6
1.2
0.8
0.4
0
VIN 3.5V IOUT2 OC
VIN 3.5V IOUT1 OC
-50
-30
-10
10
20
50
70
90
110
TEMPERATURE (°C)
FIGURE 41. OUTPUT CURRENT LIMIT vs TEMPERATURE
FN6858.0
September 21, 2009
12
ISL8088
Block Diagram
SHUTDOWN
SOFT-
START
27pF
200k
SHUTDOWN
VIN
+
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
EN1
0.6V
BANDGAP
+
+
EAMP
LX1
COMP
-
-
3pF
PGND
SLOPE
COMP
+
+
FB1
CSA1
+
-
SCP
0.3V
1.6k
-
+
OCP
0.59V
-
+
PG1
SKIP
+
0.09V
-
OSCILLATOR
VIN
0.552V
-
ZERO-CROSS
SENSING
1M
PG
1ms
DELAY
SGND
SYNC
SHUTDOWN
SHUTDOWN
THERMAL
SHUTDOWN
27pF
200k
SOFT-
START
SHUTDOWN
+
VIN
EN2
0.6V
+
BANDGAP
+
EAMP
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
COMP
-
-
LX2
3pF
PGND
SLOPE
COMP
+
+
FB2
CSA2
-
-
SCP
0.3V
+
1.6k
+
OCP
0.59V
0.09V
-
+
0.552V
-
+
PG2
SKIP
-
ZERO-CROSS
SENSING
FN6858.0
September 21, 2009
13
ISL8088
The dotted lines illustrate the sum of the compensation
ramp and the current-sense amplifier CSA-output.
Theory of Operation
The ISL8088 is a dual 800mA step-down switching
regulator optimized for battery-powered or mobile
applications. The regulator operates at 2.25MHz fixed
switching frequency under heavy load conditions to allow
small external inductor and capacitors to be used for
minimal printed-circuit board (PCB) area. At light load,
the regulator reduces the switching frequency, unless
forced to the fixed frequency, to minimize the switching
loss and to maximize the battery life. The two channels
are in-phase operation. The quiescent current when the
outputs are not loaded is typically only 30µA. The supply
current is typically only 6.5µA when the regulator is shut
down.
The output voltage is regulated by controlling the
reference voltage to the current loop. The bandgap
circuit outputs a 0.6V reference voltage to the voltage
control loop. The feedback signal comes from the V
FB
pin. The soft-start block only affects the operation during
the start-up and will be discussed separately shortly. The
error amplifier is a transconductance amplifier that
converts the voltage error signal to a current output. The
voltage loop is internally compensated with the 27pF and
200kΩ RC network. The maximum EAMP voltage output
is precisely clamped to 0.8V.
V
EAMP
PWM Control Scheme
Pulling the SYNC pin LOW (<0.4V) forces the converter
into PWM mode in the next switching cycle regardless of
output current. Each of the channels of the ISL8088
employ the current-mode pulse-width modulation
(PWM) control scheme for fast transient response and
pulse-by-pulse current limiting shown in the “Block
Diagram” on page 13. The current loop consists of the
oscillator, the PWM comparator COMP, current sensing
circuit, and the slope compensation for the current loop
stability. The current sensing circuit consists of the
resistance of the P-Channel MOSFET when it is turned
on and the current sense amplifier CSA1 (or CSA2 on
Channel 2). The gain for the current sensing circuit is
typically 0.285V/A. The control reference for the current
loops comes from the error amplifier EAMP of the
voltage loop.
V
CSA
DUTY
CYCLE
I
L
V
OUT
FIGURE 42. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNC pin HIGH (>2.0V) forces the converter
into PFM mode. The ISL8088 enters a pulse-skipping
mode at light load to minimize the switching loss by
reducing the switching frequency. Figure 43 illustrates
the skip-mode operation. A zero-cross sensing circuit
shown in the “Block Diagram” on page 13 monitors the
N-MOSFET current for zero crossing. When 8 consecutive
cycles of the N-MOSFET crossing zero are detected, the
regulator enters the skip mode. During the 8 detecting
cycles, the current in the inductor is allowed to become
negative. The counter is reset to zero when the current in
any cycle does not cross zero.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the
MOSFET starts to ramp-up. When the sum of the
current amplifier CSA1 (or CSA2) and the compensation
slope (0.33V/µs) reaches the control reference of the
current loop, the PWM comparator COMP sends a signal
to the PWM logic to turn off the P-MOSFET and to turn
on the N-Channel MOSFET. The N-MOSFET stays on
until the end of the PWM cycle. Figure 42 shows the
typical operating waveforms during the PWM operation.
PWM
PFM
CLOCK
8 CYCLES
PFM CURRENT LIMIT
I
L
LOAD CURRENT
0
NOMINAL +1.5%
V
OUT
NOMINAL
FIGURE 43. SKIP MODE OPERATION WAVEFORMS
FN6858.0
September 21, 2009
14
ISL8088
Once the skip mode is entered, the pulse modulation
UVLO
starts being controlled by the SKIP comparator shown in
the “Block Diagram” on page 13. Each pulse cycle is still
synchronized by the PWM clock. The P-MOSFET is turned
on at the clock and turned off when its current reaches
the threshold of 250mA. As the average inductor current
in each cycle is higher than the average current of the
load, the output voltage rises cycle over cycle. When the
output voltage reaches 1.5% above the nominal voltage,
the P-MOSFET is turned off immediately. Then the
inductor current is fully discharged to zero and stays at
zero. The output voltage reduces gradually due to the
load current discharging the output capacitor. When the
output voltage drops to the nominal voltage, the
P-MOSFET will be turned on again at the clock, repeating
the previous operations.
When the input voltage is below the undervoltage lock
out (UVLO) threshold, the regulator is disabled.
Enable
The enable (EN1, EN2) input allows user to control the
turning on or off the regulator for purposes such as
power-up sequencing. The regulator is enabled, there is
typically a 600µs delay for waking up the bandgap
reference, then the soft start-up begins.
Soft-Start-Up
The soft-start-up eliminates the in-rush current during
the start-up. The soft-start block outputs a ramp
reference to both the voltage loop and the current loop.
The two ramps limit the inductor current rising speed as
well as the output voltage speed so that the output
voltage rises in a controlled fashion. At the very
beginning of the start-up, the output voltage is less than
0.2V; hence the PWM operating frequency is 1/3 of the
normal frequency.
The regulator resumes normal PWM mode operation
when the output voltage drops 1.5% below the nominal
voltage.
Synchronization Control
The frequency of operation can be synchronized up to
4MHz by an external signal applied to the SYNC pin. The
falling edge on the SYNC triggered the rising edge of the
PWM ON pulse.
In force PWM mode, the IC will continue to start-up in
PFM mode to support pre-biased load applications.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs, or the
output undervoltage fault latch is set, the outputs
discharge to GND through an internal 100Ω switch.
Overcurrent Protection
CSA1 and CSA2 is used to monitor output 1 and output 2
channels respectively. The overcurrent protection is
realized by monitoring the CSA_ output with the OCP
threshold logic, as shown in “Block Diagram” on page 13.
The current sensing circuit has a gain of 0.285V/A, from
the P-MOSFET current to the CSA_output. When the
CSA_ output reaches the threshold of 590mV, the OCP
comparator is tripped to turn off the P-MOSFET
immediately. The overcurrent function protects the
switching converter from a shorted output by
monitoring the current flowing through the upper
MOSFETs.
Power MOSFETs
The power MOSFETs are optimize for best efficiency. The
ON-resistance for the P-MOSFET is typically 180mΩ and
the ON- resistance for the N-MOSFET is typical 180mΩ.
100% Duty Cycle
The ISL8088 features 100% duty cycle operation to
maximize the battery life. When the battery voltage
drops to a level that the ISL8088 can no longer maintain
the regulation at the output, the regulator completely
turns on the P-MOSFET. The maximum dropout voltage
under the 100% duty-cycle operation is the product of
the load current and the ON-resistance of the P-MOSFET.
Upon detection of overcurrent condition, the upper
MOSFET will be immediately turned off and will not be
turned on again until the next switching cycle.
Thermal Shut Down
PG
The ISL8088 has built-in thermal protection. When the
internal temperature reaches +150°C, the regulator is
completely shut down. As the temperature drops to
+130°C, the ISL8088 resumes operation by stepping
through a soft-start-up.
The power-good signal, (PG) monitors both of the output
channels. When powering up, the open-collector
power-on-reset output holds low for about 1ms after V
O1
and V
O2
reaches the preset voltages. The PG output also
serves as a 1ms delayed Power-Good signal. If one of the
output is disabled, then PG only monitors the active
channels. There is an internal 1MΩ pull-up resistor.
Applications Information
Output Inductor and Capacitor Selection
To consider steady state and transient operation,
ISL8088 typically uses a 2.2µH output inductor. Higher or
lower inductor values can be used to optimize the total
converter system performance. For example, for higher
output voltage 3.3V applications, in order to decrease the
inductor current ripple and output voltage ripple, the
TABLE 1. PG
PG1
PG2
EN1
EN2
INTERNAL INTERNAL
PG
0
0
0
1
1
0
1
0
1
X
X
1
1
X
1
X
1
1
1
1
FN6858.0
September 21, 2009
15
ISL8088
output inductor value can be increased. The inductor
ripple current can be expressed as shown in Equation 1:
The output voltage programming resistor, R (or R in
2 5
Channel 2), will depend on the desired output voltage of
the regulator. The value for the feedback resistor is
typically between 0Ω and 750kΩ as shown in Equation 2.
V
⎛
⎞
⎟
⎠
O
---------
V
• 1 –
⎜
O
V
⎝
IN
(EQ. 1)
--------------------------------------
ΔI =
Let R = 100kΩ, then R will be:
3
2
L • f
S
V
⎛
⎜
⎝
⎞
OUT
(EQ. 2)
---------------
R
= R
– 1
⎟
The inductor’s saturation current rating needs be at least
larger than the peak current. The ISL8088 protects the
typical peak current 1.2A. The saturation current needs
be over 1.8A for maximum output current application.
2
3
V
⎠
FB
If the output voltage desired is 0.6V, then R is left
unpopulated and short R . For faster response
performance, add 47pF in parallel to R .
3
2
ISL8088 uses internal compensation network and the
output capacitor value is dependent on the output
voltage. The ceramic capacitor is recommended to be
X5R or X7R. The recommended minimum output
capacitor values are shown in Table 2 for the ISL8088.
2
Input Capacitor Selection
The main functions for the input capacitor is to provide
decoupling of the parasitic inductance and to provide
filtering function to prevent the switching current flowing
back to the battery rail. One 10µF X5R or X7R ceramic
capacitor is a good starting point for the input capacitor
selection for both channels.
TABLE 2. OUTPUT CAPACITOR VALUE vs V
ISL8088
OUT
V
C
(µF)
L
OUT
OUT
(V)
0.8
1.2
1.6
1.8
2.5
3.3
3.6
(µH)
PCB Layout Recommendation
10
1.0~2.2
1.0~2.2
1.0~2.2
1.5~3.3
1.5~3.3
1.5~4.7
1.5~4.7
The PCB layout is a very important converter design step
to make sure the designed converter works well. For
ISL8088, the power loop is composed of the output
10
10
inductor (L’s), the output capacitor (COUT1 and C
),
OUT2
10
the LX’s pins, and the GND pin. It is necessary to make
the power loop as small as possible and the connecting
traces among them should be direct, short and wide. The
switching node of the converter, the LX_ pins, and the
traces connected to the node are very noisy, so keep the
voltage feedback trace away from these noisy traces. The
input capacitor should be placed as closely as possible to
the VIN pin. The ground of input and output capacitors
should be connected as closely as possible. The heat of
the IC is mainly dissipated through the thermal pad.
Maximizing the copper area connected to the thermal
pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to
add at least 5 vias ground connection within the pad for
the best thermal relief.
10
6.8
8.6
In Table 2, the minimum output capacitor value is given
for different output voltage to make sure the whole
converter system is stable.
Output Voltage Selection
The output voltage of the regulator can be programmed
via an external resistor divider that is used to scale the
output voltage relative to the internal reference voltage
and feed it back to the inverting input of the error
amplifier. Refer to “Typical Application” on page 3.
FN6858.0
September 21, 2009
16
ISL8088
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
9/21/09
FN6858.0
Initial release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL8088
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
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FN6858.0
September 21, 2009
17
ISL8088
Package Outline Drawing
L10.3x3C
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 2, 09/09
6
3.00
A
B
PIN #1 INDEX AREA
10
1
2
6
PIN 1
INDEX AREA
10 x 0.25
6
C B
0.10
(4X)
1.64
10x 0.40
TOP VIEW
BOTTOM VIEW
5
M C B
(4X)
0.10
PACKAGE
OUTLINE
SEE DETAIL "X"
(10 x 0.60)
(10x 0.25)
0.10
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
1.64
TYPICAL RECOMMENDED LAND PATTERN
5
0.20 REF
0.05
C
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
7.
COMPLAINT TO JEDEC MO-229-WEED-3 except for E-PAD
dimensions.
FN6858.0
September 21, 2009
18
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