ISL8563IB [INTERSIL]

+3V to +5.5V, 1Microamp, 250kbps, EIA/TIA-562, EIA/TIA-232 Transmitters/Receivers; + 3V至+ 5.5V , 1Microamp , 250kbps的, EIA / TIA- 562 , EIA / TIA- 232发射器/接收器
ISL8563IB
型号: ISL8563IB
厂家: Intersil    Intersil
描述:

+3V to +5.5V, 1Microamp, 250kbps, EIA/TIA-562, EIA/TIA-232 Transmitters/Receivers
+ 3V至+ 5.5V , 1Microamp , 250kbps的, EIA / TIA- 562 , EIA / TIA- 232发射器/接收器

文件: 总10页 (文件大小:240K)
中文:  中文翻译
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ISL8563  
TM  
Data Sheet  
March 2001  
File Number 6005  
+3V to +5.5V, 1Microamp, 250kbps,  
EIA/TIA-562, EIA/TIA-232  
Transmitters/Receivers  
Features  
• Drop in Replacement for MAX563, with Improved Output  
Voltage (±5V) for Enhanced Noise Immunity  
The Intersil ISL8563 contains 3.0V to 5.5V powered  
transmitters/receivers which meet ElA/TIA-562 and  
• Available as ±15kV ESD Protected Version (ISL8563E)  
• Meets EIA/TIA-562, and EIA/TIA-232 Specifications at 3V  
• Latch-Up Free  
ElA/TIA-232 specifications, even at V  
= 3.0V. Targeted  
tle  
85  
CC  
applications are PDAs, Palmtops, and notebook and laptop  
computers where the low operational, and even lower  
standby, power consumption is critical. Efficient on-chip  
charge pumps, coupled with a manual powerdown function,  
reduce the standby supply current to a 1µA trickle. Small  
footprint packaging, and the use of small, low value  
capacitors ensure board space savings as well. Data rates  
greater than 250kbps are guaranteed at worst case load  
conditions. The ISL8563 is fully compatible with 3.3V only  
systems, mixed 3.3V and 5.0V systems, and 5.0V only  
systems.  
• On-Chip Voltage Converters Require Only Four External  
0.1µF Capacitors  
• Receivers Active in Powerdown  
jec  
V
• Receiver Hysteresis For Improved Noise Immunity  
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps  
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 4V/µs  
• Wide Power Supply Range. . . . . . . . Single +3V to +5.5V  
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA  
V,  
cro  
,
kb  
Applications  
This product features an improved charge pump which  
delivers ±5V transmitter supplies, allowing the use of the  
ISL8563 in RS-562 and RS-232 applications. RS-562  
applications will benefit from the improved noise immunity  
afforded by the ±5V output swing capability.  
• Any System Requiring RS-562/RS-232 Communication  
Ports  
/TI  
62,  
/TI  
32  
s
ers  
ei  
)
- Battery Powered, Hand-Held, and Portable Equipment  
- Laptop Computers, Notebooks, Palmtops  
- Digital Cameras  
- Bar Code Readers  
Table 1 summarizes the features of the device represented  
by this data sheet, while Application Note AN9863  
summarizes the features of each device comprising the 3V  
RS-232 family.  
Related Literature  
Technical Brief TB363 “Guidelines for Handling and  
Processing Moisture Sensitive Surface Mount Devices  
(SMDs)”  
tho  
For a drop-in compatible part with ±15kV ESD protection,  
please see the ISL8563E data sheet.  
• Application Note AN9863, “3V to +5.5V, 250K-1Mbps,  
RS-232 Transmitters/Receivers”  
w
Ordering Information  
Pinout  
TEMP.  
o
rsi  
PART NO.  
ISL8563CB  
ISL8563CB-T  
ISL8563CP  
ISL8563IB  
RANGE ( C)  
0 to 70  
PACKAGE  
18 Ld SOIC  
PKG. NO.  
M18.3  
ISL8563 (PDIP, SOIC)  
TOP VIEW  
por  
n,  
ico  
cto  
-
EN  
C1+  
V+  
1
2
3
4
5
6
7
8
9
18 SHDN  
17  
0 to 70  
Tape and Reel  
18 Ld PDIP  
M18.3  
E18.3  
M18.3  
M18.3  
V
CC  
0 to 70  
16 GND  
15 T1  
-40 to 85  
-40 to 85  
18 Ld SOIC  
C1-  
C2+  
C2-  
V-  
OUT  
ISL8563IB-T  
Tape and Reel  
14 R1  
13 R1  
12 T1  
IN  
V
OUT  
IN  
IN  
ect  
T2  
11 T2  
10  
OUT  
R2  
IN  
R2  
OUT  
an  
y
el,  
,
TABLE 1. SUMMARY OF FEATURES  
DATA  
NO. OF  
MONITOR Rx.  
(R  
MANUAL  
POWER-  
DOWN?  
AUTOMATIC  
POWERDOWN  
FUNCTION?  
PART  
NUMBER  
NO. OF NO. OF  
RATE  
(kbps)  
Rx. ENABLE  
FUNCTION?  
READY  
OUTPUT?  
Tx.  
Rx.  
)
OUTB  
ISL8563  
2
2
0
250  
YES  
NO  
YES  
NO  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2001, All Rights Reserved  
1
ISL8563  
Pin Descriptions  
PIN  
FUNCTION  
V
System Power Supply Input (3.0V to 5.5V).  
CC  
V+  
V-  
Internally Generated Positive Transmitter Supply (+5.5V).  
Internally Generated Negative Transmitter Supply (-5.5V).  
Ground Connection.  
GND  
C1+  
C1-  
C2+  
C2-  
External Capacitor (Voltage Doubler) is connected to this lead.  
External Capacitor (Voltage Doubler) is connected to this lead.  
External Capacitor (Voltage Inverter) is connected to this lead.  
External Capacitor (Voltage Inverter) is connected to this lead.  
TTL/CMOS Compatible Transmitter Inputs with pull-up resistors.  
RS-562/RS-232 level (nominally ±5.5V) transmitter outputs.  
RS-562/RS-232 compatible receiver inputs.  
T
IN  
T
OUT  
R
IN  
R
TTL/CMOS Level Receiver Outputs.  
OUT  
EN  
Active Low Receiver Enable Control.  
SHDN  
Active Low Input which shuts down transmitters and on-board power supply, to place device in low power mode.  
Typical Operating Circuit  
ISL8563  
+3.3V  
C
+
0.1µF  
17  
C
0.1µF  
3
2
C1+  
1
V
CC  
+
+
+
+
V+  
V-  
0.1µF  
4
5
3
7
C1-  
C
0.1µF  
2
C2+  
C
4
0.1µF  
6
C2-  
V
CC  
400kΩ  
T
T
1
2
12  
15  
T1  
T2  
T1  
IN  
OUT  
OUT  
V
CC  
400kΩ  
8
11  
13  
T2  
IN  
TTL/CMOS  
LOGIC LEVELS  
RS-562/232  
LEVELS  
14  
R1  
R1  
OUT  
IN  
IN  
5kΩ  
R
1
9
10  
1
R2  
R2  
OUT  
5kΩ  
R
2
EN  
18  
V
CC  
SHDN  
GND  
16  
2
ISL8563  
Absolute Maximum Ratings  
Thermal Information  
o
V
to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
CC  
JA  
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V  
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V  
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V  
Input Voltages  
18 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .  
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .  
Moisture Sensitivity (see Technical Brief TB363)  
All Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1  
Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C  
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C  
(SOIC - Lead Tips Only)  
80  
75  
o
o
T
, EN, SHDN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V  
IN  
o
R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V  
IN  
Output Voltages  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V  
o
T
OUT  
R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V  
+0.3V  
OUT  
Short Circuit Duration  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous  
CC  
Operating Conditions  
T
OUT  
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table  
Temperature Range  
ISL8563CX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C  
ISL8563IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C  
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.  
JA  
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.  
CC  
1
4
o
Typicals are at T = 25 C  
A
TEMP  
o
PARAMETER  
RS-562/RS-232 TRANSMITTERS  
Output Voltage Swing  
TEST CONDITIONS  
( C)  
MIN  
TYP  
MAX  
UNITS  
All Transmitter Outputs Loaded with 3kto Ground  
= 3kΩ, C = 1000pF, One Transmitter Switching and  
Full  
Full  
±5.0  
±5.4  
-
-
V
Maximum Data Rate  
R
250  
500  
kbps  
L
L
Maintaining ±5V Output Swing  
Input Logic Threshold Low  
Input Logic Threshold High  
Transmitter Pull-Up Input Current  
T
T
T
Full  
Full  
Full  
Full  
Full  
Full  
Full  
-
-
-
0.8  
-
V
V
IN  
IN  
IN  
V
= 3.0V to 5.0V  
2.4  
CC  
SHDN = V  
-
2
20  
µA  
µA  
µA  
CC  
SHDN = GND  
-
±0.01  
-
±1.0  
±10  
-
Output Leakage Current  
Output Resistance  
V
V
V
= ±12V, V  
= 0V or 3.6V to 5.5V, SHDN = GND  
CC  
-
300  
-
OUT  
= V+ = V- = 0V, Transmitter Output = ±2V  
10M  
±35  
CC  
Output Short-Circuit Current  
RS-562/RS-232 RECEIVERS  
Input Voltage Range  
= 0V  
±60  
mA  
OUT  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
-25  
-
-
25  
0.6  
0.8  
-
V
V
Input Threshold Low  
V
V
V
V
V
= 3.3V  
1.2  
1.5  
1.5  
1.8  
0.5  
5
CC  
CC  
CC  
CC  
CC  
= 5.0V  
-
V
Input Threshold High  
= 3.3V  
2.4  
2.4  
0.1  
3
V
= 5.0V  
-
V
Input Hysteresis  
= 3.0V to 3.6V  
1.0  
7
V
Input Resistance  
kΩ  
V
Output Voltage Low  
Output Voltage High  
Output Leakage Current  
EN Input Logic Threshold Low  
EN Input Logic Threshold High  
POWER SUPPLY  
I
I
= 3.2mA  
= -1.0mA  
-
-
0.4  
-
OUT  
OUT  
V
-0.6  
V
-0.1  
V
CC  
CC  
EN = V  
CC  
-
-
±0.05  
±10  
0.8  
-
µA  
V
-
-
V
= 3.0V to 5.0V  
2.4  
V
CC  
Operating Supply Voltage  
Supply Current  
Full  
Full  
25  
3.0  
-
0.5  
14  
5.5  
6.0  
-
V
SHDN = V  
CC  
All Outputs Unloaded  
All Outputs loaded, R = 3kΩ  
-
-
-
-
-
mA  
mA  
µA  
µA  
µA  
L
Supply Current, Powerdown  
SHDN Input Leakage Current  
SHDN = GND  
25  
1
10  
Full  
Full  
1
25  
±0.01  
±1.0  
3
ISL8563  
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.  
CC  
1
4
o
Typicals are at T = 25 C (Continued)  
A
TEMP  
o
PARAMETER  
TEST CONDITIONS  
( C)  
MIN  
-
TYP  
MAX  
0.8  
-
UNITS  
SHDN Input Logic Threshold Low  
SHDN Input Logic Threshold High  
AC CHARACTERISTICS  
Full  
Full  
-
-
V
V
V
V
= 3.0V to 5.0V  
2.4  
CC  
CC  
Transition Region Slew Rate  
= 3.3V, R = 3kto 7kΩ, Measured From 3V to -3V or  
25  
4
-
30  
V/µs  
L
-3V to 3V, C = 50pF to 2500pF  
L
Transmitter Propagation Delay  
Receiver Propagation Delay  
Transmitter Input to  
Transmitter Output,  
t
t
(Note 2)  
(Note 2)  
Full  
Full  
-
-
1
1
3.5  
3.5  
µs  
µs  
PHL  
PLH  
C
= 1000pF, R = 3kΩ  
L
L
Receiver Input to Receiver  
t
t
t
t
t
t
(Note 3)  
(Note 3)  
Full  
Full  
Full  
Full  
25  
-
-
-
-
-
-
-
-
0.3  
0.3  
1.0  
µs  
µs  
ns  
ns  
µs  
ns  
ns  
ns  
PHL  
PLH  
ER  
Output, C = 150pF  
L
1.0  
Receiver Output Enable Time  
Receiver Output Disable Time  
Transmitter Output Enable Time  
Figure 1  
Figure 1  
Figure 2  
125  
160  
17  
500  
500  
DR  
ET  
-
-
-
-
Transmitter Output Disable Time Figure 2  
25  
600  
100  
100  
DT  
Transmitter Skew  
Receiver Skew  
t
t
- t  
PHL PLH  
(Note 2)  
(Note 3)  
25  
- t  
PHL PLH  
25  
ESD PERFORMANCE  
RS-562 Pins (T  
, R  
)
Human Body Model  
25  
25  
25  
25  
-
-
-
-
±15  
±8  
-
-
-
-
kV  
kV  
kV  
kV  
OUT IN  
IEC1000-4-2 Contact Discharge  
IEC1000-4-2 Air Gap Discharge  
Human Body Model  
±8  
All Other Pins  
NOTES:  
±3  
2. Transmitter is measured at the transmitter zero crossing points.  
3. Receiver is measured at the receiver 50 percent crossing points.  
Test Waveforms  
V
CC  
t
V
CC  
EN INPUT  
0V  
0V  
SHDN INPUT  
t
ER  
ET  
+3.7V  
-3.7V  
V
- 0.6V  
0.5V  
CC  
CC  
0V  
RECEIVER  
OUTPUT  
TRANSMITTER  
OUTPUT  
C
= 50pF  
C
R
= 150pF to GND  
L
+0.4V  
L
L
R
= 3kΩ  
= 1kto 0.5V  
L
CC  
V
V
CC  
CC  
SHDN INPUT  
0V  
0V  
EN INPUT  
t
DR  
t
DT  
V
V+  
OH  
+3.7V  
-3.7V  
V
- 0.1V  
+ 0.1V  
OH  
TRANSMITTER  
OUTPUT  
0.5V  
CC  
RECEIVER  
OUTPUT  
0V  
C
= 50pF  
L
V
V
C
= 150pF to GND  
OL  
OL  
L
V-  
R
= 3kΩ  
L
R
= 1kto 0.5V  
CC  
L
FIGURE 2. TRANSMITTER OUTPUT ENABLE AND DISABLE  
TIMING  
FIGURE 1. RECEIVER OUTPUT ENABLE AND DISABLE TIMING  
4
ISL8563  
(V  
= 0V). The receivers’ Schmitt trigger input stage uses  
Detailed Description  
CC  
hysteresis (even in powerdown) to increase noise immunity  
and decrease errors due to slow input signal transitions.  
The ISL8563 operates from a single +3V to +5.5V supply,  
guarantees a 250kbps minimum data rate, requires only four  
small external 0.1µF capacitors, features low power  
consumption, and meets all ElA/TIA-562 and EIA/TIA-232  
specifications. The circuit is divided into three sections: The  
charge pump, the transmitters, and the receivers.  
The ISL8563 inverting receivers disable only when EN is  
driven high. Standard receivers driving powered down  
peripherals must be disabled to prevent current flow through  
the peripheral’s protection diodes (see Figures 4 and 5).  
Charge-Pump  
V
CC  
Intersil’s new ISL8563 utilizes regulated on-chip dual charge  
pumps as voltage doublers, and voltage inverters to  
R
R
XIN  
XOUT  
generate ±5.5V transmitter supplies from a V  
supply as  
GND V  
V  
-25V V  
+25V  
5kΩ  
CC  
ROUT  
CC  
RIN  
low as 3.0V. This allows these devices to maintain RS-232  
compliant output levels over the ±10% tolerance range of  
3.3V powered systems. The efficient on-chip power supplies  
require only four small, external 0.1µF capacitors for the  
GND  
FIGURE 3. INVERTING RECEIVER CONNECTIONS  
Powerdown Functionality  
voltage doubler and inverter functions over the full V  
CC  
This 3V device requires a nominal supply current of 0.3mA  
during normal operation (not in powerdown mode). This is  
considerably less than the 5mA to 11mA current required by  
5V devices. The already low current requirement drops  
significantly when the device enters powerdown mode. In  
powerdown, supply current drops to 1µA, because the on-  
range. The charge pumps operate discontinuously (i.e., they  
turn off as soon as the V+ and V- supplies are pumped up to  
the nominal values), resulting in significant power savings.  
Transmitters  
The transmitters are proprietary, low dropout, inverting  
drivers that translate TTL/CMOS inputs to EIA/TIA-562/232  
output levels. Coupled with the on-chip ±5.5V supplies,  
these transmitters deliver true RS-562/232 levels over a  
wide range of single supply system voltages.  
chip charge pump turns off (V+ collapses to V , V-  
CC  
collapses to GND), the transmitter outputs three-state, and  
the transmitter input pull-ups disable. This micro-power  
mode makes the ISL8563 ideal for battery powered and  
portable applications.  
All transmitter outputs disable and assume a high  
impedance state when the device enters the powerdown  
mode (see Table 2). These outputs may be driven to ±12V  
when disabled.  
Software Controlled (Manual) Powerdown  
The ISL8563, is forced into its low power, stand by state via  
a simple shutdown (SHDN) pin. Driving this pin high enables  
normal operation, while driving it low forces the IC into its  
All devices guarantee a 250kbps data rate (V  
= ±5V) for  
3.0V, with one  
OUT  
powerdown state. Connect SHDN to V  
if the powerdown  
full load conditions (3kand 1000pF), V  
CC  
CC  
transmitter operating at full speed. Under more typical  
conditions of V 3.3V, R = 3k, and C = 250pF, one  
function isn’t needed. Note that all the receiver outputs  
remain enabled during shutdown (see Table 2). For the  
lowest power consumption during powerdown, the receivers  
should also be disabled by driving the EN input high (see  
next section, and Figures 4 and 5). The time required to exit  
powerdown, and resume transmission is less than 30µs.  
CC  
L
L
transmitter easily operates at 900kbps.  
Unused transmitter inputs may be left unconnected because  
they will be pulled to V by the on-chip pull-up resistors.  
CC  
Forcing the ISL8563 into power down disables the pull-up  
resistors to further minimize power.  
Receiver ENABLE Control  
The device also features an EN input to control the receiver  
outputs. Driving EN high disables all the receiver outputs  
placing them in a high impedance state. This is useful to  
eliminate supply current, due to a receiver output forward  
biasing the protection diode, when driving the input of a  
Receivers  
The ISL8563 contains standard inverting receivers that  
three-state via the EN control line. All the receivers convert  
RS-562/232 signals to CMOS output levels and accept  
inputs up to ±25V while presenting the required 3kto 7kΩ  
input impedance (see Figure 3) even if the power is off  
powered down (V  
= GND) peripheral (see Figure 4). The  
CC  
enable input has no effect on transmitters.  
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE  
SHDN INPUT  
EN INPUT  
TRANSMITTER OUTPUTS  
RECEIVER OUTPUTS  
MODE OF OPERATION  
Manual Powerdown  
L
L
L
H
L
High-Z  
High-Z  
Active  
Active  
Active  
High-Z  
Active  
High-Z  
Manual Powerdown w/Rcvr. Disabled  
Normal Operation  
H
H
H
Normal Operation w/Rcvr. Disabled  
5
ISL8563  
Transmitter Outputs When Exiting  
V
CC  
Powerdown  
V
CC  
V
Figure 6 shows the response of two transmitter outputs  
when exiting powerdown mode. As they activate, the two  
transmitter outputs properly go to opposite RS-562/232  
levels, with no glitching, ringing, nor undesirable transients.  
Each transmitter is loaded with 3kin parallel with 2500pF.  
Note that the transmitters enable only when the magnitude  
of the supplies exceed approximately 3V.  
CURRENT  
FLOW  
CC  
V
= V  
CC  
OUT  
Rx  
POWERED  
DOWN  
UART  
Tx  
OLD  
RS-562/232 CHIP  
SHDN = GND  
GND  
5V/DIV.  
SHDN  
FIGURE 4. POWER DRAIN THROUGH POWERED DOWN  
PERIPHERAL  
T1  
V
CC  
2V/DIV.  
TRANSITION  
DETECTOR  
TO  
WAKE-UP  
LOGIC  
ISL8563  
T2  
V
= +3.3V  
CC  
V
CC  
C1 - C4 = 0.1µF  
TIME (20µs/DIV.)  
R
T
V
= HI-Z  
X
OUT  
FIGURE 6. TRANSMITTER OUTPUTS WHEN EXITING  
POWERDOWN  
R2  
OUT  
POWERED  
DOWN  
UART  
R2  
T1  
IN  
T1  
IN  
X
High Data Rates  
The ISL8563 maintains the RS-232 ±5V minimum  
transmitter output voltages even at high data rates. Figure 7  
details a transmitter loopback test circuit, and Figure 8  
illustrates the loopback test result at 120kbps. For this test,  
all transmitters were simultaneously driving RS-232 loads in  
parallel with 1000pF, at 120kbps. Figure 9 shows the  
loopback results for a single transmitter driving 1000pF and  
an RS-232 load at 250kbps. The static transmitters were  
also loaded with an RS-232 receiver.  
OUT  
SHDN = GND, EN = V  
CC  
FIGURE 5. DISABLED RECEIVERS PREVENT POWER DRAIN  
Capacitor Selection  
The charge pumps operate with 0.1µF (or greater) capacitors  
for 3.0V V  
5.5V. Increasing the capacitor values (by a  
CC  
factor of 2) reduces ripple on the transmitter outputs and  
slightly reduces power consumption. C , C , and C can be  
increased without increasing C ’s value, however, do not  
increase C without also increasing C , C , and C to  
2
3
4
V
CC  
1
+
0.1µF  
V
CC  
V+  
V-  
+
+
1
2
3
4
C1+  
+
C
C
maintain the proper ratios (C to the other capacitors).  
1
1
2
C
3
4
C1-  
When using minimum required capacitor values, make sure  
that capacitor values do not degrade excessively with  
temperature. If in doubt, use capacitors with a larger nominal  
value. The capacitor’s equivalent series resistance (ESR)  
usually rises at low temperatures and it influences the  
amount of ripple on V+ and V-.  
ISL8563  
CC  
C2+  
C
+
V
C2-  
400kΩ  
T
T
IN  
OUT  
1000pF  
R
IN  
R
OUT  
Power Supply Decoupling  
In most circumstances a 0.1µF bypass capacitor is  
adequate. In applications that are particularly sensitive to  
EN  
SHDN  
5K  
V
CC  
power supply noise, decouple V  
to ground with a  
CC  
capacitor of the same value as the charge-pump capacitor C .  
Connect the bypass capacitor as close as possible to the IC.  
1
FIGURE 7. TRANSMITTER LOOPBACK TEST CIRCUIT  
6
ISL8563  
Interconnection with 3V and 5V Logic  
5V/DIV.  
The ISL8563 directly interface with most 5V logic families,  
including ACT and HCT CMOS. See Table 3 for more  
information on possible combinations of interconnections.  
T1  
IN  
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS  
SUPPLY VOLTAGES  
T1  
OUT  
SYSTEM  
V
CC  
POWER-SUPPLY SUPPLY  
VOLTAGE  
(V)  
VOLTAGE  
(V)  
COMPATIBILITY  
R1  
OUT  
3.3  
3.3  
Compatible with all CMOS  
families.  
V
= +3.3V  
CC  
C1 - C4 = 0.1µF  
5
5
Compatible with all TTL and  
CMOS logic families.  
5µs/DIV.  
FIGURE 8. LOOPBACK TEST AT 120kbps  
5
3.3  
Compatible with ACT and HCT  
CMOS, and with TTL.  
Incompatible with AC, HC, or  
CD4000 CMOS.  
5V/DIV.  
T1  
IN  
T1  
OUT  
R1  
OUT  
V
= +3.3V  
CC  
C1 - C4 = 0.1µF  
2µs/DIV.  
FIGURE 9. LOOPBACK TEST AT 250kbps  
o
Typical Performance Curves V = 3.3V, T = 25 C  
CC  
A
6
4
25  
20  
V
+
OUT  
2
1 TRANSMITTER AT 250kbps  
1 TRANSMITTER AT 30kbps  
0
15  
10  
-SLEW  
-2  
-4  
-6  
+SLEW  
V
-
OUT  
5
0
0
1000  
2000  
3000  
4000  
5000  
1000  
2000  
3000  
4000  
5000  
LOAD CAPACITANCE (pF)  
LOAD CAPACITANCE (pF)  
FIGURE 10. TRANSMITTER OUTPUT VOLTAGE vs LOAD  
CAPACITANCE  
FIGURE 11. SLEW RATE vs LOAD CAPACITANCE  
7
ISL8563  
o
Typical Performance Curves V = 3.3V, T = 25 C (Continued)  
CC  
A
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
45  
40  
35  
30  
25  
20  
NO LOAD  
ALL OUTPUTS STATIC  
250kbps  
120kbps  
20kbps  
15  
10  
5
0
0
1000  
2000  
3000  
4000  
5000  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
LOAD CAPACITANCE (pF)  
SUPPLY VOLTAGE (V)  
FIGURE 12. SUPPLY CURRENT vs LOAD CAPACITANCE  
WHEN TRANSMITTING DATA  
FIGURE 13. SUPPLY CURRENT vs SUPPLY VOLTAGE  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
100 mils x 100 mils (2540µm x 2540µm)  
Type: Silox  
Thickness: 13kÅ  
METALLIZATION:  
TRANSISTOR COUNT:  
Type: Metal 1: AISi(1%)  
Thickness: Metal 1: 8kÅ  
Type: Metal 2: AISi (1%)  
Thickness: Metal 2: 10kÅ  
338  
PROCESS:  
Si Gate CMOS  
SUBSTRATE POTENTIAL (POWERED UP):  
Floating  
8
ISL8563  
Dual-In-Line Plastic Packages (PDIP)  
E18.3 (JEDEC MS-001-BC ISSUE D)  
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE  
N
E1  
INDEX  
AREA  
INCHES  
MILLIMETERS  
1
2
3
N/2  
SYMBOL  
MIN  
MAX  
0.210  
-
MIN  
-
MAX  
5.33  
-
NOTES  
-B-  
A
A1  
A2  
B
-
4
-A-  
0.015  
0.115  
0.014  
0.045  
0.008  
0.845  
0.005  
0.300  
0.240  
0.39  
2.93  
0.356  
1.15  
0.204  
21.47  
0.13  
7.62  
6.10  
4
D
E
BASE  
PLANE  
0.195  
0.022  
0.070  
0.014  
0.880  
-
4.95  
0.558  
1.77  
0.355  
22.35  
-
-
A2  
A
-C-  
-
SEATING  
PLANE  
L
C
L
B1  
C
8, 10  
D1  
B1  
-
eA  
A1  
A
D1  
e
D
5
eC  
B S  
C
B
eB  
D1  
E
5
0.010 (0.25) M  
C
0.325  
0.280  
8.25  
7.11  
6
NOTES:  
E1  
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and  
Metric dimensions, the inch dimensions control.  
0.100 BSC  
0.300 BSC  
2.54 BSC  
7.62 BSC  
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  
Publication No. 95.  
e
-
0.430  
0.150  
-
10.92  
3.81  
7
B
L
0.115  
2.93  
4
9
4. Dimensions A, A1 and L are measured with the package seated in  
N
18  
18  
JEDEC seating plane gauge GS-3.  
Rev. 0 12/93  
5. D, D1, and E1 dimensions do not include mold flash or protrusions.  
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).  
e
6. E and  
are measured with the leads constrained to be perpendic-  
A
-C-  
ular to datum  
.
7. e and e are measured at the lead tips with the leads unconstrained.  
B
C
e
must be zero or greater.  
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar  
protrusions shall not exceed 0.010 inch (0.25mm).  
9. N is the maximum number of terminal positions.  
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,  
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).  
9
ISL8563  
Small Outline Plastic Packages (SOIC)  
M18.3 (JEDEC MS-013-AB ISSUE C)  
N
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE  
INDEX  
AREA  
0.25(0.010)  
M
B M  
H
INCHES  
MILLIMETERS  
E
SYMBOL  
MIN  
MAX  
MIN  
2.35  
0.10  
0.33  
0.23  
11.35  
7.40  
MAX  
2.65  
0.30  
0.51  
0.32  
11.75  
7.60  
NOTES  
-B-  
A
A1  
B
C
D
E
e
0.0926  
0.0040  
0.013  
0.1043  
0.0118  
0.0200  
0.0125  
0.4625  
0.2992  
-
-
1
2
3
L
9
SEATING PLANE  
A
0.0091  
0.4469  
0.2914  
-
-A-  
o
3
h x 45  
D
4
-C-  
0.050 BSC  
1.27 BSC  
-
α
µ
H
h
0.394  
0.010  
0.016  
0.419  
0.029  
0.050  
10.00  
0.25  
0.40  
10.65  
0.75  
1.27  
-
e
A1  
C
5
B
0.10(0.004)  
L
6
0.25(0.010) M  
C A M B S  
N
α
18  
18  
7
o
o
o
o
0
8
0
8
-
NOTES:  
Rev. 0 12/93  
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  
Publication Number 95.  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate burrs.  
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006  
inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions. Interlead  
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.  
5. The chamfer on the body is optional. If it is not present, a visual index  
feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above  
the seating plane, shall not exceed a maximum value of 0.61mm  
(0.024 inch)  
10. Controlling dimension: MILLIMETER. Converted inch dimensions are  
not necessarily exact.  
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.  
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-  
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.  
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Intersil Ltd.  
2401 Palm Bay Rd., Mail Stop 53-204  
Palm Bay, FL 32905  
TEL: (321) 724-7000  
FAX: (321) 724-7240  
Mercure Center  
8F-2, 96, Sec. 1, Chien-kuo North,  
Taipei, Taiwan 104  
Republic of China  
TEL: 886-2-2515-8508  
FAX: 886-2-2515-8369  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
10  

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